2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/types.h>
56 #include <linux/errno.h>
57 #include <linux/ioport.h>
58 #include <linux/pci.h>
59 #include <linux/dma-mapping.h>
60 #include <linux/kernel.h>
61 #include <linux/netdevice.h>
62 #include <linux/etherdevice.h>
63 #include <linux/skbuff.h>
64 #include <linux/init.h>
65 #include <linux/delay.h>
67 #include <linux/highmem.h>
68 #include <linux/sockios.h>
69 #include <linux/firmware.h>
70 #include <linux/slab.h>
71 #include <linux/prefetch.h>
72 #include <linux/if_vlan.h>
75 #include <linux/ethtool.h>
81 #include <asm/system.h>
84 #include <asm/byteorder.h>
85 #include <asm/uaccess.h>
88 #define DRV_NAME "acenic"
92 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
93 #define ACE_IS_TIGON_I(ap) 0
94 #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96 #define ACE_IS_TIGON_I(ap) (ap->version == 1)
97 #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
100 #ifndef PCI_VENDOR_ID_ALTEON
101 #define PCI_VENDOR_ID_ALTEON 0x12ae
103 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
104 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
105 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107 #ifndef PCI_DEVICE_ID_3COM_3C985
108 #define PCI_DEVICE_ID_3COM_3C985 0x0001
110 #ifndef PCI_VENDOR_ID_NETGEAR
111 #define PCI_VENDOR_ID_NETGEAR 0x1385
112 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
115 #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
120 * Farallon used the DEC vendor ID by mistake and they seem not
123 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
124 #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
127 #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129 #ifndef PCI_VENDOR_ID_SGI
130 #define PCI_VENDOR_ID_SGI 0x10a9
132 #ifndef PCI_DEVICE_ID_SGI_ACENIC
133 #define PCI_DEVICE_ID_SGI_ACENIC 0x0009
136 static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
145 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
146 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 * Farallon used the DEC vendor ID on their cards incorrectly,
149 * then later Alteon's ID.
151 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
153 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
155 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
156 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
159 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161 #define ace_sync_irq(irq) synchronize_irq(irq)
163 #ifndef offset_in_page
164 #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
167 #define ACE_MAX_MOD_PARMS 8
168 #define BOARD_IDX_STATIC 0
169 #define BOARD_IDX_OVERFLOW -1
174 * These must be defined before the firmware is included.
176 #define MAX_TEXT_LEN 96*1024
177 #define MAX_RODATA_LEN 8*1024
178 #define MAX_DATA_LEN 2*1024
180 #ifndef tigon2FwReleaseLocal
181 #define tigon2FwReleaseLocal 0
185 * This driver currently supports Tigon I and Tigon II based cards
186 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
187 * GA620. The driver should also work on the SGI, DEC and Farallon
188 * versions of the card, however I have not been able to test that
191 * This card is really neat, it supports receive hardware checksumming
192 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
193 * firmware. Also the programming interface is quite neat, except for
194 * the parts dealing with the i2c eeprom on the card ;-)
196 * Using jumbo frames:
198 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
199 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
200 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
201 * interface number and <MTU> being the MTU value.
205 * When compiled as a loadable module, the driver allows for a number
206 * of module parameters to be specified. The driver supports the
207 * following module parameters:
209 * trace=<val> - Firmware trace level. This requires special traced
210 * firmware to replace the firmware supplied with
211 * the driver - for debugging purposes only.
213 * link=<val> - Link state. Normally you want to use the default link
214 * parameters set by the driver. This can be used to
215 * override these in case your switch doesn't negotiate
216 * the link properly. Valid values are:
217 * 0x0001 - Force half duplex link.
218 * 0x0002 - Do not negotiate line speed with the other end.
219 * 0x0010 - 10Mbit/sec link.
220 * 0x0020 - 100Mbit/sec link.
221 * 0x0040 - 1000Mbit/sec link.
222 * 0x0100 - Do not negotiate flow control.
223 * 0x0200 - Enable RX flow control Y
224 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
225 * Default value is 0x0270, ie. enable link+flow
226 * control negotiation. Negotiating the highest
227 * possible link speed with RX flow control enabled.
229 * When disabling link speed negotiation, only one link
230 * speed is allowed to be specified!
232 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
233 * to wait for more packets to arive before
234 * interrupting the host, from the time the first
237 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
238 * to wait for more packets to arive in the transmit ring,
239 * before interrupting the host, after transmitting the
240 * first packet in the ring.
242 * max_tx_desc=<val> - maximum number of transmit descriptors
243 * (packets) transmitted before interrupting the host.
245 * max_rx_desc=<val> - maximum number of receive descriptors
246 * (packets) received before interrupting the host.
248 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
249 * increments of the NIC's on board memory to be used for
250 * transmit and receive buffers. For the 1MB NIC app. 800KB
251 * is available, on the 1/2MB NIC app. 300KB is available.
252 * 68KB will always be available as a minimum for both
253 * directions. The default value is a 50/50 split.
254 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
255 * operations, default (1) is to always disable this as
256 * that is what Alteon does on NT. I have not been able
257 * to measure any real performance differences with
258 * this on my systems. Set <val>=0 if you want to
259 * enable these operations.
261 * If you use more than one NIC, specify the parameters for the
262 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
263 * run tracing on NIC #2 but not on NIC #1 and #3.
267 * - Proper multicast support.
268 * - NIC dump support.
269 * - More tuning parameters.
271 * The mini ring is not used under Linux and I am not sure it makes sense
272 * to actually use it.
274 * New interrupt handler strategy:
276 * The old interrupt handler worked using the traditional method of
277 * replacing an skbuff with a new one when a packet arrives. However
278 * the rx rings do not need to contain a static number of buffer
279 * descriptors, thus it makes sense to move the memory allocation out
280 * of the main interrupt handler and do it in a bottom half handler
281 * and only allocate new buffers when the number of buffers in the
282 * ring is below a certain threshold. In order to avoid starving the
283 * NIC under heavy load it is however necessary to force allocation
284 * when hitting a minimum threshold. The strategy for alloction is as
287 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
288 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
289 * the buffers in the interrupt handler
290 * RX_RING_THRES - maximum number of buffers in the rx ring
291 * RX_MINI_THRES - maximum number of buffers in the mini ring
292 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
294 * One advantagous side effect of this allocation approach is that the
295 * entire rx processing can be done without holding any spin lock
296 * since the rx rings and registers are totally independent of the tx
297 * ring and its registers. This of course includes the kmalloc's of
298 * new skb's. Thus start_xmit can run in parallel with rx processing
299 * and the memory allocation on SMP systems.
301 * Note that running the skb reallocation in a bottom half opens up
302 * another can of races which needs to be handled properly. In
303 * particular it can happen that the interrupt handler tries to run
304 * the reallocation while the bottom half is either running on another
305 * CPU or was interrupted on the same CPU. To get around this the
306 * driver uses bitops to prevent the reallocation routines from being
309 * TX handling can also be done without holding any spin lock, wheee
310 * this is fun! since tx_ret_csm is only written to by the interrupt
311 * handler. The case to be aware of is when shutting down the device
312 * and cleaning up where it is necessary to make sure that
313 * start_xmit() is not running while this is happening. Well DaveM
314 * informs me that this case is already protected against ... bye bye
315 * Mr. Spin Lock, it was nice to know you.
317 * TX interrupts are now partly disabled so the NIC will only generate
318 * TX interrupts for the number of coal ticks, not for the number of
319 * TX packets in the queue. This should reduce the number of TX only,
320 * ie. when no RX processing is done, interrupts seen.
324 * Threshold values for RX buffer allocation - the low water marks for
325 * when to start refilling the rings are set to 75% of the ring
326 * sizes. It seems to make sense to refill the rings entirely from the
327 * intrrupt handler once it gets below the panic threshold, that way
328 * we don't risk that the refilling is moved to another CPU when the
329 * one running the interrupt handler just got the slab code hot in its
332 #define RX_RING_SIZE 72
333 #define RX_MINI_SIZE 64
334 #define RX_JUMBO_SIZE 48
336 #define RX_PANIC_STD_THRES 16
337 #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
338 #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
339 #define RX_PANIC_MINI_THRES 12
340 #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
341 #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
342 #define RX_PANIC_JUMBO_THRES 6
343 #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
344 #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
348 * Size of the mini ring entries, basically these just should be big
349 * enough to take TCP ACKs
351 #define ACE_MINI_SIZE 100
353 #define ACE_MINI_BUFSIZE ACE_MINI_SIZE
354 #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
355 #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
358 * There seems to be a magic difference in the effect between 995 and 996
359 * but little difference between 900 and 995 ... no idea why.
361 * There is now a default set of tuning parameters which is set, depending
362 * on whether or not the user enables Jumbo frames. It's assumed that if
363 * Jumbo frames are enabled, the user wants optimal tuning for that case.
365 #define DEF_TX_COAL 400 /* 996 */
366 #define DEF_TX_MAX_DESC 60 /* was 40 */
367 #define DEF_RX_COAL 120 /* 1000 */
368 #define DEF_RX_MAX_DESC 25
369 #define DEF_TX_RATIO 21 /* 24 */
371 #define DEF_JUMBO_TX_COAL 20
372 #define DEF_JUMBO_TX_MAX_DESC 60
373 #define DEF_JUMBO_RX_COAL 30
374 #define DEF_JUMBO_RX_MAX_DESC 6
375 #define DEF_JUMBO_TX_RATIO 21
377 #if tigon2FwReleaseLocal < 20001118
379 * Standard firmware and early modifications duplicate
380 * IRQ load without this flag (coal timer is never reset).
381 * Note that with this flag tx_coal should be less than
382 * time to xmit full tx ring.
383 * 400usec is not so bad for tx ring size of 128.
385 #define TX_COAL_INTS_ONLY 1 /* worth it */
388 * With modified firmware, this is not necessary, but still useful.
390 #define TX_COAL_INTS_ONLY 1
394 #define DEF_STAT (2 * TICKS_PER_SEC)
397 static int link_state[ACE_MAX_MOD_PARMS];
398 static int trace[ACE_MAX_MOD_PARMS];
399 static int tx_coal_tick[ACE_MAX_MOD_PARMS];
400 static int rx_coal_tick[ACE_MAX_MOD_PARMS];
401 static int max_tx_desc[ACE_MAX_MOD_PARMS];
402 static int max_rx_desc[ACE_MAX_MOD_PARMS];
403 static int tx_ratio[ACE_MAX_MOD_PARMS];
404 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
406 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
407 MODULE_LICENSE("GPL");
408 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
409 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
410 MODULE_FIRMWARE("acenic/tg1.bin");
412 MODULE_FIRMWARE("acenic/tg2.bin");
414 module_param_array_named(link, link_state, int, NULL, 0);
415 module_param_array(trace, int, NULL, 0);
416 module_param_array(tx_coal_tick, int, NULL, 0);
417 module_param_array(max_tx_desc, int, NULL, 0);
418 module_param_array(rx_coal_tick, int, NULL, 0);
419 module_param_array(max_rx_desc, int, NULL, 0);
420 module_param_array(tx_ratio, int, NULL, 0);
421 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
422 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
423 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
424 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
425 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
426 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
427 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
430 static const char version[] __devinitconst =
431 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
432 " http://home.cern.ch/~jes/gige/acenic.html\n";
434 static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
435 static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
436 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
438 static const struct ethtool_ops ace_ethtool_ops = {
439 .get_settings = ace_get_settings,
440 .set_settings = ace_set_settings,
441 .get_drvinfo = ace_get_drvinfo,
444 static void ace_watchdog(struct net_device *dev);
446 static const struct net_device_ops ace_netdev_ops = {
447 .ndo_open = ace_open,
448 .ndo_stop = ace_close,
449 .ndo_tx_timeout = ace_watchdog,
450 .ndo_get_stats = ace_get_stats,
451 .ndo_start_xmit = ace_start_xmit,
452 .ndo_set_rx_mode = ace_set_multicast_list,
453 .ndo_validate_addr = eth_validate_addr,
454 .ndo_set_mac_address = ace_set_mac_addr,
455 .ndo_change_mtu = ace_change_mtu,
458 static int __devinit acenic_probe_one(struct pci_dev *pdev,
459 const struct pci_device_id *id)
461 struct net_device *dev;
462 struct ace_private *ap;
463 static int boards_found;
465 dev = alloc_etherdev(sizeof(struct ace_private));
469 SET_NETDEV_DEV(dev, &pdev->dev);
471 ap = netdev_priv(dev);
473 ap->name = pci_name(pdev);
475 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
476 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
478 dev->watchdog_timeo = 5*HZ;
480 dev->netdev_ops = &ace_netdev_ops;
481 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
483 /* we only display this string ONCE */
487 if (pci_enable_device(pdev))
488 goto fail_free_netdev;
491 * Enable master mode before we start playing with the
492 * pci_command word since pci_set_master() will modify
495 pci_set_master(pdev);
497 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
499 /* OpenFirmware on Mac's does not set this - DOH.. */
500 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
501 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
502 "access - was not enabled by BIOS/Firmware\n",
504 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
505 pci_write_config_word(ap->pdev, PCI_COMMAND,
510 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
511 if (ap->pci_latency <= 0x40) {
512 ap->pci_latency = 0x40;
513 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
517 * Remap the regs into kernel space - this is abuse of
518 * dev->base_addr since it was means for I/O port
519 * addresses but who gives a damn.
521 dev->base_addr = pci_resource_start(pdev, 0);
522 ap->regs = ioremap(dev->base_addr, 0x4000);
524 printk(KERN_ERR "%s: Unable to map I/O register, "
525 "AceNIC %i will be disabled.\n",
526 ap->name, boards_found);
527 goto fail_free_netdev;
530 switch(pdev->vendor) {
531 case PCI_VENDOR_ID_ALTEON:
532 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
533 printk(KERN_INFO "%s: Farallon PN9100-T ",
536 printk(KERN_INFO "%s: Alteon AceNIC ",
540 case PCI_VENDOR_ID_3COM:
541 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
543 case PCI_VENDOR_ID_NETGEAR:
544 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
546 case PCI_VENDOR_ID_DEC:
547 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
548 printk(KERN_INFO "%s: Farallon PN9000-SX ",
552 case PCI_VENDOR_ID_SGI:
553 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
556 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
560 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
561 printk("irq %d\n", pdev->irq);
563 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
564 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
565 printk(KERN_ERR "%s: Driver compiled without Tigon I"
566 " support - NIC disabled\n", dev->name);
571 if (ace_allocate_descriptors(dev))
572 goto fail_free_netdev;
575 if (boards_found >= ACE_MAX_MOD_PARMS)
576 ap->board_idx = BOARD_IDX_OVERFLOW;
578 ap->board_idx = boards_found;
580 ap->board_idx = BOARD_IDX_STATIC;
584 goto fail_free_netdev;
586 if (register_netdev(dev)) {
587 printk(KERN_ERR "acenic: device registration failed\n");
590 ap->name = dev->name;
592 if (ap->pci_using_dac)
593 dev->features |= NETIF_F_HIGHDMA;
595 pci_set_drvdata(pdev, dev);
601 ace_init_cleanup(dev);
607 static void __devexit acenic_remove_one(struct pci_dev *pdev)
609 struct net_device *dev = pci_get_drvdata(pdev);
610 struct ace_private *ap = netdev_priv(dev);
611 struct ace_regs __iomem *regs = ap->regs;
614 unregister_netdev(dev);
616 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
617 if (ap->version >= 2)
618 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
621 * This clears any pending interrupts
623 writel(1, ®s->Mb0Lo);
624 readl(®s->CpuCtrl); /* flush */
627 * Make sure no other CPUs are processing interrupts
628 * on the card before the buffers are being released.
629 * Otherwise one might experience some `interesting'
632 * Then release the RX buffers - jumbo buffers were
633 * already released in ace_close().
635 ace_sync_irq(dev->irq);
637 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
638 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
641 struct ring_info *ringp;
644 ringp = &ap->skb->rx_std_skbuff[i];
645 mapping = dma_unmap_addr(ringp, mapping);
646 pci_unmap_page(ap->pdev, mapping,
650 ap->rx_std_ring[i].size = 0;
651 ap->skb->rx_std_skbuff[i].skb = NULL;
656 if (ap->version >= 2) {
657 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
658 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
661 struct ring_info *ringp;
664 ringp = &ap->skb->rx_mini_skbuff[i];
665 mapping = dma_unmap_addr(ringp,mapping);
666 pci_unmap_page(ap->pdev, mapping,
670 ap->rx_mini_ring[i].size = 0;
671 ap->skb->rx_mini_skbuff[i].skb = NULL;
677 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
678 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
680 struct ring_info *ringp;
683 ringp = &ap->skb->rx_jumbo_skbuff[i];
684 mapping = dma_unmap_addr(ringp, mapping);
685 pci_unmap_page(ap->pdev, mapping,
689 ap->rx_jumbo_ring[i].size = 0;
690 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
695 ace_init_cleanup(dev);
699 static struct pci_driver acenic_pci_driver = {
701 .id_table = acenic_pci_tbl,
702 .probe = acenic_probe_one,
703 .remove = __devexit_p(acenic_remove_one),
706 static int __init acenic_init(void)
708 return pci_register_driver(&acenic_pci_driver);
711 static void __exit acenic_exit(void)
713 pci_unregister_driver(&acenic_pci_driver);
716 module_init(acenic_init);
717 module_exit(acenic_exit);
719 static void ace_free_descriptors(struct net_device *dev)
721 struct ace_private *ap = netdev_priv(dev);
724 if (ap->rx_std_ring != NULL) {
725 size = (sizeof(struct rx_desc) *
726 (RX_STD_RING_ENTRIES +
727 RX_JUMBO_RING_ENTRIES +
728 RX_MINI_RING_ENTRIES +
729 RX_RETURN_RING_ENTRIES));
730 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
731 ap->rx_ring_base_dma);
732 ap->rx_std_ring = NULL;
733 ap->rx_jumbo_ring = NULL;
734 ap->rx_mini_ring = NULL;
735 ap->rx_return_ring = NULL;
737 if (ap->evt_ring != NULL) {
738 size = (sizeof(struct event) * EVT_RING_ENTRIES);
739 pci_free_consistent(ap->pdev, size, ap->evt_ring,
743 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
744 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
745 pci_free_consistent(ap->pdev, size, ap->tx_ring,
750 if (ap->evt_prd != NULL) {
751 pci_free_consistent(ap->pdev, sizeof(u32),
752 (void *)ap->evt_prd, ap->evt_prd_dma);
755 if (ap->rx_ret_prd != NULL) {
756 pci_free_consistent(ap->pdev, sizeof(u32),
757 (void *)ap->rx_ret_prd,
759 ap->rx_ret_prd = NULL;
761 if (ap->tx_csm != NULL) {
762 pci_free_consistent(ap->pdev, sizeof(u32),
763 (void *)ap->tx_csm, ap->tx_csm_dma);
769 static int ace_allocate_descriptors(struct net_device *dev)
771 struct ace_private *ap = netdev_priv(dev);
774 size = (sizeof(struct rx_desc) *
775 (RX_STD_RING_ENTRIES +
776 RX_JUMBO_RING_ENTRIES +
777 RX_MINI_RING_ENTRIES +
778 RX_RETURN_RING_ENTRIES));
780 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
781 &ap->rx_ring_base_dma);
782 if (ap->rx_std_ring == NULL)
785 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
786 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
787 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
789 size = (sizeof(struct event) * EVT_RING_ENTRIES);
791 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
793 if (ap->evt_ring == NULL)
797 * Only allocate a host TX ring for the Tigon II, the Tigon I
798 * has to use PCI registers for this ;-(
800 if (!ACE_IS_TIGON_I(ap)) {
801 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
803 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
806 if (ap->tx_ring == NULL)
810 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
812 if (ap->evt_prd == NULL)
815 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
816 &ap->rx_ret_prd_dma);
817 if (ap->rx_ret_prd == NULL)
820 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
822 if (ap->tx_csm == NULL)
829 ace_init_cleanup(dev);
835 * Generic cleanup handling data allocated during init. Used when the
836 * module is unloaded or if an error occurs during initialization
838 static void ace_init_cleanup(struct net_device *dev)
840 struct ace_private *ap;
842 ap = netdev_priv(dev);
844 ace_free_descriptors(dev);
847 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
848 ap->info, ap->info_dma);
850 kfree(ap->trace_buf);
853 free_irq(dev->irq, dev);
860 * Commands are considered to be slow.
862 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
866 idx = readl(®s->CmdPrd);
868 writel(*(u32 *)(cmd), ®s->CmdRng[idx]);
869 idx = (idx + 1) % CMD_RING_ENTRIES;
871 writel(idx, ®s->CmdPrd);
875 static int __devinit ace_init(struct net_device *dev)
877 struct ace_private *ap;
878 struct ace_regs __iomem *regs;
879 struct ace_info *info = NULL;
880 struct pci_dev *pdev;
883 u32 tig_ver, mac1, mac2, tmp, pci_state;
884 int board_idx, ecode = 0;
886 unsigned char cache_size;
888 ap = netdev_priv(dev);
891 board_idx = ap->board_idx;
894 * aman@sgi.com - its useful to do a NIC reset here to
895 * address the `Firmware not running' problem subsequent
896 * to any crashes involving the NIC
898 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl);
899 readl(®s->HostCtrl); /* PCI write posting */
903 * Don't access any other registers before this point!
907 * This will most likely need BYTE_SWAP once we switch
908 * to using __raw_writel()
910 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
913 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
916 readl(®s->HostCtrl); /* PCI write posting */
919 * Stop the NIC CPU and clear pending interrupts
921 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
922 readl(®s->CpuCtrl); /* PCI write posting */
923 writel(0, ®s->Mb0Lo);
925 tig_ver = readl(®s->HostCtrl) >> 28;
928 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
931 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
932 tig_ver, ap->firmware_major, ap->firmware_minor,
934 writel(0, ®s->LocalCtrl);
936 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
940 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
941 tig_ver, ap->firmware_major, ap->firmware_minor,
943 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl);
944 readl(®s->CpuBCtrl); /* PCI write posting */
946 * The SRAM bank size does _not_ indicate the amount
947 * of memory on the card, it controls the _bank_ size!
948 * Ie. a 1MB AceNIC will have two banks of 512KB.
950 writel(SRAM_BANK_512K, ®s->LocalCtrl);
951 writel(SYNC_SRAM_TIMING, ®s->MiscCfg);
953 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
956 printk(KERN_WARNING " Unsupported Tigon version detected "
963 * ModeStat _must_ be set after the SRAM settings as this change
964 * seems to corrupt the ModeStat and possible other registers.
965 * The SRAM settings survive resets and setting it to the same
966 * value a second time works as well. This is what caused the
967 * `Firmware not running' problem on the Tigon II.
970 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
971 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
973 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
974 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat);
976 readl(®s->ModeStat); /* PCI write posting */
979 for(i = 0; i < 4; i++) {
983 t = read_eeprom_byte(dev, 0x8c+i);
991 for(i = 4; i < 8; i++) {
995 t = read_eeprom_byte(dev, 0x8c+i);
1003 writel(mac1, ®s->MacAddrHi);
1004 writel(mac2, ®s->MacAddrLo);
1006 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1007 dev->dev_addr[1] = mac1 & 0xff;
1008 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1009 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1010 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1011 dev->dev_addr[5] = mac2 & 0xff;
1013 printk("MAC: %pM\n", dev->dev_addr);
1016 * Looks like this is necessary to deal with on all architectures,
1017 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1018 * Ie. having two NICs in the machine, one will have the cache
1019 * line set at boot time, the other will not.
1022 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1024 if (cache_size != SMP_CACHE_BYTES) {
1025 printk(KERN_INFO " PCI cache line size set incorrectly "
1026 "(%i bytes) by BIOS/FW, ", cache_size);
1027 if (cache_size > SMP_CACHE_BYTES)
1028 printk("expecting %i\n", SMP_CACHE_BYTES);
1030 printk("correcting to %i\n", SMP_CACHE_BYTES);
1031 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1032 SMP_CACHE_BYTES >> 2);
1036 pci_state = readl(®s->PciState);
1037 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1038 "latency: %i clks\n",
1039 (pci_state & PCI_32BIT) ? 32 : 64,
1040 (pci_state & PCI_66MHZ) ? 66 : 33,
1044 * Set the max DMA transfer size. Seems that for most systems
1045 * the performance is better when no MAX parameter is
1046 * set. However for systems enabling PCI write and invalidate,
1047 * DMA writes must be set to the L1 cache line size to get
1048 * optimal performance.
1050 * The default is now to turn the PCI write and invalidate off
1051 * - that is what Alteon does for NT.
1053 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1054 if (ap->version >= 2) {
1055 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1057 * Tuning parameters only supported for 8 cards
1059 if (board_idx == BOARD_IDX_OVERFLOW ||
1060 dis_pci_mem_inval[board_idx]) {
1061 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1062 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1063 pci_write_config_word(pdev, PCI_COMMAND,
1065 printk(KERN_INFO " Disabling PCI memory "
1066 "write and invalidate\n");
1068 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1069 printk(KERN_INFO " PCI memory write & invalidate "
1070 "enabled by BIOS, enabling counter measures\n");
1072 switch(SMP_CACHE_BYTES) {
1074 tmp |= DMA_WRITE_MAX_16;
1077 tmp |= DMA_WRITE_MAX_32;
1080 tmp |= DMA_WRITE_MAX_64;
1083 tmp |= DMA_WRITE_MAX_128;
1086 printk(KERN_INFO " Cache line size %i not "
1087 "supported, PCI write and invalidate "
1088 "disabled\n", SMP_CACHE_BYTES);
1089 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1090 pci_write_config_word(pdev, PCI_COMMAND,
1098 * On this platform, we know what the best dma settings
1099 * are. We use 64-byte maximum bursts, because if we
1100 * burst larger than the cache line size (or even cross
1101 * a 64byte boundary in a single burst) the UltraSparc
1102 * PCI controller will disconnect at 64-byte multiples.
1104 * Read-multiple will be properly enabled above, and when
1105 * set will give the PCI controller proper hints about
1108 tmp &= ~DMA_READ_WRITE_MASK;
1109 tmp |= DMA_READ_MAX_64;
1110 tmp |= DMA_WRITE_MAX_64;
1113 tmp &= ~DMA_READ_WRITE_MASK;
1114 tmp |= DMA_READ_MAX_128;
1116 * All the docs say MUST NOT. Well, I did.
1117 * Nothing terrible happens, if we load wrong size.
1118 * Bit w&i still works better!
1120 tmp |= DMA_WRITE_MAX_128;
1122 writel(tmp, ®s->PciState);
1126 * The Host PCI bus controller driver has to set FBB.
1127 * If all devices on that PCI bus support FBB, then the controller
1128 * can enable FBB support in the Host PCI Bus controller (or on
1129 * the PCI-PCI bridge if that applies).
1133 * I have received reports from people having problems when this
1136 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1137 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1138 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1139 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1144 * Configure DMA attributes.
1146 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1147 ap->pci_using_dac = 1;
1148 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1149 ap->pci_using_dac = 0;
1156 * Initialize the generic info block and the command+event rings
1157 * and the control blocks for the transmit and receive rings
1158 * as they need to be setup once and for all.
1160 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1168 * Get the memory for the skb rings.
1170 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1175 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1178 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1179 DRV_NAME, pdev->irq);
1182 dev->irq = pdev->irq;
1185 spin_lock_init(&ap->debug_lock);
1186 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1187 ap->last_std_rx = 0;
1188 ap->last_mini_rx = 0;
1191 memset(ap->info, 0, sizeof(struct ace_info));
1192 memset(ap->skb, 0, sizeof(struct ace_skb));
1194 ecode = ace_load_firmware(dev);
1200 tmp_ptr = ap->info_dma;
1201 writel(tmp_ptr >> 32, ®s->InfoPtrHi);
1202 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo);
1204 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1206 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1207 info->evt_ctrl.flags = 0;
1211 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1212 writel(0, ®s->EvtCsm);
1214 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1215 info->cmd_ctrl.flags = 0;
1216 info->cmd_ctrl.max_len = 0;
1218 for (i = 0; i < CMD_RING_ENTRIES; i++)
1219 writel(0, ®s->CmdRng[i]);
1221 writel(0, ®s->CmdPrd);
1222 writel(0, ®s->CmdCsm);
1224 tmp_ptr = ap->info_dma;
1225 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1226 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1228 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1229 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1230 info->rx_std_ctrl.flags =
1231 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1233 memset(ap->rx_std_ring, 0,
1234 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1236 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1237 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1239 ap->rx_std_skbprd = 0;
1240 atomic_set(&ap->cur_rx_bufs, 0);
1242 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1243 (ap->rx_ring_base_dma +
1244 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1245 info->rx_jumbo_ctrl.max_len = 0;
1246 info->rx_jumbo_ctrl.flags =
1247 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1249 memset(ap->rx_jumbo_ring, 0,
1250 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1252 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1253 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1255 ap->rx_jumbo_skbprd = 0;
1256 atomic_set(&ap->cur_jumbo_bufs, 0);
1258 memset(ap->rx_mini_ring, 0,
1259 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1261 if (ap->version >= 2) {
1262 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1263 (ap->rx_ring_base_dma +
1264 (sizeof(struct rx_desc) *
1265 (RX_STD_RING_ENTRIES +
1266 RX_JUMBO_RING_ENTRIES))));
1267 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1268 info->rx_mini_ctrl.flags =
1269 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1271 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1272 ap->rx_mini_ring[i].flags =
1273 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1275 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1276 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1277 info->rx_mini_ctrl.max_len = 0;
1280 ap->rx_mini_skbprd = 0;
1281 atomic_set(&ap->cur_mini_bufs, 0);
1283 set_aceaddr(&info->rx_return_ctrl.rngptr,
1284 (ap->rx_ring_base_dma +
1285 (sizeof(struct rx_desc) *
1286 (RX_STD_RING_ENTRIES +
1287 RX_JUMBO_RING_ENTRIES +
1288 RX_MINI_RING_ENTRIES))));
1289 info->rx_return_ctrl.flags = 0;
1290 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1292 memset(ap->rx_return_ring, 0,
1293 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1295 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1296 *(ap->rx_ret_prd) = 0;
1298 writel(TX_RING_BASE, ®s->WinBase);
1300 if (ACE_IS_TIGON_I(ap)) {
1301 ap->tx_ring = (__force struct tx_desc *) regs->Window;
1302 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1303 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1304 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1306 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1308 memset(ap->tx_ring, 0,
1309 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1311 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1314 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1315 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1318 * The Tigon I does not like having the TX ring in host memory ;-(
1320 if (!ACE_IS_TIGON_I(ap))
1321 tmp |= RCB_FLG_TX_HOST_RING;
1322 #if TX_COAL_INTS_ONLY
1323 tmp |= RCB_FLG_COAL_INT_ONLY;
1325 info->tx_ctrl.flags = tmp;
1327 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1330 * Potential item for tuning parameter
1333 writel(DMA_THRESH_16W, ®s->DmaReadCfg);
1334 writel(DMA_THRESH_16W, ®s->DmaWriteCfg);
1336 writel(DMA_THRESH_8W, ®s->DmaReadCfg);
1337 writel(DMA_THRESH_8W, ®s->DmaWriteCfg);
1340 writel(0, ®s->MaskInt);
1341 writel(1, ®s->IfIdx);
1344 * McKinley boxes do not like us fiddling with AssistState
1347 writel(1, ®s->AssistState);
1350 writel(DEF_STAT, ®s->TuneStatTicks);
1351 writel(DEF_TRACE, ®s->TuneTrace);
1353 ace_set_rxtx_parms(dev, 0);
1355 if (board_idx == BOARD_IDX_OVERFLOW) {
1356 printk(KERN_WARNING "%s: more than %i NICs detected, "
1357 "ignoring module parameters!\n",
1358 ap->name, ACE_MAX_MOD_PARMS);
1359 } else if (board_idx >= 0) {
1360 if (tx_coal_tick[board_idx])
1361 writel(tx_coal_tick[board_idx],
1362 ®s->TuneTxCoalTicks);
1363 if (max_tx_desc[board_idx])
1364 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc);
1366 if (rx_coal_tick[board_idx])
1367 writel(rx_coal_tick[board_idx],
1368 ®s->TuneRxCoalTicks);
1369 if (max_rx_desc[board_idx])
1370 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc);
1372 if (trace[board_idx])
1373 writel(trace[board_idx], ®s->TuneTrace);
1375 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1376 writel(tx_ratio[board_idx], ®s->TxBufRat);
1380 * Default link parameters
1382 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1383 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1384 if(ap->version >= 2)
1385 tmp |= LNK_TX_FLOW_CTL_Y;
1388 * Override link default parameters
1390 if ((board_idx >= 0) && link_state[board_idx]) {
1391 int option = link_state[board_idx];
1395 if (option & 0x01) {
1396 printk(KERN_INFO "%s: Setting half duplex link\n",
1398 tmp &= ~LNK_FULL_DUPLEX;
1401 tmp &= ~LNK_NEGOTIATE;
1408 if ((option & 0x70) == 0) {
1409 printk(KERN_WARNING "%s: No media speed specified, "
1410 "forcing auto negotiation\n", ap->name);
1411 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1412 LNK_100MB | LNK_10MB;
1414 if ((option & 0x100) == 0)
1415 tmp |= LNK_NEG_FCTL;
1417 printk(KERN_INFO "%s: Disabling flow control "
1418 "negotiation\n", ap->name);
1420 tmp |= LNK_RX_FLOW_CTL_Y;
1421 if ((option & 0x400) && (ap->version >= 2)) {
1422 printk(KERN_INFO "%s: Enabling TX flow control\n",
1424 tmp |= LNK_TX_FLOW_CTL_Y;
1429 writel(tmp, ®s->TuneLink);
1430 if (ap->version >= 2)
1431 writel(tmp, ®s->TuneFastLink);
1433 writel(ap->firmware_start, ®s->Pc);
1435 writel(0, ®s->Mb0Lo);
1438 * Set tx_csm before we start receiving interrupts, otherwise
1439 * the interrupt handler might think it is supposed to process
1440 * tx ints before we are up and running, which may cause a null
1441 * pointer access in the int handler.
1444 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1447 ace_set_txprd(regs, ap, 0);
1448 writel(0, ®s->RxRetCsm);
1451 * Enable DMA engine now.
1452 * If we do this sooner, Mckinley box pukes.
1453 * I assume it's because Tigon II DMA engine wants to check
1454 * *something* even before the CPU is started.
1456 writel(1, ®s->AssistState); /* enable DMA */
1461 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl);
1462 readl(®s->CpuCtrl);
1465 * Wait for the firmware to spin up - max 3 seconds.
1467 myjif = jiffies + 3 * HZ;
1468 while (time_before(jiffies, myjif) && !ap->fw_running)
1471 if (!ap->fw_running) {
1472 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1475 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl);
1476 readl(®s->CpuCtrl);
1478 /* aman@sgi.com - account for badly behaving firmware/NIC:
1479 * - have observed that the NIC may continue to generate
1480 * interrupts for some reason; attempt to stop it - halt
1481 * second CPU for Tigon II cards, and also clear Mb0
1482 * - if we're a module, we'll fail to load if this was
1483 * the only GbE card in the system => if the kernel does
1484 * see an interrupt from the NIC, code to handle it is
1485 * gone and OOps! - so free_irq also
1487 if (ap->version >= 2)
1488 writel(readl(®s->CpuBCtrl) | CPU_HALT,
1490 writel(0, ®s->Mb0Lo);
1491 readl(®s->Mb0Lo);
1498 * We load the ring here as there seem to be no way to tell the
1499 * firmware to wipe the ring without re-initializing it.
1501 if (!test_and_set_bit(0, &ap->std_refill_busy))
1502 ace_load_std_rx_ring(dev, RX_RING_SIZE);
1504 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1506 if (ap->version >= 2) {
1507 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1508 ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1510 printk(KERN_ERR "%s: Someone is busy refilling "
1511 "the RX mini ring\n", ap->name);
1516 ace_init_cleanup(dev);
1521 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1523 struct ace_private *ap = netdev_priv(dev);
1524 struct ace_regs __iomem *regs = ap->regs;
1525 int board_idx = ap->board_idx;
1527 if (board_idx >= 0) {
1529 if (!tx_coal_tick[board_idx])
1530 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks);
1531 if (!max_tx_desc[board_idx])
1532 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc);
1533 if (!rx_coal_tick[board_idx])
1534 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks);
1535 if (!max_rx_desc[board_idx])
1536 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc);
1537 if (!tx_ratio[board_idx])
1538 writel(DEF_TX_RATIO, ®s->TxBufRat);
1540 if (!tx_coal_tick[board_idx])
1541 writel(DEF_JUMBO_TX_COAL,
1542 ®s->TuneTxCoalTicks);
1543 if (!max_tx_desc[board_idx])
1544 writel(DEF_JUMBO_TX_MAX_DESC,
1545 ®s->TuneMaxTxDesc);
1546 if (!rx_coal_tick[board_idx])
1547 writel(DEF_JUMBO_RX_COAL,
1548 ®s->TuneRxCoalTicks);
1549 if (!max_rx_desc[board_idx])
1550 writel(DEF_JUMBO_RX_MAX_DESC,
1551 ®s->TuneMaxRxDesc);
1552 if (!tx_ratio[board_idx])
1553 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat);
1559 static void ace_watchdog(struct net_device *data)
1561 struct net_device *dev = data;
1562 struct ace_private *ap = netdev_priv(dev);
1563 struct ace_regs __iomem *regs = ap->regs;
1566 * We haven't received a stats update event for more than 2.5
1567 * seconds and there is data in the transmit queue, thus we
1568 * assume the card is stuck.
1570 if (*ap->tx_csm != ap->tx_ret_csm) {
1571 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1572 dev->name, (unsigned int)readl(®s->HostCtrl));
1573 /* This can happen due to ieee flow control. */
1575 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1578 netif_wake_queue(dev);
1584 static void ace_tasklet(unsigned long arg)
1586 struct net_device *dev = (struct net_device *) arg;
1587 struct ace_private *ap = netdev_priv(dev);
1590 cur_size = atomic_read(&ap->cur_rx_bufs);
1591 if ((cur_size < RX_LOW_STD_THRES) &&
1592 !test_and_set_bit(0, &ap->std_refill_busy)) {
1594 printk("refilling buffers (current %i)\n", cur_size);
1596 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1599 if (ap->version >= 2) {
1600 cur_size = atomic_read(&ap->cur_mini_bufs);
1601 if ((cur_size < RX_LOW_MINI_THRES) &&
1602 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1604 printk("refilling mini buffers (current %i)\n",
1607 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1611 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1612 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1613 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1615 printk("refilling jumbo buffers (current %i)\n", cur_size);
1617 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1619 ap->tasklet_pending = 0;
1624 * Copy the contents of the NIC's trace buffer to kernel memory.
1626 static void ace_dump_trace(struct ace_private *ap)
1630 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1637 * Load the standard rx ring.
1639 * Loading rings is safe without holding the spin lock since this is
1640 * done only before the device is enabled, thus no interrupts are
1641 * generated and by the interrupt handler/tasklet handler.
1643 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1645 struct ace_private *ap = netdev_priv(dev);
1646 struct ace_regs __iomem *regs = ap->regs;
1650 prefetchw(&ap->cur_rx_bufs);
1652 idx = ap->rx_std_skbprd;
1654 for (i = 0; i < nr_bufs; i++) {
1655 struct sk_buff *skb;
1659 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1663 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1664 offset_in_page(skb->data),
1666 PCI_DMA_FROMDEVICE);
1667 ap->skb->rx_std_skbuff[idx].skb = skb;
1668 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1671 rd = &ap->rx_std_ring[idx];
1672 set_aceaddr(&rd->addr, mapping);
1673 rd->size = ACE_STD_BUFSIZE;
1675 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1681 atomic_add(i, &ap->cur_rx_bufs);
1682 ap->rx_std_skbprd = idx;
1684 if (ACE_IS_TIGON_I(ap)) {
1686 cmd.evt = C_SET_RX_PRD_IDX;
1688 cmd.idx = ap->rx_std_skbprd;
1689 ace_issue_cmd(regs, &cmd);
1691 writel(idx, ®s->RxStdPrd);
1696 clear_bit(0, &ap->std_refill_busy);
1700 printk(KERN_INFO "Out of memory when allocating "
1701 "standard receive buffers\n");
1706 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1708 struct ace_private *ap = netdev_priv(dev);
1709 struct ace_regs __iomem *regs = ap->regs;
1712 prefetchw(&ap->cur_mini_bufs);
1714 idx = ap->rx_mini_skbprd;
1715 for (i = 0; i < nr_bufs; i++) {
1716 struct sk_buff *skb;
1720 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1724 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1725 offset_in_page(skb->data),
1727 PCI_DMA_FROMDEVICE);
1728 ap->skb->rx_mini_skbuff[idx].skb = skb;
1729 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1732 rd = &ap->rx_mini_ring[idx];
1733 set_aceaddr(&rd->addr, mapping);
1734 rd->size = ACE_MINI_BUFSIZE;
1736 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1742 atomic_add(i, &ap->cur_mini_bufs);
1744 ap->rx_mini_skbprd = idx;
1746 writel(idx, ®s->RxMiniPrd);
1750 clear_bit(0, &ap->mini_refill_busy);
1753 printk(KERN_INFO "Out of memory when allocating "
1754 "mini receive buffers\n");
1760 * Load the jumbo rx ring, this may happen at any time if the MTU
1761 * is changed to a value > 1500.
1763 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1765 struct ace_private *ap = netdev_priv(dev);
1766 struct ace_regs __iomem *regs = ap->regs;
1769 idx = ap->rx_jumbo_skbprd;
1771 for (i = 0; i < nr_bufs; i++) {
1772 struct sk_buff *skb;
1776 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1780 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1781 offset_in_page(skb->data),
1783 PCI_DMA_FROMDEVICE);
1784 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1785 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1788 rd = &ap->rx_jumbo_ring[idx];
1789 set_aceaddr(&rd->addr, mapping);
1790 rd->size = ACE_JUMBO_BUFSIZE;
1792 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1798 atomic_add(i, &ap->cur_jumbo_bufs);
1799 ap->rx_jumbo_skbprd = idx;
1801 if (ACE_IS_TIGON_I(ap)) {
1803 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1805 cmd.idx = ap->rx_jumbo_skbprd;
1806 ace_issue_cmd(regs, &cmd);
1808 writel(idx, ®s->RxJumboPrd);
1813 clear_bit(0, &ap->jumbo_refill_busy);
1816 if (net_ratelimit())
1817 printk(KERN_INFO "Out of memory when allocating "
1818 "jumbo receive buffers\n");
1824 * All events are considered to be slow (RX/TX ints do not generate
1825 * events) and are handled here, outside the main interrupt handler,
1826 * to reduce the size of the handler.
1828 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1830 struct ace_private *ap;
1832 ap = netdev_priv(dev);
1834 while (evtcsm != evtprd) {
1835 switch (ap->evt_ring[evtcsm].evt) {
1837 printk(KERN_INFO "%s: Firmware up and running\n",
1842 case E_STATS_UPDATED:
1846 u16 code = ap->evt_ring[evtcsm].code;
1850 u32 state = readl(&ap->regs->GigLnkState);
1851 printk(KERN_WARNING "%s: Optical link UP "
1852 "(%s Duplex, Flow Control: %s%s)\n",
1854 state & LNK_FULL_DUPLEX ? "Full":"Half",
1855 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1856 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1860 printk(KERN_WARNING "%s: Optical link DOWN\n",
1863 case E_C_LINK_10_100:
1864 printk(KERN_WARNING "%s: 10/100BaseT link "
1868 printk(KERN_ERR "%s: Unknown optical link "
1869 "state %02x\n", ap->name, code);
1874 switch(ap->evt_ring[evtcsm].code) {
1875 case E_C_ERR_INVAL_CMD:
1876 printk(KERN_ERR "%s: invalid command error\n",
1879 case E_C_ERR_UNIMP_CMD:
1880 printk(KERN_ERR "%s: unimplemented command "
1881 "error\n", ap->name);
1883 case E_C_ERR_BAD_CFG:
1884 printk(KERN_ERR "%s: bad config error\n",
1888 printk(KERN_ERR "%s: unknown error %02x\n",
1889 ap->name, ap->evt_ring[evtcsm].code);
1892 case E_RESET_JUMBO_RNG:
1895 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1896 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1897 ap->rx_jumbo_ring[i].size = 0;
1898 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1899 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1900 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1904 if (ACE_IS_TIGON_I(ap)) {
1906 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1909 ace_issue_cmd(ap->regs, &cmd);
1911 writel(0, &((ap->regs)->RxJumboPrd));
1916 ap->rx_jumbo_skbprd = 0;
1917 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1919 clear_bit(0, &ap->jumbo_refill_busy);
1923 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1924 ap->name, ap->evt_ring[evtcsm].evt);
1926 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1933 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1935 struct ace_private *ap = netdev_priv(dev);
1937 int mini_count = 0, std_count = 0;
1941 prefetchw(&ap->cur_rx_bufs);
1942 prefetchw(&ap->cur_mini_bufs);
1944 while (idx != rxretprd) {
1945 struct ring_info *rip;
1946 struct sk_buff *skb;
1947 struct rx_desc *rxdesc, *retdesc;
1949 int bd_flags, desc_type, mapsize;
1953 /* make sure the rx descriptor isn't read before rxretprd */
1954 if (idx == rxretcsm)
1957 retdesc = &ap->rx_return_ring[idx];
1958 skbidx = retdesc->idx;
1959 bd_flags = retdesc->flags;
1960 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1964 * Normal frames do not have any flags set
1966 * Mini and normal frames arrive frequently,
1967 * so use a local counter to avoid doing
1968 * atomic operations for each packet arriving.
1971 rip = &ap->skb->rx_std_skbuff[skbidx];
1972 mapsize = ACE_STD_BUFSIZE;
1973 rxdesc = &ap->rx_std_ring[skbidx];
1977 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1978 mapsize = ACE_JUMBO_BUFSIZE;
1979 rxdesc = &ap->rx_jumbo_ring[skbidx];
1980 atomic_dec(&ap->cur_jumbo_bufs);
1983 rip = &ap->skb->rx_mini_skbuff[skbidx];
1984 mapsize = ACE_MINI_BUFSIZE;
1985 rxdesc = &ap->rx_mini_ring[skbidx];
1989 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1990 "returned by NIC\n", dev->name,
1997 pci_unmap_page(ap->pdev,
1998 dma_unmap_addr(rip, mapping),
2000 PCI_DMA_FROMDEVICE);
2001 skb_put(skb, retdesc->size);
2006 csum = retdesc->tcp_udp_csum;
2008 skb->protocol = eth_type_trans(skb, dev);
2011 * Instead of forcing the poor tigon mips cpu to calculate
2012 * pseudo hdr checksum, we do this ourselves.
2014 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2015 skb->csum = htons(csum);
2016 skb->ip_summed = CHECKSUM_COMPLETE;
2018 skb_checksum_none_assert(skb);
2022 if ((bd_flags & BD_FLG_VLAN_TAG))
2023 __vlan_hwaccel_put_tag(skb, retdesc->vlan);
2026 dev->stats.rx_packets++;
2027 dev->stats.rx_bytes += retdesc->size;
2029 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2032 atomic_sub(std_count, &ap->cur_rx_bufs);
2033 if (!ACE_IS_TIGON_I(ap))
2034 atomic_sub(mini_count, &ap->cur_mini_bufs);
2038 * According to the documentation RxRetCsm is obsolete with
2039 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2041 if (ACE_IS_TIGON_I(ap)) {
2042 writel(idx, &ap->regs->RxRetCsm);
2053 static inline void ace_tx_int(struct net_device *dev,
2056 struct ace_private *ap = netdev_priv(dev);
2059 struct sk_buff *skb;
2060 struct tx_ring_info *info;
2062 info = ap->skb->tx_skbuff + idx;
2065 if (dma_unmap_len(info, maplen)) {
2066 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2067 dma_unmap_len(info, maplen),
2069 dma_unmap_len_set(info, maplen, 0);
2073 dev->stats.tx_packets++;
2074 dev->stats.tx_bytes += skb->len;
2075 dev_kfree_skb_irq(skb);
2079 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2080 } while (idx != txcsm);
2082 if (netif_queue_stopped(dev))
2083 netif_wake_queue(dev);
2086 ap->tx_ret_csm = txcsm;
2088 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2090 * We could try to make it before. In this case we would get
2091 * the following race condition: hard_start_xmit on other cpu
2092 * enters after we advanced tx_ret_csm and fills space,
2093 * which we have just freed, so that we make illegal device wakeup.
2094 * There is no good way to workaround this (at entry
2095 * to ace_start_xmit detects this condition and prevents
2096 * ring corruption, but it is not a good workaround.)
2098 * When tx_ret_csm is advanced after, we wake up device _only_
2099 * if we really have some space in ring (though the core doing
2100 * hard_start_xmit can see full ring for some period and has to
2101 * synchronize.) Superb.
2102 * BUT! We get another subtle race condition. hard_start_xmit
2103 * may think that ring is full between wakeup and advancing
2104 * tx_ret_csm and will stop device instantly! It is not so bad.
2105 * We are guaranteed that there is something in ring, so that
2106 * the next irq will resume transmission. To speedup this we could
2107 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2108 * (see ace_start_xmit).
2110 * Well, this dilemma exists in all lock-free devices.
2111 * We, following scheme used in drivers by Donald Becker,
2112 * select the least dangerous.
2118 static irqreturn_t ace_interrupt(int irq, void *dev_id)
2120 struct net_device *dev = (struct net_device *)dev_id;
2121 struct ace_private *ap = netdev_priv(dev);
2122 struct ace_regs __iomem *regs = ap->regs;
2124 u32 txcsm, rxretcsm, rxretprd;
2128 * In case of PCI shared interrupts or spurious interrupts,
2129 * we want to make sure it is actually our interrupt before
2130 * spending any time in here.
2132 if (!(readl(®s->HostCtrl) & IN_INT))
2136 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2137 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2138 * writel(0, ®s->Mb0Lo).
2140 * "IRQ avoidance" recommended in docs applies to IRQs served
2141 * threads and it is wrong even for that case.
2143 writel(0, ®s->Mb0Lo);
2144 readl(®s->Mb0Lo);
2147 * There is no conflict between transmit handling in
2148 * start_xmit and receive processing, thus there is no reason
2149 * to take a spin lock for RX handling. Wait until we start
2150 * working on the other stuff - hey we don't need a spin lock
2153 rxretprd = *ap->rx_ret_prd;
2154 rxretcsm = ap->cur_rx;
2156 if (rxretprd != rxretcsm)
2157 ace_rx_int(dev, rxretprd, rxretcsm);
2159 txcsm = *ap->tx_csm;
2160 idx = ap->tx_ret_csm;
2164 * If each skb takes only one descriptor this check degenerates
2165 * to identity, because new space has just been opened.
2166 * But if skbs are fragmented we must check that this index
2167 * update releases enough of space, otherwise we just
2168 * wait for device to make more work.
2170 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2171 ace_tx_int(dev, txcsm, idx);
2174 evtcsm = readl(®s->EvtCsm);
2175 evtprd = *ap->evt_prd;
2177 if (evtcsm != evtprd) {
2178 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2179 writel(evtcsm, ®s->EvtCsm);
2183 * This has to go last in the interrupt handler and run with
2184 * the spin lock released ... what lock?
2186 if (netif_running(dev)) {
2188 int run_tasklet = 0;
2190 cur_size = atomic_read(&ap->cur_rx_bufs);
2191 if (cur_size < RX_LOW_STD_THRES) {
2192 if ((cur_size < RX_PANIC_STD_THRES) &&
2193 !test_and_set_bit(0, &ap->std_refill_busy)) {
2195 printk("low on std buffers %i\n", cur_size);
2197 ace_load_std_rx_ring(dev,
2198 RX_RING_SIZE - cur_size);
2203 if (!ACE_IS_TIGON_I(ap)) {
2204 cur_size = atomic_read(&ap->cur_mini_bufs);
2205 if (cur_size < RX_LOW_MINI_THRES) {
2206 if ((cur_size < RX_PANIC_MINI_THRES) &&
2207 !test_and_set_bit(0,
2208 &ap->mini_refill_busy)) {
2210 printk("low on mini buffers %i\n",
2213 ace_load_mini_rx_ring(dev,
2214 RX_MINI_SIZE - cur_size);
2221 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2222 if (cur_size < RX_LOW_JUMBO_THRES) {
2223 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2224 !test_and_set_bit(0,
2225 &ap->jumbo_refill_busy)){
2227 printk("low on jumbo buffers %i\n",
2230 ace_load_jumbo_rx_ring(dev,
2231 RX_JUMBO_SIZE - cur_size);
2236 if (run_tasklet && !ap->tasklet_pending) {
2237 ap->tasklet_pending = 1;
2238 tasklet_schedule(&ap->ace_tasklet);
2245 static int ace_open(struct net_device *dev)
2247 struct ace_private *ap = netdev_priv(dev);
2248 struct ace_regs __iomem *regs = ap->regs;
2251 if (!(ap->fw_running)) {
2252 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2256 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu);
2258 cmd.evt = C_CLEAR_STATS;
2261 ace_issue_cmd(regs, &cmd);
2263 cmd.evt = C_HOST_STATE;
2264 cmd.code = C_C_STACK_UP;
2266 ace_issue_cmd(regs, &cmd);
2269 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2270 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2272 if (dev->flags & IFF_PROMISC) {
2273 cmd.evt = C_SET_PROMISC_MODE;
2274 cmd.code = C_C_PROMISC_ENABLE;
2276 ace_issue_cmd(regs, &cmd);
2284 cmd.evt = C_LNK_NEGOTIATION;
2287 ace_issue_cmd(regs, &cmd);
2290 netif_start_queue(dev);
2293 * Setup the bottom half rx ring refill handler
2295 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2300 static int ace_close(struct net_device *dev)
2302 struct ace_private *ap = netdev_priv(dev);
2303 struct ace_regs __iomem *regs = ap->regs;
2305 unsigned long flags;
2309 * Without (or before) releasing irq and stopping hardware, this
2310 * is an absolute non-sense, by the way. It will be reset instantly
2313 netif_stop_queue(dev);
2317 cmd.evt = C_SET_PROMISC_MODE;
2318 cmd.code = C_C_PROMISC_DISABLE;
2320 ace_issue_cmd(regs, &cmd);
2324 cmd.evt = C_HOST_STATE;
2325 cmd.code = C_C_STACK_DOWN;
2327 ace_issue_cmd(regs, &cmd);
2329 tasklet_kill(&ap->ace_tasklet);
2332 * Make sure one CPU is not processing packets while
2333 * buffers are being released by another.
2336 local_irq_save(flags);
2339 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2340 struct sk_buff *skb;
2341 struct tx_ring_info *info;
2343 info = ap->skb->tx_skbuff + i;
2346 if (dma_unmap_len(info, maplen)) {
2347 if (ACE_IS_TIGON_I(ap)) {
2348 /* NB: TIGON_1 is special, tx_ring is in io space */
2349 struct tx_desc __iomem *tx;
2350 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
2351 writel(0, &tx->addr.addrhi);
2352 writel(0, &tx->addr.addrlo);
2353 writel(0, &tx->flagsize);
2355 memset(ap->tx_ring + i, 0,
2356 sizeof(struct tx_desc));
2357 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2358 dma_unmap_len(info, maplen),
2360 dma_unmap_len_set(info, maplen, 0);
2369 cmd.evt = C_RESET_JUMBO_RNG;
2372 ace_issue_cmd(regs, &cmd);
2375 ace_unmask_irq(dev);
2376 local_irq_restore(flags);
2382 static inline dma_addr_t
2383 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2384 struct sk_buff *tail, u32 idx)
2387 struct tx_ring_info *info;
2389 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2390 offset_in_page(skb->data),
2391 skb->len, PCI_DMA_TODEVICE);
2393 info = ap->skb->tx_skbuff + idx;
2395 dma_unmap_addr_set(info, mapping, mapping);
2396 dma_unmap_len_set(info, maplen, skb->len);
2402 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2403 u32 flagsize, u32 vlan_tag)
2405 #if !USE_TX_COAL_NOW
2406 flagsize &= ~BD_FLG_COAL_NOW;
2409 if (ACE_IS_TIGON_I(ap)) {
2410 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
2411 writel(addr >> 32, &io->addr.addrhi);
2412 writel(addr & 0xffffffff, &io->addr.addrlo);
2413 writel(flagsize, &io->flagsize);
2414 writel(vlan_tag, &io->vlanres);
2416 desc->addr.addrhi = addr >> 32;
2417 desc->addr.addrlo = addr;
2418 desc->flagsize = flagsize;
2419 desc->vlanres = vlan_tag;
2424 static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2425 struct net_device *dev)
2427 struct ace_private *ap = netdev_priv(dev);
2428 struct ace_regs __iomem *regs = ap->regs;
2429 struct tx_desc *desc;
2431 unsigned long maxjiff = jiffies + 3*HZ;
2436 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2439 if (!skb_shinfo(skb)->nr_frags) {
2443 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2444 flagsize = (skb->len << 16) | (BD_FLG_END);
2445 if (skb->ip_summed == CHECKSUM_PARTIAL)
2446 flagsize |= BD_FLG_TCP_UDP_SUM;
2447 if (vlan_tx_tag_present(skb)) {
2448 flagsize |= BD_FLG_VLAN_TAG;
2449 vlan_tag = vlan_tx_tag_get(skb);
2451 desc = ap->tx_ring + idx;
2452 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2454 /* Look at ace_tx_int for explanations. */
2455 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2456 flagsize |= BD_FLG_COAL_NOW;
2458 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2464 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2465 flagsize = (skb_headlen(skb) << 16);
2466 if (skb->ip_summed == CHECKSUM_PARTIAL)
2467 flagsize |= BD_FLG_TCP_UDP_SUM;
2468 if (vlan_tx_tag_present(skb)) {
2469 flagsize |= BD_FLG_VLAN_TAG;
2470 vlan_tag = vlan_tx_tag_get(skb);
2473 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2475 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2477 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2478 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2479 struct tx_ring_info *info;
2481 len += skb_frag_size(frag);
2482 info = ap->skb->tx_skbuff + idx;
2483 desc = ap->tx_ring + idx;
2485 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
2486 skb_frag_size(frag),
2489 flagsize = skb_frag_size(frag) << 16;
2490 if (skb->ip_summed == CHECKSUM_PARTIAL)
2491 flagsize |= BD_FLG_TCP_UDP_SUM;
2492 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2494 if (i == skb_shinfo(skb)->nr_frags - 1) {
2495 flagsize |= BD_FLG_END;
2496 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2497 flagsize |= BD_FLG_COAL_NOW;
2500 * Only the last fragment frees
2507 dma_unmap_addr_set(info, mapping, mapping);
2508 dma_unmap_len_set(info, maplen, skb_frag_size(frag));
2509 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2515 ace_set_txprd(regs, ap, idx);
2517 if (flagsize & BD_FLG_COAL_NOW) {
2518 netif_stop_queue(dev);
2521 * A TX-descriptor producer (an IRQ) might have gotten
2522 * between, making the ring free again. Since xmit is
2523 * serialized, this is the only situation we have to
2526 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2527 netif_wake_queue(dev);
2530 return NETDEV_TX_OK;
2534 * This race condition is unavoidable with lock-free drivers.
2535 * We wake up the queue _before_ tx_prd is advanced, so that we can
2536 * enter hard_start_xmit too early, while tx ring still looks closed.
2537 * This happens ~1-4 times per 100000 packets, so that we can allow
2538 * to loop syncing to other CPU. Probably, we need an additional
2539 * wmb() in ace_tx_intr as well.
2541 * Note that this race is relieved by reserving one more entry
2542 * in tx ring than it is necessary (see original non-SG driver).
2543 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2544 * is already overkill.
2546 * Alternative is to return with 1 not throttling queue. In this
2547 * case loop becomes longer, no more useful effects.
2549 if (time_before(jiffies, maxjiff)) {
2555 /* The ring is stuck full. */
2556 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2557 return NETDEV_TX_BUSY;
2561 static int ace_change_mtu(struct net_device *dev, int new_mtu)
2563 struct ace_private *ap = netdev_priv(dev);
2564 struct ace_regs __iomem *regs = ap->regs;
2566 if (new_mtu > ACE_JUMBO_MTU)
2569 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu);
2572 if (new_mtu > ACE_STD_MTU) {
2574 printk(KERN_INFO "%s: Enabling Jumbo frame "
2575 "support\n", dev->name);
2577 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2578 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2579 ace_set_rxtx_parms(dev, 1);
2582 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2583 ace_sync_irq(dev->irq);
2584 ace_set_rxtx_parms(dev, 0);
2588 cmd.evt = C_RESET_JUMBO_RNG;
2591 ace_issue_cmd(regs, &cmd);
2598 static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2600 struct ace_private *ap = netdev_priv(dev);
2601 struct ace_regs __iomem *regs = ap->regs;
2604 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2606 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2607 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2608 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2609 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2611 ecmd->port = PORT_FIBRE;
2612 ecmd->transceiver = XCVR_INTERNAL;
2614 link = readl(®s->GigLnkState);
2615 if (link & LNK_1000MB)
2616 ethtool_cmd_speed_set(ecmd, SPEED_1000);
2618 link = readl(®s->FastLnkState);
2619 if (link & LNK_100MB)
2620 ethtool_cmd_speed_set(ecmd, SPEED_100);
2621 else if (link & LNK_10MB)
2622 ethtool_cmd_speed_set(ecmd, SPEED_10);
2624 ethtool_cmd_speed_set(ecmd, 0);
2626 if (link & LNK_FULL_DUPLEX)
2627 ecmd->duplex = DUPLEX_FULL;
2629 ecmd->duplex = DUPLEX_HALF;
2631 if (link & LNK_NEGOTIATE)
2632 ecmd->autoneg = AUTONEG_ENABLE;
2634 ecmd->autoneg = AUTONEG_DISABLE;
2638 * Current struct ethtool_cmd is insufficient
2640 ecmd->trace = readl(®s->TuneTrace);
2642 ecmd->txcoal = readl(®s->TuneTxCoalTicks);
2643 ecmd->rxcoal = readl(®s->TuneRxCoalTicks);
2645 ecmd->maxtxpkt = readl(®s->TuneMaxTxDesc);
2646 ecmd->maxrxpkt = readl(®s->TuneMaxRxDesc);
2651 static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2653 struct ace_private *ap = netdev_priv(dev);
2654 struct ace_regs __iomem *regs = ap->regs;
2657 link = readl(®s->GigLnkState);
2658 if (link & LNK_1000MB)
2661 link = readl(®s->FastLnkState);
2662 if (link & LNK_100MB)
2664 else if (link & LNK_10MB)
2670 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2671 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2672 if (!ACE_IS_TIGON_I(ap))
2673 link |= LNK_TX_FLOW_CTL_Y;
2674 if (ecmd->autoneg == AUTONEG_ENABLE)
2675 link |= LNK_NEGOTIATE;
2676 if (ethtool_cmd_speed(ecmd) != speed) {
2677 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2678 switch (ethtool_cmd_speed(ecmd)) {
2691 if (ecmd->duplex == DUPLEX_FULL)
2692 link |= LNK_FULL_DUPLEX;
2694 if (link != ap->link) {
2696 printk(KERN_INFO "%s: Renegotiating link state\n",
2700 writel(link, ®s->TuneLink);
2701 if (!ACE_IS_TIGON_I(ap))
2702 writel(link, ®s->TuneFastLink);
2705 cmd.evt = C_LNK_NEGOTIATION;
2708 ace_issue_cmd(regs, &cmd);
2713 static void ace_get_drvinfo(struct net_device *dev,
2714 struct ethtool_drvinfo *info)
2716 struct ace_private *ap = netdev_priv(dev);
2718 strlcpy(info->driver, "acenic", sizeof(info->driver));
2719 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2720 ap->firmware_major, ap->firmware_minor,
2724 strlcpy(info->bus_info, pci_name(ap->pdev),
2725 sizeof(info->bus_info));
2730 * Set the hardware MAC address.
2732 static int ace_set_mac_addr(struct net_device *dev, void *p)
2734 struct ace_private *ap = netdev_priv(dev);
2735 struct ace_regs __iomem *regs = ap->regs;
2736 struct sockaddr *addr=p;
2740 if(netif_running(dev))
2743 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2745 da = (u8 *)dev->dev_addr;
2747 writel(da[0] << 8 | da[1], ®s->MacAddrHi);
2748 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2751 cmd.evt = C_SET_MAC_ADDR;
2754 ace_issue_cmd(regs, &cmd);
2760 static void ace_set_multicast_list(struct net_device *dev)
2762 struct ace_private *ap = netdev_priv(dev);
2763 struct ace_regs __iomem *regs = ap->regs;
2766 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2767 cmd.evt = C_SET_MULTICAST_MODE;
2768 cmd.code = C_C_MCAST_ENABLE;
2770 ace_issue_cmd(regs, &cmd);
2772 } else if (ap->mcast_all) {
2773 cmd.evt = C_SET_MULTICAST_MODE;
2774 cmd.code = C_C_MCAST_DISABLE;
2776 ace_issue_cmd(regs, &cmd);
2780 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2781 cmd.evt = C_SET_PROMISC_MODE;
2782 cmd.code = C_C_PROMISC_ENABLE;
2784 ace_issue_cmd(regs, &cmd);
2786 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2787 cmd.evt = C_SET_PROMISC_MODE;
2788 cmd.code = C_C_PROMISC_DISABLE;
2790 ace_issue_cmd(regs, &cmd);
2795 * For the time being multicast relies on the upper layers
2796 * filtering it properly. The Firmware does not allow one to
2797 * set the entire multicast list at a time and keeping track of
2798 * it here is going to be messy.
2800 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
2801 cmd.evt = C_SET_MULTICAST_MODE;
2802 cmd.code = C_C_MCAST_ENABLE;
2804 ace_issue_cmd(regs, &cmd);
2805 }else if (!ap->mcast_all) {
2806 cmd.evt = C_SET_MULTICAST_MODE;
2807 cmd.code = C_C_MCAST_DISABLE;
2809 ace_issue_cmd(regs, &cmd);
2814 static struct net_device_stats *ace_get_stats(struct net_device *dev)
2816 struct ace_private *ap = netdev_priv(dev);
2817 struct ace_mac_stats __iomem *mac_stats =
2818 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2820 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2821 dev->stats.multicast = readl(&mac_stats->kept_mc);
2822 dev->stats.collisions = readl(&mac_stats->coll);
2828 static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2831 void __iomem *tdest;
2838 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2839 min_t(u32, size, ACE_WINDOW_SIZE));
2840 tdest = (void __iomem *) ®s->Window +
2841 (dest & (ACE_WINDOW_SIZE - 1));
2842 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
2843 for (i = 0; i < (tsize / 4); i++) {
2844 /* Firmware is big-endian */
2845 writel(be32_to_cpup(src), tdest);
2855 static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2857 void __iomem *tdest;
2864 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2865 min_t(u32, size, ACE_WINDOW_SIZE));
2866 tdest = (void __iomem *) ®s->Window +
2867 (dest & (ACE_WINDOW_SIZE - 1));
2868 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase);
2870 for (i = 0; i < (tsize / 4); i++) {
2871 writel(0, tdest + i*4);
2881 * Download the firmware into the SRAM on the NIC
2883 * This operation requires the NIC to be halted and is performed with
2884 * interrupts disabled and with the spinlock hold.
2886 static int __devinit ace_load_firmware(struct net_device *dev)
2888 const struct firmware *fw;
2889 const char *fw_name = "acenic/tg2.bin";
2890 struct ace_private *ap = netdev_priv(dev);
2891 struct ace_regs __iomem *regs = ap->regs;
2892 const __be32 *fw_data;
2896 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) {
2897 printk(KERN_ERR "%s: trying to download firmware while the "
2898 "CPU is running!\n", ap->name);
2902 if (ACE_IS_TIGON_I(ap))
2903 fw_name = "acenic/tg1.bin";
2905 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2907 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2912 fw_data = (void *)fw->data;
2914 /* Firmware blob starts with version numbers, followed by
2915 load and start address. Remainder is the blob to be loaded
2916 contiguously from load address. We don't bother to represent
2917 the BSS/SBSS sections any more, since we were clearing the
2918 whole thing anyway. */
2919 ap->firmware_major = fw->data[0];
2920 ap->firmware_minor = fw->data[1];
2921 ap->firmware_fix = fw->data[2];
2923 ap->firmware_start = be32_to_cpu(fw_data[1]);
2924 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2925 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2926 ap->name, ap->firmware_start, fw_name);
2931 load_addr = be32_to_cpu(fw_data[2]);
2932 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2933 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2934 ap->name, load_addr, fw_name);
2940 * Do not try to clear more than 512KiB or we end up seeing
2941 * funny things on NICs with only 512KiB SRAM
2943 ace_clear(regs, 0x2000, 0x80000-0x2000);
2944 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2946 release_firmware(fw);
2952 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2954 * Accessing the EEPROM is `interesting' to say the least - don't read
2955 * this code right after dinner.
2957 * This is all about black magic and bit-banging the device .... I
2958 * wonder in what hospital they have put the guy who designed the i2c
2961 * Oh yes, this is only the beginning!
2963 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2964 * code i2c readout code by beta testing all my hacks.
2966 static void __devinit eeprom_start(struct ace_regs __iomem *regs)
2970 readl(®s->LocalCtrl);
2971 udelay(ACE_SHORT_DELAY);
2972 local = readl(®s->LocalCtrl);
2973 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2974 writel(local, ®s->LocalCtrl);
2975 readl(®s->LocalCtrl);
2977 udelay(ACE_SHORT_DELAY);
2978 local |= EEPROM_CLK_OUT;
2979 writel(local, ®s->LocalCtrl);
2980 readl(®s->LocalCtrl);
2982 udelay(ACE_SHORT_DELAY);
2983 local &= ~EEPROM_DATA_OUT;
2984 writel(local, ®s->LocalCtrl);
2985 readl(®s->LocalCtrl);
2987 udelay(ACE_SHORT_DELAY);
2988 local &= ~EEPROM_CLK_OUT;
2989 writel(local, ®s->LocalCtrl);
2990 readl(®s->LocalCtrl);
2995 static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3000 udelay(ACE_SHORT_DELAY);
3001 local = readl(®s->LocalCtrl);
3002 local &= ~EEPROM_DATA_OUT;
3003 local |= EEPROM_WRITE_ENABLE;
3004 writel(local, ®s->LocalCtrl);
3005 readl(®s->LocalCtrl);
3008 for (i = 0; i < 8; i++, magic <<= 1) {
3009 udelay(ACE_SHORT_DELAY);
3011 local |= EEPROM_DATA_OUT;
3013 local &= ~EEPROM_DATA_OUT;
3014 writel(local, ®s->LocalCtrl);
3015 readl(®s->LocalCtrl);
3018 udelay(ACE_SHORT_DELAY);
3019 local |= EEPROM_CLK_OUT;
3020 writel(local, ®s->LocalCtrl);
3021 readl(®s->LocalCtrl);
3023 udelay(ACE_SHORT_DELAY);
3024 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3025 writel(local, ®s->LocalCtrl);
3026 readl(®s->LocalCtrl);
3032 static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3037 local = readl(®s->LocalCtrl);
3038 local &= ~EEPROM_WRITE_ENABLE;
3039 writel(local, ®s->LocalCtrl);
3040 readl(®s->LocalCtrl);
3042 udelay(ACE_LONG_DELAY);
3043 local |= EEPROM_CLK_OUT;
3044 writel(local, ®s->LocalCtrl);
3045 readl(®s->LocalCtrl);
3047 udelay(ACE_SHORT_DELAY);
3048 /* sample data in middle of high clk */
3049 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0;
3050 udelay(ACE_SHORT_DELAY);
3052 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3053 readl(®s->LocalCtrl);
3060 static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3064 udelay(ACE_SHORT_DELAY);
3065 local = readl(®s->LocalCtrl);
3066 local |= EEPROM_WRITE_ENABLE;
3067 writel(local, ®s->LocalCtrl);
3068 readl(®s->LocalCtrl);
3070 udelay(ACE_SHORT_DELAY);
3071 local &= ~EEPROM_DATA_OUT;
3072 writel(local, ®s->LocalCtrl);
3073 readl(®s->LocalCtrl);
3075 udelay(ACE_SHORT_DELAY);
3076 local |= EEPROM_CLK_OUT;
3077 writel(local, ®s->LocalCtrl);
3078 readl(®s->LocalCtrl);
3080 udelay(ACE_SHORT_DELAY);
3081 local |= EEPROM_DATA_OUT;
3082 writel(local, ®s->LocalCtrl);
3083 readl(®s->LocalCtrl);
3085 udelay(ACE_LONG_DELAY);
3086 local &= ~EEPROM_CLK_OUT;
3087 writel(local, ®s->LocalCtrl);
3093 * Read a whole byte from the EEPROM.
3095 static int __devinit read_eeprom_byte(struct net_device *dev,
3096 unsigned long offset)
3098 struct ace_private *ap = netdev_priv(dev);
3099 struct ace_regs __iomem *regs = ap->regs;
3100 unsigned long flags;
3106 * Don't take interrupts on this CPU will bit banging
3107 * the %#%#@$ I2C device
3109 local_irq_save(flags);
3113 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3114 if (eeprom_check_ack(regs)) {
3115 local_irq_restore(flags);
3116 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3118 goto eeprom_read_error;
3121 eeprom_prep(regs, (offset >> 8) & 0xff);
3122 if (eeprom_check_ack(regs)) {
3123 local_irq_restore(flags);
3124 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3127 goto eeprom_read_error;
3130 eeprom_prep(regs, offset & 0xff);
3131 if (eeprom_check_ack(regs)) {
3132 local_irq_restore(flags);
3133 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3136 goto eeprom_read_error;
3140 eeprom_prep(regs, EEPROM_READ_SELECT);
3141 if (eeprom_check_ack(regs)) {
3142 local_irq_restore(flags);
3143 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3146 goto eeprom_read_error;
3149 for (i = 0; i < 8; i++) {
3150 local = readl(®s->LocalCtrl);
3151 local &= ~EEPROM_WRITE_ENABLE;
3152 writel(local, ®s->LocalCtrl);
3153 readl(®s->LocalCtrl);
3154 udelay(ACE_LONG_DELAY);
3156 local |= EEPROM_CLK_OUT;
3157 writel(local, ®s->LocalCtrl);
3158 readl(®s->LocalCtrl);
3160 udelay(ACE_SHORT_DELAY);
3161 /* sample data mid high clk */
3162 result = (result << 1) |
3163 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0);
3164 udelay(ACE_SHORT_DELAY);
3166 local = readl(®s->LocalCtrl);
3167 local &= ~EEPROM_CLK_OUT;
3168 writel(local, ®s->LocalCtrl);
3169 readl(®s->LocalCtrl);
3170 udelay(ACE_SHORT_DELAY);
3173 local |= EEPROM_WRITE_ENABLE;
3174 writel(local, ®s->LocalCtrl);
3175 readl(®s->LocalCtrl);
3177 udelay(ACE_SHORT_DELAY);
3181 local |= EEPROM_DATA_OUT;
3182 writel(local, ®s->LocalCtrl);
3183 readl(®s->LocalCtrl);
3185 udelay(ACE_SHORT_DELAY);
3186 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl);
3187 readl(®s->LocalCtrl);
3188 udelay(ACE_LONG_DELAY);
3189 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl);
3190 readl(®s->LocalCtrl);
3192 udelay(ACE_SHORT_DELAY);
3195 local_irq_restore(flags);
3200 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",