1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
275 static struct vortex_chip_info {
280 } vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
374 {NULL,}, /* NULL terminated list. */
378 static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
426 {0,} /* 0 terminated list. */
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
439 #define EL3_STATUS 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459 /* The SetRxFilter command accepts the following classes: */
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463 /* Bits in the general status register. */
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490 /* EEPROM locations. */
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
497 enum Window2 { /* Window 2. */
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
532 /* Boomerang bus master control registers. */
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
558 #define DO_ZEROCOPY 1
560 #define DO_ZEROCOPY 0
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
570 } frag[1+MAX_SKB_FRAGS];
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1, /* accept large frames */
637 handling_irq:1; /* private in_irq indicator */
638 /* {get|set}_wol operations are already serialized by rtnl.
639 * no additional locking is required for the enable_wol and acpi_set_WOL()
644 u16 available_media; /* From Wn3_Options. */
645 u16 capabilities, info1, info2; /* Various, from EEPROM. */
646 u16 advertising; /* NWay media advertisement */
647 unsigned char phys[2]; /* MII device addresses. */
648 u16 deferred; /* Resend these interrupts when we
649 * bale from the ISR */
650 u16 io_size; /* Size of PCI region (for release_region) */
652 /* Serialises access to hardware other than MII and variables below.
653 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
656 spinlock_t mii_lock; /* Serialises access to MII */
657 struct mii_if_info mii; /* MII lib hooks/info */
658 spinlock_t window_lock; /* Serialises access to windowed regs */
659 int window; /* Register window */
662 static void window_set(struct vortex_private *vp, int window)
664 if (window != vp->window) {
665 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
670 #define DEFINE_WINDOW_IO(size) \
672 window_read ## size(struct vortex_private *vp, int window, int addr) \
674 unsigned long flags; \
676 spin_lock_irqsave(&vp->window_lock, flags); \
677 window_set(vp, window); \
678 ret = ioread ## size(vp->ioaddr + addr); \
679 spin_unlock_irqrestore(&vp->window_lock, flags); \
683 window_write ## size(struct vortex_private *vp, u ## size value, \
684 int window, int addr) \
686 unsigned long flags; \
687 spin_lock_irqsave(&vp->window_lock, flags); \
688 window_set(vp, window); \
689 iowrite ## size(value, vp->ioaddr + addr); \
690 spin_unlock_irqrestore(&vp->window_lock, flags); \
697 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
699 #define DEVICE_PCI(dev) NULL
702 #define VORTEX_PCI(vp) \
703 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
706 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
708 #define DEVICE_EISA(dev) NULL
711 #define VORTEX_EISA(vp) \
712 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
714 /* The action to take with a media selection timer tick.
715 Note that we deviate from the 3Com order by checking 10base2 before AUI.
718 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
719 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
722 static const struct media_table {
724 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
725 mask:8, /* The transceiver-present bit in Wn3_Config.*/
726 next:8; /* The media type to try next. */
727 int wait; /* Time before we check media status. */
729 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
730 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
731 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
732 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
733 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
734 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
735 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
736 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
737 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
738 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
739 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
743 const char str[ETH_GSTRING_LEN];
744 } ethtool_stats_keys[] = {
746 { "tx_max_collisions" },
747 { "tx_multiple_collisions" },
748 { "tx_single_collisions" },
752 /* number of ETHTOOL_GSTATS u64's */
753 #define VORTEX_NUM_STATS 5
755 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
756 int chip_idx, int card_idx);
757 static int vortex_up(struct net_device *dev);
758 static void vortex_down(struct net_device *dev, int final);
759 static int vortex_open(struct net_device *dev);
760 static void mdio_sync(struct vortex_private *vp, int bits);
761 static int mdio_read(struct net_device *dev, int phy_id, int location);
762 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
763 static void vortex_timer(unsigned long arg);
764 static void rx_oom_timer(unsigned long arg);
765 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
766 struct net_device *dev);
767 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
768 struct net_device *dev);
769 static int vortex_rx(struct net_device *dev);
770 static int boomerang_rx(struct net_device *dev);
771 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
772 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
773 static int vortex_close(struct net_device *dev);
774 static void dump_tx_ring(struct net_device *dev);
775 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
776 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
777 static void set_rx_mode(struct net_device *dev);
779 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
781 static void vortex_tx_timeout(struct net_device *dev);
782 static void acpi_set_WOL(struct net_device *dev);
783 static const struct ethtool_ops vortex_ethtool_ops;
784 static void set_8021q_mode(struct net_device *dev, int enable);
786 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
787 /* Option count limit only -- unlimited interfaces are supported. */
789 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
790 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
795 static int global_options = -1;
796 static int global_full_duplex = -1;
797 static int global_enable_wol = -1;
798 static int global_use_mmio = -1;
800 /* Variables to work-around the Compaq PCI BIOS32 problem. */
801 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
802 static struct net_device *compaq_net_device;
804 static int vortex_cards_found;
806 module_param(debug, int, 0);
807 module_param(global_options, int, 0);
808 module_param_array(options, int, NULL, 0);
809 module_param(global_full_duplex, int, 0);
810 module_param_array(full_duplex, int, NULL, 0);
811 module_param_array(hw_checksums, int, NULL, 0);
812 module_param_array(flow_ctrl, int, NULL, 0);
813 module_param(global_enable_wol, int, 0);
814 module_param_array(enable_wol, int, NULL, 0);
815 module_param(rx_copybreak, int, 0);
816 module_param(max_interrupt_work, int, 0);
817 module_param(compaq_ioaddr, int, 0);
818 module_param(compaq_irq, int, 0);
819 module_param(compaq_device_id, int, 0);
820 module_param(watchdog, int, 0);
821 module_param(global_use_mmio, int, 0);
822 module_param_array(use_mmio, int, NULL, 0);
823 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
824 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
825 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
826 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
827 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
828 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
829 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
830 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
831 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
832 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
833 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
834 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
835 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
836 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
837 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
838 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
839 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
841 #ifdef CONFIG_NET_POLL_CONTROLLER
842 static void poll_vortex(struct net_device *dev)
844 struct vortex_private *vp = netdev_priv(dev);
846 local_irq_save(flags);
847 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
848 local_irq_restore(flags);
854 static int vortex_suspend(struct device *dev)
856 struct pci_dev *pdev = to_pci_dev(dev);
857 struct net_device *ndev = pci_get_drvdata(pdev);
859 if (!ndev || !netif_running(ndev))
862 netif_device_detach(ndev);
863 vortex_down(ndev, 1);
868 static int vortex_resume(struct device *dev)
870 struct pci_dev *pdev = to_pci_dev(dev);
871 struct net_device *ndev = pci_get_drvdata(pdev);
874 if (!ndev || !netif_running(ndev))
877 err = vortex_up(ndev);
881 netif_device_attach(ndev);
886 static const struct dev_pm_ops vortex_pm_ops = {
887 .suspend = vortex_suspend,
888 .resume = vortex_resume,
889 .freeze = vortex_suspend,
890 .thaw = vortex_resume,
891 .poweroff = vortex_suspend,
892 .restore = vortex_resume,
895 #define VORTEX_PM_OPS (&vortex_pm_ops)
897 #else /* !CONFIG_PM */
899 #define VORTEX_PM_OPS NULL
901 #endif /* !CONFIG_PM */
904 static struct eisa_device_id vortex_eisa_ids[] = {
905 { "TCM5920", CH_3C592 },
906 { "TCM5970", CH_3C597 },
909 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
911 static int __init vortex_eisa_probe(struct device *device)
913 void __iomem *ioaddr;
914 struct eisa_device *edev;
916 edev = to_eisa_device(device);
918 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
921 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
923 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
924 edev->id.driver_data, vortex_cards_found)) {
925 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
929 vortex_cards_found++;
934 static int vortex_eisa_remove(struct device *device)
936 struct eisa_device *edev;
937 struct net_device *dev;
938 struct vortex_private *vp;
939 void __iomem *ioaddr;
941 edev = to_eisa_device(device);
942 dev = eisa_get_drvdata(edev);
945 pr_err("vortex_eisa_remove called for Compaq device!\n");
949 vp = netdev_priv(dev);
952 unregister_netdev(dev);
953 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
954 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
960 static struct eisa_driver vortex_eisa_driver = {
961 .id_table = vortex_eisa_ids,
964 .probe = vortex_eisa_probe,
965 .remove = vortex_eisa_remove
969 #endif /* CONFIG_EISA */
971 /* returns count found (>= 0), or negative on error */
972 static int __init vortex_eisa_init(void)
975 int orig_cards_found = vortex_cards_found;
980 err = eisa_driver_register (&vortex_eisa_driver);
983 * Because of the way EISA bus is probed, we cannot assume
984 * any device have been found when we exit from
985 * eisa_driver_register (the bus root driver may not be
986 * initialized yet). So we blindly assume something was
987 * found, and let the sysfs magic happened...
993 /* Special code to work-around the Compaq PCI BIOS32 problem. */
995 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
996 compaq_irq, compaq_device_id, vortex_cards_found++);
999 return vortex_cards_found - orig_cards_found + eisa_found;
1002 /* returns count (>= 0), or negative on error */
1003 static int vortex_init_one(struct pci_dev *pdev,
1004 const struct pci_device_id *ent)
1006 int rc, unit, pci_bar;
1007 struct vortex_chip_info *vci;
1008 void __iomem *ioaddr;
1010 /* wake up and enable device */
1011 rc = pci_enable_device(pdev);
1015 unit = vortex_cards_found;
1017 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1018 /* Determine the default if the user didn't override us */
1019 vci = &vortex_info_tbl[ent->driver_data];
1020 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1021 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1022 pci_bar = use_mmio[unit] ? 1 : 0;
1024 pci_bar = global_use_mmio ? 1 : 0;
1026 ioaddr = pci_iomap(pdev, pci_bar, 0);
1027 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1028 ioaddr = pci_iomap(pdev, 0, 0);
1030 pci_disable_device(pdev);
1035 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1036 ent->driver_data, unit);
1038 pci_iounmap(pdev, ioaddr);
1039 pci_disable_device(pdev);
1043 vortex_cards_found++;
1049 static const struct net_device_ops boomrang_netdev_ops = {
1050 .ndo_open = vortex_open,
1051 .ndo_stop = vortex_close,
1052 .ndo_start_xmit = boomerang_start_xmit,
1053 .ndo_tx_timeout = vortex_tx_timeout,
1054 .ndo_get_stats = vortex_get_stats,
1056 .ndo_do_ioctl = vortex_ioctl,
1058 .ndo_set_rx_mode = set_rx_mode,
1059 .ndo_change_mtu = eth_change_mtu,
1060 .ndo_set_mac_address = eth_mac_addr,
1061 .ndo_validate_addr = eth_validate_addr,
1062 #ifdef CONFIG_NET_POLL_CONTROLLER
1063 .ndo_poll_controller = poll_vortex,
1067 static const struct net_device_ops vortex_netdev_ops = {
1068 .ndo_open = vortex_open,
1069 .ndo_stop = vortex_close,
1070 .ndo_start_xmit = vortex_start_xmit,
1071 .ndo_tx_timeout = vortex_tx_timeout,
1072 .ndo_get_stats = vortex_get_stats,
1074 .ndo_do_ioctl = vortex_ioctl,
1076 .ndo_set_rx_mode = set_rx_mode,
1077 .ndo_change_mtu = eth_change_mtu,
1078 .ndo_set_mac_address = eth_mac_addr,
1079 .ndo_validate_addr = eth_validate_addr,
1080 #ifdef CONFIG_NET_POLL_CONTROLLER
1081 .ndo_poll_controller = poll_vortex,
1086 * Start up the PCI/EISA device which is described by *gendev.
1087 * Return 0 on success.
1089 * NOTE: pdev can be NULL, for the case of a Compaq device
1091 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1092 int chip_idx, int card_idx)
1094 struct vortex_private *vp;
1096 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1098 struct net_device *dev;
1099 static int printed_version;
1100 int retval, print_info;
1101 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1102 const char *print_name = "3c59x";
1103 struct pci_dev *pdev = NULL;
1104 struct eisa_device *edev = NULL;
1106 if (!printed_version) {
1107 pr_info("%s", version);
1108 printed_version = 1;
1112 if ((pdev = DEVICE_PCI(gendev))) {
1113 print_name = pci_name(pdev);
1116 if ((edev = DEVICE_EISA(gendev))) {
1117 print_name = dev_name(&edev->dev);
1121 dev = alloc_etherdev(sizeof(*vp));
1126 SET_NETDEV_DEV(dev, gendev);
1127 vp = netdev_priv(dev);
1129 option = global_options;
1131 /* The lower four bits are the media type. */
1132 if (dev->mem_start) {
1134 * The 'options' param is passed in as the third arg to the
1135 * LILO 'ether=' argument for non-modular use
1137 option = dev->mem_start;
1139 else if (card_idx < MAX_UNITS) {
1140 if (options[card_idx] >= 0)
1141 option = options[card_idx];
1145 if (option & 0x8000)
1147 if (option & 0x4000)
1149 if (option & 0x0400)
1153 print_info = (vortex_debug > 1);
1155 pr_info("See Documentation/networking/vortex.txt\n");
1157 pr_info("%s: 3Com %s %s at %p.\n",
1159 pdev ? "PCI" : "EISA",
1163 dev->base_addr = (unsigned long)ioaddr;
1166 vp->ioaddr = ioaddr;
1167 vp->large_frames = mtu > 1500;
1168 vp->drv_flags = vci->drv_flags;
1169 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1170 vp->io_size = vci->io_size;
1171 vp->card_idx = card_idx;
1174 /* module list only for Compaq device */
1175 if (gendev == NULL) {
1176 compaq_net_device = dev;
1179 /* PCI-only startup logic */
1181 /* EISA resources already marked, so only PCI needs to do this here */
1182 /* Ignore return value, because Cardbus drivers already allocate for us */
1183 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1184 vp->must_free_region = 1;
1186 /* enable bus-mastering if necessary */
1187 if (vci->flags & PCI_USES_MASTER)
1188 pci_set_master(pdev);
1190 if (vci->drv_flags & IS_VORTEX) {
1192 u8 new_latency = 248;
1194 /* Check the PCI latency value. On the 3c590 series the latency timer
1195 must be set to the maximum value to avoid data corruption that occurs
1196 when the timer expires during a transfer. This bug exists the Vortex
1198 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1199 if (pci_latency < new_latency) {
1200 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1201 print_name, pci_latency, new_latency);
1202 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1207 spin_lock_init(&vp->lock);
1208 spin_lock_init(&vp->mii_lock);
1209 spin_lock_init(&vp->window_lock);
1210 vp->gendev = gendev;
1212 vp->mii.mdio_read = mdio_read;
1213 vp->mii.mdio_write = mdio_write;
1214 vp->mii.phy_id_mask = 0x1f;
1215 vp->mii.reg_num_mask = 0x1f;
1217 /* Makes sure rings are at least 16 byte aligned. */
1218 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1219 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1225 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1226 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1228 /* if we are a PCI driver, we store info in pdev->driver_data
1229 * instead of a module list */
1231 pci_set_drvdata(pdev, dev);
1233 eisa_set_drvdata(edev, dev);
1235 vp->media_override = 7;
1237 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1238 if (vp->media_override != 7)
1240 vp->full_duplex = (option & 0x200) ? 1 : 0;
1241 vp->bus_master = (option & 16) ? 1 : 0;
1244 if (global_full_duplex > 0)
1245 vp->full_duplex = 1;
1246 if (global_enable_wol > 0)
1249 if (card_idx < MAX_UNITS) {
1250 if (full_duplex[card_idx] > 0)
1251 vp->full_duplex = 1;
1252 if (flow_ctrl[card_idx] > 0)
1254 if (enable_wol[card_idx] > 0)
1258 vp->mii.force_media = vp->full_duplex;
1259 vp->options = option;
1260 /* Read the station address from the EEPROM. */
1264 if (vci->drv_flags & EEPROM_8BIT)
1266 else if (vci->drv_flags & EEPROM_OFFSET)
1267 base = EEPROM_Read + 0x30;
1271 for (i = 0; i < 0x40; i++) {
1273 window_write16(vp, base + i, 0, Wn0EepromCmd);
1274 /* Pause for at least 162 us. for the read to take place. */
1275 for (timer = 10; timer >= 0; timer--) {
1277 if ((window_read16(vp, 0, Wn0EepromCmd) &
1281 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1284 for (i = 0; i < 0x18; i++)
1285 checksum ^= eeprom[i];
1286 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1287 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1289 checksum ^= eeprom[i++];
1290 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1292 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1293 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1294 for (i = 0; i < 3; i++)
1295 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1296 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1336 (unsigned long long)pci_resource_start(pdev, 2),
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1343 if (vp->drv_flags & INVERT_MII_PWR)
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1359 pr_info("Full duplex capable\n");
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1383 vp->autoselect = AUTOSELECT(config);
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1392 dev->if_port = vp->default_media;
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1426 mii_preamble_required--;
1428 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1438 vp->mii.phy_id = vp->phys[0];
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1461 dev->netdev_ops = &vortex_netdev_ops;
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1474 vp->pm_state_valid = 1;
1475 pci_save_state(VORTEX_PCI(vp));
1478 retval = register_netdev(dev);
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1489 if (vp->must_free_region)
1490 release_region(dev->base_addr, vci->io_size);
1492 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1498 issue_and_wait(struct net_device *dev, int cmd)
1500 struct vortex_private *vp = netdev_priv(dev);
1501 void __iomem *ioaddr = vp->ioaddr;
1504 iowrite16(cmd, ioaddr + EL3_CMD);
1505 for (i = 0; i < 2000; i++) {
1506 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1510 /* OK, that didn't work. Do it the slow way. One second */
1511 for (i = 0; i < 100000; i++) {
1512 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1513 if (vortex_debug > 1)
1514 pr_info("%s: command 0x%04x took %d usecs\n",
1515 dev->name, cmd, i * 10);
1520 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1521 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1525 vortex_set_duplex(struct net_device *dev)
1527 struct vortex_private *vp = netdev_priv(dev);
1529 pr_info("%s: setting %s-duplex.\n",
1530 dev->name, (vp->full_duplex) ? "full" : "half");
1532 /* Set the full-duplex bit. */
1534 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1535 (vp->large_frames ? 0x40 : 0) |
1536 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1541 static void vortex_check_media(struct net_device *dev, unsigned int init)
1543 struct vortex_private *vp = netdev_priv(dev);
1544 unsigned int ok_to_print = 0;
1546 if (vortex_debug > 3)
1549 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1550 vp->full_duplex = vp->mii.full_duplex;
1551 vortex_set_duplex(dev);
1553 vortex_set_duplex(dev);
1558 vortex_up(struct net_device *dev)
1560 struct vortex_private *vp = netdev_priv(dev);
1561 void __iomem *ioaddr = vp->ioaddr;
1562 unsigned int config;
1563 int i, mii_reg1, mii_reg5, err = 0;
1565 if (VORTEX_PCI(vp)) {
1566 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1567 if (vp->pm_state_valid)
1568 pci_restore_state(VORTEX_PCI(vp));
1569 err = pci_enable_device(VORTEX_PCI(vp));
1571 pr_warning("%s: Could not enable device\n",
1577 /* Before initializing select the active media port. */
1578 config = window_read32(vp, 3, Wn3_Config);
1580 if (vp->media_override != 7) {
1581 pr_info("%s: Media override to transceiver %d (%s).\n",
1582 dev->name, vp->media_override,
1583 media_tbl[vp->media_override].name);
1584 dev->if_port = vp->media_override;
1585 } else if (vp->autoselect) {
1587 if (vortex_debug > 1)
1588 pr_info("%s: using NWAY device table, not %d\n",
1589 dev->name, dev->if_port);
1590 dev->if_port = XCVR_NWAY;
1592 /* Find first available media type, starting with 100baseTx. */
1593 dev->if_port = XCVR_100baseTx;
1594 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1595 dev->if_port = media_tbl[dev->if_port].next;
1596 if (vortex_debug > 1)
1597 pr_info("%s: first available media type: %s\n",
1598 dev->name, media_tbl[dev->if_port].name);
1601 dev->if_port = vp->default_media;
1602 if (vortex_debug > 1)
1603 pr_info("%s: using default media %s\n",
1604 dev->name, media_tbl[dev->if_port].name);
1607 init_timer(&vp->timer);
1608 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1609 vp->timer.data = (unsigned long)dev;
1610 vp->timer.function = vortex_timer; /* timer handler */
1611 add_timer(&vp->timer);
1613 init_timer(&vp->rx_oom_timer);
1614 vp->rx_oom_timer.data = (unsigned long)dev;
1615 vp->rx_oom_timer.function = rx_oom_timer;
1617 if (vortex_debug > 1)
1618 pr_debug("%s: Initial media type %s.\n",
1619 dev->name, media_tbl[dev->if_port].name);
1621 vp->full_duplex = vp->mii.force_media;
1622 config = BFINS(config, dev->if_port, 20, 4);
1623 if (vortex_debug > 6)
1624 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1625 window_write32(vp, config, 3, Wn3_Config);
1627 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1628 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1629 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1630 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1631 vp->mii.full_duplex = vp->full_duplex;
1633 vortex_check_media(dev, 1);
1636 vortex_set_duplex(dev);
1638 issue_and_wait(dev, TxReset);
1640 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1642 issue_and_wait(dev, RxReset|0x04);
1645 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1647 if (vortex_debug > 1) {
1648 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1649 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1652 /* Set the station address and mask in window 2 each time opened. */
1653 for (i = 0; i < 6; i++)
1654 window_write8(vp, dev->dev_addr[i], 2, i);
1655 for (; i < 12; i+=2)
1656 window_write16(vp, 0, 2, i);
1658 if (vp->cb_fn_base) {
1659 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1660 if (vp->drv_flags & INVERT_LED_PWR)
1662 if (vp->drv_flags & INVERT_MII_PWR)
1664 window_write16(vp, n, 2, Wn2_ResetOptions);
1667 if (dev->if_port == XCVR_10base2)
1668 /* Start the thinnet transceiver. We should really wait 50ms...*/
1669 iowrite16(StartCoax, ioaddr + EL3_CMD);
1670 if (dev->if_port != XCVR_NWAY) {
1672 (window_read16(vp, 4, Wn4_Media) &
1673 ~(Media_10TP|Media_SQE)) |
1674 media_tbl[dev->if_port].media_bits,
1678 /* Switch to the stats window, and clear all stats by reading. */
1679 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1680 for (i = 0; i < 10; i++)
1681 window_read8(vp, 6, i);
1682 window_read16(vp, 6, 10);
1683 window_read16(vp, 6, 12);
1684 /* New: On the Vortex we must also clear the BadSSD counter. */
1685 window_read8(vp, 4, 12);
1686 /* ..and on the Boomerang we enable the extra statistics bits. */
1687 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1689 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1690 vp->cur_rx = vp->dirty_rx = 0;
1691 /* Initialize the RxEarly register as recommended. */
1692 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1693 iowrite32(0x0020, ioaddr + PktStatus);
1694 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1696 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1697 vp->cur_tx = vp->dirty_tx = 0;
1698 if (vp->drv_flags & IS_BOOMERANG)
1699 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1700 /* Clear the Rx, Tx rings. */
1701 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1702 vp->rx_ring[i].status = 0;
1703 for (i = 0; i < TX_RING_SIZE; i++)
1704 vp->tx_skbuff[i] = NULL;
1705 iowrite32(0, ioaddr + DownListPtr);
1707 /* Set receiver mode: presumably accept b-case and phys addr only. */
1709 /* enable 802.1q tagged frames */
1710 set_8021q_mode(dev, 1);
1711 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1713 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1714 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1715 /* Allow status bits to be seen. */
1716 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1717 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1718 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1719 (vp->bus_master ? DMADone : 0);
1720 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1721 (vp->full_bus_master_rx ? 0 : RxComplete) |
1722 StatsFull | HostError | TxComplete | IntReq
1723 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1724 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1725 /* Ack all pending events, and set active indicator mask. */
1726 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1728 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1729 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1730 iowrite32(0x8000, vp->cb_fn_base + 4);
1731 netif_start_queue (dev);
1737 vortex_open(struct net_device *dev)
1739 struct vortex_private *vp = netdev_priv(dev);
1743 /* Use the now-standard shared IRQ implementation. */
1744 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1745 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1746 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1750 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1751 if (vortex_debug > 2)
1752 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1753 for (i = 0; i < RX_RING_SIZE; i++) {
1754 struct sk_buff *skb;
1755 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1756 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1757 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1759 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1761 vp->rx_skbuff[i] = skb;
1763 break; /* Bad news! */
1765 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1766 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1768 if (i != RX_RING_SIZE) {
1770 pr_emerg("%s: no memory for rx ring\n", dev->name);
1771 for (j = 0; j < i; j++) {
1772 if (vp->rx_skbuff[j]) {
1773 dev_kfree_skb(vp->rx_skbuff[j]);
1774 vp->rx_skbuff[j] = NULL;
1780 /* Wrap the ring. */
1781 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1784 retval = vortex_up(dev);
1789 free_irq(dev->irq, dev);
1791 if (vortex_debug > 1)
1792 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1798 vortex_timer(unsigned long data)
1800 struct net_device *dev = (struct net_device *)data;
1801 struct vortex_private *vp = netdev_priv(dev);
1802 void __iomem *ioaddr = vp->ioaddr;
1803 int next_tick = 60*HZ;
1807 if (vortex_debug > 2) {
1808 pr_debug("%s: Media selection timer tick happened, %s.\n",
1809 dev->name, media_tbl[dev->if_port].name);
1810 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1813 media_status = window_read16(vp, 4, Wn4_Media);
1814 switch (dev->if_port) {
1815 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1816 if (media_status & Media_LnkBeat) {
1817 netif_carrier_on(dev);
1819 if (vortex_debug > 1)
1820 pr_debug("%s: Media %s has link beat, %x.\n",
1821 dev->name, media_tbl[dev->if_port].name, media_status);
1823 netif_carrier_off(dev);
1824 if (vortex_debug > 1) {
1825 pr_debug("%s: Media %s has no link beat, %x.\n",
1826 dev->name, media_tbl[dev->if_port].name, media_status);
1830 case XCVR_MII: case XCVR_NWAY:
1833 vortex_check_media(dev, 0);
1836 default: /* Other media types handled by Tx timeouts. */
1837 if (vortex_debug > 1)
1838 pr_debug("%s: Media %s has no indication, %x.\n",
1839 dev->name, media_tbl[dev->if_port].name, media_status);
1843 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1847 goto leave_media_alone;
1850 unsigned int config;
1852 spin_lock_irq(&vp->lock);
1855 dev->if_port = media_tbl[dev->if_port].next;
1856 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1857 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1858 dev->if_port = vp->default_media;
1859 if (vortex_debug > 1)
1860 pr_debug("%s: Media selection failing, using default %s port.\n",
1861 dev->name, media_tbl[dev->if_port].name);
1863 if (vortex_debug > 1)
1864 pr_debug("%s: Media selection failed, now trying %s port.\n",
1865 dev->name, media_tbl[dev->if_port].name);
1866 next_tick = media_tbl[dev->if_port].wait;
1869 (media_status & ~(Media_10TP|Media_SQE)) |
1870 media_tbl[dev->if_port].media_bits,
1873 config = window_read32(vp, 3, Wn3_Config);
1874 config = BFINS(config, dev->if_port, 20, 4);
1875 window_write32(vp, config, 3, Wn3_Config);
1877 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1879 if (vortex_debug > 1)
1880 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1881 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1883 spin_unlock_irq(&vp->lock);
1887 if (vortex_debug > 2)
1888 pr_debug("%s: Media selection timer finished, %s.\n",
1889 dev->name, media_tbl[dev->if_port].name);
1891 mod_timer(&vp->timer, RUN_AT(next_tick));
1893 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1896 static void vortex_tx_timeout(struct net_device *dev)
1898 struct vortex_private *vp = netdev_priv(dev);
1899 void __iomem *ioaddr = vp->ioaddr;
1901 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1902 dev->name, ioread8(ioaddr + TxStatus),
1903 ioread16(ioaddr + EL3_STATUS));
1904 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1905 window_read16(vp, 4, Wn4_NetDiag),
1906 window_read16(vp, 4, Wn4_Media),
1907 ioread32(ioaddr + PktStatus),
1908 window_read16(vp, 4, Wn4_FIFODiag));
1909 /* Slight code bloat to be user friendly. */
1910 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1911 pr_err("%s: Transmitter encountered 16 collisions --"
1912 " network cable problem?\n", dev->name);
1913 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1914 pr_err("%s: Interrupt posted but not delivered --"
1915 " IRQ blocked by another device?\n", dev->name);
1916 /* Bad idea here.. but we might as well handle a few events. */
1919 * Block interrupts because vortex_interrupt does a bare spin_lock()
1921 unsigned long flags;
1922 local_irq_save(flags);
1923 if (vp->full_bus_master_tx)
1924 boomerang_interrupt(dev->irq, dev);
1926 vortex_interrupt(dev->irq, dev);
1927 local_irq_restore(flags);
1931 if (vortex_debug > 0)
1934 issue_and_wait(dev, TxReset);
1936 dev->stats.tx_errors++;
1937 if (vp->full_bus_master_tx) {
1938 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1939 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1940 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1941 ioaddr + DownListPtr);
1942 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1943 netif_wake_queue (dev);
1944 if (vp->drv_flags & IS_BOOMERANG)
1945 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1946 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1948 dev->stats.tx_dropped++;
1949 netif_wake_queue(dev);
1952 /* Issue Tx Enable */
1953 iowrite16(TxEnable, ioaddr + EL3_CMD);
1954 dev->trans_start = jiffies; /* prevent tx timeout */
1958 * Handle uncommon interrupt sources. This is a separate routine to minimize
1962 vortex_error(struct net_device *dev, int status)
1964 struct vortex_private *vp = netdev_priv(dev);
1965 void __iomem *ioaddr = vp->ioaddr;
1966 int do_tx_reset = 0, reset_mask = 0;
1967 unsigned char tx_status = 0;
1969 if (vortex_debug > 2) {
1970 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1973 if (status & TxComplete) { /* Really "TxError" for us. */
1974 tx_status = ioread8(ioaddr + TxStatus);
1975 /* Presumably a tx-timeout. We must merely re-enable. */
1976 if (vortex_debug > 2 ||
1977 (tx_status != 0x88 && vortex_debug > 0)) {
1978 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1979 dev->name, tx_status);
1980 if (tx_status == 0x82) {
1981 pr_err("Probably a duplex mismatch. See "
1982 "Documentation/networking/vortex.txt\n");
1986 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1987 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1988 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1989 iowrite8(0, ioaddr + TxStatus);
1990 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1992 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1994 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1995 } else { /* Merely re-enable the transmitter. */
1996 iowrite16(TxEnable, ioaddr + EL3_CMD);
2000 if (status & RxEarly) /* Rx early is unused. */
2001 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2003 if (status & StatsFull) { /* Empty statistics. */
2004 static int DoneDidThat;
2005 if (vortex_debug > 4)
2006 pr_debug("%s: Updating stats.\n", dev->name);
2007 update_stats(ioaddr, dev);
2008 /* HACK: Disable statistics as an interrupt source. */
2009 /* This occurs when we have the wrong media type! */
2010 if (DoneDidThat == 0 &&
2011 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2012 pr_warning("%s: Updating statistics failed, disabling "
2013 "stats as an interrupt source.\n", dev->name);
2014 iowrite16(SetIntrEnb |
2015 (window_read16(vp, 5, 10) & ~StatsFull),
2017 vp->intr_enable &= ~StatsFull;
2021 if (status & IntReq) { /* Restore all interrupt sources. */
2022 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2023 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2025 if (status & HostError) {
2027 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2028 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2029 dev->name, fifo_diag);
2030 /* Adapter failure requires Tx/Rx reset and reinit. */
2031 if (vp->full_bus_master_tx) {
2032 int bus_status = ioread32(ioaddr + PktStatus);
2033 /* 0x80000000 PCI master abort. */
2034 /* 0x40000000 PCI target abort. */
2036 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2038 /* In this case, blow the card away */
2039 /* Must not enter D3 or we can't legally issue the reset! */
2040 vortex_down(dev, 0);
2041 issue_and_wait(dev, TotalReset | 0xff);
2042 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2043 } else if (fifo_diag & 0x0400)
2045 if (fifo_diag & 0x3000) {
2046 /* Reset Rx fifo and upload logic */
2047 issue_and_wait(dev, RxReset|0x07);
2048 /* Set the Rx filter to the current state. */
2050 /* enable 802.1q VLAN tagged frames */
2051 set_8021q_mode(dev, 1);
2052 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2053 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2058 issue_and_wait(dev, TxReset|reset_mask);
2059 iowrite16(TxEnable, ioaddr + EL3_CMD);
2060 if (!vp->full_bus_master_tx)
2061 netif_wake_queue(dev);
2066 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2068 struct vortex_private *vp = netdev_priv(dev);
2069 void __iomem *ioaddr = vp->ioaddr;
2071 /* Put out the doubleword header... */
2072 iowrite32(skb->len, ioaddr + TX_FIFO);
2073 if (vp->bus_master) {
2074 /* Set the bus-master controller to transfer the packet. */
2075 int len = (skb->len + 3) & ~3;
2076 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2078 spin_lock_irq(&vp->window_lock);
2080 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2081 iowrite16(len, ioaddr + Wn7_MasterLen);
2082 spin_unlock_irq(&vp->window_lock);
2084 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2085 /* netif_wake_queue() will be called at the DMADone interrupt. */
2087 /* ... and the packet rounded to a doubleword. */
2088 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2089 dev_kfree_skb (skb);
2090 if (ioread16(ioaddr + TxFree) > 1536) {
2091 netif_start_queue (dev); /* AKPM: redundant? */
2093 /* Interrupt us when the FIFO has room for max-sized packet. */
2094 netif_stop_queue(dev);
2095 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2100 /* Clear the Tx status stack. */
2105 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2106 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2107 if (vortex_debug > 2)
2108 pr_debug("%s: Tx error, status %2.2x.\n",
2109 dev->name, tx_status);
2110 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2111 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2112 if (tx_status & 0x30) {
2113 issue_and_wait(dev, TxReset);
2115 iowrite16(TxEnable, ioaddr + EL3_CMD);
2117 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2120 return NETDEV_TX_OK;
2124 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2126 struct vortex_private *vp = netdev_priv(dev);
2127 void __iomem *ioaddr = vp->ioaddr;
2128 /* Calculate the next Tx descriptor entry. */
2129 int entry = vp->cur_tx % TX_RING_SIZE;
2130 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2131 unsigned long flags;
2133 if (vortex_debug > 6) {
2134 pr_debug("boomerang_start_xmit()\n");
2135 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2136 dev->name, vp->cur_tx);
2140 * We can't allow a recursion from our interrupt handler back into the
2141 * tx routine, as they take the same spin lock, and that causes
2142 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2145 if (vp->handling_irq)
2146 return NETDEV_TX_BUSY;
2148 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2149 if (vortex_debug > 0)
2150 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2152 netif_stop_queue(dev);
2153 return NETDEV_TX_BUSY;
2156 vp->tx_skbuff[entry] = skb;
2158 vp->tx_ring[entry].next = 0;
2160 if (skb->ip_summed != CHECKSUM_PARTIAL)
2161 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2163 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2165 if (!skb_shinfo(skb)->nr_frags) {
2166 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2167 skb->len, PCI_DMA_TODEVICE));
2168 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2172 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2173 skb_headlen(skb), PCI_DMA_TODEVICE));
2174 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2176 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2177 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2179 vp->tx_ring[entry].frag[i+1].addr =
2180 cpu_to_le32(pci_map_single(
2182 (void *)skb_frag_address(frag),
2183 skb_frag_size(frag), PCI_DMA_TODEVICE));
2185 if (i == skb_shinfo(skb)->nr_frags-1)
2186 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2188 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2192 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2193 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2194 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2197 spin_lock_irqsave(&vp->lock, flags);
2198 /* Wait for the stall to complete. */
2199 issue_and_wait(dev, DownStall);
2200 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2201 if (ioread32(ioaddr + DownListPtr) == 0) {
2202 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2203 vp->queued_packet++;
2207 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2208 netif_stop_queue (dev);
2209 } else { /* Clear previous interrupt enable. */
2210 #if defined(tx_interrupt_mitigation)
2211 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2212 * were selected, this would corrupt DN_COMPLETE. No?
2214 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2217 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2218 spin_unlock_irqrestore(&vp->lock, flags);
2219 return NETDEV_TX_OK;
2222 /* The interrupt handler does all of the Rx thread work and cleans up
2223 after the Tx thread. */
2226 * This is the ISR for the vortex series chips.
2227 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2231 vortex_interrupt(int irq, void *dev_id)
2233 struct net_device *dev = dev_id;
2234 struct vortex_private *vp = netdev_priv(dev);
2235 void __iomem *ioaddr;
2237 int work_done = max_interrupt_work;
2240 ioaddr = vp->ioaddr;
2241 spin_lock(&vp->lock);
2243 status = ioread16(ioaddr + EL3_STATUS);
2245 if (vortex_debug > 6)
2246 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2248 if ((status & IntLatch) == 0)
2249 goto handler_exit; /* No interrupt: shared IRQs cause this */
2252 if (status & IntReq) {
2253 status |= vp->deferred;
2257 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2260 if (vortex_debug > 4)
2261 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2262 dev->name, status, ioread8(ioaddr + Timer));
2264 spin_lock(&vp->window_lock);
2268 if (vortex_debug > 5)
2269 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2271 if (status & RxComplete)
2274 if (status & TxAvailable) {
2275 if (vortex_debug > 5)
2276 pr_debug(" TX room bit was handled.\n");
2277 /* There's room in the FIFO for a full-sized packet. */
2278 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2279 netif_wake_queue (dev);
2282 if (status & DMADone) {
2283 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2284 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2285 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2286 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2287 if (ioread16(ioaddr + TxFree) > 1536) {
2289 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2290 * insufficient FIFO room, the TxAvailable test will succeed and call
2291 * netif_wake_queue()
2293 netif_wake_queue(dev);
2294 } else { /* Interrupt when FIFO has room for max-sized packet. */
2295 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2296 netif_stop_queue(dev);
2300 /* Check for all uncommon interrupts at once. */
2301 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2302 if (status == 0xffff)
2304 if (status & RxEarly)
2306 spin_unlock(&vp->window_lock);
2307 vortex_error(dev, status);
2308 spin_lock(&vp->window_lock);
2312 if (--work_done < 0) {
2313 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2315 /* Disable all pending interrupts. */
2317 vp->deferred |= status;
2318 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2320 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2321 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2322 /* The timer will reenable interrupts. */
2323 mod_timer(&vp->timer, jiffies + 1*HZ);
2326 /* Acknowledge the IRQ. */
2327 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2328 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2330 spin_unlock(&vp->window_lock);
2332 if (vortex_debug > 4)
2333 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2336 spin_unlock(&vp->lock);
2337 return IRQ_RETVAL(handled);
2341 * This is the ISR for the boomerang series chips.
2342 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2346 boomerang_interrupt(int irq, void *dev_id)
2348 struct net_device *dev = dev_id;
2349 struct vortex_private *vp = netdev_priv(dev);
2350 void __iomem *ioaddr;
2352 int work_done = max_interrupt_work;
2354 ioaddr = vp->ioaddr;
2358 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2359 * and boomerang_start_xmit
2361 spin_lock(&vp->lock);
2362 vp->handling_irq = 1;
2364 status = ioread16(ioaddr + EL3_STATUS);
2366 if (vortex_debug > 6)
2367 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2369 if ((status & IntLatch) == 0)
2370 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2372 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2373 if (vortex_debug > 1)
2374 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2378 if (status & IntReq) {
2379 status |= vp->deferred;
2383 if (vortex_debug > 4)
2384 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2385 dev->name, status, ioread8(ioaddr + Timer));
2387 if (vortex_debug > 5)
2388 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2390 if (status & UpComplete) {
2391 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2392 if (vortex_debug > 5)
2393 pr_debug("boomerang_interrupt->boomerang_rx\n");
2397 if (status & DownComplete) {
2398 unsigned int dirty_tx = vp->dirty_tx;
2400 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2401 while (vp->cur_tx - dirty_tx > 0) {
2402 int entry = dirty_tx % TX_RING_SIZE;
2403 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2404 if (ioread32(ioaddr + DownListPtr) ==
2405 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2406 break; /* It still hasn't been processed. */
2408 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2409 break; /* It still hasn't been processed. */
2412 if (vp->tx_skbuff[entry]) {
2413 struct sk_buff *skb = vp->tx_skbuff[entry];
2416 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2417 pci_unmap_single(VORTEX_PCI(vp),
2418 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2419 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2422 pci_unmap_single(VORTEX_PCI(vp),
2423 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2425 dev_kfree_skb_irq(skb);
2426 vp->tx_skbuff[entry] = NULL;
2428 pr_debug("boomerang_interrupt: no skb!\n");
2430 /* dev->stats.tx_packets++; Counted below. */
2433 vp->dirty_tx = dirty_tx;
2434 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2435 if (vortex_debug > 6)
2436 pr_debug("boomerang_interrupt: wake queue\n");
2437 netif_wake_queue (dev);
2441 /* Check for all uncommon interrupts at once. */
2442 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2443 vortex_error(dev, status);
2445 if (--work_done < 0) {
2446 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2448 /* Disable all pending interrupts. */
2450 vp->deferred |= status;
2451 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2453 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2454 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2455 /* The timer will reenable interrupts. */
2456 mod_timer(&vp->timer, jiffies + 1*HZ);
2459 /* Acknowledge the IRQ. */
2460 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2461 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2462 iowrite32(0x8000, vp->cb_fn_base + 4);
2464 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2466 if (vortex_debug > 4)
2467 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2470 vp->handling_irq = 0;
2471 spin_unlock(&vp->lock);
2475 static int vortex_rx(struct net_device *dev)
2477 struct vortex_private *vp = netdev_priv(dev);
2478 void __iomem *ioaddr = vp->ioaddr;
2482 if (vortex_debug > 5)
2483 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2484 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2485 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2486 if (rx_status & 0x4000) { /* Error, update stats. */
2487 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2488 if (vortex_debug > 2)
2489 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2490 dev->stats.rx_errors++;
2491 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2492 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2493 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2494 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2495 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2497 /* The packet length: up to 4.5K!. */
2498 int pkt_len = rx_status & 0x1fff;
2499 struct sk_buff *skb;
2501 skb = netdev_alloc_skb(dev, pkt_len + 5);
2502 if (vortex_debug > 4)
2503 pr_debug("Receiving packet size %d status %4.4x.\n",
2504 pkt_len, rx_status);
2506 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2507 /* 'skb_put()' points to the start of sk_buff data area. */
2508 if (vp->bus_master &&
2509 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2510 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2511 pkt_len, PCI_DMA_FROMDEVICE);
2512 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2513 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2514 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2515 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2517 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2519 ioread32_rep(ioaddr + RX_FIFO,
2520 skb_put(skb, pkt_len),
2521 (pkt_len + 3) >> 2);
2523 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2524 skb->protocol = eth_type_trans(skb, dev);
2526 dev->stats.rx_packets++;
2527 /* Wait a limited time to go to next packet. */
2528 for (i = 200; i >= 0; i--)
2529 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2532 } else if (vortex_debug > 0)
2533 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2534 dev->name, pkt_len);
2535 dev->stats.rx_dropped++;
2537 issue_and_wait(dev, RxDiscard);
2544 boomerang_rx(struct net_device *dev)
2546 struct vortex_private *vp = netdev_priv(dev);
2547 int entry = vp->cur_rx % RX_RING_SIZE;
2548 void __iomem *ioaddr = vp->ioaddr;
2550 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2552 if (vortex_debug > 5)
2553 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2555 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2556 if (--rx_work_limit < 0)
2558 if (rx_status & RxDError) { /* Error, update stats. */
2559 unsigned char rx_error = rx_status >> 16;
2560 if (vortex_debug > 2)
2561 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2562 dev->stats.rx_errors++;
2563 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2564 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2565 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2566 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2567 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2569 /* The packet length: up to 4.5K!. */
2570 int pkt_len = rx_status & 0x1fff;
2571 struct sk_buff *skb;
2572 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2574 if (vortex_debug > 4)
2575 pr_debug("Receiving packet size %d status %4.4x.\n",
2576 pkt_len, rx_status);
2578 /* Check if the packet is long enough to just accept without
2579 copying to a properly sized skbuff. */
2580 if (pkt_len < rx_copybreak &&
2581 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2582 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2583 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2584 /* 'skb_put()' points to the start of sk_buff data area. */
2585 memcpy(skb_put(skb, pkt_len),
2586 vp->rx_skbuff[entry]->data,
2588 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2591 /* Pass up the skbuff already on the Rx ring. */
2592 skb = vp->rx_skbuff[entry];
2593 vp->rx_skbuff[entry] = NULL;
2594 skb_put(skb, pkt_len);
2595 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2598 skb->protocol = eth_type_trans(skb, dev);
2599 { /* Use hardware checksum info. */
2600 int csum_bits = rx_status & 0xee000000;
2602 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2603 csum_bits == (IPChksumValid | UDPChksumValid))) {
2604 skb->ip_summed = CHECKSUM_UNNECESSARY;
2609 dev->stats.rx_packets++;
2611 entry = (++vp->cur_rx) % RX_RING_SIZE;
2613 /* Refill the Rx ring buffers. */
2614 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2615 struct sk_buff *skb;
2616 entry = vp->dirty_rx % RX_RING_SIZE;
2617 if (vp->rx_skbuff[entry] == NULL) {
2618 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2620 static unsigned long last_jif;
2621 if (time_after(jiffies, last_jif + 10 * HZ)) {
2622 pr_warning("%s: memory shortage\n", dev->name);
2625 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2626 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2627 break; /* Bad news! */
2630 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2631 vp->rx_skbuff[entry] = skb;
2633 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2634 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2640 * If we've hit a total OOM refilling the Rx ring we poll once a second
2641 * for some memory. Otherwise there is no way to restart the rx process.
2644 rx_oom_timer(unsigned long arg)
2646 struct net_device *dev = (struct net_device *)arg;
2647 struct vortex_private *vp = netdev_priv(dev);
2649 spin_lock_irq(&vp->lock);
2650 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2652 if (vortex_debug > 1) {
2653 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2654 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2656 spin_unlock_irq(&vp->lock);
2660 vortex_down(struct net_device *dev, int final_down)
2662 struct vortex_private *vp = netdev_priv(dev);
2663 void __iomem *ioaddr = vp->ioaddr;
2665 netif_stop_queue (dev);
2667 del_timer_sync(&vp->rx_oom_timer);
2668 del_timer_sync(&vp->timer);
2670 /* Turn off statistics ASAP. We update dev->stats below. */
2671 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2673 /* Disable the receiver and transmitter. */
2674 iowrite16(RxDisable, ioaddr + EL3_CMD);
2675 iowrite16(TxDisable, ioaddr + EL3_CMD);
2677 /* Disable receiving 802.1q tagged frames */
2678 set_8021q_mode(dev, 0);
2680 if (dev->if_port == XCVR_10base2)
2681 /* Turn off thinnet power. Green! */
2682 iowrite16(StopCoax, ioaddr + EL3_CMD);
2684 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2686 update_stats(ioaddr, dev);
2687 if (vp->full_bus_master_rx)
2688 iowrite32(0, ioaddr + UpListPtr);
2689 if (vp->full_bus_master_tx)
2690 iowrite32(0, ioaddr + DownListPtr);
2692 if (final_down && VORTEX_PCI(vp)) {
2693 vp->pm_state_valid = 1;
2694 pci_save_state(VORTEX_PCI(vp));
2700 vortex_close(struct net_device *dev)
2702 struct vortex_private *vp = netdev_priv(dev);
2703 void __iomem *ioaddr = vp->ioaddr;
2706 if (netif_device_present(dev))
2707 vortex_down(dev, 1);
2709 if (vortex_debug > 1) {
2710 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2711 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2712 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2713 " tx_queued %d Rx pre-checksummed %d.\n",
2714 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2718 if (vp->rx_csumhits &&
2719 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2720 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2721 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2725 free_irq(dev->irq, dev);
2727 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2728 for (i = 0; i < RX_RING_SIZE; i++)
2729 if (vp->rx_skbuff[i]) {
2730 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2731 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2732 dev_kfree_skb(vp->rx_skbuff[i]);
2733 vp->rx_skbuff[i] = NULL;
2736 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2737 for (i = 0; i < TX_RING_SIZE; i++) {
2738 if (vp->tx_skbuff[i]) {
2739 struct sk_buff *skb = vp->tx_skbuff[i];
2743 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2744 pci_unmap_single(VORTEX_PCI(vp),
2745 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2746 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2749 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2752 vp->tx_skbuff[i] = NULL;
2761 dump_tx_ring(struct net_device *dev)
2763 if (vortex_debug > 0) {
2764 struct vortex_private *vp = netdev_priv(dev);
2765 void __iomem *ioaddr = vp->ioaddr;
2767 if (vp->full_bus_master_tx) {
2769 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2771 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2772 vp->full_bus_master_tx,
2773 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2774 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2775 pr_err(" Transmit list %8.8x vs. %p.\n",
2776 ioread32(ioaddr + DownListPtr),
2777 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2778 issue_and_wait(dev, DownStall);
2779 for (i = 0; i < TX_RING_SIZE; i++) {
2780 unsigned int length;
2783 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2785 length = le32_to_cpu(vp->tx_ring[i].length);
2787 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2788 i, &vp->tx_ring[i], length,
2789 le32_to_cpu(vp->tx_ring[i].status));
2792 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2797 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2799 struct vortex_private *vp = netdev_priv(dev);
2800 void __iomem *ioaddr = vp->ioaddr;
2801 unsigned long flags;
2803 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2804 spin_lock_irqsave (&vp->lock, flags);
2805 update_stats(ioaddr, dev);
2806 spin_unlock_irqrestore (&vp->lock, flags);
2811 /* Update statistics.
2812 Unlike with the EL3 we need not worry about interrupts changing
2813 the window setting from underneath us, but we must still guard
2814 against a race condition with a StatsUpdate interrupt updating the
2815 table. This is done by checking that the ASM (!) code generated uses
2816 atomic updates with '+='.
2818 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2820 struct vortex_private *vp = netdev_priv(dev);
2822 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2823 /* Switch to the stats window, and read everything. */
2824 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2825 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2826 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2827 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2828 dev->stats.tx_packets += window_read8(vp, 6, 6);
2829 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2831 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2832 /* Don't bother with register 9, an extension of registers 6&7.
2833 If we do use the 6&7 values the atomic update assumption above
2835 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2836 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2837 /* Extra stats for get_ethtool_stats() */
2838 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2839 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2840 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2841 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2843 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2844 + vp->xstats.tx_single_collisions
2845 + vp->xstats.tx_max_collisions;
2848 u8 up = window_read8(vp, 4, 13);
2849 dev->stats.rx_bytes += (up & 0x0f) << 16;
2850 dev->stats.tx_bytes += (up & 0xf0) << 12;
2854 static int vortex_nway_reset(struct net_device *dev)
2856 struct vortex_private *vp = netdev_priv(dev);
2858 return mii_nway_restart(&vp->mii);
2861 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2863 struct vortex_private *vp = netdev_priv(dev);
2865 return mii_ethtool_gset(&vp->mii, cmd);
2868 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2870 struct vortex_private *vp = netdev_priv(dev);
2872 return mii_ethtool_sset(&vp->mii, cmd);
2875 static u32 vortex_get_msglevel(struct net_device *dev)
2877 return vortex_debug;
2880 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2885 static int vortex_get_sset_count(struct net_device *dev, int sset)
2889 return VORTEX_NUM_STATS;
2895 static void vortex_get_ethtool_stats(struct net_device *dev,
2896 struct ethtool_stats *stats, u64 *data)
2898 struct vortex_private *vp = netdev_priv(dev);
2899 void __iomem *ioaddr = vp->ioaddr;
2900 unsigned long flags;
2902 spin_lock_irqsave(&vp->lock, flags);
2903 update_stats(ioaddr, dev);
2904 spin_unlock_irqrestore(&vp->lock, flags);
2906 data[0] = vp->xstats.tx_deferred;
2907 data[1] = vp->xstats.tx_max_collisions;
2908 data[2] = vp->xstats.tx_multiple_collisions;
2909 data[3] = vp->xstats.tx_single_collisions;
2910 data[4] = vp->xstats.rx_bad_ssd;
2914 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2916 switch (stringset) {
2918 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2926 static void vortex_get_drvinfo(struct net_device *dev,
2927 struct ethtool_drvinfo *info)
2929 struct vortex_private *vp = netdev_priv(dev);
2931 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2932 if (VORTEX_PCI(vp)) {
2933 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2934 sizeof(info->bus_info));
2936 if (VORTEX_EISA(vp))
2937 strlcpy(info->bus_info, dev_name(vp->gendev),
2938 sizeof(info->bus_info));
2940 snprintf(info->bus_info, sizeof(info->bus_info),
2941 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2945 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2947 struct vortex_private *vp = netdev_priv(dev);
2949 if (!VORTEX_PCI(vp))
2952 wol->supported = WAKE_MAGIC;
2956 wol->wolopts |= WAKE_MAGIC;
2959 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2961 struct vortex_private *vp = netdev_priv(dev);
2963 if (!VORTEX_PCI(vp))
2966 if (wol->wolopts & ~WAKE_MAGIC)
2969 if (wol->wolopts & WAKE_MAGIC)
2978 static const struct ethtool_ops vortex_ethtool_ops = {
2979 .get_drvinfo = vortex_get_drvinfo,
2980 .get_strings = vortex_get_strings,
2981 .get_msglevel = vortex_get_msglevel,
2982 .set_msglevel = vortex_set_msglevel,
2983 .get_ethtool_stats = vortex_get_ethtool_stats,
2984 .get_sset_count = vortex_get_sset_count,
2985 .get_settings = vortex_get_settings,
2986 .set_settings = vortex_set_settings,
2987 .get_link = ethtool_op_get_link,
2988 .nway_reset = vortex_nway_reset,
2989 .get_wol = vortex_get_wol,
2990 .set_wol = vortex_set_wol,
2995 * Must power the device up to do MDIO operations
2997 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3000 struct vortex_private *vp = netdev_priv(dev);
3001 pci_power_t state = 0;
3004 state = VORTEX_PCI(vp)->current_state;
3006 /* The kernel core really should have pci_get_power_state() */
3009 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3010 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3012 pci_set_power_state(VORTEX_PCI(vp), state);
3019 /* Pre-Cyclone chips have no documented multicast filter, so the only
3020 multicast setting is to receive all multicast frames. At least
3021 the chip has a very clean way to set the mode, unlike many others. */
3022 static void set_rx_mode(struct net_device *dev)
3024 struct vortex_private *vp = netdev_priv(dev);
3025 void __iomem *ioaddr = vp->ioaddr;
3028 if (dev->flags & IFF_PROMISC) {
3029 if (vortex_debug > 3)
3030 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3031 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3032 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3033 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3035 new_mode = SetRxFilter | RxStation | RxBroadcast;
3037 iowrite16(new_mode, ioaddr + EL3_CMD);
3040 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3041 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3042 Note that this must be done after each RxReset due to some backwards
3043 compatibility logic in the Cyclone and Tornado ASICs */
3045 /* The Ethernet Type used for 802.1q tagged frames */
3046 #define VLAN_ETHER_TYPE 0x8100
3048 static void set_8021q_mode(struct net_device *dev, int enable)
3050 struct vortex_private *vp = netdev_priv(dev);
3053 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3054 /* cyclone and tornado chipsets can recognize 802.1q
3055 * tagged frames and treat them correctly */
3057 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3059 max_pkt_size += 4; /* 802.1Q VLAN tag */
3061 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3063 /* set VlanEtherType to let the hardware checksumming
3064 treat tagged frames correctly */
3065 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3067 /* on older cards we have to enable large frames */
3069 vp->large_frames = dev->mtu > 1500 || enable;
3071 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3072 if (vp->large_frames)
3076 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3081 static void set_8021q_mode(struct net_device *dev, int enable)
3088 /* MII transceiver control section.
3089 Read and write the MII registers using software-generated serial
3090 MDIO protocol. See the MII specifications or DP83840A data sheet
3093 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3094 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3095 "overclocking" issues. */
3096 static void mdio_delay(struct vortex_private *vp)
3098 window_read32(vp, 4, Wn4_PhysicalMgmt);
3101 #define MDIO_SHIFT_CLK 0x01
3102 #define MDIO_DIR_WRITE 0x04
3103 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3104 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3105 #define MDIO_DATA_READ 0x02
3106 #define MDIO_ENB_IN 0x00
3108 /* Generate the preamble required for initial synchronization and
3109 a few older transceivers. */
3110 static void mdio_sync(struct vortex_private *vp, int bits)
3112 /* Establish sync by sending at least 32 logic ones. */
3113 while (-- bits >= 0) {
3114 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3116 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3117 4, Wn4_PhysicalMgmt);
3122 static int mdio_read(struct net_device *dev, int phy_id, int location)
3125 struct vortex_private *vp = netdev_priv(dev);
3126 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3127 unsigned int retval = 0;
3129 spin_lock_bh(&vp->mii_lock);
3131 if (mii_preamble_required)
3134 /* Shift the read command bits out. */
3135 for (i = 14; i >= 0; i--) {
3136 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3137 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3139 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3140 4, Wn4_PhysicalMgmt);
3143 /* Read the two transition, 16 data, and wire-idle bits. */
3144 for (i = 19; i > 0; i--) {
3145 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3147 retval = (retval << 1) |
3148 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3149 MDIO_DATA_READ) ? 1 : 0);
3150 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3151 4, Wn4_PhysicalMgmt);
3155 spin_unlock_bh(&vp->mii_lock);
3157 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3160 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3162 struct vortex_private *vp = netdev_priv(dev);
3163 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3166 spin_lock_bh(&vp->mii_lock);
3168 if (mii_preamble_required)
3171 /* Shift the command bits out. */
3172 for (i = 31; i >= 0; i--) {
3173 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3174 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3176 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3177 4, Wn4_PhysicalMgmt);
3180 /* Leave the interface idle. */
3181 for (i = 1; i >= 0; i--) {
3182 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3184 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3185 4, Wn4_PhysicalMgmt);
3189 spin_unlock_bh(&vp->mii_lock);
3192 /* ACPI: Advanced Configuration and Power Interface. */
3193 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3194 static void acpi_set_WOL(struct net_device *dev)
3196 struct vortex_private *vp = netdev_priv(dev);
3197 void __iomem *ioaddr = vp->ioaddr;
3199 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3201 if (vp->enable_wol) {
3202 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3203 window_write16(vp, 2, 7, 0x0c);
3204 /* The RxFilter must accept the WOL frames. */
3205 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3206 iowrite16(RxEnable, ioaddr + EL3_CMD);
3208 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3209 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3215 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3218 /* Change the power state to D3; RxEnable doesn't take effect. */
3219 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3224 static void vortex_remove_one(struct pci_dev *pdev)
3226 struct net_device *dev = pci_get_drvdata(pdev);
3227 struct vortex_private *vp;
3230 pr_err("vortex_remove_one called for Compaq device!\n");
3234 vp = netdev_priv(dev);
3237 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3239 unregister_netdev(dev);
3241 if (VORTEX_PCI(vp)) {
3242 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3243 if (vp->pm_state_valid)
3244 pci_restore_state(VORTEX_PCI(vp));
3245 pci_disable_device(VORTEX_PCI(vp));
3247 /* Should really use issue_and_wait() here */
3248 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3249 vp->ioaddr + EL3_CMD);
3251 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3253 pci_free_consistent(pdev,
3254 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3255 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3258 if (vp->must_free_region)
3259 release_region(dev->base_addr, vp->io_size);
3264 static struct pci_driver vortex_driver = {
3266 .probe = vortex_init_one,
3267 .remove = vortex_remove_one,
3268 .id_table = vortex_pci_tbl,
3269 .driver.pm = VORTEX_PM_OPS,
3273 static int vortex_have_pci;
3274 static int vortex_have_eisa;
3277 static int __init vortex_init(void)
3279 int pci_rc, eisa_rc;
3281 pci_rc = pci_register_driver(&vortex_driver);
3282 eisa_rc = vortex_eisa_init();
3285 vortex_have_pci = 1;
3287 vortex_have_eisa = 1;
3289 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3293 static void __exit vortex_eisa_cleanup(void)
3295 struct vortex_private *vp;
3296 void __iomem *ioaddr;
3299 /* Take care of the EISA devices */
3300 eisa_driver_unregister(&vortex_eisa_driver);
3303 if (compaq_net_device) {
3304 vp = netdev_priv(compaq_net_device);
3305 ioaddr = ioport_map(compaq_net_device->base_addr,
3308 unregister_netdev(compaq_net_device);
3309 iowrite16(TotalReset, ioaddr + EL3_CMD);
3310 release_region(compaq_net_device->base_addr,
3313 free_netdev(compaq_net_device);
3318 static void __exit vortex_cleanup(void)
3320 if (vortex_have_pci)
3321 pci_unregister_driver(&vortex_driver);
3322 if (vortex_have_eisa)
3323 vortex_eisa_cleanup();
3327 module_init(vortex_init);
3328 module_exit(vortex_cleanup);