1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 mac->ops.set_lan_id(hw);
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
79 * @hw: pointer to the HW structure
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
86 struct e1000_bus_info *bus = &hw->bus;
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
101 * Sets the LAN function id to zero for a single port device.
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
105 struct e1000_bus_info *bus = &hw->bus;
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
147 * Setups the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
154 u8 mac_addr[ETH_ALEN] = {0};
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
159 e1000e_rar_set(hw, hw->mac.addr, 0);
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
186 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
187 &nvm_alt_mac_addr_offset);
189 e_dbg("NVM Read Error\n");
193 if (nvm_alt_mac_addr_offset == 0xFFFF) {
194 /* There is no Alternate MAC Address */
198 if (hw->bus.func == E1000_FUNC_1)
199 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
200 for (i = 0; i < ETH_ALEN; i += 2) {
201 offset = nvm_alt_mac_addr_offset + (i >> 1);
202 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
204 e_dbg("NVM Read Error\n");
208 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
209 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
212 /* if multicast bit is set, the alternate address will not be used */
213 if (alt_mac_addr[0] & 0x01) {
214 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
219 * We have a valid alternate MAC address, and we want to treat it the
220 * same as the normal permanent MAC address stored by the HW into the
221 * RAR. Do this by mapping this address into RAR0.
223 e1000e_rar_set(hw, alt_mac_addr, 0);
230 * e1000e_rar_set - Set receive address register
231 * @hw: pointer to the HW structure
232 * @addr: pointer to the receive address
233 * @index: receive address array register
235 * Sets the receive address array register at index to the address passed
238 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
240 u32 rar_low, rar_high;
243 * HW expects these in little endian so we reverse the byte order
244 * from network order (big endian) to little endian
246 rar_low = ((u32) addr[0] |
247 ((u32) addr[1] << 8) |
248 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
250 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
252 /* If MAC address zero, no need to set the AV bit */
253 if (rar_low || rar_high)
254 rar_high |= E1000_RAH_AV;
257 * Some bridges will combine consecutive 32-bit writes into
258 * a single burst write, which will malfunction on some parts.
259 * The flushes avoid this.
261 ew32(RAL(index), rar_low);
263 ew32(RAH(index), rar_high);
268 * e1000_hash_mc_addr - Generate a multicast hash value
269 * @hw: pointer to the HW structure
270 * @mc_addr: pointer to a multicast address
272 * Generates a multicast address hash value which is used to determine
273 * the multicast filter table array address and new table value. See
274 * e1000_mta_set_generic()
276 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
278 u32 hash_value, hash_mask;
281 /* Register count multiplied by bits per register */
282 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
285 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
286 * where 0xFF would still fall within the hash mask.
288 while (hash_mask >> bit_shift != 0xFF)
292 * The portion of the address that is used for the hash table
293 * is determined by the mc_filter_type setting.
294 * The algorithm is such that there is a total of 8 bits of shifting.
295 * The bit_shift for a mc_filter_type of 0 represents the number of
296 * left-shifts where the MSB of mc_addr[5] would still fall within
297 * the hash_mask. Case 0 does this exactly. Since there are a total
298 * of 8 bits of shifting, then mc_addr[4] will shift right the
299 * remaining number of bits. Thus 8 - bit_shift. The rest of the
300 * cases are a variation of this algorithm...essentially raising the
301 * number of bits to shift mc_addr[5] left, while still keeping the
302 * 8-bit shifting total.
304 * For example, given the following Destination MAC Address and an
305 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
306 * we can see that the bit_shift for case 0 is 4. These are the hash
307 * values resulting from each mc_filter_type...
308 * [0] [1] [2] [3] [4] [5]
312 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
313 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
314 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
315 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
317 switch (hw->mac.mc_filter_type) {
332 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
333 (((u16) mc_addr[5]) << bit_shift)));
339 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
340 * @hw: pointer to the HW structure
341 * @mc_addr_list: array of multicast addresses to program
342 * @mc_addr_count: number of multicast addresses to program
344 * Updates entire Multicast Table Array.
345 * The caller must have a packed mc_addr_list of multicast addresses.
347 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
348 u8 *mc_addr_list, u32 mc_addr_count)
350 u32 hash_value, hash_bit, hash_reg;
353 /* clear mta_shadow */
354 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
356 /* update mta_shadow from mc_addr_list */
357 for (i = 0; (u32) i < mc_addr_count; i++) {
358 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
360 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
361 hash_bit = hash_value & 0x1F;
363 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
364 mc_addr_list += (ETH_ALEN);
367 /* replace the entire MTA table */
368 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
369 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
374 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
375 * @hw: pointer to the HW structure
377 * Clears the base hardware counters by reading the counter registers.
379 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
421 * e1000e_check_for_copper_link - Check for link (Copper)
422 * @hw: pointer to the HW structure
424 * Checks to see of the link status of the hardware has changed. If a
425 * change in link status has been detected, then we read the PHY registers
426 * to get the current speed/duplex if link exists.
428 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
430 struct e1000_mac_info *mac = &hw->mac;
435 * We only want to go out to the PHY registers to see if Auto-Neg
436 * has completed and/or if our link status has changed. The
437 * get_link_status flag is set upon receiving a Link Status
438 * Change or Rx Sequence Error interrupt.
440 if (!mac->get_link_status)
444 * First we want to see if the MII Status Register reports
445 * link. If so, then we want to get the current speed/duplex
448 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
453 return ret_val; /* No link detected */
455 mac->get_link_status = false;
458 * Check if there was DownShift, must be checked
459 * immediately after link-up
461 e1000e_check_downshift(hw);
464 * If we are forcing speed/duplex, then we simply return since
465 * we have already determined whether we have link or not.
468 ret_val = -E1000_ERR_CONFIG;
473 * Auto-Neg is enabled. Auto Speed Detection takes care
474 * of MAC speed/duplex configuration. So we only need to
475 * configure Collision Distance in the MAC.
477 e1000e_config_collision_dist(hw);
480 * Configure Flow Control now that Auto-Neg has completed.
481 * First, we need to restore the desired flow control
482 * settings because we may have had to re-autoneg with a
483 * different link partner.
485 ret_val = e1000e_config_fc_after_link_up(hw);
487 e_dbg("Error configuring flow control\n");
494 * e1000e_check_for_fiber_link - Check for link (Fiber)
495 * @hw: pointer to the HW structure
497 * Checks for link up on the hardware. If link is not up and we have
498 * a signal, then we need to force link up.
500 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
502 struct e1000_mac_info *mac = &hw->mac;
509 status = er32(STATUS);
513 * If we don't have link (auto-negotiation failed or link partner
514 * cannot auto-negotiate), the cable is plugged in (we have signal),
515 * and our link partner is not trying to auto-negotiate with us (we
516 * are receiving idles or data), we need to force link up. We also
517 * need to give auto-negotiation time to complete, in case the cable
518 * was just plugged in. The autoneg_failed flag does this.
520 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
521 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
522 (!(rxcw & E1000_RXCW_C))) {
523 if (mac->autoneg_failed == 0) {
524 mac->autoneg_failed = 1;
527 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
529 /* Disable auto-negotiation in the TXCW register */
530 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
532 /* Force link-up and also force full-duplex. */
534 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
537 /* Configure Flow Control after forcing link up. */
538 ret_val = e1000e_config_fc_after_link_up(hw);
540 e_dbg("Error configuring flow control\n");
543 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
545 * If we are forcing link and we are receiving /C/ ordered
546 * sets, re-enable auto-negotiation in the TXCW register
547 * and disable forced link in the Device Control register
548 * in an attempt to auto-negotiate with our link partner.
550 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
551 ew32(TXCW, mac->txcw);
552 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
554 mac->serdes_has_link = true;
561 * e1000e_check_for_serdes_link - Check for link (Serdes)
562 * @hw: pointer to the HW structure
564 * Checks for link up on the hardware. If link is not up and we have
565 * a signal, then we need to force link up.
567 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
569 struct e1000_mac_info *mac = &hw->mac;
576 status = er32(STATUS);
580 * If we don't have link (auto-negotiation failed or link partner
581 * cannot auto-negotiate), and our link partner is not trying to
582 * auto-negotiate with us (we are receiving idles or data),
583 * we need to force link up. We also need to give auto-negotiation
586 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
587 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
588 if (mac->autoneg_failed == 0) {
589 mac->autoneg_failed = 1;
592 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
594 /* Disable auto-negotiation in the TXCW register */
595 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
597 /* Force link-up and also force full-duplex. */
599 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
602 /* Configure Flow Control after forcing link up. */
603 ret_val = e1000e_config_fc_after_link_up(hw);
605 e_dbg("Error configuring flow control\n");
608 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
610 * If we are forcing link and we are receiving /C/ ordered
611 * sets, re-enable auto-negotiation in the TXCW register
612 * and disable forced link in the Device Control register
613 * in an attempt to auto-negotiate with our link partner.
615 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
616 ew32(TXCW, mac->txcw);
617 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
619 mac->serdes_has_link = true;
620 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
622 * If we force link for non-auto-negotiation switch, check
623 * link status based on MAC synchronization for internal
626 /* SYNCH bit and IV bit are sticky. */
629 if (rxcw & E1000_RXCW_SYNCH) {
630 if (!(rxcw & E1000_RXCW_IV)) {
631 mac->serdes_has_link = true;
632 e_dbg("SERDES: Link up - forced.\n");
635 mac->serdes_has_link = false;
636 e_dbg("SERDES: Link down - force failed.\n");
640 if (E1000_TXCW_ANE & er32(TXCW)) {
641 status = er32(STATUS);
642 if (status & E1000_STATUS_LU) {
643 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
646 if (rxcw & E1000_RXCW_SYNCH) {
647 if (!(rxcw & E1000_RXCW_IV)) {
648 mac->serdes_has_link = true;
649 e_dbg("SERDES: Link up - autoneg "
650 "completed successfully.\n");
652 mac->serdes_has_link = false;
653 e_dbg("SERDES: Link down - invalid"
654 "codewords detected in autoneg.\n");
657 mac->serdes_has_link = false;
658 e_dbg("SERDES: Link down - no sync.\n");
661 mac->serdes_has_link = false;
662 e_dbg("SERDES: Link down - autoneg failed\n");
670 * e1000_set_default_fc_generic - Set flow control default values
671 * @hw: pointer to the HW structure
673 * Read the EEPROM for the default values for flow control and store the
676 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
682 * Read and store word 0x0F of the EEPROM. This word contains bits
683 * that determine the hardware's default PAUSE (flow control) mode,
684 * a bit that determines whether the HW defaults to enabling or
685 * disabling auto-negotiation, and the direction of the
686 * SW defined pins. If there is no SW over-ride of the flow
687 * control setting, then the variable hw->fc will
688 * be initialized based on a value in the EEPROM.
690 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
693 e_dbg("NVM Read Error\n");
697 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
698 hw->fc.requested_mode = e1000_fc_none;
699 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
701 hw->fc.requested_mode = e1000_fc_tx_pause;
703 hw->fc.requested_mode = e1000_fc_full;
709 * e1000e_setup_link - Setup flow control and link settings
710 * @hw: pointer to the HW structure
712 * Determines which flow control settings to use, then configures flow
713 * control. Calls the appropriate media-specific link configuration
714 * function. Assuming the adapter has a valid link partner, a valid link
715 * should be established. Assumes the hardware has previously been reset
716 * and the transmitter and receiver are not enabled.
718 s32 e1000e_setup_link(struct e1000_hw *hw)
720 struct e1000_mac_info *mac = &hw->mac;
724 * In the case of the phy reset being blocked, we already have a link.
725 * We do not need to set it up again.
727 if (e1000_check_reset_block(hw))
731 * If requested flow control is set to default, set flow control
732 * based on the EEPROM flow control settings.
734 if (hw->fc.requested_mode == e1000_fc_default) {
735 ret_val = e1000_set_default_fc_generic(hw);
741 * Save off the requested flow control mode for use later. Depending
742 * on the link partner's capabilities, we may or may not use this mode.
744 hw->fc.current_mode = hw->fc.requested_mode;
746 e_dbg("After fix-ups FlowControl is now = %x\n",
747 hw->fc.current_mode);
749 /* Call the necessary media_type subroutine to configure the link. */
750 ret_val = mac->ops.setup_physical_interface(hw);
755 * Initialize the flow control address, type, and PAUSE timer
756 * registers to their default values. This is done even if flow
757 * control is disabled, because it does not hurt anything to
758 * initialize these registers.
760 e_dbg("Initializing the Flow Control address, type and timer regs\n");
761 ew32(FCT, FLOW_CONTROL_TYPE);
762 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
763 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
765 ew32(FCTTV, hw->fc.pause_time);
767 return e1000e_set_fc_watermarks(hw);
771 * e1000_commit_fc_settings_generic - Configure flow control
772 * @hw: pointer to the HW structure
774 * Write the flow control settings to the Transmit Config Word Register (TXCW)
775 * base on the flow control settings in e1000_mac_info.
777 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
779 struct e1000_mac_info *mac = &hw->mac;
783 * Check for a software override of the flow control settings, and
784 * setup the device accordingly. If auto-negotiation is enabled, then
785 * software will have to set the "PAUSE" bits to the correct value in
786 * the Transmit Config Word Register (TXCW) and re-start auto-
787 * negotiation. However, if auto-negotiation is disabled, then
788 * software will have to manually configure the two flow control enable
789 * bits in the CTRL register.
791 * The possible values of the "fc" parameter are:
792 * 0: Flow control is completely disabled
793 * 1: Rx flow control is enabled (we can receive pause frames,
794 * but not send pause frames).
795 * 2: Tx flow control is enabled (we can send pause frames but we
796 * do not support receiving pause frames).
797 * 3: Both Rx and Tx flow control (symmetric) are enabled.
799 switch (hw->fc.current_mode) {
801 /* Flow control completely disabled by a software over-ride. */
802 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
804 case e1000_fc_rx_pause:
806 * Rx Flow control is enabled and Tx Flow control is disabled
807 * by a software over-ride. Since there really isn't a way to
808 * advertise that we are capable of Rx Pause ONLY, we will
809 * advertise that we support both symmetric and asymmetric Rx
810 * PAUSE. Later, we will disable the adapter's ability to send
813 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
815 case e1000_fc_tx_pause:
817 * Tx Flow control is enabled, and Rx Flow control is disabled,
818 * by a software over-ride.
820 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
824 * Flow control (both Rx and Tx) is enabled by a software
827 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
830 e_dbg("Flow control param set incorrectly\n");
831 return -E1000_ERR_CONFIG;
842 * e1000_poll_fiber_serdes_link_generic - Poll for link up
843 * @hw: pointer to the HW structure
845 * Polls for link up by reading the status register, if link fails to come
846 * up with auto-negotiation, then the link is forced if a signal is detected.
848 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
850 struct e1000_mac_info *mac = &hw->mac;
855 * If we have a signal (the cable is plugged in, or assumed true for
856 * serdes media) then poll for a "Link-Up" indication in the Device
857 * Status Register. Time-out if a link isn't seen in 500 milliseconds
858 * seconds (Auto-negotiation should complete in less than 500
859 * milliseconds even if the other end is doing it in SW).
861 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
863 status = er32(STATUS);
864 if (status & E1000_STATUS_LU)
867 if (i == FIBER_LINK_UP_LIMIT) {
868 e_dbg("Never got a valid link from auto-neg!!!\n");
869 mac->autoneg_failed = 1;
871 * AutoNeg failed to achieve a link, so we'll call
872 * mac->check_for_link. This routine will force the
873 * link up if we detect a signal. This will allow us to
874 * communicate with non-autonegotiating link partners.
876 ret_val = mac->ops.check_for_link(hw);
878 e_dbg("Error while checking for link\n");
881 mac->autoneg_failed = 0;
883 mac->autoneg_failed = 0;
884 e_dbg("Valid Link Found\n");
891 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
892 * @hw: pointer to the HW structure
894 * Configures collision distance and flow control for fiber and serdes
895 * links. Upon successful setup, poll for link.
897 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
904 /* Take the link out of reset */
905 ctrl &= ~E1000_CTRL_LRST;
907 e1000e_config_collision_dist(hw);
909 ret_val = e1000_commit_fc_settings_generic(hw);
914 * Since auto-negotiation is enabled, take the link out of reset (the
915 * link will be in reset, because we previously reset the chip). This
916 * will restart auto-negotiation. If auto-negotiation is successful
917 * then the link-up status bit will be set and the flow control enable
918 * bits (RFCE and TFCE) will be set according to their negotiated value.
920 e_dbg("Auto-negotiation enabled\n");
927 * For these adapters, the SW definable pin 1 is set when the optics
928 * detect a signal. If we have a signal, then poll for a "Link-Up"
931 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
932 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
933 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
935 e_dbg("No signal detected\n");
942 * e1000e_config_collision_dist - Configure collision distance
943 * @hw: pointer to the HW structure
945 * Configures the collision distance to the default value and is used
946 * during link setup. Currently no func pointer exists and all
947 * implementations are handled in the generic version of this function.
949 void e1000e_config_collision_dist(struct e1000_hw *hw)
955 tctl &= ~E1000_TCTL_COLD;
956 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
963 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
964 * @hw: pointer to the HW structure
966 * Sets the flow control high/low threshold (watermark) registers. If
967 * flow control XON frame transmission is enabled, then set XON frame
968 * transmission as well.
970 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
972 u32 fcrtl = 0, fcrth = 0;
975 * Set the flow control receive threshold registers. Normally,
976 * these registers will be set to a default threshold that may be
977 * adjusted later by the driver's runtime code. However, if the
978 * ability to transmit pause frames is not enabled, then these
979 * registers will be set to 0.
981 if (hw->fc.current_mode & e1000_fc_tx_pause) {
983 * We need to set up the Receive Threshold high and low water
984 * marks as well as (optionally) enabling the transmission of
987 fcrtl = hw->fc.low_water;
988 fcrtl |= E1000_FCRTL_XONE;
989 fcrth = hw->fc.high_water;
998 * e1000e_force_mac_fc - Force the MAC's flow control settings
999 * @hw: pointer to the HW structure
1001 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1002 * device control register to reflect the adapter settings. TFCE and RFCE
1003 * need to be explicitly set by software when a copper PHY is used because
1004 * autonegotiation is managed by the PHY rather than the MAC. Software must
1005 * also configure these bits when link is forced on a fiber connection.
1007 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1014 * Because we didn't get link via the internal auto-negotiation
1015 * mechanism (we either forced link or we got link via PHY
1016 * auto-neg), we have to manually enable/disable transmit an
1017 * receive flow control.
1019 * The "Case" statement below enables/disable flow control
1020 * according to the "hw->fc.current_mode" parameter.
1022 * The possible values of the "fc" parameter are:
1023 * 0: Flow control is completely disabled
1024 * 1: Rx flow control is enabled (we can receive pause
1025 * frames but not send pause frames).
1026 * 2: Tx flow control is enabled (we can send pause frames
1027 * frames but we do not receive pause frames).
1028 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1029 * other: No other values should be possible at this point.
1031 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1033 switch (hw->fc.current_mode) {
1035 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1037 case e1000_fc_rx_pause:
1038 ctrl &= (~E1000_CTRL_TFCE);
1039 ctrl |= E1000_CTRL_RFCE;
1041 case e1000_fc_tx_pause:
1042 ctrl &= (~E1000_CTRL_RFCE);
1043 ctrl |= E1000_CTRL_TFCE;
1046 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1049 e_dbg("Flow control param set incorrectly\n");
1050 return -E1000_ERR_CONFIG;
1059 * e1000e_config_fc_after_link_up - Configures flow control after link
1060 * @hw: pointer to the HW structure
1062 * Checks the status of auto-negotiation after link up to ensure that the
1063 * speed and duplex were not forced. If the link needed to be forced, then
1064 * flow control needs to be forced also. If auto-negotiation is enabled
1065 * and did not fail, then we configure flow control based on our link
1068 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1070 struct e1000_mac_info *mac = &hw->mac;
1072 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1076 * Check for the case where we have fiber media and auto-neg failed
1077 * so we had to force link. In this case, we need to force the
1078 * configuration of the MAC to match the "fc" parameter.
1080 if (mac->autoneg_failed) {
1081 if (hw->phy.media_type == e1000_media_type_fiber ||
1082 hw->phy.media_type == e1000_media_type_internal_serdes)
1083 ret_val = e1000e_force_mac_fc(hw);
1085 if (hw->phy.media_type == e1000_media_type_copper)
1086 ret_val = e1000e_force_mac_fc(hw);
1090 e_dbg("Error forcing flow control settings\n");
1095 * Check for the case where we have copper media and auto-neg is
1096 * enabled. In this case, we need to check and see if Auto-Neg
1097 * has completed, and if so, how the PHY and link partner has
1098 * flow control configured.
1100 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1102 * Read the MII Status Register and check to see if AutoNeg
1103 * has completed. We read this twice because this reg has
1104 * some "sticky" (latched) bits.
1106 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1109 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1113 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1114 e_dbg("Copper PHY and Auto Neg "
1115 "has not completed.\n");
1120 * The AutoNeg process has completed, so we now need to
1121 * read both the Auto Negotiation Advertisement
1122 * Register (Address 4) and the Auto_Negotiation Base
1123 * Page Ability Register (Address 5) to determine how
1124 * flow control was negotiated.
1126 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1129 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1134 * Two bits in the Auto Negotiation Advertisement Register
1135 * (Address 4) and two bits in the Auto Negotiation Base
1136 * Page Ability Register (Address 5) determine flow control
1137 * for both the PHY and the link partner. The following
1138 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1139 * 1999, describes these PAUSE resolution bits and how flow
1140 * control is determined based upon these settings.
1141 * NOTE: DC = Don't Care
1143 * LOCAL DEVICE | LINK PARTNER
1144 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1145 *-------|---------|-------|---------|--------------------
1146 * 0 | 0 | DC | DC | e1000_fc_none
1147 * 0 | 1 | 0 | DC | e1000_fc_none
1148 * 0 | 1 | 1 | 0 | e1000_fc_none
1149 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1150 * 1 | 0 | 0 | DC | e1000_fc_none
1151 * 1 | DC | 1 | DC | e1000_fc_full
1152 * 1 | 1 | 0 | 0 | e1000_fc_none
1153 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1155 * Are both PAUSE bits set to 1? If so, this implies
1156 * Symmetric Flow Control is enabled at both ends. The
1157 * ASM_DIR bits are irrelevant per the spec.
1159 * For Symmetric Flow Control:
1161 * LOCAL DEVICE | LINK PARTNER
1162 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1163 *-------|---------|-------|---------|--------------------
1164 * 1 | DC | 1 | DC | E1000_fc_full
1167 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1168 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1170 * Now we need to check if the user selected Rx ONLY
1171 * of pause frames. In this case, we had to advertise
1172 * FULL flow control because we could not advertise Rx
1173 * ONLY. Hence, we must now check to see if we need to
1174 * turn OFF the TRANSMISSION of PAUSE frames.
1176 if (hw->fc.requested_mode == e1000_fc_full) {
1177 hw->fc.current_mode = e1000_fc_full;
1178 e_dbg("Flow Control = FULL.\r\n");
1180 hw->fc.current_mode = e1000_fc_rx_pause;
1181 e_dbg("Flow Control = "
1182 "RX PAUSE frames only.\r\n");
1186 * For receiving PAUSE frames ONLY.
1188 * LOCAL DEVICE | LINK PARTNER
1189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1190 *-------|---------|-------|---------|--------------------
1191 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1193 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1194 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1195 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1196 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1197 hw->fc.current_mode = e1000_fc_tx_pause;
1198 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1201 * For transmitting PAUSE frames ONLY.
1203 * LOCAL DEVICE | LINK PARTNER
1204 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1205 *-------|---------|-------|---------|--------------------
1206 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1208 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1209 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1210 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1211 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1212 hw->fc.current_mode = e1000_fc_rx_pause;
1213 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1216 * Per the IEEE spec, at this point flow control
1217 * should be disabled.
1219 hw->fc.current_mode = e1000_fc_none;
1220 e_dbg("Flow Control = NONE.\r\n");
1224 * Now we need to do one last check... If we auto-
1225 * negotiated to HALF DUPLEX, flow control should not be
1226 * enabled per IEEE 802.3 spec.
1228 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1230 e_dbg("Error getting link speed and duplex\n");
1234 if (duplex == HALF_DUPLEX)
1235 hw->fc.current_mode = e1000_fc_none;
1238 * Now we call a subroutine to actually force the MAC
1239 * controller to use the correct flow control settings.
1241 ret_val = e1000e_force_mac_fc(hw);
1243 e_dbg("Error forcing flow control settings\n");
1252 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1253 * @hw: pointer to the HW structure
1254 * @speed: stores the current speed
1255 * @duplex: stores the current duplex
1257 * Read the status register for the current speed/duplex and store the current
1258 * speed and duplex for copper connections.
1260 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1264 status = er32(STATUS);
1265 if (status & E1000_STATUS_SPEED_1000)
1266 *speed = SPEED_1000;
1267 else if (status & E1000_STATUS_SPEED_100)
1272 if (status & E1000_STATUS_FD)
1273 *duplex = FULL_DUPLEX;
1275 *duplex = HALF_DUPLEX;
1277 e_dbg("%u Mbps, %s Duplex\n",
1278 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10,
1279 *duplex == FULL_DUPLEX ? "Full" : "Half");
1285 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1286 * @hw: pointer to the HW structure
1287 * @speed: stores the current speed
1288 * @duplex: stores the current duplex
1290 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1291 * for fiber/serdes links.
1293 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1295 *speed = SPEED_1000;
1296 *duplex = FULL_DUPLEX;
1302 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1303 * @hw: pointer to the HW structure
1305 * Acquire the HW semaphore to access the PHY or NVM
1307 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1310 s32 timeout = hw->nvm.word_size + 1;
1313 /* Get the SW semaphore */
1314 while (i < timeout) {
1316 if (!(swsm & E1000_SWSM_SMBI))
1324 e_dbg("Driver can't access device - SMBI bit is set.\n");
1325 return -E1000_ERR_NVM;
1328 /* Get the FW semaphore. */
1329 for (i = 0; i < timeout; i++) {
1331 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1333 /* Semaphore acquired if bit latched */
1334 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1341 /* Release semaphores */
1342 e1000e_put_hw_semaphore(hw);
1343 e_dbg("Driver can't access the NVM\n");
1344 return -E1000_ERR_NVM;
1351 * e1000e_put_hw_semaphore - Release hardware semaphore
1352 * @hw: pointer to the HW structure
1354 * Release hardware semaphore used to access the PHY or NVM
1356 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1361 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1366 * e1000e_get_auto_rd_done - Check for auto read completion
1367 * @hw: pointer to the HW structure
1369 * Check EEPROM for Auto Read done bit.
1371 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1375 while (i < AUTO_READ_DONE_TIMEOUT) {
1376 if (er32(EECD) & E1000_EECD_AUTO_RD)
1382 if (i == AUTO_READ_DONE_TIMEOUT) {
1383 e_dbg("Auto read by HW from NVM has not completed.\n");
1384 return -E1000_ERR_RESET;
1391 * e1000e_valid_led_default - Verify a valid default LED config
1392 * @hw: pointer to the HW structure
1393 * @data: pointer to the NVM (EEPROM)
1395 * Read the EEPROM for the current default LED configuration. If the
1396 * LED configuration is not valid, set to a valid LED configuration.
1398 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1402 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1404 e_dbg("NVM Read Error\n");
1408 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1409 *data = ID_LED_DEFAULT;
1415 * e1000e_id_led_init -
1416 * @hw: pointer to the HW structure
1419 s32 e1000e_id_led_init(struct e1000_hw *hw)
1421 struct e1000_mac_info *mac = &hw->mac;
1423 const u32 ledctl_mask = 0x000000FF;
1424 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1425 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1427 const u16 led_mask = 0x0F;
1429 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1433 mac->ledctl_default = er32(LEDCTL);
1434 mac->ledctl_mode1 = mac->ledctl_default;
1435 mac->ledctl_mode2 = mac->ledctl_default;
1437 for (i = 0; i < 4; i++) {
1438 temp = (data >> (i << 2)) & led_mask;
1440 case ID_LED_ON1_DEF2:
1441 case ID_LED_ON1_ON2:
1442 case ID_LED_ON1_OFF2:
1443 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1444 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1446 case ID_LED_OFF1_DEF2:
1447 case ID_LED_OFF1_ON2:
1448 case ID_LED_OFF1_OFF2:
1449 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1450 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1457 case ID_LED_DEF1_ON2:
1458 case ID_LED_ON1_ON2:
1459 case ID_LED_OFF1_ON2:
1460 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1461 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1463 case ID_LED_DEF1_OFF2:
1464 case ID_LED_ON1_OFF2:
1465 case ID_LED_OFF1_OFF2:
1466 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1467 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1479 * e1000e_setup_led_generic - Configures SW controllable LED
1480 * @hw: pointer to the HW structure
1482 * This prepares the SW controllable LED for use and saves the current state
1483 * of the LED so it can be later restored.
1485 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1489 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1490 return -E1000_ERR_CONFIG;
1493 if (hw->phy.media_type == e1000_media_type_fiber) {
1494 ledctl = er32(LEDCTL);
1495 hw->mac.ledctl_default = ledctl;
1497 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1498 E1000_LEDCTL_LED0_BLINK |
1499 E1000_LEDCTL_LED0_MODE_MASK);
1500 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1501 E1000_LEDCTL_LED0_MODE_SHIFT);
1502 ew32(LEDCTL, ledctl);
1503 } else if (hw->phy.media_type == e1000_media_type_copper) {
1504 ew32(LEDCTL, hw->mac.ledctl_mode1);
1511 * e1000e_cleanup_led_generic - Set LED config to default operation
1512 * @hw: pointer to the HW structure
1514 * Remove the current LED configuration and set the LED configuration
1515 * to the default value, saved from the EEPROM.
1517 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1519 ew32(LEDCTL, hw->mac.ledctl_default);
1524 * e1000e_blink_led - Blink LED
1525 * @hw: pointer to the HW structure
1527 * Blink the LEDs which are set to be on.
1529 s32 e1000e_blink_led(struct e1000_hw *hw)
1531 u32 ledctl_blink = 0;
1534 if (hw->phy.media_type == e1000_media_type_fiber) {
1535 /* always blink LED0 for PCI-E fiber */
1536 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1537 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1540 * set the blink bit for each LED that's "on" (0x0E)
1543 ledctl_blink = hw->mac.ledctl_mode2;
1544 for (i = 0; i < 4; i++)
1545 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1546 E1000_LEDCTL_MODE_LED_ON)
1547 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1551 ew32(LEDCTL, ledctl_blink);
1557 * e1000e_led_on_generic - Turn LED on
1558 * @hw: pointer to the HW structure
1562 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1566 switch (hw->phy.media_type) {
1567 case e1000_media_type_fiber:
1569 ctrl &= ~E1000_CTRL_SWDPIN0;
1570 ctrl |= E1000_CTRL_SWDPIO0;
1573 case e1000_media_type_copper:
1574 ew32(LEDCTL, hw->mac.ledctl_mode2);
1584 * e1000e_led_off_generic - Turn LED off
1585 * @hw: pointer to the HW structure
1589 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1593 switch (hw->phy.media_type) {
1594 case e1000_media_type_fiber:
1596 ctrl |= E1000_CTRL_SWDPIN0;
1597 ctrl |= E1000_CTRL_SWDPIO0;
1600 case e1000_media_type_copper:
1601 ew32(LEDCTL, hw->mac.ledctl_mode1);
1611 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1612 * @hw: pointer to the HW structure
1613 * @no_snoop: bitmap of snoop events
1615 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1617 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1623 gcr &= ~(PCIE_NO_SNOOP_ALL);
1630 * e1000e_disable_pcie_master - Disables PCI-express master access
1631 * @hw: pointer to the HW structure
1633 * Returns 0 if successful, else returns -10
1634 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1635 * the master requests to be disabled.
1637 * Disables PCI-Express master access and verifies there are no pending
1640 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1643 s32 timeout = MASTER_DISABLE_TIMEOUT;
1646 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1650 if (!(er32(STATUS) &
1651 E1000_STATUS_GIO_MASTER_ENABLE))
1658 e_dbg("Master requests are pending.\n");
1659 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1666 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1667 * @hw: pointer to the HW structure
1669 * Reset the Adaptive Interframe Spacing throttle to default values.
1671 void e1000e_reset_adaptive(struct e1000_hw *hw)
1673 struct e1000_mac_info *mac = &hw->mac;
1675 if (!mac->adaptive_ifs) {
1676 e_dbg("Not in Adaptive IFS mode!\n");
1680 mac->current_ifs_val = 0;
1681 mac->ifs_min_val = IFS_MIN;
1682 mac->ifs_max_val = IFS_MAX;
1683 mac->ifs_step_size = IFS_STEP;
1684 mac->ifs_ratio = IFS_RATIO;
1686 mac->in_ifs_mode = false;
1693 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1694 * @hw: pointer to the HW structure
1696 * Update the Adaptive Interframe Spacing Throttle value based on the
1697 * time between transmitted packets and time between collisions.
1699 void e1000e_update_adaptive(struct e1000_hw *hw)
1701 struct e1000_mac_info *mac = &hw->mac;
1703 if (!mac->adaptive_ifs) {
1704 e_dbg("Not in Adaptive IFS mode!\n");
1708 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1709 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1710 mac->in_ifs_mode = true;
1711 if (mac->current_ifs_val < mac->ifs_max_val) {
1712 if (!mac->current_ifs_val)
1713 mac->current_ifs_val = mac->ifs_min_val;
1715 mac->current_ifs_val +=
1717 ew32(AIT, mac->current_ifs_val);
1721 if (mac->in_ifs_mode &&
1722 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1723 mac->current_ifs_val = 0;
1724 mac->in_ifs_mode = false;
1733 * e1000_raise_eec_clk - Raise EEPROM clock
1734 * @hw: pointer to the HW structure
1735 * @eecd: pointer to the EEPROM
1737 * Enable/Raise the EEPROM clock bit.
1739 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1741 *eecd = *eecd | E1000_EECD_SK;
1744 udelay(hw->nvm.delay_usec);
1748 * e1000_lower_eec_clk - Lower EEPROM clock
1749 * @hw: pointer to the HW structure
1750 * @eecd: pointer to the EEPROM
1752 * Clear/Lower the EEPROM clock bit.
1754 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1756 *eecd = *eecd & ~E1000_EECD_SK;
1759 udelay(hw->nvm.delay_usec);
1763 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1764 * @hw: pointer to the HW structure
1765 * @data: data to send to the EEPROM
1766 * @count: number of bits to shift out
1768 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1769 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1770 * In order to do this, "data" must be broken down into bits.
1772 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1774 struct e1000_nvm_info *nvm = &hw->nvm;
1775 u32 eecd = er32(EECD);
1778 mask = 0x01 << (count - 1);
1779 if (nvm->type == e1000_nvm_eeprom_spi)
1780 eecd |= E1000_EECD_DO;
1783 eecd &= ~E1000_EECD_DI;
1786 eecd |= E1000_EECD_DI;
1791 udelay(nvm->delay_usec);
1793 e1000_raise_eec_clk(hw, &eecd);
1794 e1000_lower_eec_clk(hw, &eecd);
1799 eecd &= ~E1000_EECD_DI;
1804 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1805 * @hw: pointer to the HW structure
1806 * @count: number of bits to shift in
1808 * In order to read a register from the EEPROM, we need to shift 'count' bits
1809 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1810 * the EEPROM (setting the SK bit), and then reading the value of the data out
1811 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1814 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1822 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1825 for (i = 0; i < count; i++) {
1827 e1000_raise_eec_clk(hw, &eecd);
1831 eecd &= ~E1000_EECD_DI;
1832 if (eecd & E1000_EECD_DO)
1835 e1000_lower_eec_clk(hw, &eecd);
1842 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1843 * @hw: pointer to the HW structure
1844 * @ee_reg: EEPROM flag for polling
1846 * Polls the EEPROM status bit for either read or write completion based
1847 * upon the value of 'ee_reg'.
1849 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1851 u32 attempts = 100000;
1854 for (i = 0; i < attempts; i++) {
1855 if (ee_reg == E1000_NVM_POLL_READ)
1860 if (reg & E1000_NVM_RW_REG_DONE)
1866 return -E1000_ERR_NVM;
1870 * e1000e_acquire_nvm - Generic request for access to EEPROM
1871 * @hw: pointer to the HW structure
1873 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1874 * Return successful if access grant bit set, else clear the request for
1875 * EEPROM access and return -E1000_ERR_NVM (-1).
1877 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1879 u32 eecd = er32(EECD);
1880 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1882 ew32(EECD, eecd | E1000_EECD_REQ);
1886 if (eecd & E1000_EECD_GNT)
1894 eecd &= ~E1000_EECD_REQ;
1896 e_dbg("Could not acquire NVM grant\n");
1897 return -E1000_ERR_NVM;
1904 * e1000_standby_nvm - Return EEPROM to standby state
1905 * @hw: pointer to the HW structure
1907 * Return the EEPROM to a standby state.
1909 static void e1000_standby_nvm(struct e1000_hw *hw)
1911 struct e1000_nvm_info *nvm = &hw->nvm;
1912 u32 eecd = er32(EECD);
1914 if (nvm->type == e1000_nvm_eeprom_spi) {
1915 /* Toggle CS to flush commands */
1916 eecd |= E1000_EECD_CS;
1919 udelay(nvm->delay_usec);
1920 eecd &= ~E1000_EECD_CS;
1923 udelay(nvm->delay_usec);
1928 * e1000_stop_nvm - Terminate EEPROM command
1929 * @hw: pointer to the HW structure
1931 * Terminates the current command by inverting the EEPROM's chip select pin.
1933 static void e1000_stop_nvm(struct e1000_hw *hw)
1938 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1940 eecd |= E1000_EECD_CS;
1941 e1000_lower_eec_clk(hw, &eecd);
1946 * e1000e_release_nvm - Release exclusive access to EEPROM
1947 * @hw: pointer to the HW structure
1949 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1951 void e1000e_release_nvm(struct e1000_hw *hw)
1958 eecd &= ~E1000_EECD_REQ;
1963 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1964 * @hw: pointer to the HW structure
1966 * Setups the EEPROM for reading and writing.
1968 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1970 struct e1000_nvm_info *nvm = &hw->nvm;
1971 u32 eecd = er32(EECD);
1975 if (nvm->type == e1000_nvm_eeprom_spi) {
1976 /* Clear SK and CS */
1977 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1980 timeout = NVM_MAX_RETRY_SPI;
1983 * Read "Status Register" repeatedly until the LSB is cleared.
1984 * The EEPROM will signal that the command has been completed
1985 * by clearing bit 0 of the internal status register. If it's
1986 * not cleared within 'timeout', then error out.
1989 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1990 hw->nvm.opcode_bits);
1991 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1992 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1996 e1000_standby_nvm(hw);
2001 e_dbg("SPI NVM Status error\n");
2002 return -E1000_ERR_NVM;
2010 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2011 * @hw: pointer to the HW structure
2012 * @offset: offset of word in the EEPROM to read
2013 * @words: number of words to read
2014 * @data: word read from the EEPROM
2016 * Reads a 16 bit word from the EEPROM using the EERD register.
2018 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2020 struct e1000_nvm_info *nvm = &hw->nvm;
2025 * A check for invalid values: offset too large, too many words,
2026 * too many words for the offset, and not enough words.
2028 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2030 e_dbg("nvm parameter(s) out of bounds\n");
2031 return -E1000_ERR_NVM;
2034 for (i = 0; i < words; i++) {
2035 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2036 E1000_NVM_RW_REG_START;
2039 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2043 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2050 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2051 * @hw: pointer to the HW structure
2052 * @offset: offset within the EEPROM to be written to
2053 * @words: number of words to write
2054 * @data: 16 bit word(s) to be written to the EEPROM
2056 * Writes data to EEPROM at offset using SPI interface.
2058 * If e1000e_update_nvm_checksum is not called after this function , the
2059 * EEPROM will most likely contain an invalid checksum.
2061 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2063 struct e1000_nvm_info *nvm = &hw->nvm;
2068 * A check for invalid values: offset too large, too many words,
2069 * and not enough words.
2071 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2073 e_dbg("nvm parameter(s) out of bounds\n");
2074 return -E1000_ERR_NVM;
2077 ret_val = nvm->ops.acquire(hw);
2083 while (widx < words) {
2084 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2086 ret_val = e1000_ready_nvm_eeprom(hw);
2088 nvm->ops.release(hw);
2092 e1000_standby_nvm(hw);
2094 /* Send the WRITE ENABLE command (8 bit opcode) */
2095 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2098 e1000_standby_nvm(hw);
2101 * Some SPI eeproms use the 8th address bit embedded in the
2104 if ((nvm->address_bits == 8) && (offset >= 128))
2105 write_opcode |= NVM_A8_OPCODE_SPI;
2107 /* Send the Write command (8-bit opcode + addr) */
2108 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2109 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2112 /* Loop to allow for up to whole page write of eeprom */
2113 while (widx < words) {
2114 u16 word_out = data[widx];
2115 word_out = (word_out >> 8) | (word_out << 8);
2116 e1000_shift_out_eec_bits(hw, word_out, 16);
2119 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2120 e1000_standby_nvm(hw);
2127 nvm->ops.release(hw);
2132 * e1000_read_mac_addr_generic - Read device MAC address
2133 * @hw: pointer to the HW structure
2135 * Reads the device MAC address from the EEPROM and stores the value.
2136 * Since devices with two ports use the same EEPROM, we increment the
2137 * last bit in the MAC address for the second port.
2139 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2145 rar_high = er32(RAH(0));
2146 rar_low = er32(RAL(0));
2148 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2149 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2151 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2152 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2154 for (i = 0; i < ETH_ALEN; i++)
2155 hw->mac.addr[i] = hw->mac.perm_addr[i];
2161 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2162 * @hw: pointer to the HW structure
2164 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2165 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2167 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2173 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2174 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2176 e_dbg("NVM Read Error\n");
2179 checksum += nvm_data;
2182 if (checksum != (u16) NVM_SUM) {
2183 e_dbg("NVM Checksum Invalid\n");
2184 return -E1000_ERR_NVM;
2191 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2192 * @hw: pointer to the HW structure
2194 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2195 * up to the checksum. Then calculates the EEPROM checksum and writes the
2196 * value to the EEPROM.
2198 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2204 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2205 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2207 e_dbg("NVM Read Error while updating checksum.\n");
2210 checksum += nvm_data;
2212 checksum = (u16) NVM_SUM - checksum;
2213 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2215 e_dbg("NVM Write Error while updating checksum.\n");
2221 * e1000e_reload_nvm - Reloads EEPROM
2222 * @hw: pointer to the HW structure
2224 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2225 * extended control register.
2227 void e1000e_reload_nvm(struct e1000_hw *hw)
2232 ctrl_ext = er32(CTRL_EXT);
2233 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2234 ew32(CTRL_EXT, ctrl_ext);
2239 * e1000_calculate_checksum - Calculate checksum for buffer
2240 * @buffer: pointer to EEPROM
2241 * @length: size of EEPROM to calculate a checksum for
2243 * Calculates the checksum for some buffer on a specified length. The
2244 * checksum calculated is returned.
2246 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2254 for (i = 0; i < length; i++)
2257 return (u8) (0 - sum);
2261 * e1000_mng_enable_host_if - Checks host interface is enabled
2262 * @hw: pointer to the HW structure
2264 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2266 * This function checks whether the HOST IF is enabled for command operation
2267 * and also checks whether the previous command is completed. It busy waits
2268 * in case of previous command is not completed.
2270 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2275 if (!(hw->mac.arc_subsystem_valid)) {
2276 e_dbg("ARC subsystem not valid.\n");
2277 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2280 /* Check that the host interface is enabled. */
2282 if ((hicr & E1000_HICR_EN) == 0) {
2283 e_dbg("E1000_HOST_EN bit disabled.\n");
2284 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2286 /* check the previous command is completed */
2287 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2289 if (!(hicr & E1000_HICR_C))
2294 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2295 e_dbg("Previous command timeout failed .\n");
2296 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2303 * e1000e_check_mng_mode_generic - check management mode
2304 * @hw: pointer to the HW structure
2306 * Reads the firmware semaphore register and returns true (>0) if
2307 * manageability is enabled, else false (0).
2309 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2311 u32 fwsm = er32(FWSM);
2313 return (fwsm & E1000_FWSM_MODE_MASK) ==
2314 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2318 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2319 * @hw: pointer to the HW structure
2321 * Enables packet filtering on transmit packets if manageability is enabled
2322 * and host interface is enabled.
2324 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2326 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2327 u32 *buffer = (u32 *)&hw->mng_cookie;
2329 s32 ret_val, hdr_csum, csum;
2332 hw->mac.tx_pkt_filtering = true;
2334 /* No manageability, no filtering */
2335 if (!e1000e_check_mng_mode(hw)) {
2336 hw->mac.tx_pkt_filtering = false;
2341 * If we can't read from the host interface for whatever
2342 * reason, disable filtering.
2344 ret_val = e1000_mng_enable_host_if(hw);
2346 hw->mac.tx_pkt_filtering = false;
2350 /* Read in the header. Length and offset are in dwords. */
2351 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2352 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2353 for (i = 0; i < len; i++)
2354 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2355 hdr_csum = hdr->checksum;
2357 csum = e1000_calculate_checksum((u8 *)hdr,
2358 E1000_MNG_DHCP_COOKIE_LENGTH);
2360 * If either the checksums or signature don't match, then
2361 * the cookie area isn't considered valid, in which case we
2362 * take the safe route of assuming Tx filtering is enabled.
2364 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2365 hw->mac.tx_pkt_filtering = true;
2369 /* Cookie area is valid, make the final check for filtering. */
2370 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2371 hw->mac.tx_pkt_filtering = false;
2376 return hw->mac.tx_pkt_filtering;
2380 * e1000_mng_write_cmd_header - Writes manageability command header
2381 * @hw: pointer to the HW structure
2382 * @hdr: pointer to the host interface command header
2384 * Writes the command header after does the checksum calculation.
2386 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2387 struct e1000_host_mng_command_header *hdr)
2389 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2391 /* Write the whole command header structure with new checksum. */
2393 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2396 /* Write the relevant command block into the ram area. */
2397 for (i = 0; i < length; i++) {
2398 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2399 *((u32 *) hdr + i));
2407 * e1000_mng_host_if_write - Write to the manageability host interface
2408 * @hw: pointer to the HW structure
2409 * @buffer: pointer to the host interface buffer
2410 * @length: size of the buffer
2411 * @offset: location in the buffer to write to
2412 * @sum: sum of the data (not checksum)
2414 * This function writes the buffer content at the offset given on the host if.
2415 * It also does alignment considerations to do the writes in most efficient
2416 * way. Also fills up the sum of the buffer in *buffer parameter.
2418 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2419 u16 length, u16 offset, u8 *sum)
2422 u8 *bufptr = buffer;
2424 u16 remaining, i, j, prev_bytes;
2426 /* sum = only sum of the data and it is not checksum */
2428 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2429 return -E1000_ERR_PARAM;
2432 prev_bytes = offset & 0x3;
2436 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2437 for (j = prev_bytes; j < sizeof(u32); j++) {
2438 *(tmp + j) = *bufptr++;
2441 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2442 length -= j - prev_bytes;
2446 remaining = length & 0x3;
2447 length -= remaining;
2449 /* Calculate length in DWORDs */
2453 * The device driver writes the relevant command block into the
2456 for (i = 0; i < length; i++) {
2457 for (j = 0; j < sizeof(u32); j++) {
2458 *(tmp + j) = *bufptr++;
2462 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2465 for (j = 0; j < sizeof(u32); j++) {
2467 *(tmp + j) = *bufptr++;
2473 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2480 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2481 * @hw: pointer to the HW structure
2482 * @buffer: pointer to the host interface
2483 * @length: size of the buffer
2485 * Writes the DHCP information to the host interface.
2487 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2489 struct e1000_host_mng_command_header hdr;
2493 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2494 hdr.command_length = length;
2499 /* Enable the host interface */
2500 ret_val = e1000_mng_enable_host_if(hw);
2504 /* Populate the host interface with the contents of "buffer". */
2505 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2506 sizeof(hdr), &(hdr.checksum));
2510 /* Write the manageability command header */
2511 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2515 /* Tell the ARC a new command is pending. */
2517 ew32(HICR, hicr | E1000_HICR_C);
2523 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2524 * @hw: pointer to the HW structure
2526 * Verifies the hardware needs to leave interface enabled so that frames can
2527 * be directed to and from the management interface.
2529 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2533 bool ret_val = false;
2537 if (!(manc & E1000_MANC_RCV_TCO_EN))
2540 if (hw->mac.has_fwsm) {
2542 factps = er32(FACTPS);
2544 if (!(factps & E1000_FACTPS_MNGCG) &&
2545 ((fwsm & E1000_FWSM_MODE_MASK) ==
2546 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2550 } else if ((hw->mac.type == e1000_82574) ||
2551 (hw->mac.type == e1000_82583)) {
2554 factps = er32(FACTPS);
2555 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2557 if (!(factps & E1000_FACTPS_MNGCG) &&
2558 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2559 (e1000_mng_mode_pt << 13))) {
2563 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2564 !(manc & E1000_MANC_ASF_EN)) {
2573 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2578 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2580 e_dbg("NVM Read Error\n");
2583 *pba_num = (u32)(nvm_data << 16);
2585 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2587 e_dbg("NVM Read Error\n");
2590 *pba_num |= nvm_data;