1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_bus_info *bus = &hw->bus;
55 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, pci_header_type, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
73 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
74 status = er32(STATUS);
75 bus->func = (status & E1000_STATUS_FUNC_MASK)
76 >> E1000_STATUS_FUNC_SHIFT;
85 * e1000e_write_vfta - Write value to VLAN filter table
86 * @hw: pointer to the HW structure
87 * @offset: register offset in VLAN filter table
88 * @value: register value written to VLAN filter table
90 * Writes value at the given offset in the register array which stores
91 * the VLAN filter table.
93 void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
95 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
100 * e1000e_init_rx_addrs - Initialize receive address's
101 * @hw: pointer to the HW structure
102 * @rar_count: receive address registers
104 * Setups the receive address registers by setting the base receive address
105 * register to the devices MAC address and clearing all the other receive
106 * address registers to 0.
108 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
112 /* Setup the receive address */
113 hw_dbg(hw, "Programming MAC Address into RAR[0]\n");
115 e1000e_rar_set(hw, hw->mac.addr, 0);
117 /* Zero out the other (rar_entry_count - 1) receive addresses */
118 hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);
119 for (i = 1; i < rar_count; i++) {
120 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
122 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
128 * e1000e_rar_set - Set receive address register
129 * @hw: pointer to the HW structure
130 * @addr: pointer to the receive address
131 * @index: receive address array register
133 * Sets the receive address array register at index to the address passed
136 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
138 u32 rar_low, rar_high;
141 * HW expects these in little endian so we reverse the byte order
142 * from network order (big endian) to little endian
144 rar_low = ((u32) addr[0] |
145 ((u32) addr[1] << 8) |
146 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
148 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
150 rar_high |= E1000_RAH_AV;
152 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
153 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
157 * e1000_hash_mc_addr - Generate a multicast hash value
158 * @hw: pointer to the HW structure
159 * @mc_addr: pointer to a multicast address
161 * Generates a multicast address hash value which is used to determine
162 * the multicast filter table array address and new table value. See
163 * e1000_mta_set_generic()
165 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
167 u32 hash_value, hash_mask;
170 /* Register count multiplied by bits per register */
171 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
174 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
175 * where 0xFF would still fall within the hash mask.
177 while (hash_mask >> bit_shift != 0xFF)
181 * The portion of the address that is used for the hash table
182 * is determined by the mc_filter_type setting.
183 * The algorithm is such that there is a total of 8 bits of shifting.
184 * The bit_shift for a mc_filter_type of 0 represents the number of
185 * left-shifts where the MSB of mc_addr[5] would still fall within
186 * the hash_mask. Case 0 does this exactly. Since there are a total
187 * of 8 bits of shifting, then mc_addr[4] will shift right the
188 * remaining number of bits. Thus 8 - bit_shift. The rest of the
189 * cases are a variation of this algorithm...essentially raising the
190 * number of bits to shift mc_addr[5] left, while still keeping the
191 * 8-bit shifting total.
193 * For example, given the following Destination MAC Address and an
194 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
195 * we can see that the bit_shift for case 0 is 4. These are the hash
196 * values resulting from each mc_filter_type...
197 * [0] [1] [2] [3] [4] [5]
201 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
202 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
203 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
204 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
206 switch (hw->mac.mc_filter_type) {
221 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
222 (((u16) mc_addr[5]) << bit_shift)));
228 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
229 * @hw: pointer to the HW structure
230 * @mc_addr_list: array of multicast addresses to program
231 * @mc_addr_count: number of multicast addresses to program
232 * @rar_used_count: the first RAR register free to program
233 * @rar_count: total number of supported Receive Address Registers
235 * Updates the Receive Address Registers and Multicast Table Array.
236 * The caller must have a packed mc_addr_list of multicast addresses.
237 * The parameter rar_count will usually be hw->mac.rar_entry_count
238 * unless there are workarounds that change this.
240 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
241 u8 *mc_addr_list, u32 mc_addr_count,
242 u32 rar_used_count, u32 rar_count)
245 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
248 printk(KERN_ERR "multicast array memory allocation failed\n");
253 * Load the first set of multicast addresses into the exact
254 * filters (RAR). If there are not enough to fill the RAR
255 * array, clear the filters.
257 for (i = rar_used_count; i < rar_count; i++) {
259 e1000e_rar_set(hw, mc_addr_list, i);
261 mc_addr_list += ETH_ALEN;
263 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
265 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
270 /* Load any remaining multicast addresses into the hash table. */
271 for (; mc_addr_count > 0; mc_addr_count--) {
272 u32 hash_value, hash_reg, hash_bit, mta;
273 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
274 hw_dbg(hw, "Hash value = 0x%03X\n", hash_value);
275 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
276 hash_bit = hash_value & 0x1F;
277 mta = (1 << hash_bit);
278 mcarray[hash_reg] |= mta;
279 mc_addr_list += ETH_ALEN;
282 /* write the hash table completely */
283 for (i = 0; i < hw->mac.mta_reg_count; i++)
284 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
291 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
292 * @hw: pointer to the HW structure
294 * Clears the base hardware counters by reading the counter registers.
296 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
300 temp = er32(CRCERRS);
301 temp = er32(SYMERRS);
306 temp = er32(LATECOL);
313 temp = er32(XOFFRXC);
314 temp = er32(XOFFTXC);
340 * e1000e_check_for_copper_link - Check for link (Copper)
341 * @hw: pointer to the HW structure
343 * Checks to see of the link status of the hardware has changed. If a
344 * change in link status has been detected, then we read the PHY registers
345 * to get the current speed/duplex if link exists.
347 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
349 struct e1000_mac_info *mac = &hw->mac;
354 * We only want to go out to the PHY registers to see if Auto-Neg
355 * has completed and/or if our link status has changed. The
356 * get_link_status flag is set upon receiving a Link Status
357 * Change or Rx Sequence Error interrupt.
359 if (!mac->get_link_status)
363 * First we want to see if the MII Status Register reports
364 * link. If so, then we want to get the current speed/duplex
367 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
372 return ret_val; /* No link detected */
374 mac->get_link_status = 0;
377 * Check if there was DownShift, must be checked
378 * immediately after link-up
380 e1000e_check_downshift(hw);
383 * If we are forcing speed/duplex, then we simply return since
384 * we have already determined whether we have link or not.
387 ret_val = -E1000_ERR_CONFIG;
392 * Auto-Neg is enabled. Auto Speed Detection takes care
393 * of MAC speed/duplex configuration. So we only need to
394 * configure Collision Distance in the MAC.
396 e1000e_config_collision_dist(hw);
399 * Configure Flow Control now that Auto-Neg has completed.
400 * First, we need to restore the desired flow control
401 * settings because we may have had to re-autoneg with a
402 * different link partner.
404 ret_val = e1000e_config_fc_after_link_up(hw);
406 hw_dbg(hw, "Error configuring flow control\n");
413 * e1000e_check_for_fiber_link - Check for link (Fiber)
414 * @hw: pointer to the HW structure
416 * Checks for link up on the hardware. If link is not up and we have
417 * a signal, then we need to force link up.
419 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
421 struct e1000_mac_info *mac = &hw->mac;
428 status = er32(STATUS);
432 * If we don't have link (auto-negotiation failed or link partner
433 * cannot auto-negotiate), the cable is plugged in (we have signal),
434 * and our link partner is not trying to auto-negotiate with us (we
435 * are receiving idles or data), we need to force link up. We also
436 * need to give auto-negotiation time to complete, in case the cable
437 * was just plugged in. The autoneg_failed flag does this.
439 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
440 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
441 (!(rxcw & E1000_RXCW_C))) {
442 if (mac->autoneg_failed == 0) {
443 mac->autoneg_failed = 1;
446 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
448 /* Disable auto-negotiation in the TXCW register */
449 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
451 /* Force link-up and also force full-duplex. */
453 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
456 /* Configure Flow Control after forcing link up. */
457 ret_val = e1000e_config_fc_after_link_up(hw);
459 hw_dbg(hw, "Error configuring flow control\n");
462 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
464 * If we are forcing link and we are receiving /C/ ordered
465 * sets, re-enable auto-negotiation in the TXCW register
466 * and disable forced link in the Device Control register
467 * in an attempt to auto-negotiate with our link partner.
469 hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
470 ew32(TXCW, mac->txcw);
471 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
473 mac->serdes_has_link = true;
480 * e1000e_check_for_serdes_link - Check for link (Serdes)
481 * @hw: pointer to the HW structure
483 * Checks for link up on the hardware. If link is not up and we have
484 * a signal, then we need to force link up.
486 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
488 struct e1000_mac_info *mac = &hw->mac;
495 status = er32(STATUS);
499 * If we don't have link (auto-negotiation failed or link partner
500 * cannot auto-negotiate), and our link partner is not trying to
501 * auto-negotiate with us (we are receiving idles or data),
502 * we need to force link up. We also need to give auto-negotiation
505 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
506 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
507 if (mac->autoneg_failed == 0) {
508 mac->autoneg_failed = 1;
511 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
513 /* Disable auto-negotiation in the TXCW register */
514 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
516 /* Force link-up and also force full-duplex. */
518 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
521 /* Configure Flow Control after forcing link up. */
522 ret_val = e1000e_config_fc_after_link_up(hw);
524 hw_dbg(hw, "Error configuring flow control\n");
527 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
529 * If we are forcing link and we are receiving /C/ ordered
530 * sets, re-enable auto-negotiation in the TXCW register
531 * and disable forced link in the Device Control register
532 * in an attempt to auto-negotiate with our link partner.
534 hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
535 ew32(TXCW, mac->txcw);
536 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
538 mac->serdes_has_link = true;
539 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
541 * If we force link for non-auto-negotiation switch, check
542 * link status based on MAC synchronization for internal
545 /* SYNCH bit and IV bit are sticky. */
548 if (rxcw & E1000_RXCW_SYNCH) {
549 if (!(rxcw & E1000_RXCW_IV)) {
550 mac->serdes_has_link = true;
551 hw_dbg(hw, "SERDES: Link up - forced.\n");
554 mac->serdes_has_link = false;
555 hw_dbg(hw, "SERDES: Link down - force failed.\n");
559 if (E1000_TXCW_ANE & er32(TXCW)) {
560 status = er32(STATUS);
561 if (status & E1000_STATUS_LU) {
562 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
565 if (rxcw & E1000_RXCW_SYNCH) {
566 if (!(rxcw & E1000_RXCW_IV)) {
567 mac->serdes_has_link = true;
568 hw_dbg(hw, "SERDES: Link up - autoneg "
569 "completed sucessfully.\n");
571 mac->serdes_has_link = false;
572 hw_dbg(hw, "SERDES: Link down - invalid"
573 "codewords detected in autoneg.\n");
576 mac->serdes_has_link = false;
577 hw_dbg(hw, "SERDES: Link down - no sync.\n");
580 mac->serdes_has_link = false;
581 hw_dbg(hw, "SERDES: Link down - autoneg failed\n");
589 * e1000_set_default_fc_generic - Set flow control default values
590 * @hw: pointer to the HW structure
592 * Read the EEPROM for the default values for flow control and store the
595 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
601 * Read and store word 0x0F of the EEPROM. This word contains bits
602 * that determine the hardware's default PAUSE (flow control) mode,
603 * a bit that determines whether the HW defaults to enabling or
604 * disabling auto-negotiation, and the direction of the
605 * SW defined pins. If there is no SW over-ride of the flow
606 * control setting, then the variable hw->fc will
607 * be initialized based on a value in the EEPROM.
609 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
612 hw_dbg(hw, "NVM Read Error\n");
616 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
617 hw->fc.requested_mode = e1000_fc_none;
618 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
620 hw->fc.requested_mode = e1000_fc_tx_pause;
622 hw->fc.requested_mode = e1000_fc_full;
628 * e1000e_setup_link - Setup flow control and link settings
629 * @hw: pointer to the HW structure
631 * Determines which flow control settings to use, then configures flow
632 * control. Calls the appropriate media-specific link configuration
633 * function. Assuming the adapter has a valid link partner, a valid link
634 * should be established. Assumes the hardware has previously been reset
635 * and the transmitter and receiver are not enabled.
637 s32 e1000e_setup_link(struct e1000_hw *hw)
639 struct e1000_mac_info *mac = &hw->mac;
643 * In the case of the phy reset being blocked, we already have a link.
644 * We do not need to set it up again.
646 if (e1000_check_reset_block(hw))
650 * If requested flow control is set to default, set flow control
651 * based on the EEPROM flow control settings.
653 if (hw->fc.requested_mode == e1000_fc_default) {
654 ret_val = e1000_set_default_fc_generic(hw);
660 * Save off the requested flow control mode for use later. Depending
661 * on the link partner's capabilities, we may or may not use this mode.
663 hw->fc.current_mode = hw->fc.requested_mode;
665 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
666 hw->fc.current_mode);
668 /* Call the necessary media_type subroutine to configure the link. */
669 ret_val = mac->ops.setup_physical_interface(hw);
674 * Initialize the flow control address, type, and PAUSE timer
675 * registers to their default values. This is done even if flow
676 * control is disabled, because it does not hurt anything to
677 * initialize these registers.
679 hw_dbg(hw, "Initializing the Flow Control address, type and timer regs\n");
680 ew32(FCT, FLOW_CONTROL_TYPE);
681 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
682 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
684 ew32(FCTTV, hw->fc.pause_time);
686 return e1000e_set_fc_watermarks(hw);
690 * e1000_commit_fc_settings_generic - Configure flow control
691 * @hw: pointer to the HW structure
693 * Write the flow control settings to the Transmit Config Word Register (TXCW)
694 * base on the flow control settings in e1000_mac_info.
696 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
698 struct e1000_mac_info *mac = &hw->mac;
702 * Check for a software override of the flow control settings, and
703 * setup the device accordingly. If auto-negotiation is enabled, then
704 * software will have to set the "PAUSE" bits to the correct value in
705 * the Transmit Config Word Register (TXCW) and re-start auto-
706 * negotiation. However, if auto-negotiation is disabled, then
707 * software will have to manually configure the two flow control enable
708 * bits in the CTRL register.
710 * The possible values of the "fc" parameter are:
711 * 0: Flow control is completely disabled
712 * 1: Rx flow control is enabled (we can receive pause frames,
713 * but not send pause frames).
714 * 2: Tx flow control is enabled (we can send pause frames but we
715 * do not support receiving pause frames).
716 * 3: Both Rx and Tx flow control (symmetric) are enabled.
718 switch (hw->fc.current_mode) {
720 /* Flow control completely disabled by a software over-ride. */
721 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
723 case e1000_fc_rx_pause:
725 * Rx Flow control is enabled and Tx Flow control is disabled
726 * by a software over-ride. Since there really isn't a way to
727 * advertise that we are capable of Rx Pause ONLY, we will
728 * advertise that we support both symmetric and asymmetric Rx
729 * PAUSE. Later, we will disable the adapter's ability to send
732 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
734 case e1000_fc_tx_pause:
736 * Tx Flow control is enabled, and Rx Flow control is disabled,
737 * by a software over-ride.
739 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
743 * Flow control (both Rx and Tx) is enabled by a software
746 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
749 hw_dbg(hw, "Flow control param set incorrectly\n");
750 return -E1000_ERR_CONFIG;
761 * e1000_poll_fiber_serdes_link_generic - Poll for link up
762 * @hw: pointer to the HW structure
764 * Polls for link up by reading the status register, if link fails to come
765 * up with auto-negotiation, then the link is forced if a signal is detected.
767 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
769 struct e1000_mac_info *mac = &hw->mac;
774 * If we have a signal (the cable is plugged in, or assumed true for
775 * serdes media) then poll for a "Link-Up" indication in the Device
776 * Status Register. Time-out if a link isn't seen in 500 milliseconds
777 * seconds (Auto-negotiation should complete in less than 500
778 * milliseconds even if the other end is doing it in SW).
780 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
782 status = er32(STATUS);
783 if (status & E1000_STATUS_LU)
786 if (i == FIBER_LINK_UP_LIMIT) {
787 hw_dbg(hw, "Never got a valid link from auto-neg!!!\n");
788 mac->autoneg_failed = 1;
790 * AutoNeg failed to achieve a link, so we'll call
791 * mac->check_for_link. This routine will force the
792 * link up if we detect a signal. This will allow us to
793 * communicate with non-autonegotiating link partners.
795 ret_val = mac->ops.check_for_link(hw);
797 hw_dbg(hw, "Error while checking for link\n");
800 mac->autoneg_failed = 0;
802 mac->autoneg_failed = 0;
803 hw_dbg(hw, "Valid Link Found\n");
810 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
811 * @hw: pointer to the HW structure
813 * Configures collision distance and flow control for fiber and serdes
814 * links. Upon successful setup, poll for link.
816 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
823 /* Take the link out of reset */
824 ctrl &= ~E1000_CTRL_LRST;
826 e1000e_config_collision_dist(hw);
828 ret_val = e1000_commit_fc_settings_generic(hw);
833 * Since auto-negotiation is enabled, take the link out of reset (the
834 * link will be in reset, because we previously reset the chip). This
835 * will restart auto-negotiation. If auto-negotiation is successful
836 * then the link-up status bit will be set and the flow control enable
837 * bits (RFCE and TFCE) will be set according to their negotiated value.
839 hw_dbg(hw, "Auto-negotiation enabled\n");
846 * For these adapters, the SW definable pin 1 is set when the optics
847 * detect a signal. If we have a signal, then poll for a "Link-Up"
850 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
851 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
852 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
854 hw_dbg(hw, "No signal detected\n");
861 * e1000e_config_collision_dist - Configure collision distance
862 * @hw: pointer to the HW structure
864 * Configures the collision distance to the default value and is used
865 * during link setup. Currently no func pointer exists and all
866 * implementations are handled in the generic version of this function.
868 void e1000e_config_collision_dist(struct e1000_hw *hw)
874 tctl &= ~E1000_TCTL_COLD;
875 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
882 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
883 * @hw: pointer to the HW structure
885 * Sets the flow control high/low threshold (watermark) registers. If
886 * flow control XON frame transmission is enabled, then set XON frame
887 * transmission as well.
889 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
891 u32 fcrtl = 0, fcrth = 0;
894 * Set the flow control receive threshold registers. Normally,
895 * these registers will be set to a default threshold that may be
896 * adjusted later by the driver's runtime code. However, if the
897 * ability to transmit pause frames is not enabled, then these
898 * registers will be set to 0.
900 if (hw->fc.current_mode & e1000_fc_tx_pause) {
902 * We need to set up the Receive Threshold high and low water
903 * marks as well as (optionally) enabling the transmission of
906 fcrtl = hw->fc.low_water;
907 fcrtl |= E1000_FCRTL_XONE;
908 fcrth = hw->fc.high_water;
917 * e1000e_force_mac_fc - Force the MAC's flow control settings
918 * @hw: pointer to the HW structure
920 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
921 * device control register to reflect the adapter settings. TFCE and RFCE
922 * need to be explicitly set by software when a copper PHY is used because
923 * autonegotiation is managed by the PHY rather than the MAC. Software must
924 * also configure these bits when link is forced on a fiber connection.
926 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
933 * Because we didn't get link via the internal auto-negotiation
934 * mechanism (we either forced link or we got link via PHY
935 * auto-neg), we have to manually enable/disable transmit an
936 * receive flow control.
938 * The "Case" statement below enables/disable flow control
939 * according to the "hw->fc.current_mode" parameter.
941 * The possible values of the "fc" parameter are:
942 * 0: Flow control is completely disabled
943 * 1: Rx flow control is enabled (we can receive pause
944 * frames but not send pause frames).
945 * 2: Tx flow control is enabled (we can send pause frames
946 * frames but we do not receive pause frames).
947 * 3: Both Rx and Tx flow control (symmetric) is enabled.
948 * other: No other values should be possible at this point.
950 hw_dbg(hw, "hw->fc.current_mode = %u\n", hw->fc.current_mode);
952 switch (hw->fc.current_mode) {
954 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
956 case e1000_fc_rx_pause:
957 ctrl &= (~E1000_CTRL_TFCE);
958 ctrl |= E1000_CTRL_RFCE;
960 case e1000_fc_tx_pause:
961 ctrl &= (~E1000_CTRL_RFCE);
962 ctrl |= E1000_CTRL_TFCE;
965 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
968 hw_dbg(hw, "Flow control param set incorrectly\n");
969 return -E1000_ERR_CONFIG;
978 * e1000e_config_fc_after_link_up - Configures flow control after link
979 * @hw: pointer to the HW structure
981 * Checks the status of auto-negotiation after link up to ensure that the
982 * speed and duplex were not forced. If the link needed to be forced, then
983 * flow control needs to be forced also. If auto-negotiation is enabled
984 * and did not fail, then we configure flow control based on our link
987 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
989 struct e1000_mac_info *mac = &hw->mac;
991 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
995 * Check for the case where we have fiber media and auto-neg failed
996 * so we had to force link. In this case, we need to force the
997 * configuration of the MAC to match the "fc" parameter.
999 if (mac->autoneg_failed) {
1000 if (hw->phy.media_type == e1000_media_type_fiber ||
1001 hw->phy.media_type == e1000_media_type_internal_serdes)
1002 ret_val = e1000e_force_mac_fc(hw);
1004 if (hw->phy.media_type == e1000_media_type_copper)
1005 ret_val = e1000e_force_mac_fc(hw);
1009 hw_dbg(hw, "Error forcing flow control settings\n");
1014 * Check for the case where we have copper media and auto-neg is
1015 * enabled. In this case, we need to check and see if Auto-Neg
1016 * has completed, and if so, how the PHY and link partner has
1017 * flow control configured.
1019 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1021 * Read the MII Status Register and check to see if AutoNeg
1022 * has completed. We read this twice because this reg has
1023 * some "sticky" (latched) bits.
1025 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1028 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1032 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1033 hw_dbg(hw, "Copper PHY and Auto Neg "
1034 "has not completed.\n");
1039 * The AutoNeg process has completed, so we now need to
1040 * read both the Auto Negotiation Advertisement
1041 * Register (Address 4) and the Auto_Negotiation Base
1042 * Page Ability Register (Address 5) to determine how
1043 * flow control was negotiated.
1045 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1048 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1053 * Two bits in the Auto Negotiation Advertisement Register
1054 * (Address 4) and two bits in the Auto Negotiation Base
1055 * Page Ability Register (Address 5) determine flow control
1056 * for both the PHY and the link partner. The following
1057 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1058 * 1999, describes these PAUSE resolution bits and how flow
1059 * control is determined based upon these settings.
1060 * NOTE: DC = Don't Care
1062 * LOCAL DEVICE | LINK PARTNER
1063 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1064 *-------|---------|-------|---------|--------------------
1065 * 0 | 0 | DC | DC | e1000_fc_none
1066 * 0 | 1 | 0 | DC | e1000_fc_none
1067 * 0 | 1 | 1 | 0 | e1000_fc_none
1068 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1069 * 1 | 0 | 0 | DC | e1000_fc_none
1070 * 1 | DC | 1 | DC | e1000_fc_full
1071 * 1 | 1 | 0 | 0 | e1000_fc_none
1072 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1075 * Are both PAUSE bits set to 1? If so, this implies
1076 * Symmetric Flow Control is enabled at both ends. The
1077 * ASM_DIR bits are irrelevant per the spec.
1079 * For Symmetric Flow Control:
1081 * LOCAL DEVICE | LINK PARTNER
1082 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1083 *-------|---------|-------|---------|--------------------
1084 * 1 | DC | 1 | DC | E1000_fc_full
1087 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1088 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1090 * Now we need to check if the user selected Rx ONLY
1091 * of pause frames. In this case, we had to advertise
1092 * FULL flow control because we could not advertise Rx
1093 * ONLY. Hence, we must now check to see if we need to
1094 * turn OFF the TRANSMISSION of PAUSE frames.
1096 if (hw->fc.requested_mode == e1000_fc_full) {
1097 hw->fc.current_mode = e1000_fc_full;
1098 hw_dbg(hw, "Flow Control = FULL.\r\n");
1100 hw->fc.current_mode = e1000_fc_rx_pause;
1101 hw_dbg(hw, "Flow Control = "
1102 "RX PAUSE frames only.\r\n");
1106 * For receiving PAUSE frames ONLY.
1108 * LOCAL DEVICE | LINK PARTNER
1109 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1110 *-------|---------|-------|---------|--------------------
1111 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1114 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1115 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1116 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1117 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1118 hw->fc.current_mode = e1000_fc_tx_pause;
1119 hw_dbg(hw, "Flow Control = Tx PAUSE frames only.\r\n");
1122 * For transmitting PAUSE frames ONLY.
1124 * LOCAL DEVICE | LINK PARTNER
1125 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1126 *-------|---------|-------|---------|--------------------
1127 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1130 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1131 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1132 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1133 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1134 hw->fc.current_mode = e1000_fc_rx_pause;
1135 hw_dbg(hw, "Flow Control = Rx PAUSE frames only.\r\n");
1138 * Per the IEEE spec, at this point flow control
1139 * should be disabled.
1141 hw->fc.current_mode = e1000_fc_none;
1142 hw_dbg(hw, "Flow Control = NONE.\r\n");
1146 * Now we need to do one last check... If we auto-
1147 * negotiated to HALF DUPLEX, flow control should not be
1148 * enabled per IEEE 802.3 spec.
1150 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1152 hw_dbg(hw, "Error getting link speed and duplex\n");
1156 if (duplex == HALF_DUPLEX)
1157 hw->fc.current_mode = e1000_fc_none;
1160 * Now we call a subroutine to actually force the MAC
1161 * controller to use the correct flow control settings.
1163 ret_val = e1000e_force_mac_fc(hw);
1165 hw_dbg(hw, "Error forcing flow control settings\n");
1174 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1175 * @hw: pointer to the HW structure
1176 * @speed: stores the current speed
1177 * @duplex: stores the current duplex
1179 * Read the status register for the current speed/duplex and store the current
1180 * speed and duplex for copper connections.
1182 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1186 status = er32(STATUS);
1187 if (status & E1000_STATUS_SPEED_1000) {
1188 *speed = SPEED_1000;
1189 hw_dbg(hw, "1000 Mbs, ");
1190 } else if (status & E1000_STATUS_SPEED_100) {
1192 hw_dbg(hw, "100 Mbs, ");
1195 hw_dbg(hw, "10 Mbs, ");
1198 if (status & E1000_STATUS_FD) {
1199 *duplex = FULL_DUPLEX;
1200 hw_dbg(hw, "Full Duplex\n");
1202 *duplex = HALF_DUPLEX;
1203 hw_dbg(hw, "Half Duplex\n");
1210 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1211 * @hw: pointer to the HW structure
1212 * @speed: stores the current speed
1213 * @duplex: stores the current duplex
1215 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1216 * for fiber/serdes links.
1218 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1220 *speed = SPEED_1000;
1221 *duplex = FULL_DUPLEX;
1227 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1228 * @hw: pointer to the HW structure
1230 * Acquire the HW semaphore to access the PHY or NVM
1232 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1235 s32 timeout = hw->nvm.word_size + 1;
1238 /* Get the SW semaphore */
1239 while (i < timeout) {
1241 if (!(swsm & E1000_SWSM_SMBI))
1249 hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n");
1250 return -E1000_ERR_NVM;
1253 /* Get the FW semaphore. */
1254 for (i = 0; i < timeout; i++) {
1256 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1258 /* Semaphore acquired if bit latched */
1259 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1266 /* Release semaphores */
1267 e1000e_put_hw_semaphore(hw);
1268 hw_dbg(hw, "Driver can't access the NVM\n");
1269 return -E1000_ERR_NVM;
1276 * e1000e_put_hw_semaphore - Release hardware semaphore
1277 * @hw: pointer to the HW structure
1279 * Release hardware semaphore used to access the PHY or NVM
1281 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1286 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1291 * e1000e_get_auto_rd_done - Check for auto read completion
1292 * @hw: pointer to the HW structure
1294 * Check EEPROM for Auto Read done bit.
1296 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1300 while (i < AUTO_READ_DONE_TIMEOUT) {
1301 if (er32(EECD) & E1000_EECD_AUTO_RD)
1307 if (i == AUTO_READ_DONE_TIMEOUT) {
1308 hw_dbg(hw, "Auto read by HW from NVM has not completed.\n");
1309 return -E1000_ERR_RESET;
1316 * e1000e_valid_led_default - Verify a valid default LED config
1317 * @hw: pointer to the HW structure
1318 * @data: pointer to the NVM (EEPROM)
1320 * Read the EEPROM for the current default LED configuration. If the
1321 * LED configuration is not valid, set to a valid LED configuration.
1323 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1327 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1329 hw_dbg(hw, "NVM Read Error\n");
1333 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1334 *data = ID_LED_DEFAULT;
1340 * e1000e_id_led_init -
1341 * @hw: pointer to the HW structure
1344 s32 e1000e_id_led_init(struct e1000_hw *hw)
1346 struct e1000_mac_info *mac = &hw->mac;
1348 const u32 ledctl_mask = 0x000000FF;
1349 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1350 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1352 const u16 led_mask = 0x0F;
1354 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1358 mac->ledctl_default = er32(LEDCTL);
1359 mac->ledctl_mode1 = mac->ledctl_default;
1360 mac->ledctl_mode2 = mac->ledctl_default;
1362 for (i = 0; i < 4; i++) {
1363 temp = (data >> (i << 2)) & led_mask;
1365 case ID_LED_ON1_DEF2:
1366 case ID_LED_ON1_ON2:
1367 case ID_LED_ON1_OFF2:
1368 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1369 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1371 case ID_LED_OFF1_DEF2:
1372 case ID_LED_OFF1_ON2:
1373 case ID_LED_OFF1_OFF2:
1374 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1375 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1382 case ID_LED_DEF1_ON2:
1383 case ID_LED_ON1_ON2:
1384 case ID_LED_OFF1_ON2:
1385 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1386 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1388 case ID_LED_DEF1_OFF2:
1389 case ID_LED_ON1_OFF2:
1390 case ID_LED_OFF1_OFF2:
1391 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1392 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1404 * e1000e_setup_led_generic - Configures SW controllable LED
1405 * @hw: pointer to the HW structure
1407 * This prepares the SW controllable LED for use and saves the current state
1408 * of the LED so it can be later restored.
1410 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1414 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1415 return -E1000_ERR_CONFIG;
1418 if (hw->phy.media_type == e1000_media_type_fiber) {
1419 ledctl = er32(LEDCTL);
1420 hw->mac.ledctl_default = ledctl;
1422 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1423 E1000_LEDCTL_LED0_BLINK |
1424 E1000_LEDCTL_LED0_MODE_MASK);
1425 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1426 E1000_LEDCTL_LED0_MODE_SHIFT);
1427 ew32(LEDCTL, ledctl);
1428 } else if (hw->phy.media_type == e1000_media_type_copper) {
1429 ew32(LEDCTL, hw->mac.ledctl_mode1);
1436 * e1000e_cleanup_led_generic - Set LED config to default operation
1437 * @hw: pointer to the HW structure
1439 * Remove the current LED configuration and set the LED configuration
1440 * to the default value, saved from the EEPROM.
1442 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1444 ew32(LEDCTL, hw->mac.ledctl_default);
1449 * e1000e_blink_led - Blink LED
1450 * @hw: pointer to the HW structure
1452 * Blink the LEDs which are set to be on.
1454 s32 e1000e_blink_led(struct e1000_hw *hw)
1456 u32 ledctl_blink = 0;
1459 if (hw->phy.media_type == e1000_media_type_fiber) {
1460 /* always blink LED0 for PCI-E fiber */
1461 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1462 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1465 * set the blink bit for each LED that's "on" (0x0E)
1468 ledctl_blink = hw->mac.ledctl_mode2;
1469 for (i = 0; i < 4; i++)
1470 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1471 E1000_LEDCTL_MODE_LED_ON)
1472 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1476 ew32(LEDCTL, ledctl_blink);
1482 * e1000e_led_on_generic - Turn LED on
1483 * @hw: pointer to the HW structure
1487 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1491 switch (hw->phy.media_type) {
1492 case e1000_media_type_fiber:
1494 ctrl &= ~E1000_CTRL_SWDPIN0;
1495 ctrl |= E1000_CTRL_SWDPIO0;
1498 case e1000_media_type_copper:
1499 ew32(LEDCTL, hw->mac.ledctl_mode2);
1509 * e1000e_led_off_generic - Turn LED off
1510 * @hw: pointer to the HW structure
1514 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1518 switch (hw->phy.media_type) {
1519 case e1000_media_type_fiber:
1521 ctrl |= E1000_CTRL_SWDPIN0;
1522 ctrl |= E1000_CTRL_SWDPIO0;
1525 case e1000_media_type_copper:
1526 ew32(LEDCTL, hw->mac.ledctl_mode1);
1536 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1537 * @hw: pointer to the HW structure
1538 * @no_snoop: bitmap of snoop events
1540 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1542 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1548 gcr &= ~(PCIE_NO_SNOOP_ALL);
1555 * e1000e_disable_pcie_master - Disables PCI-express master access
1556 * @hw: pointer to the HW structure
1558 * Returns 0 if successful, else returns -10
1559 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1560 * the master requests to be disabled.
1562 * Disables PCI-Express master access and verifies there are no pending
1565 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1568 s32 timeout = MASTER_DISABLE_TIMEOUT;
1571 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1575 if (!(er32(STATUS) &
1576 E1000_STATUS_GIO_MASTER_ENABLE))
1583 hw_dbg(hw, "Master requests are pending.\n");
1584 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1591 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1592 * @hw: pointer to the HW structure
1594 * Reset the Adaptive Interframe Spacing throttle to default values.
1596 void e1000e_reset_adaptive(struct e1000_hw *hw)
1598 struct e1000_mac_info *mac = &hw->mac;
1600 mac->current_ifs_val = 0;
1601 mac->ifs_min_val = IFS_MIN;
1602 mac->ifs_max_val = IFS_MAX;
1603 mac->ifs_step_size = IFS_STEP;
1604 mac->ifs_ratio = IFS_RATIO;
1606 mac->in_ifs_mode = 0;
1611 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1612 * @hw: pointer to the HW structure
1614 * Update the Adaptive Interframe Spacing Throttle value based on the
1615 * time between transmitted packets and time between collisions.
1617 void e1000e_update_adaptive(struct e1000_hw *hw)
1619 struct e1000_mac_info *mac = &hw->mac;
1621 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1622 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1623 mac->in_ifs_mode = 1;
1624 if (mac->current_ifs_val < mac->ifs_max_val) {
1625 if (!mac->current_ifs_val)
1626 mac->current_ifs_val = mac->ifs_min_val;
1628 mac->current_ifs_val +=
1630 ew32(AIT, mac->current_ifs_val);
1634 if (mac->in_ifs_mode &&
1635 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1636 mac->current_ifs_val = 0;
1637 mac->in_ifs_mode = 0;
1644 * e1000_raise_eec_clk - Raise EEPROM clock
1645 * @hw: pointer to the HW structure
1646 * @eecd: pointer to the EEPROM
1648 * Enable/Raise the EEPROM clock bit.
1650 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1652 *eecd = *eecd | E1000_EECD_SK;
1655 udelay(hw->nvm.delay_usec);
1659 * e1000_lower_eec_clk - Lower EEPROM clock
1660 * @hw: pointer to the HW structure
1661 * @eecd: pointer to the EEPROM
1663 * Clear/Lower the EEPROM clock bit.
1665 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1667 *eecd = *eecd & ~E1000_EECD_SK;
1670 udelay(hw->nvm.delay_usec);
1674 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1675 * @hw: pointer to the HW structure
1676 * @data: data to send to the EEPROM
1677 * @count: number of bits to shift out
1679 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1680 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1681 * In order to do this, "data" must be broken down into bits.
1683 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1685 struct e1000_nvm_info *nvm = &hw->nvm;
1686 u32 eecd = er32(EECD);
1689 mask = 0x01 << (count - 1);
1690 if (nvm->type == e1000_nvm_eeprom_spi)
1691 eecd |= E1000_EECD_DO;
1694 eecd &= ~E1000_EECD_DI;
1697 eecd |= E1000_EECD_DI;
1702 udelay(nvm->delay_usec);
1704 e1000_raise_eec_clk(hw, &eecd);
1705 e1000_lower_eec_clk(hw, &eecd);
1710 eecd &= ~E1000_EECD_DI;
1715 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1716 * @hw: pointer to the HW structure
1717 * @count: number of bits to shift in
1719 * In order to read a register from the EEPROM, we need to shift 'count' bits
1720 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1721 * the EEPROM (setting the SK bit), and then reading the value of the data out
1722 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1725 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1733 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1736 for (i = 0; i < count; i++) {
1738 e1000_raise_eec_clk(hw, &eecd);
1742 eecd &= ~E1000_EECD_DI;
1743 if (eecd & E1000_EECD_DO)
1746 e1000_lower_eec_clk(hw, &eecd);
1753 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1754 * @hw: pointer to the HW structure
1755 * @ee_reg: EEPROM flag for polling
1757 * Polls the EEPROM status bit for either read or write completion based
1758 * upon the value of 'ee_reg'.
1760 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1762 u32 attempts = 100000;
1765 for (i = 0; i < attempts; i++) {
1766 if (ee_reg == E1000_NVM_POLL_READ)
1771 if (reg & E1000_NVM_RW_REG_DONE)
1777 return -E1000_ERR_NVM;
1781 * e1000e_acquire_nvm - Generic request for access to EEPROM
1782 * @hw: pointer to the HW structure
1784 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1785 * Return successful if access grant bit set, else clear the request for
1786 * EEPROM access and return -E1000_ERR_NVM (-1).
1788 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1790 u32 eecd = er32(EECD);
1791 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1793 ew32(EECD, eecd | E1000_EECD_REQ);
1797 if (eecd & E1000_EECD_GNT)
1805 eecd &= ~E1000_EECD_REQ;
1807 hw_dbg(hw, "Could not acquire NVM grant\n");
1808 return -E1000_ERR_NVM;
1815 * e1000_standby_nvm - Return EEPROM to standby state
1816 * @hw: pointer to the HW structure
1818 * Return the EEPROM to a standby state.
1820 static void e1000_standby_nvm(struct e1000_hw *hw)
1822 struct e1000_nvm_info *nvm = &hw->nvm;
1823 u32 eecd = er32(EECD);
1825 if (nvm->type == e1000_nvm_eeprom_spi) {
1826 /* Toggle CS to flush commands */
1827 eecd |= E1000_EECD_CS;
1830 udelay(nvm->delay_usec);
1831 eecd &= ~E1000_EECD_CS;
1834 udelay(nvm->delay_usec);
1839 * e1000_stop_nvm - Terminate EEPROM command
1840 * @hw: pointer to the HW structure
1842 * Terminates the current command by inverting the EEPROM's chip select pin.
1844 static void e1000_stop_nvm(struct e1000_hw *hw)
1849 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1851 eecd |= E1000_EECD_CS;
1852 e1000_lower_eec_clk(hw, &eecd);
1857 * e1000e_release_nvm - Release exclusive access to EEPROM
1858 * @hw: pointer to the HW structure
1860 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1862 void e1000e_release_nvm(struct e1000_hw *hw)
1869 eecd &= ~E1000_EECD_REQ;
1874 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1875 * @hw: pointer to the HW structure
1877 * Setups the EEPROM for reading and writing.
1879 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1881 struct e1000_nvm_info *nvm = &hw->nvm;
1882 u32 eecd = er32(EECD);
1886 if (nvm->type == e1000_nvm_eeprom_spi) {
1887 /* Clear SK and CS */
1888 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1891 timeout = NVM_MAX_RETRY_SPI;
1894 * Read "Status Register" repeatedly until the LSB is cleared.
1895 * The EEPROM will signal that the command has been completed
1896 * by clearing bit 0 of the internal status register. If it's
1897 * not cleared within 'timeout', then error out.
1900 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1901 hw->nvm.opcode_bits);
1902 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1903 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1907 e1000_standby_nvm(hw);
1912 hw_dbg(hw, "SPI NVM Status error\n");
1913 return -E1000_ERR_NVM;
1921 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1922 * @hw: pointer to the HW structure
1923 * @offset: offset of word in the EEPROM to read
1924 * @words: number of words to read
1925 * @data: word read from the EEPROM
1927 * Reads a 16 bit word from the EEPROM using the EERD register.
1929 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1931 struct e1000_nvm_info *nvm = &hw->nvm;
1936 * A check for invalid values: offset too large, too many words,
1937 * too many words for the offset, and not enough words.
1939 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1941 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1942 return -E1000_ERR_NVM;
1945 for (i = 0; i < words; i++) {
1946 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
1947 E1000_NVM_RW_REG_START;
1950 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
1954 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
1961 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1962 * @hw: pointer to the HW structure
1963 * @offset: offset within the EEPROM to be written to
1964 * @words: number of words to write
1965 * @data: 16 bit word(s) to be written to the EEPROM
1967 * Writes data to EEPROM at offset using SPI interface.
1969 * If e1000e_update_nvm_checksum is not called after this function , the
1970 * EEPROM will most likely contain an invalid checksum.
1972 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1974 struct e1000_nvm_info *nvm = &hw->nvm;
1979 * A check for invalid values: offset too large, too many words,
1980 * and not enough words.
1982 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1984 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1985 return -E1000_ERR_NVM;
1988 ret_val = nvm->ops.acquire_nvm(hw);
1994 while (widx < words) {
1995 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
1997 ret_val = e1000_ready_nvm_eeprom(hw);
1999 nvm->ops.release_nvm(hw);
2003 e1000_standby_nvm(hw);
2005 /* Send the WRITE ENABLE command (8 bit opcode) */
2006 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2009 e1000_standby_nvm(hw);
2012 * Some SPI eeproms use the 8th address bit embedded in the
2015 if ((nvm->address_bits == 8) && (offset >= 128))
2016 write_opcode |= NVM_A8_OPCODE_SPI;
2018 /* Send the Write command (8-bit opcode + addr) */
2019 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2020 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2023 /* Loop to allow for up to whole page write of eeprom */
2024 while (widx < words) {
2025 u16 word_out = data[widx];
2026 word_out = (word_out >> 8) | (word_out << 8);
2027 e1000_shift_out_eec_bits(hw, word_out, 16);
2030 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2031 e1000_standby_nvm(hw);
2038 nvm->ops.release_nvm(hw);
2043 * e1000e_read_mac_addr - Read device MAC address
2044 * @hw: pointer to the HW structure
2046 * Reads the device MAC address from the EEPROM and stores the value.
2047 * Since devices with two ports use the same EEPROM, we increment the
2048 * last bit in the MAC address for the second port.
2050 s32 e1000e_read_mac_addr(struct e1000_hw *hw)
2053 u16 offset, nvm_data, i;
2054 u16 mac_addr_offset = 0;
2056 if (hw->mac.type == e1000_82571) {
2057 /* Check for an alternate MAC address. An alternate MAC
2058 * address can be setup by pre-boot software and must be
2059 * treated like a permanent address and must override the
2060 * actual permanent MAC address.*/
2061 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
2064 hw_dbg(hw, "NVM Read Error\n");
2067 if (mac_addr_offset == 0xFFFF)
2068 mac_addr_offset = 0;
2070 if (mac_addr_offset) {
2071 if (hw->bus.func == E1000_FUNC_1)
2072 mac_addr_offset += ETH_ALEN/sizeof(u16);
2074 /* make sure we have a valid mac address here
2075 * before using it */
2076 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
2079 hw_dbg(hw, "NVM Read Error\n");
2082 if (nvm_data & 0x0001)
2083 mac_addr_offset = 0;
2086 if (mac_addr_offset)
2087 hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
2090 for (i = 0; i < ETH_ALEN; i += 2) {
2091 offset = mac_addr_offset + (i >> 1);
2092 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
2094 hw_dbg(hw, "NVM Read Error\n");
2097 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
2098 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
2101 /* Flip last bit of mac address if we're on second port */
2102 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1)
2103 hw->mac.perm_addr[5] ^= 1;
2105 for (i = 0; i < ETH_ALEN; i++)
2106 hw->mac.addr[i] = hw->mac.perm_addr[i];
2112 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2113 * @hw: pointer to the HW structure
2115 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2116 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2118 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2124 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2125 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2127 hw_dbg(hw, "NVM Read Error\n");
2130 checksum += nvm_data;
2133 if (checksum != (u16) NVM_SUM) {
2134 hw_dbg(hw, "NVM Checksum Invalid\n");
2135 return -E1000_ERR_NVM;
2142 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2143 * @hw: pointer to the HW structure
2145 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2146 * up to the checksum. Then calculates the EEPROM checksum and writes the
2147 * value to the EEPROM.
2149 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2155 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2156 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2158 hw_dbg(hw, "NVM Read Error while updating checksum.\n");
2161 checksum += nvm_data;
2163 checksum = (u16) NVM_SUM - checksum;
2164 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2166 hw_dbg(hw, "NVM Write Error while updating checksum.\n");
2172 * e1000e_reload_nvm - Reloads EEPROM
2173 * @hw: pointer to the HW structure
2175 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2176 * extended control register.
2178 void e1000e_reload_nvm(struct e1000_hw *hw)
2183 ctrl_ext = er32(CTRL_EXT);
2184 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2185 ew32(CTRL_EXT, ctrl_ext);
2190 * e1000_calculate_checksum - Calculate checksum for buffer
2191 * @buffer: pointer to EEPROM
2192 * @length: size of EEPROM to calculate a checksum for
2194 * Calculates the checksum for some buffer on a specified length. The
2195 * checksum calculated is returned.
2197 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2205 for (i = 0; i < length; i++)
2208 return (u8) (0 - sum);
2212 * e1000_mng_enable_host_if - Checks host interface is enabled
2213 * @hw: pointer to the HW structure
2215 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2217 * This function checks whether the HOST IF is enabled for command operation
2218 * and also checks whether the previous command is completed. It busy waits
2219 * in case of previous command is not completed.
2221 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2226 /* Check that the host interface is enabled. */
2228 if ((hicr & E1000_HICR_EN) == 0) {
2229 hw_dbg(hw, "E1000_HOST_EN bit disabled.\n");
2230 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2232 /* check the previous command is completed */
2233 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2235 if (!(hicr & E1000_HICR_C))
2240 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2241 hw_dbg(hw, "Previous command timeout failed .\n");
2242 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2249 * e1000e_check_mng_mode_generic - check management mode
2250 * @hw: pointer to the HW structure
2252 * Reads the firmware semaphore register and returns true (>0) if
2253 * manageability is enabled, else false (0).
2255 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2257 u32 fwsm = er32(FWSM);
2259 return (fwsm & E1000_FWSM_MODE_MASK) ==
2260 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2264 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2265 * @hw: pointer to the HW structure
2267 * Enables packet filtering on transmit packets if manageability is enabled
2268 * and host interface is enabled.
2270 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2272 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2273 u32 *buffer = (u32 *)&hw->mng_cookie;
2275 s32 ret_val, hdr_csum, csum;
2278 /* No manageability, no filtering */
2279 if (!e1000e_check_mng_mode(hw)) {
2280 hw->mac.tx_pkt_filtering = 0;
2285 * If we can't read from the host interface for whatever
2286 * reason, disable filtering.
2288 ret_val = e1000_mng_enable_host_if(hw);
2290 hw->mac.tx_pkt_filtering = 0;
2294 /* Read in the header. Length and offset are in dwords. */
2295 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2296 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2297 for (i = 0; i < len; i++)
2298 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2299 hdr_csum = hdr->checksum;
2301 csum = e1000_calculate_checksum((u8 *)hdr,
2302 E1000_MNG_DHCP_COOKIE_LENGTH);
2304 * If either the checksums or signature don't match, then
2305 * the cookie area isn't considered valid, in which case we
2306 * take the safe route of assuming Tx filtering is enabled.
2308 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2309 hw->mac.tx_pkt_filtering = 1;
2313 /* Cookie area is valid, make the final check for filtering. */
2314 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2315 hw->mac.tx_pkt_filtering = 0;
2319 hw->mac.tx_pkt_filtering = 1;
2324 * e1000_mng_write_cmd_header - Writes manageability command header
2325 * @hw: pointer to the HW structure
2326 * @hdr: pointer to the host interface command header
2328 * Writes the command header after does the checksum calculation.
2330 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2331 struct e1000_host_mng_command_header *hdr)
2333 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2335 /* Write the whole command header structure with new checksum. */
2337 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2340 /* Write the relevant command block into the ram area. */
2341 for (i = 0; i < length; i++) {
2342 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2343 *((u32 *) hdr + i));
2351 * e1000_mng_host_if_write - Writes to the manageability host interface
2352 * @hw: pointer to the HW structure
2353 * @buffer: pointer to the host interface buffer
2354 * @length: size of the buffer
2355 * @offset: location in the buffer to write to
2356 * @sum: sum of the data (not checksum)
2358 * This function writes the buffer content at the offset given on the host if.
2359 * It also does alignment considerations to do the writes in most efficient
2360 * way. Also fills up the sum of the buffer in *buffer parameter.
2362 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2363 u16 length, u16 offset, u8 *sum)
2366 u8 *bufptr = buffer;
2368 u16 remaining, i, j, prev_bytes;
2370 /* sum = only sum of the data and it is not checksum */
2372 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2373 return -E1000_ERR_PARAM;
2376 prev_bytes = offset & 0x3;
2380 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2381 for (j = prev_bytes; j < sizeof(u32); j++) {
2382 *(tmp + j) = *bufptr++;
2385 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2386 length -= j - prev_bytes;
2390 remaining = length & 0x3;
2391 length -= remaining;
2393 /* Calculate length in DWORDs */
2397 * The device driver writes the relevant command block into the
2400 for (i = 0; i < length; i++) {
2401 for (j = 0; j < sizeof(u32); j++) {
2402 *(tmp + j) = *bufptr++;
2406 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2409 for (j = 0; j < sizeof(u32); j++) {
2411 *(tmp + j) = *bufptr++;
2417 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2424 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2425 * @hw: pointer to the HW structure
2426 * @buffer: pointer to the host interface
2427 * @length: size of the buffer
2429 * Writes the DHCP information to the host interface.
2431 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2433 struct e1000_host_mng_command_header hdr;
2437 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2438 hdr.command_length = length;
2443 /* Enable the host interface */
2444 ret_val = e1000_mng_enable_host_if(hw);
2448 /* Populate the host interface with the contents of "buffer". */
2449 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2450 sizeof(hdr), &(hdr.checksum));
2454 /* Write the manageability command header */
2455 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2459 /* Tell the ARC a new command is pending. */
2461 ew32(HICR, hicr | E1000_HICR_C);
2467 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2468 * @hw: pointer to the HW structure
2470 * Verifies the hardware needs to allow ARPs to be processed by the host.
2472 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2480 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2481 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2484 if (hw->mac.arc_subsystem_valid) {
2486 factps = er32(FACTPS);
2488 if (!(factps & E1000_FACTPS_MNGCG) &&
2489 ((fwsm & E1000_FWSM_MODE_MASK) ==
2490 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2495 if ((manc & E1000_MANC_SMBUS_EN) &&
2496 !(manc & E1000_MANC_ASF_EN)) {
2505 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2510 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2512 hw_dbg(hw, "NVM Read Error\n");
2515 *pba_num = (u32)(nvm_data << 16);
2517 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2519 hw_dbg(hw, "NVM Read Error\n");
2522 *pba_num |= nvm_data;