drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include <linux/netdevice.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/delay.h>
  60 #include <linux/pci.h>
  61
  62 #include "e1000.h"
  63
  64 #define ICH_FLASH_GFPREG                0x0000
  65 #define ICH_FLASH_HSFSTS                0x0004
  66 #define ICH_FLASH_HSFCTL                0x0006
  67 #define ICH_FLASH_FADDR                 0x0008
  68 #define ICH_FLASH_FDATA0                0x0010
  69 #define ICH_FLASH_PR0                   0x0074
  70
  71 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  72 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  73 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  74 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  75 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  76
  77 #define ICH_CYCLE_READ                  0
  78 #define ICH_CYCLE_WRITE                 2
  79 #define ICH_CYCLE_ERASE                 3
  80
  81 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  82 #define FLASH_SECTOR_ADDR_SHIFT         12
  83
  84 #define ICH_FLASH_SEG_SIZE_256          256
  85 #define ICH_FLASH_SEG_SIZE_4K           4096
  86 #define ICH_FLASH_SEG_SIZE_8K           8192
  87 #define ICH_FLASH_SEG_SIZE_64K          65536
  88
  89
  90 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  91
  92 #define E1000_ICH_MNG_IAMT_MODE         0x2
  93
  94 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  95                                  (ID_LED_DEF1_OFF2 <<  8) | \
  96                                  (ID_LED_DEF1_ON2  <<  4) | \
  97                                  (ID_LED_DEF1_DEF2))
  98
  99 #define E1000_ICH_NVM_SIG_WORD          0x13
 100 #define E1000_ICH_NVM_SIG_MASK          0xC000
 101 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 102 #define E1000_ICH_NVM_SIG_VALUE         0x80
 103
 104 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 105
 106 #define E1000_FEXTNVM_SW_CONFIG         1
 107 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 108
 109 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 110
 111 #define E1000_ICH_RAR_ENTRIES           7
 112
 113 #define PHY_PAGE_SHIFT 5
 114 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 115                            ((reg) & MAX_PHY_REG_ADDRESS))
 116 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 117 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 118
 119 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 120 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 121 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 122
 123 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 124
 125 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 126 /* Offset 04h HSFSTS */
 127 union ich8_hws_flash_status {
 128         struct ich8_hsfsts {
 129                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 130                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 131                 u16 dael       :1; /* bit 2 Direct Access error Log */
 132                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 133                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 134                 u16 reserved1  :2; /* bit 13:6 Reserved */
 135                 u16 reserved2  :6; /* bit 13:6 Reserved */
 136                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 137                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 138         } hsf_status;
 139         u16 regval;
 140 };
 141
 142 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 143 /* Offset 06h FLCTL */
 144 union ich8_hws_flash_ctrl {
 145         struct ich8_hsflctl {
 146                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 147                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 148                 u16 reserved   :5;   /* 7:3 Reserved  */
 149                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 150                 u16 flockdn    :6;   /* 15:10 Reserved */
 151         } hsf_ctrl;
 152         u16 regval;
 153 };
 154
 155 /* ICH Flash Region Access Permissions */
 156 union ich8_hws_flash_regacc {
 157         struct ich8_flracc {
 158                 u32 grra      :8; /* 0:7 GbE region Read Access */
 159                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 160                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 161                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 162         } hsf_flregacc;
 163         u16 regval;
 164 };
 165
 166 /* ICH Flash Protected Region */
 167 union ich8_flash_protected_range {
 168         struct ich8_pr {
 169                 u32 base:13;     /* 0:12 Protected Range Base */
 170                 u32 reserved1:2; /* 13:14 Reserved */
 171                 u32 rpe:1;       /* 15 Read Protection Enable */
 172                 u32 limit:13;    /* 16:28 Protected Range Limit */
 173                 u32 reserved2:2; /* 29:30 Reserved */
 174                 u32 wpe:1;       /* 31 Write Protection Enable */
 175         } range;
 176         u32 regval;
 177 };
 178
 179 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 180 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 181 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 182 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 183 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 184 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 185                                                 u32 offset, u8 byte);
 186 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 187                                          u8 *data);
 188 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 189                                          u16 *data);
 190 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 191                                          u8 size, u16 *data);
 192 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 193 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 194 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 195 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 196 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 197 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 198 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 199 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 200 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 201 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 202 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 203
 204 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 205 {
 206         return readw(hw->flash_address + reg);
 207 }
 208
 209 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 210 {
 211         return readl(hw->flash_address + reg);
 212 }
 213
 214 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 215 {
 216         writew(val, hw->flash_address + reg);
 217 }
 218
 219 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 220 {
 221         writel(val, hw->flash_address + reg);
 222 }
 223
 224 #define er16flash(reg)          __er16flash(hw, (reg))
 225 #define er32flash(reg)          __er32flash(hw, (reg))
 226 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 227 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 228
 229 /**
 230  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 231  *  @hw: pointer to the HW structure
 232  *
 233  *  Initialize family-specific PHY parameters and function pointers.
 234  **/
 235 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 236 {
 237         struct e1000_phy_info *phy = &hw->phy;
 238         s32 ret_val = 0;
 239
 240         phy->addr                     = 1;
 241         phy->reset_delay_us           = 100;
 242
 243         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 244         phy->ops.read_phy_reg         = e1000_read_phy_reg_hv;
 245         phy->ops.write_phy_reg        = e1000_write_phy_reg_hv;
 246         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 247
 248         phy->id = e1000_phy_unknown;
 249         e1000e_get_phy_id(hw);
 250         phy->type = e1000e_get_phy_type_from_id(phy->id);
 251
 252         if (phy->type == e1000_phy_82577) {
 253                 phy->ops.check_polarity = e1000_check_polarity_82577;
 254                 phy->ops.force_speed_duplex =
 255                         e1000_phy_force_speed_duplex_82577;
 256                 phy->ops.get_cable_length   = e1000_get_cable_length_82577;
 257                 phy->ops.get_phy_info = e1000_get_phy_info_82577;
 258                 phy->ops.commit_phy = e1000e_phy_sw_reset;
 259         }
 260
 261         return ret_val;
 262 }
 263
 264 /**
 265  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 266  *  @hw: pointer to the HW structure
 267  *
 268  *  Initialize family-specific PHY parameters and function pointers.
 269  **/
 270 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 271 {
 272         struct e1000_phy_info *phy = &hw->phy;
 273         s32 ret_val;
 274         u16 i = 0;
 275
 276         phy->addr                       = 1;
 277         phy->reset_delay_us             = 100;
 278
 279         /*
 280          * We may need to do this twice - once for IGP and if that fails,
 281          * we'll set BM func pointers and try again
 282          */
 283         ret_val = e1000e_determine_phy_address(hw);
 284         if (ret_val) {
 285                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 286                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 287                 ret_val = e1000e_determine_phy_address(hw);
 288                 if (ret_val)
 289                         return ret_val;
 290         }
 291
 292         phy->id = 0;
 293         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 294                (i++ < 100)) {
 295                 msleep(1);
 296                 ret_val = e1000e_get_phy_id(hw);
 297                 if (ret_val)
 298                         return ret_val;
 299         }
 300
 301         /* Verify phy id */
 302         switch (phy->id) {
 303         case IGP03E1000_E_PHY_ID:
 304                 phy->type = e1000_phy_igp_3;
 305                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 306                 break;
 307         case IFE_E_PHY_ID:
 308         case IFE_PLUS_E_PHY_ID:
 309         case IFE_C_E_PHY_ID:
 310                 phy->type = e1000_phy_ife;
 311                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 312                 break;
 313         case BME1000_E_PHY_ID:
 314                 phy->type = e1000_phy_bm;
 315                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 316                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 317                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 318                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 319                 break;
 320         default:
 321                 return -E1000_ERR_PHY;
 322                 break;
 323         }
 324
 325         phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
 326
 327         return 0;
 328 }
 329
 330 /**
 331  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 332  *  @hw: pointer to the HW structure
 333  *
 334  *  Initialize family-specific NVM parameters and function
 335  *  pointers.
 336  **/
 337 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 338 {
 339         struct e1000_nvm_info *nvm = &hw->nvm;
 340         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 341         union ich8_hws_flash_status hsfsts;
 342         u32 gfpreg;
 343         u32 sector_base_addr;
 344         u32 sector_end_addr;
 345         u16 i;
 346
 347         /* Can't read flash registers if the register set isn't mapped. */
 348         if (!hw->flash_address) {
 349                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 350                 return -E1000_ERR_CONFIG;
 351         }
 352
 353         nvm->type = e1000_nvm_flash_sw;
 354
 355         gfpreg = er32flash(ICH_FLASH_GFPREG);
 356
 357         /*
 358          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 359          * Add 1 to sector_end_addr since this sector is included in
 360          * the overall size.
 361          */
 362         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 363         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 364
 365         /* flash_base_addr is byte-aligned */
 366         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 367
 368         /*
 369          * find total size of the NVM, then cut in half since the total
 370          * size represents two separate NVM banks.
 371          */
 372         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 373                                 << FLASH_SECTOR_ADDR_SHIFT;
 374         nvm->flash_bank_size /= 2;
 375         /* Adjust to word count */
 376         nvm->flash_bank_size /= sizeof(u16);
 377
 378         /*
 379          * Make sure the flash bank size does not overwrite the 4k
 380          * sector ranges. We may have 64k allotted to us but we only care
 381          * about the first 2 4k sectors. Therefore, if we have anything less
 382          * than 64k set in the HSFSTS register, we will reduce the bank size
 383          * down to 4k and let the rest remain unused. If berasesz == 3, then
 384          * we are working in 64k mode. Otherwise we are not.
 385          */
 386         if (nvm->flash_bank_size > E1000_ICH8_SHADOW_RAM_WORDS) {
 387                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 388                 if (hsfsts.hsf_status.berasesz != 3)
 389                         nvm->flash_bank_size = E1000_ICH8_SHADOW_RAM_WORDS;
 390         }
 391
 392         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 393
 394         /* Clear shadow ram */
 395         for (i = 0; i < nvm->word_size; i++) {
 396                 dev_spec->shadow_ram[i].modified = 0;
 397                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 398         }
 399
 400         return 0;
 401 }
 402
 403 /**
 404  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 405  *  @hw: pointer to the HW structure
 406  *
 407  *  Initialize family-specific MAC parameters and function
 408  *  pointers.
 409  **/
 410 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 411 {
 412         struct e1000_hw *hw = &adapter->hw;
 413         struct e1000_mac_info *mac = &hw->mac;
 414
 415         /* Set media type function pointer */
 416         hw->phy.media_type = e1000_media_type_copper;
 417
 418         /* Set mta register count */
 419         mac->mta_reg_count = 32;
 420         /* Set rar entry count */
 421         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 422         if (mac->type == e1000_ich8lan)
 423                 mac->rar_entry_count--;
 424         /* Set if manageability features are enabled. */
 425         mac->arc_subsystem_valid = 1;
 426
 427         /* LED operations */
 428         switch (mac->type) {
 429         case e1000_ich8lan:
 430         case e1000_ich9lan:
 431         case e1000_ich10lan:
 432                 /* ID LED init */
 433                 mac->ops.id_led_init = e1000e_id_led_init;
 434                 /* setup LED */
 435                 mac->ops.setup_led = e1000e_setup_led_generic;
 436                 /* cleanup LED */
 437                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 438                 /* turn on/off LED */
 439                 mac->ops.led_on = e1000_led_on_ich8lan;
 440                 mac->ops.led_off = e1000_led_off_ich8lan;
 441                 break;
 442         case e1000_pchlan:
 443                 /* ID LED init */
 444                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 445                 /* setup LED */
 446                 mac->ops.setup_led = e1000_setup_led_pchlan;
 447                 /* cleanup LED */
 448                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 449                 /* turn on/off LED */
 450                 mac->ops.led_on = e1000_led_on_pchlan;
 451                 mac->ops.led_off = e1000_led_off_pchlan;
 452                 break;
 453         default:
 454                 break;
 455         }
 456
 457         /* Enable PCS Lock-loss workaround for ICH8 */
 458         if (mac->type == e1000_ich8lan)
 459                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 460
 461         return 0;
 462 }
 463
 464 /**
 465  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 466  *  @hw: pointer to the HW structure
 467  *
 468  *  Checks to see of the link status of the hardware has changed.  If a
 469  *  change in link status has been detected, then we read the PHY registers
 470  *  to get the current speed/duplex if link exists.
 471  **/
 472 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 473 {
 474         struct e1000_mac_info *mac = &hw->mac;
 475         s32 ret_val;
 476         bool link;
 477
 478         /*
 479          * We only want to go out to the PHY registers to see if Auto-Neg
 480          * has completed and/or if our link status has changed.  The
 481          * get_link_status flag is set upon receiving a Link Status
 482          * Change or Rx Sequence Error interrupt.
 483          */
 484         if (!mac->get_link_status) {
 485                 ret_val = 0;
 486                 goto out;
 487         }
 488
 489         if (hw->mac.type == e1000_pchlan) {
 490                 ret_val = e1000e_write_kmrn_reg(hw,
 491                                                    E1000_KMRNCTRLSTA_K1_CONFIG,
 492                                                    E1000_KMRNCTRLSTA_K1_ENABLE);
 493                 if (ret_val)
 494                         goto out;
 495         }
 496
 497         /*
 498          * First we want to see if the MII Status Register reports
 499          * link.  If so, then we want to get the current speed/duplex
 500          * of the PHY.
 501          */
 502         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 503         if (ret_val)
 504                 goto out;
 505
 506         if (!link)
 507                 goto out; /* No link detected */
 508
 509         mac->get_link_status = false;
 510
 511         if (hw->phy.type == e1000_phy_82578) {
 512                 ret_val = e1000_link_stall_workaround_hv(hw);
 513                 if (ret_val)
 514                         goto out;
 515         }
 516
 517         /*
 518          * Check if there was DownShift, must be checked
 519          * immediately after link-up
 520          */
 521         e1000e_check_downshift(hw);
 522
 523         /*
 524          * If we are forcing speed/duplex, then we simply return since
 525          * we have already determined whether we have link or not.
 526          */
 527         if (!mac->autoneg) {
 528                 ret_val = -E1000_ERR_CONFIG;
 529                 goto out;
 530         }
 531
 532         /*
 533          * Auto-Neg is enabled.  Auto Speed Detection takes care
 534          * of MAC speed/duplex configuration.  So we only need to
 535          * configure Collision Distance in the MAC.
 536          */
 537         e1000e_config_collision_dist(hw);
 538
 539         /*
 540          * Configure Flow Control now that Auto-Neg has completed.
 541          * First, we need to restore the desired flow control
 542          * settings because we may have had to re-autoneg with a
 543          * different link partner.
 544          */
 545         ret_val = e1000e_config_fc_after_link_up(hw);
 546         if (ret_val)
 547                 hw_dbg(hw, "Error configuring flow control\n");
 548
 549 out:
 550         return ret_val;
 551 }
 552
 553 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 554 {
 555         struct e1000_hw *hw = &adapter->hw;
 556         s32 rc;
 557
 558         rc = e1000_init_mac_params_ich8lan(adapter);
 559         if (rc)
 560                 return rc;
 561
 562         rc = e1000_init_nvm_params_ich8lan(hw);
 563         if (rc)
 564                 return rc;
 565
 566         if (hw->mac.type == e1000_pchlan)
 567                 rc = e1000_init_phy_params_pchlan(hw);
 568         else
 569                 rc = e1000_init_phy_params_ich8lan(hw);
 570         if (rc)
 571                 return rc;
 572
 573         if (adapter->hw.phy.type == e1000_phy_ife) {
 574                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 575                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 576         }
 577
 578         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 579             (adapter->hw.phy.type == e1000_phy_igp_3))
 580                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 581
 582         return 0;
 583 }
 584
 585 static DEFINE_MUTEX(nvm_mutex);
 586
 587 /**
 588  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 589  *  @hw: pointer to the HW structure
 590  *
 591  *  Acquires the software control flag for performing NVM and PHY
 592  *  operations.  This is a function pointer entry point only called by
 593  *  read/write routines for the PHY and NVM parts.
 594  **/
 595 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 596 {
 597         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 598         s32 ret_val = 0;
 599
 600         might_sleep();
 601
 602         mutex_lock(&nvm_mutex);
 603
 604         while (timeout) {
 605                 extcnf_ctrl = er32(EXTCNF_CTRL);
 606                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 607                         break;
 608
 609                 mdelay(1);
 610                 timeout--;
 611         }
 612
 613         if (!timeout) {
 614                 hw_dbg(hw, "SW/FW/HW has locked the resource for too long.\n");
 615                 ret_val = -E1000_ERR_CONFIG;
 616                 goto out;
 617         }
 618
 619         timeout = PHY_CFG_TIMEOUT * 2;
 620
 621         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 622         ew32(EXTCNF_CTRL, extcnf_ctrl);
 623
 624         while (timeout) {
 625                 extcnf_ctrl = er32(EXTCNF_CTRL);
 626                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 627                         break;
 628
 629                 mdelay(1);
 630                 timeout--;
 631         }
 632
 633         if (!timeout) {
 634                 hw_dbg(hw, "Failed to acquire the semaphore.\n");
 635                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 636                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 637                 ret_val = -E1000_ERR_CONFIG;
 638                 goto out;
 639         }
 640
 641 out:
 642         if (ret_val)
 643                 mutex_unlock(&nvm_mutex);
 644
 645         return ret_val;
 646 }
 647
 648 /**
 649  *  e1000_release_swflag_ich8lan - Release software control flag
 650  *  @hw: pointer to the HW structure
 651  *
 652  *  Releases the software control flag for performing NVM and PHY operations.
 653  *  This is a function pointer entry point only called by read/write
 654  *  routines for the PHY and NVM parts.
 655  **/
 656 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 657 {
 658         u32 extcnf_ctrl;
 659
 660         extcnf_ctrl = er32(EXTCNF_CTRL);
 661         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 662         ew32(EXTCNF_CTRL, extcnf_ctrl);
 663
 664         mutex_unlock(&nvm_mutex);
 665 }
 666
 667 /**
 668  *  e1000_check_mng_mode_ich8lan - Checks management mode
 669  *  @hw: pointer to the HW structure
 670  *
 671  *  This checks if the adapter has manageability enabled.
 672  *  This is a function pointer entry point only called by read/write
 673  *  routines for the PHY and NVM parts.
 674  **/
 675 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 676 {
 677         u32 fwsm = er32(FWSM);
 678
 679         return (fwsm & E1000_FWSM_MODE_MASK) ==
 680                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 681 }
 682
 683 /**
 684  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 685  *  @hw: pointer to the HW structure
 686  *
 687  *  Checks if firmware is blocking the reset of the PHY.
 688  *  This is a function pointer entry point only called by
 689  *  reset routines.
 690  **/
 691 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 692 {
 693         u32 fwsm;
 694
 695         fwsm = er32(FWSM);
 696
 697         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 698 }
 699
 700 /**
 701  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 702  *  @hw: pointer to the HW structure
 703  *
 704  *  Forces the speed and duplex settings of the PHY.
 705  *  This is a function pointer entry point only called by
 706  *  PHY setup routines.
 707  **/
 708 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 709 {
 710         struct e1000_phy_info *phy = &hw->phy;
 711         s32 ret_val;
 712         u16 data;
 713         bool link;
 714
 715         if (phy->type != e1000_phy_ife) {
 716                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 717                 return ret_val;
 718         }
 719
 720         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 721         if (ret_val)
 722                 return ret_val;
 723
 724         e1000e_phy_force_speed_duplex_setup(hw, &data);
 725
 726         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 727         if (ret_val)
 728                 return ret_val;
 729
 730         /* Disable MDI-X support for 10/100 */
 731         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 732         if (ret_val)
 733                 return ret_val;
 734
 735         data &= ~IFE_PMC_AUTO_MDIX;
 736         data &= ~IFE_PMC_FORCE_MDIX;
 737
 738         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 739         if (ret_val)
 740                 return ret_val;
 741
 742         hw_dbg(hw, "IFE PMC: %X\n", data);
 743
 744         udelay(1);
 745
 746         if (phy->autoneg_wait_to_complete) {
 747                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 748
 749                 ret_val = e1000e_phy_has_link_generic(hw,
 750                                                      PHY_FORCE_LIMIT,
 751                                                      100000,
 752                                                      &link);
 753                 if (ret_val)
 754                         return ret_val;
 755
 756                 if (!link)
 757                         hw_dbg(hw, "Link taking longer than expected.\n");
 758
 759                 /* Try once more */
 760                 ret_val = e1000e_phy_has_link_generic(hw,
 761                                                      PHY_FORCE_LIMIT,
 762                                                      100000,
 763                                                      &link);
 764                 if (ret_val)
 765                         return ret_val;
 766         }
 767
 768         return 0;
 769 }
 770
 771 /**
 772  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
 773  *  done after every PHY reset.
 774  **/
 775 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
 776 {
 777         s32 ret_val = 0;
 778
 779         if (hw->mac.type != e1000_pchlan)
 780                 return ret_val;
 781
 782         if (((hw->phy.type == e1000_phy_82577) &&
 783              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 784             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
 785                 /* Disable generation of early preamble */
 786                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
 787                 if (ret_val)
 788                         return ret_val;
 789
 790                 /* Preamble tuning for SSC */
 791                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
 792                 if (ret_val)
 793                         return ret_val;
 794         }
 795
 796         if (hw->phy.type == e1000_phy_82578) {
 797                 /*
 798                  * Return registers to default by doing a soft reset then
 799                  * writing 0x3140 to the control register.
 800                  */
 801                 if (hw->phy.revision < 2) {
 802                         e1000e_phy_sw_reset(hw);
 803                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
 804                 }
 805         }
 806
 807         /* Select page 0 */
 808         ret_val = hw->phy.ops.acquire_phy(hw);
 809         if (ret_val)
 810                 return ret_val;
 811         hw->phy.addr = 1;
 812         e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
 813         hw->phy.ops.release_phy(hw);
 814
 815         return ret_val;
 816 }
 817
 818 /**
 819  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
 820  *  @hw: pointer to the HW structure
 821  *
 822  *  Check the appropriate indication the MAC has finished configuring the
 823  *  PHY after a software reset.
 824  **/
 825 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
 826 {
 827         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 828
 829         /* Wait for basic configuration completes before proceeding */
 830         do {
 831                 data = er32(STATUS);
 832                 data &= E1000_STATUS_LAN_INIT_DONE;
 833                 udelay(100);
 834         } while ((!data) && --loop);
 835
 836         /*
 837          * If basic configuration is incomplete before the above loop
 838          * count reaches 0, loading the configuration from NVM will
 839          * leave the PHY in a bad state possibly resulting in no link.
 840          */
 841         if (loop == 0)
 842                 hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 843
 844         /* Clear the Init Done bit for the next init event */
 845         data = er32(STATUS);
 846         data &= ~E1000_STATUS_LAN_INIT_DONE;
 847         ew32(STATUS, data);
 848 }
 849
 850 /**
 851  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 852  *  @hw: pointer to the HW structure
 853  *
 854  *  Resets the PHY
 855  *  This is a function pointer entry point called by drivers
 856  *  or other shared routines.
 857  **/
 858 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 859 {
 860         struct e1000_phy_info *phy = &hw->phy;
 861         u32 i;
 862         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 863         s32 ret_val;
 864         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 865
 866         ret_val = e1000e_phy_hw_reset_generic(hw);
 867         if (ret_val)
 868                 return ret_val;
 869
 870         /* Allow time for h/w to get to a quiescent state after reset */
 871         mdelay(10);
 872
 873         if (hw->mac.type == e1000_pchlan) {
 874                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
 875                 if (ret_val)
 876                         return ret_val;
 877         }
 878
 879         /*
 880          * Initialize the PHY from the NVM on ICH platforms.  This
 881          * is needed due to an issue where the NVM configuration is
 882          * not properly autoloaded after power transitions.
 883          * Therefore, after each PHY reset, we will load the
 884          * configuration data out of the NVM manually.
 885          */
 886         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 887                 struct e1000_adapter *adapter = hw->adapter;
 888
 889                 /* Check if SW needs configure the PHY */
 890                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 891                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 892                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 893                 else
 894                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 895
 896                 data = er32(FEXTNVM);
 897                 if (!(data & sw_cfg_mask))
 898                         return 0;
 899
 900                 /* Wait for basic configuration completes before proceeding */
 901                 e1000_lan_init_done_ich8lan(hw);
 902
 903                 /*
 904                  * Make sure HW does not configure LCD from PHY
 905                  * extended configuration before SW configuration
 906                  */
 907                 data = er32(EXTCNF_CTRL);
 908                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 909                         return 0;
 910
 911                 cnf_size = er32(EXTCNF_SIZE);
 912                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 913                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 914                 if (!cnf_size)
 915                         return 0;
 916
 917                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 918                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 919
 920                 /* Configure LCD from extended configuration region. */
 921
 922                 /* cnf_base_addr is in DWORD */
 923                 word_addr = (u16)(cnf_base_addr << 1);
 924
 925                 for (i = 0; i < cnf_size; i++) {
 926                         ret_val = e1000_read_nvm(hw,
 927                                                 (word_addr + i * 2),
 928                                                 1,
 929                                                 &reg_data);
 930                         if (ret_val)
 931                                 return ret_val;
 932
 933                         ret_val = e1000_read_nvm(hw,
 934                                                 (word_addr + i * 2 + 1),
 935                                                 1,
 936                                                 &reg_addr);
 937                         if (ret_val)
 938                                 return ret_val;
 939
 940                         /* Save off the PHY page for future writes. */
 941                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 942                                 phy_page = reg_data;
 943                                 continue;
 944                         }
 945
 946                         reg_addr |= phy_page;
 947
 948                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 949                         if (ret_val)
 950                                 return ret_val;
 951                 }
 952         }
 953
 954         return 0;
 955 }
 956
 957 /**
 958  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 959  *  @hw: pointer to the HW structure
 960  *
 961  *  Populates "phy" structure with various feature states.
 962  *  This function is only called by other family-specific
 963  *  routines.
 964  **/
 965 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 966 {
 967         struct e1000_phy_info *phy = &hw->phy;
 968         s32 ret_val;
 969         u16 data;
 970         bool link;
 971
 972         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 973         if (ret_val)
 974                 return ret_val;
 975
 976         if (!link) {
 977                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 978                 return -E1000_ERR_CONFIG;
 979         }
 980
 981         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 982         if (ret_val)
 983                 return ret_val;
 984         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 985
 986         if (phy->polarity_correction) {
 987                 ret_val = phy->ops.check_polarity(hw);
 988                 if (ret_val)
 989                         return ret_val;
 990         } else {
 991                 /* Polarity is forced */
 992                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 993                                       ? e1000_rev_polarity_reversed
 994                                       : e1000_rev_polarity_normal;
 995         }
 996
 997         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 998         if (ret_val)
 999                 return ret_val;
1000
1001         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
1002
1003         /* The following parameters are undefined for 10/100 operation. */
1004         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1005         phy->local_rx = e1000_1000t_rx_status_undefined;
1006         phy->remote_rx = e1000_1000t_rx_status_undefined;
1007
1008         return 0;
1009 }
1010
1011 /**
1012  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1013  *  @hw: pointer to the HW structure
1014  *
1015  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
1016  *  This is a function pointer entry point called by drivers
1017  *  or other shared routines.
1018  **/
1019 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1020 {
1021         switch (hw->phy.type) {
1022         case e1000_phy_ife:
1023                 return e1000_get_phy_info_ife_ich8lan(hw);
1024                 break;
1025         case e1000_phy_igp_3:
1026         case e1000_phy_bm:
1027         case e1000_phy_82578:
1028         case e1000_phy_82577:
1029                 return e1000e_get_phy_info_igp(hw);
1030                 break;
1031         default:
1032                 break;
1033         }
1034
1035         return -E1000_ERR_PHY_TYPE;
1036 }
1037
1038 /**
1039  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
1040  *  @hw: pointer to the HW structure
1041  *
1042  *  Polarity is determined on the polarity reversal feature being enabled.
1043  *  This function is only called by other family-specific
1044  *  routines.
1045  **/
1046 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
1047 {
1048         struct e1000_phy_info *phy = &hw->phy;
1049         s32 ret_val;
1050         u16 phy_data, offset, mask;
1051
1052         /*
1053          * Polarity is determined based on the reversal feature being enabled.
1054          */
1055         if (phy->polarity_correction) {
1056                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
1057                 mask    = IFE_PESC_POLARITY_REVERSED;
1058         } else {
1059                 offset  = IFE_PHY_SPECIAL_CONTROL;
1060                 mask    = IFE_PSC_FORCE_POLARITY;
1061         }
1062
1063         ret_val = e1e_rphy(hw, offset, &phy_data);
1064
1065         if (!ret_val)
1066                 phy->cable_polarity = (phy_data & mask)
1067                                       ? e1000_rev_polarity_reversed
1068                                       : e1000_rev_polarity_normal;
1069
1070         return ret_val;
1071 }
1072
1073 /**
1074  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1075  *  @hw: pointer to the HW structure
1076  *  @active: TRUE to enable LPLU, FALSE to disable
1077  *
1078  *  Sets the LPLU D0 state according to the active flag.  When
1079  *  activating LPLU this function also disables smart speed
1080  *  and vice versa.  LPLU will not be activated unless the
1081  *  device autonegotiation advertisement meets standards of
1082  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1083  *  This is a function pointer entry point only called by
1084  *  PHY setup routines.
1085  **/
1086 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1087 {
1088         struct e1000_phy_info *phy = &hw->phy;
1089         u32 phy_ctrl;
1090         s32 ret_val = 0;
1091         u16 data;
1092
1093         if (phy->type == e1000_phy_ife)
1094                 return ret_val;
1095
1096         phy_ctrl = er32(PHY_CTRL);
1097
1098         if (active) {
1099                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1100                 ew32(PHY_CTRL, phy_ctrl);
1101
1102                 if (phy->type != e1000_phy_igp_3)
1103                         return 0;
1104
1105                 /*
1106                  * Call gig speed drop workaround on LPLU before accessing
1107                  * any PHY registers
1108                  */
1109                 if (hw->mac.type == e1000_ich8lan)
1110                         e1000e_gig_downshift_workaround_ich8lan(hw);
1111
1112                 /* When LPLU is enabled, we should disable SmartSpeed */
1113                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1114                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1115                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1116                 if (ret_val)
1117                         return ret_val;
1118         } else {
1119                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1120                 ew32(PHY_CTRL, phy_ctrl);
1121
1122                 if (phy->type != e1000_phy_igp_3)
1123                         return 0;
1124
1125                 /*
1126                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1127                  * during Dx states where the power conservation is most
1128                  * important.  During driver activity we should enable
1129                  * SmartSpeed, so performance is maintained.
1130                  */
1131                 if (phy->smart_speed == e1000_smart_speed_on) {
1132                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1133                                            &data);
1134                         if (ret_val)
1135                                 return ret_val;
1136
1137                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1138                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1139                                            data);
1140                         if (ret_val)
1141                                 return ret_val;
1142                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1143                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1144                                            &data);
1145                         if (ret_val)
1146                                 return ret_val;
1147
1148                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1149                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1150                                            data);
1151                         if (ret_val)
1152                                 return ret_val;
1153                 }
1154         }
1155
1156         return 0;
1157 }
1158
1159 /**
1160  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1161  *  @hw: pointer to the HW structure
1162  *  @active: TRUE to enable LPLU, FALSE to disable
1163  *
1164  *  Sets the LPLU D3 state according to the active flag.  When
1165  *  activating LPLU this function also disables smart speed
1166  *  and vice versa.  LPLU will not be activated unless the
1167  *  device autonegotiation advertisement meets standards of
1168  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1169  *  This is a function pointer entry point only called by
1170  *  PHY setup routines.
1171  **/
1172 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1173 {
1174         struct e1000_phy_info *phy = &hw->phy;
1175         u32 phy_ctrl;
1176         s32 ret_val;
1177         u16 data;
1178
1179         phy_ctrl = er32(PHY_CTRL);
1180
1181         if (!active) {
1182                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1183                 ew32(PHY_CTRL, phy_ctrl);
1184
1185                 if (phy->type != e1000_phy_igp_3)
1186                         return 0;
1187
1188                 /*
1189                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1190                  * during Dx states where the power conservation is most
1191                  * important.  During driver activity we should enable
1192                  * SmartSpeed, so performance is maintained.
1193                  */
1194                 if (phy->smart_speed == e1000_smart_speed_on) {
1195                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1196                                            &data);
1197                         if (ret_val)
1198                                 return ret_val;
1199
1200                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1201                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1202                                            data);
1203                         if (ret_val)
1204                                 return ret_val;
1205                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1206                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1207                                            &data);
1208                         if (ret_val)
1209                                 return ret_val;
1210
1211                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1212                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1213                                            data);
1214                         if (ret_val)
1215                                 return ret_val;
1216                 }
1217         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1218                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1219                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1220                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1221                 ew32(PHY_CTRL, phy_ctrl);
1222
1223                 if (phy->type != e1000_phy_igp_3)
1224                         return 0;
1225
1226                 /*
1227                  * Call gig speed drop workaround on LPLU before accessing
1228                  * any PHY registers
1229                  */
1230                 if (hw->mac.type == e1000_ich8lan)
1231                         e1000e_gig_downshift_workaround_ich8lan(hw);
1232
1233                 /* When LPLU is enabled, we should disable SmartSpeed */
1234                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1235                 if (ret_val)
1236                         return ret_val;
1237
1238                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1239                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1240         }
1241
1242         return 0;
1243 }
1244
1245 /**
1246  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1247  *  @hw: pointer to the HW structure
1248  *  @bank:  pointer to the variable that returns the active bank
1249  *
1250  *  Reads signature byte from the NVM using the flash access registers.
1251  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1252  **/
1253 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1254 {
1255         u32 eecd;
1256         struct e1000_nvm_info *nvm = &hw->nvm;
1257         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1258         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1259         u8 sig_byte = 0;
1260         s32 ret_val = 0;
1261
1262         switch (hw->mac.type) {
1263         case e1000_ich8lan:
1264         case e1000_ich9lan:
1265                 eecd = er32(EECD);
1266                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1267                     E1000_EECD_SEC1VAL_VALID_MASK) {
1268                         if (eecd & E1000_EECD_SEC1VAL)
1269                                 *bank = 1;
1270                         else
1271                                 *bank = 0;
1272
1273                         return 0;
1274                 }
1275                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
1276                        "reading flash signature\n");
1277                 /* fall-thru */
1278         default:
1279                 /* set bank to 0 in case flash read fails */
1280                 *bank = 0;
1281
1282                 /* Check bank 0 */
1283                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1284                                                         &sig_byte);
1285                 if (ret_val)
1286                         return ret_val;
1287                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1288                     E1000_ICH_NVM_SIG_VALUE) {
1289                         *bank = 0;
1290                         return 0;
1291                 }
1292
1293                 /* Check bank 1 */
1294                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1295                                                         bank1_offset,
1296                                                         &sig_byte);
1297                 if (ret_val)
1298                         return ret_val;
1299                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1300                     E1000_ICH_NVM_SIG_VALUE) {
1301                         *bank = 1;
1302                         return 0;
1303                 }
1304
1305                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1306                 return -E1000_ERR_NVM;
1307         }
1308
1309         return 0;
1310 }
1311
1312 /**
1313  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1314  *  @hw: pointer to the HW structure
1315  *  @offset: The offset (in bytes) of the word(s) to read.
1316  *  @words: Size of data to read in words
1317  *  @data: Pointer to the word(s) to read at offset.
1318  *
1319  *  Reads a word(s) from the NVM using the flash access registers.
1320  **/
1321 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1322                                   u16 *data)
1323 {
1324         struct e1000_nvm_info *nvm = &hw->nvm;
1325         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1326         u32 act_offset;
1327         s32 ret_val;
1328         u32 bank = 0;
1329         u16 i, word;
1330
1331         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1332             (words == 0)) {
1333                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1334                 return -E1000_ERR_NVM;
1335         }
1336
1337         ret_val = e1000_acquire_swflag_ich8lan(hw);
1338         if (ret_val)
1339                 goto out;
1340
1341         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1342         if (ret_val)
1343                 goto release;
1344
1345         act_offset = (bank) ? nvm->flash_bank_size : 0;
1346         act_offset += offset;
1347
1348         for (i = 0; i < words; i++) {
1349                 if ((dev_spec->shadow_ram) &&
1350                     (dev_spec->shadow_ram[offset+i].modified)) {
1351                         data[i] = dev_spec->shadow_ram[offset+i].value;
1352                 } else {
1353                         ret_val = e1000_read_flash_word_ich8lan(hw,
1354                                                                 act_offset + i,
1355                                                                 &word);
1356                         if (ret_val)
1357                                 break;
1358                         data[i] = word;
1359                 }
1360         }
1361
1362 release:
1363         e1000_release_swflag_ich8lan(hw);
1364
1365 out:
1366         if (ret_val)
1367                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1368
1369         return ret_val;
1370 }
1371
1372 /**
1373  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  This function does initial flash setup so that a new read/write/erase cycle
1377  *  can be started.
1378  **/
1379 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1380 {
1381         union ich8_hws_flash_status hsfsts;
1382         s32 ret_val = -E1000_ERR_NVM;
1383         s32 i = 0;
1384
1385         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1386
1387         /* Check if the flash descriptor is valid */
1388         if (hsfsts.hsf_status.fldesvalid == 0) {
1389                 hw_dbg(hw, "Flash descriptor invalid.  "
1390                          "SW Sequencing must be used.");
1391                 return -E1000_ERR_NVM;
1392         }
1393
1394         /* Clear FCERR and DAEL in hw status by writing 1 */
1395         hsfsts.hsf_status.flcerr = 1;
1396         hsfsts.hsf_status.dael = 1;
1397
1398         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1399
1400         /*
1401          * Either we should have a hardware SPI cycle in progress
1402          * bit to check against, in order to start a new cycle or
1403          * FDONE bit should be changed in the hardware so that it
1404          * is 1 after hardware reset, which can then be used as an
1405          * indication whether a cycle is in progress or has been
1406          * completed.
1407          */
1408
1409         if (hsfsts.hsf_status.flcinprog == 0) {
1410                 /*
1411                  * There is no cycle running at present,
1412                  * so we can start a cycle
1413                  * Begin by setting Flash Cycle Done.
1414                  */
1415                 hsfsts.hsf_status.flcdone = 1;
1416                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1417                 ret_val = 0;
1418         } else {
1419                 /*
1420                  * otherwise poll for sometime so the current
1421                  * cycle has a chance to end before giving up.
1422                  */
1423                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1424                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1425                         if (hsfsts.hsf_status.flcinprog == 0) {
1426                                 ret_val = 0;
1427                                 break;
1428                         }
1429                         udelay(1);
1430                 }
1431                 if (ret_val == 0) {
1432                         /*
1433                          * Successful in waiting for previous cycle to timeout,
1434                          * now set the Flash Cycle Done.
1435                          */
1436                         hsfsts.hsf_status.flcdone = 1;
1437                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1438                 } else {
1439                         hw_dbg(hw, "Flash controller busy, cannot get access");
1440                 }
1441         }
1442
1443         return ret_val;
1444 }
1445
1446 /**
1447  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1448  *  @hw: pointer to the HW structure
1449  *  @timeout: maximum time to wait for completion
1450  *
1451  *  This function starts a flash cycle and waits for its completion.
1452  **/
1453 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1454 {
1455         union ich8_hws_flash_ctrl hsflctl;
1456         union ich8_hws_flash_status hsfsts;
1457         s32 ret_val = -E1000_ERR_NVM;
1458         u32 i = 0;
1459
1460         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1461         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1462         hsflctl.hsf_ctrl.flcgo = 1;
1463         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1464
1465         /* wait till FDONE bit is set to 1 */
1466         do {
1467                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1468                 if (hsfsts.hsf_status.flcdone == 1)
1469                         break;
1470                 udelay(1);
1471         } while (i++ < timeout);
1472
1473         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1474                 return 0;
1475
1476         return ret_val;
1477 }
1478
1479 /**
1480  *  e1000_read_flash_word_ich8lan - Read word from flash
1481  *  @hw: pointer to the HW structure
1482  *  @offset: offset to data location
1483  *  @data: pointer to the location for storing the data
1484  *
1485  *  Reads the flash word at offset into data.  Offset is converted
1486  *  to bytes before read.
1487  **/
1488 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1489                                          u16 *data)
1490 {
1491         /* Must convert offset into bytes. */
1492         offset <<= 1;
1493
1494         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1495 }
1496
1497 /**
1498  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1499  *  @hw: pointer to the HW structure
1500  *  @offset: The offset of the byte to read.
1501  *  @data: Pointer to a byte to store the value read.
1502  *
1503  *  Reads a single byte from the NVM using the flash access registers.
1504  **/
1505 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1506                                          u8 *data)
1507 {
1508         s32 ret_val;
1509         u16 word = 0;
1510
1511         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1512         if (ret_val)
1513                 return ret_val;
1514
1515         *data = (u8)word;
1516
1517         return 0;
1518 }
1519
1520 /**
1521  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1522  *  @hw: pointer to the HW structure
1523  *  @offset: The offset (in bytes) of the byte or word to read.
1524  *  @size: Size of data to read, 1=byte 2=word
1525  *  @data: Pointer to the word to store the value read.
1526  *
1527  *  Reads a byte or word from the NVM using the flash access registers.
1528  **/
1529 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1530                                          u8 size, u16 *data)
1531 {
1532         union ich8_hws_flash_status hsfsts;
1533         union ich8_hws_flash_ctrl hsflctl;
1534         u32 flash_linear_addr;
1535         u32 flash_data = 0;
1536         s32 ret_val = -E1000_ERR_NVM;
1537         u8 count = 0;
1538
1539         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1540                 return -E1000_ERR_NVM;
1541
1542         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1543                             hw->nvm.flash_base_addr;
1544
1545         do {
1546                 udelay(1);
1547                 /* Steps */
1548                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1549                 if (ret_val != 0)
1550                         break;
1551
1552                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1553                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1554                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1555                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1556                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1557
1558                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1559
1560                 ret_val = e1000_flash_cycle_ich8lan(hw,
1561                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1562
1563                 /*
1564                  * Check if FCERR is set to 1, if set to 1, clear it
1565                  * and try the whole sequence a few more times, else
1566                  * read in (shift in) the Flash Data0, the order is
1567                  * least significant byte first msb to lsb
1568                  */
1569                 if (ret_val == 0) {
1570                         flash_data = er32flash(ICH_FLASH_FDATA0);
1571                         if (size == 1) {
1572                                 *data = (u8)(flash_data & 0x000000FF);
1573                         } else if (size == 2) {
1574                                 *data = (u16)(flash_data & 0x0000FFFF);
1575                         }
1576                         break;
1577                 } else {
1578                         /*
1579                          * If we've gotten here, then things are probably
1580                          * completely hosed, but if the error condition is
1581                          * detected, it won't hurt to give it another try...
1582                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1583                          */
1584                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1585                         if (hsfsts.hsf_status.flcerr == 1) {
1586                                 /* Repeat for some time before giving up. */
1587                                 continue;
1588                         } else if (hsfsts.hsf_status.flcdone == 0) {
1589                                 hw_dbg(hw, "Timeout error - flash cycle "
1590                                          "did not complete.");
1591                                 break;
1592                         }
1593                 }
1594         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1595
1596         return ret_val;
1597 }
1598
1599 /**
1600  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1601  *  @hw: pointer to the HW structure
1602  *  @offset: The offset (in bytes) of the word(s) to write.
1603  *  @words: Size of data to write in words
1604  *  @data: Pointer to the word(s) to write at offset.
1605  *
1606  *  Writes a byte or word to the NVM using the flash access registers.
1607  **/
1608 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1609                                    u16 *data)
1610 {
1611         struct e1000_nvm_info *nvm = &hw->nvm;
1612         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1613         s32 ret_val;
1614         u16 i;
1615
1616         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1617             (words == 0)) {
1618                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1619                 return -E1000_ERR_NVM;
1620         }
1621
1622         ret_val = e1000_acquire_swflag_ich8lan(hw);
1623         if (ret_val)
1624                 return ret_val;
1625
1626         for (i = 0; i < words; i++) {
1627                 dev_spec->shadow_ram[offset+i].modified = 1;
1628                 dev_spec->shadow_ram[offset+i].value = data[i];
1629         }
1630
1631         e1000_release_swflag_ich8lan(hw);
1632
1633         return 0;
1634 }
1635
1636 /**
1637  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1638  *  @hw: pointer to the HW structure
1639  *
1640  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1641  *  which writes the checksum to the shadow ram.  The changes in the shadow
1642  *  ram are then committed to the EEPROM by processing each bank at a time
1643  *  checking for the modified bit and writing only the pending changes.
1644  *  After a successful commit, the shadow ram is cleared and is ready for
1645  *  future writes.
1646  **/
1647 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1648 {
1649         struct e1000_nvm_info *nvm = &hw->nvm;
1650         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1651         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1652         s32 ret_val;
1653         u16 data;
1654
1655         ret_val = e1000e_update_nvm_checksum_generic(hw);
1656         if (ret_val)
1657                 goto out;
1658
1659         if (nvm->type != e1000_nvm_flash_sw)
1660                 goto out;
1661
1662         ret_val = e1000_acquire_swflag_ich8lan(hw);
1663         if (ret_val)
1664                 goto out;
1665
1666         /*
1667          * We're writing to the opposite bank so if we're on bank 1,
1668          * write to bank 0 etc.  We also need to erase the segment that
1669          * is going to be written
1670          */
1671         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1672         if (ret_val) {
1673                 e1000_release_swflag_ich8lan(hw);
1674                 goto out;
1675         }
1676
1677         if (bank == 0) {
1678                 new_bank_offset = nvm->flash_bank_size;
1679                 old_bank_offset = 0;
1680                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1681                 if (ret_val) {
1682                         e1000_release_swflag_ich8lan(hw);
1683                         goto out;
1684                 }
1685         } else {
1686                 old_bank_offset = nvm->flash_bank_size;
1687                 new_bank_offset = 0;
1688                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1689                 if (ret_val) {
1690                         e1000_release_swflag_ich8lan(hw);
1691                         goto out;
1692                 }
1693         }
1694
1695         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1696                 /*
1697                  * Determine whether to write the value stored
1698                  * in the other NVM bank or a modified value stored
1699                  * in the shadow RAM
1700                  */
1701                 if (dev_spec->shadow_ram[i].modified) {
1702                         data = dev_spec->shadow_ram[i].value;
1703                 } else {
1704                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1705                                                                 old_bank_offset,
1706                                                                 &data);
1707                         if (ret_val)
1708                                 break;
1709                 }
1710
1711                 /*
1712                  * If the word is 0x13, then make sure the signature bits
1713                  * (15:14) are 11b until the commit has completed.
1714                  * This will allow us to write 10b which indicates the
1715                  * signature is valid.  We want to do this after the write
1716                  * has completed so that we don't mark the segment valid
1717                  * while the write is still in progress
1718                  */
1719                 if (i == E1000_ICH_NVM_SIG_WORD)
1720                         data |= E1000_ICH_NVM_SIG_MASK;
1721
1722                 /* Convert offset to bytes. */
1723                 act_offset = (i + new_bank_offset) << 1;
1724
1725                 udelay(100);
1726                 /* Write the bytes to the new bank. */
1727                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1728                                                                act_offset,
1729                                                                (u8)data);
1730                 if (ret_val)
1731                         break;
1732
1733                 udelay(100);
1734                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1735                                                           act_offset + 1,
1736                                                           (u8)(data >> 8));
1737                 if (ret_val)
1738                         break;
1739         }
1740
1741         /*
1742          * Don't bother writing the segment valid bits if sector
1743          * programming failed.
1744          */
1745         if (ret_val) {
1746                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1747                 hw_dbg(hw, "Flash commit failed.\n");
1748                 e1000_release_swflag_ich8lan(hw);
1749                 goto out;
1750         }
1751
1752         /*
1753          * Finally validate the new segment by setting bit 15:14
1754          * to 10b in word 0x13 , this can be done without an
1755          * erase as well since these bits are 11 to start with
1756          * and we need to change bit 14 to 0b
1757          */
1758         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1759         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1760         if (ret_val) {
1761                 e1000_release_swflag_ich8lan(hw);
1762                 goto out;
1763         }
1764         data &= 0xBFFF;
1765         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1766                                                        act_offset * 2 + 1,
1767                                                        (u8)(data >> 8));
1768         if (ret_val) {
1769                 e1000_release_swflag_ich8lan(hw);
1770                 goto out;
1771         }
1772
1773         /*
1774          * And invalidate the previously valid segment by setting
1775          * its signature word (0x13) high_byte to 0b. This can be
1776          * done without an erase because flash erase sets all bits
1777          * to 1's. We can write 1's to 0's without an erase
1778          */
1779         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1780         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1781         if (ret_val) {
1782                 e1000_release_swflag_ich8lan(hw);
1783                 goto out;
1784         }
1785
1786         /* Great!  Everything worked, we can now clear the cached entries. */
1787         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1788                 dev_spec->shadow_ram[i].modified = 0;
1789                 dev_spec->shadow_ram[i].value = 0xFFFF;
1790         }
1791
1792         e1000_release_swflag_ich8lan(hw);
1793
1794         /*
1795          * Reload the EEPROM, or else modifications will not appear
1796          * until after the next adapter reset.
1797          */
1798         e1000e_reload_nvm(hw);
1799         msleep(10);
1800
1801 out:
1802         if (ret_val)
1803                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1804
1805         return ret_val;
1806 }
1807
1808 /**
1809  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1810  *  @hw: pointer to the HW structure
1811  *
1812  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1813  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1814  *  calculated, in which case we need to calculate the checksum and set bit 6.
1815  **/
1816 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1817 {
1818         s32 ret_val;
1819         u16 data;
1820
1821         /*
1822          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1823          * needs to be fixed.  This bit is an indication that the NVM
1824          * was prepared by OEM software and did not calculate the
1825          * checksum...a likely scenario.
1826          */
1827         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1828         if (ret_val)
1829                 return ret_val;
1830
1831         if ((data & 0x40) == 0) {
1832                 data |= 0x40;
1833                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1834                 if (ret_val)
1835                         return ret_val;
1836                 ret_val = e1000e_update_nvm_checksum(hw);
1837                 if (ret_val)
1838                         return ret_val;
1839         }
1840
1841         return e1000e_validate_nvm_checksum_generic(hw);
1842 }
1843
1844 /**
1845  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1846  *  @hw: pointer to the HW structure
1847  *
1848  *  To prevent malicious write/erase of the NVM, set it to be read-only
1849  *  so that the hardware ignores all write/erase cycles of the NVM via
1850  *  the flash control registers.  The shadow-ram copy of the NVM will
1851  *  still be updated, however any updates to this copy will not stick
1852  *  across driver reloads.
1853  **/
1854 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1855 {
1856         union ich8_flash_protected_range pr0;
1857         union ich8_hws_flash_status hsfsts;
1858         u32 gfpreg;
1859         s32 ret_val;
1860
1861         ret_val = e1000_acquire_swflag_ich8lan(hw);
1862         if (ret_val)
1863                 return;
1864
1865         gfpreg = er32flash(ICH_FLASH_GFPREG);
1866
1867         /* Write-protect GbE Sector of NVM */
1868         pr0.regval = er32flash(ICH_FLASH_PR0);
1869         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1870         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1871         pr0.range.wpe = true;
1872         ew32flash(ICH_FLASH_PR0, pr0.regval);
1873
1874         /*
1875          * Lock down a subset of GbE Flash Control Registers, e.g.
1876          * PR0 to prevent the write-protection from being lifted.
1877          * Once FLOCKDN is set, the registers protected by it cannot
1878          * be written until FLOCKDN is cleared by a hardware reset.
1879          */
1880         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1881         hsfsts.hsf_status.flockdn = true;
1882         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1883
1884         e1000_release_swflag_ich8lan(hw);
1885 }
1886
1887 /**
1888  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1889  *  @hw: pointer to the HW structure
1890  *  @offset: The offset (in bytes) of the byte/word to read.
1891  *  @size: Size of data to read, 1=byte 2=word
1892  *  @data: The byte(s) to write to the NVM.
1893  *
1894  *  Writes one/two bytes to the NVM using the flash access registers.
1895  **/
1896 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1897                                           u8 size, u16 data)
1898 {
1899         union ich8_hws_flash_status hsfsts;
1900         union ich8_hws_flash_ctrl hsflctl;
1901         u32 flash_linear_addr;
1902         u32 flash_data = 0;
1903         s32 ret_val;
1904         u8 count = 0;
1905
1906         if (size < 1 || size > 2 || data > size * 0xff ||
1907             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1908                 return -E1000_ERR_NVM;
1909
1910         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1911                             hw->nvm.flash_base_addr;
1912
1913         do {
1914                 udelay(1);
1915                 /* Steps */
1916                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1917                 if (ret_val)
1918                         break;
1919
1920                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1921                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1922                 hsflctl.hsf_ctrl.fldbcount = size -1;
1923                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1924                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1925
1926                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1927
1928                 if (size == 1)
1929                         flash_data = (u32)data & 0x00FF;
1930                 else
1931                         flash_data = (u32)data;
1932
1933                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1934
1935                 /*
1936                  * check if FCERR is set to 1 , if set to 1, clear it
1937                  * and try the whole sequence a few more times else done
1938                  */
1939                 ret_val = e1000_flash_cycle_ich8lan(hw,
1940                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1941                 if (!ret_val)
1942                         break;
1943
1944                 /*
1945                  * If we're here, then things are most likely
1946                  * completely hosed, but if the error condition
1947                  * is detected, it won't hurt to give it another
1948                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1949                  */
1950                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1951                 if (hsfsts.hsf_status.flcerr == 1)
1952                         /* Repeat for some time before giving up. */
1953                         continue;
1954                 if (hsfsts.hsf_status.flcdone == 0) {
1955                         hw_dbg(hw, "Timeout error - flash cycle "
1956                                  "did not complete.");
1957                         break;
1958                 }
1959         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1960
1961         return ret_val;
1962 }
1963
1964 /**
1965  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1966  *  @hw: pointer to the HW structure
1967  *  @offset: The index of the byte to read.
1968  *  @data: The byte to write to the NVM.
1969  *
1970  *  Writes a single byte to the NVM using the flash access registers.
1971  **/
1972 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1973                                           u8 data)
1974 {
1975         u16 word = (u16)data;
1976
1977         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1978 }
1979
1980 /**
1981  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1982  *  @hw: pointer to the HW structure
1983  *  @offset: The offset of the byte to write.
1984  *  @byte: The byte to write to the NVM.
1985  *
1986  *  Writes a single byte to the NVM using the flash access registers.
1987  *  Goes through a retry algorithm before giving up.
1988  **/
1989 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1990                                                 u32 offset, u8 byte)
1991 {
1992         s32 ret_val;
1993         u16 program_retries;
1994
1995         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1996         if (!ret_val)
1997                 return ret_val;
1998
1999         for (program_retries = 0; program_retries < 100; program_retries++) {
2000                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
2001                 udelay(100);
2002                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2003                 if (!ret_val)
2004                         break;
2005         }
2006         if (program_retries == 100)
2007                 return -E1000_ERR_NVM;
2008
2009         return 0;
2010 }
2011
2012 /**
2013  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2014  *  @hw: pointer to the HW structure
2015  *  @bank: 0 for first bank, 1 for second bank, etc.
2016  *
2017  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2018  *  bank N is 4096 * N + flash_reg_addr.
2019  **/
2020 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2021 {
2022         struct e1000_nvm_info *nvm = &hw->nvm;
2023         union ich8_hws_flash_status hsfsts;
2024         union ich8_hws_flash_ctrl hsflctl;
2025         u32 flash_linear_addr;
2026         /* bank size is in 16bit words - adjust to bytes */
2027         u32 flash_bank_size = nvm->flash_bank_size * 2;
2028         s32 ret_val;
2029         s32 count = 0;
2030         s32 iteration;
2031         s32 sector_size;
2032         s32 j;
2033
2034         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2035
2036         /*
2037          * Determine HW Sector size: Read BERASE bits of hw flash status
2038          * register
2039          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2040          *     consecutive sectors.  The start index for the nth Hw sector
2041          *     can be calculated as = bank * 4096 + n * 256
2042          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2043          *     The start index for the nth Hw sector can be calculated
2044          *     as = bank * 4096
2045          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2046          *     (ich9 only, otherwise error condition)
2047          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2048          */
2049         switch (hsfsts.hsf_status.berasesz) {
2050         case 0:
2051                 /* Hw sector size 256 */
2052                 sector_size = ICH_FLASH_SEG_SIZE_256;
2053                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2054                 break;
2055         case 1:
2056                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2057                 iteration = 1;
2058                 break;
2059         case 2:
2060                 if (hw->mac.type == e1000_ich9lan) {
2061                         sector_size = ICH_FLASH_SEG_SIZE_8K;
2062                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
2063                 } else {
2064                         return -E1000_ERR_NVM;
2065                 }
2066                 break;
2067         case 3:
2068                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2069                 iteration = 1;
2070                 break;
2071         default:
2072                 return -E1000_ERR_NVM;
2073         }
2074
2075         /* Start with the base address, then add the sector offset. */
2076         flash_linear_addr = hw->nvm.flash_base_addr;
2077         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
2078
2079         for (j = 0; j < iteration ; j++) {
2080                 do {
2081                         /* Steps */
2082                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2083                         if (ret_val)
2084                                 return ret_val;
2085
2086                         /*
2087                          * Write a value 11 (block Erase) in Flash
2088                          * Cycle field in hw flash control
2089                          */
2090                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2091                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2092                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2093
2094                         /*
2095                          * Write the last 24 bits of an index within the
2096                          * block into Flash Linear address field in Flash
2097                          * Address.
2098                          */
2099                         flash_linear_addr += (j * sector_size);
2100                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2101
2102                         ret_val = e1000_flash_cycle_ich8lan(hw,
2103                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2104                         if (ret_val == 0)
2105                                 break;
2106
2107                         /*
2108                          * Check if FCERR is set to 1.  If 1,
2109                          * clear it and try the whole sequence
2110                          * a few more times else Done
2111                          */
2112                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2113                         if (hsfsts.hsf_status.flcerr == 1)
2114                                 /* repeat for some time before giving up */
2115                                 continue;
2116                         else if (hsfsts.hsf_status.flcdone == 0)
2117                                 return ret_val;
2118                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2119         }
2120
2121         return 0;
2122 }
2123
2124 /**
2125  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2126  *  @hw: pointer to the HW structure
2127  *  @data: Pointer to the LED settings
2128  *
2129  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2130  *  settings is all 0's or F's, set the LED default to a valid LED default
2131  *  setting.
2132  **/
2133 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2134 {
2135         s32 ret_val;
2136
2137         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2138         if (ret_val) {
2139                 hw_dbg(hw, "NVM Read Error\n");
2140                 return ret_val;
2141         }
2142
2143         if (*data == ID_LED_RESERVED_0000 ||
2144             *data == ID_LED_RESERVED_FFFF)
2145                 *data = ID_LED_DEFAULT_ICH8LAN;
2146
2147         return 0;
2148 }
2149
2150 /**
2151  *  e1000_id_led_init_pchlan - store LED configurations
2152  *  @hw: pointer to the HW structure
2153  *
2154  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2155  *  the PHY LED configuration register.
2156  *
2157  *  PCH also does not have an "always on" or "always off" mode which
2158  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2159  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2160  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2161  *  link based on logic in e1000_led_[on|off]_pchlan().
2162  **/
2163 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2164 {
2165         struct e1000_mac_info *mac = &hw->mac;
2166         s32 ret_val;
2167         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2168         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2169         u16 data, i, temp, shift;
2170
2171         /* Get default ID LED modes */
2172         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2173         if (ret_val)
2174                 goto out;
2175
2176         mac->ledctl_default = er32(LEDCTL);
2177         mac->ledctl_mode1 = mac->ledctl_default;
2178         mac->ledctl_mode2 = mac->ledctl_default;
2179
2180         for (i = 0; i < 4; i++) {
2181                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2182                 shift = (i * 5);
2183                 switch (temp) {
2184                 case ID_LED_ON1_DEF2:
2185                 case ID_LED_ON1_ON2:
2186                 case ID_LED_ON1_OFF2:
2187                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2188                         mac->ledctl_mode1 |= (ledctl_on << shift);
2189                         break;
2190                 case ID_LED_OFF1_DEF2:
2191                 case ID_LED_OFF1_ON2:
2192                 case ID_LED_OFF1_OFF2:
2193                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2194                         mac->ledctl_mode1 |= (ledctl_off << shift);
2195                         break;
2196                 default:
2197                         /* Do nothing */
2198                         break;
2199                 }
2200                 switch (temp) {
2201                 case ID_LED_DEF1_ON2:
2202                 case ID_LED_ON1_ON2:
2203                 case ID_LED_OFF1_ON2:
2204                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2205                         mac->ledctl_mode2 |= (ledctl_on << shift);
2206                         break;
2207                 case ID_LED_DEF1_OFF2:
2208                 case ID_LED_ON1_OFF2:
2209                 case ID_LED_OFF1_OFF2:
2210                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2211                         mac->ledctl_mode2 |= (ledctl_off << shift);
2212                         break;
2213                 default:
2214                         /* Do nothing */
2215                         break;
2216                 }
2217         }
2218
2219 out:
2220         return ret_val;
2221 }
2222
2223 /**
2224  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2225  *  @hw: pointer to the HW structure
2226  *
2227  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2228  *  register, so the the bus width is hard coded.
2229  **/
2230 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2231 {
2232         struct e1000_bus_info *bus = &hw->bus;
2233         s32 ret_val;
2234
2235         ret_val = e1000e_get_bus_info_pcie(hw);
2236
2237         /*
2238          * ICH devices are "PCI Express"-ish.  They have
2239          * a configuration space, but do not contain
2240          * PCI Express Capability registers, so bus width
2241          * must be hardcoded.
2242          */
2243         if (bus->width == e1000_bus_width_unknown)
2244                 bus->width = e1000_bus_width_pcie_x1;
2245
2246         return ret_val;
2247 }
2248
2249 /**
2250  *  e1000_reset_hw_ich8lan - Reset the hardware
2251  *  @hw: pointer to the HW structure
2252  *
2253  *  Does a full reset of the hardware which includes a reset of the PHY and
2254  *  MAC.
2255  **/
2256 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2257 {
2258         u32 ctrl, icr, kab;
2259         s32 ret_val;
2260
2261         /*
2262          * Prevent the PCI-E bus from sticking if there is no TLP connection
2263          * on the last TLP read/write transaction when MAC is reset.
2264          */
2265         ret_val = e1000e_disable_pcie_master(hw);
2266         if (ret_val) {
2267                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
2268         }
2269
2270         hw_dbg(hw, "Masking off all interrupts\n");
2271         ew32(IMC, 0xffffffff);
2272
2273         /*
2274          * Disable the Transmit and Receive units.  Then delay to allow
2275          * any pending transactions to complete before we hit the MAC
2276          * with the global reset.
2277          */
2278         ew32(RCTL, 0);
2279         ew32(TCTL, E1000_TCTL_PSP);
2280         e1e_flush();
2281
2282         msleep(10);
2283
2284         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2285         if (hw->mac.type == e1000_ich8lan) {
2286                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2287                 ew32(PBA, E1000_PBA_8K);
2288                 /* Set Packet Buffer Size to 16k. */
2289                 ew32(PBS, E1000_PBS_16K);
2290         }
2291
2292         ctrl = er32(CTRL);
2293
2294         if (!e1000_check_reset_block(hw)) {
2295                 /* Clear PHY Reset Asserted bit */
2296                 if (hw->mac.type >= e1000_pchlan) {
2297                         u32 status = er32(STATUS);
2298                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2299                 }
2300
2301                 /*
2302                  * PHY HW reset requires MAC CORE reset at the same
2303                  * time to make sure the interface between MAC and the
2304                  * external PHY is reset.
2305                  */
2306                 ctrl |= E1000_CTRL_PHY_RST;
2307         }
2308         ret_val = e1000_acquire_swflag_ich8lan(hw);
2309         /* Whether or not the swflag was acquired, we need to reset the part */
2310         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
2311         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2312         msleep(20);
2313
2314         if (!ret_val)
2315                 e1000_release_swflag_ich8lan(hw);
2316
2317         if (ctrl & E1000_CTRL_PHY_RST)
2318                 ret_val = hw->phy.ops.get_cfg_done(hw);
2319
2320         if (hw->mac.type >= e1000_ich10lan) {
2321                 e1000_lan_init_done_ich8lan(hw);
2322         } else {
2323                 ret_val = e1000e_get_auto_rd_done(hw);
2324                 if (ret_val) {
2325                         /*
2326                          * When auto config read does not complete, do not
2327                          * return with an error. This can happen in situations
2328                          * where there is no eeprom and prevents getting link.
2329                          */
2330                         hw_dbg(hw, "Auto Read Done did not complete\n");
2331                 }
2332         }
2333
2334         /*
2335          * For PCH, this write will make sure that any noise
2336          * will be detected as a CRC error and be dropped rather than show up
2337          * as a bad packet to the DMA engine.
2338          */
2339         if (hw->mac.type == e1000_pchlan)
2340                 ew32(CRC_OFFSET, 0x65656565);
2341
2342         ew32(IMC, 0xffffffff);
2343         icr = er32(ICR);
2344
2345         kab = er32(KABGTXD);
2346         kab |= E1000_KABGTXD_BGSQLBIAS;
2347         ew32(KABGTXD, kab);
2348
2349         if (hw->mac.type == e1000_pchlan)
2350                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2351
2352         return ret_val;
2353 }
2354
2355 /**
2356  *  e1000_init_hw_ich8lan - Initialize the hardware
2357  *  @hw: pointer to the HW structure
2358  *
2359  *  Prepares the hardware for transmit and receive by doing the following:
2360  *   - initialize hardware bits
2361  *   - initialize LED identification
2362  *   - setup receive address registers
2363  *   - setup flow control
2364  *   - setup transmit descriptors
2365  *   - clear statistics
2366  **/
2367 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2368 {
2369         struct e1000_mac_info *mac = &hw->mac;
2370         u32 ctrl_ext, txdctl, snoop;
2371         s32 ret_val;
2372         u16 i;
2373
2374         e1000_initialize_hw_bits_ich8lan(hw);
2375
2376         /* Initialize identification LED */
2377         ret_val = mac->ops.id_led_init(hw);
2378         if (ret_val) {
2379                 hw_dbg(hw, "Error initializing identification LED\n");
2380                 return ret_val;
2381         }
2382
2383         /* Setup the receive address. */
2384         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2385
2386         /* Zero out the Multicast HASH table */
2387         hw_dbg(hw, "Zeroing the MTA\n");
2388         for (i = 0; i < mac->mta_reg_count; i++)
2389                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2390
2391         /*
2392          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2393          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2394          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2395          */
2396         if (hw->phy.type == e1000_phy_82578) {
2397                 hw->phy.ops.read_phy_reg(hw, BM_WUC, &i);
2398                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2399                 if (ret_val)
2400                         return ret_val;
2401         }
2402
2403         /* Setup link and flow control */
2404         ret_val = e1000_setup_link_ich8lan(hw);
2405
2406         /* Set the transmit descriptor write-back policy for both queues */
2407         txdctl = er32(TXDCTL(0));
2408         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2409                  E1000_TXDCTL_FULL_TX_DESC_WB;
2410         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2411                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2412         ew32(TXDCTL(0), txdctl);
2413         txdctl = er32(TXDCTL(1));
2414         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2415                  E1000_TXDCTL_FULL_TX_DESC_WB;
2416         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2417                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2418         ew32(TXDCTL(1), txdctl);
2419
2420         /*
2421          * ICH8 has opposite polarity of no_snoop bits.
2422          * By default, we should use snoop behavior.
2423          */
2424         if (mac->type == e1000_ich8lan)
2425                 snoop = PCIE_ICH8_SNOOP_ALL;
2426         else
2427                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2428         e1000e_set_pcie_no_snoop(hw, snoop);
2429
2430         ctrl_ext = er32(CTRL_EXT);
2431         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2432         ew32(CTRL_EXT, ctrl_ext);
2433
2434         /*
2435          * Clear all of the statistics registers (clear on read).  It is
2436          * important that we do this after we have tried to establish link
2437          * because the symbol error count will increment wildly if there
2438          * is no link.
2439          */
2440         e1000_clear_hw_cntrs_ich8lan(hw);
2441
2442         return 0;
2443 }
2444 /**
2445  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2446  *  @hw: pointer to the HW structure
2447  *
2448  *  Sets/Clears required hardware bits necessary for correctly setting up the
2449  *  hardware for transmit and receive.
2450  **/
2451 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2452 {
2453         u32 reg;
2454
2455         /* Extended Device Control */
2456         reg = er32(CTRL_EXT);
2457         reg |= (1 << 22);
2458         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2459         if (hw->mac.type >= e1000_pchlan)
2460                 reg |= E1000_CTRL_EXT_PHYPDEN;
2461         ew32(CTRL_EXT, reg);
2462
2463         /* Transmit Descriptor Control 0 */
2464         reg = er32(TXDCTL(0));
2465         reg |= (1 << 22);
2466         ew32(TXDCTL(0), reg);
2467
2468         /* Transmit Descriptor Control 1 */
2469         reg = er32(TXDCTL(1));
2470         reg |= (1 << 22);
2471         ew32(TXDCTL(1), reg);
2472
2473         /* Transmit Arbitration Control 0 */
2474         reg = er32(TARC(0));
2475         if (hw->mac.type == e1000_ich8lan)
2476                 reg |= (1 << 28) | (1 << 29);
2477         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2478         ew32(TARC(0), reg);
2479
2480         /* Transmit Arbitration Control 1 */
2481         reg = er32(TARC(1));
2482         if (er32(TCTL) & E1000_TCTL_MULR)
2483                 reg &= ~(1 << 28);
2484         else
2485                 reg |= (1 << 28);
2486         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2487         ew32(TARC(1), reg);
2488
2489         /* Device Status */
2490         if (hw->mac.type == e1000_ich8lan) {
2491                 reg = er32(STATUS);
2492                 reg &= ~(1 << 31);
2493                 ew32(STATUS, reg);
2494         }
2495 }
2496
2497 /**
2498  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2499  *  @hw: pointer to the HW structure
2500  *
2501  *  Determines which flow control settings to use, then configures flow
2502  *  control.  Calls the appropriate media-specific link configuration
2503  *  function.  Assuming the adapter has a valid link partner, a valid link
2504  *  should be established.  Assumes the hardware has previously been reset
2505  *  and the transmitter and receiver are not enabled.
2506  **/
2507 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2508 {
2509         s32 ret_val;
2510
2511         if (e1000_check_reset_block(hw))
2512                 return 0;
2513
2514         /*
2515          * ICH parts do not have a word in the NVM to determine
2516          * the default flow control setting, so we explicitly
2517          * set it to full.
2518          */
2519         if (hw->fc.requested_mode == e1000_fc_default) {
2520                 /* Workaround h/w hang when Tx flow control enabled */
2521                 if (hw->mac.type == e1000_pchlan)
2522                         hw->fc.requested_mode = e1000_fc_rx_pause;
2523                 else
2524                         hw->fc.requested_mode = e1000_fc_full;
2525         }
2526
2527         /*
2528          * Save off the requested flow control mode for use later.  Depending
2529          * on the link partner's capabilities, we may or may not use this mode.
2530          */
2531         hw->fc.current_mode = hw->fc.requested_mode;
2532
2533         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2534                 hw->fc.current_mode);
2535
2536         /* Continue to configure the copper link. */
2537         ret_val = e1000_setup_copper_link_ich8lan(hw);
2538         if (ret_val)
2539                 return ret_val;
2540
2541         ew32(FCTTV, hw->fc.pause_time);
2542         if ((hw->phy.type == e1000_phy_82578) ||
2543             (hw->phy.type == e1000_phy_82577)) {
2544                 ret_val = hw->phy.ops.write_phy_reg(hw,
2545                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2546                                              hw->fc.pause_time);
2547                 if (ret_val)
2548                         return ret_val;
2549         }
2550
2551         return e1000e_set_fc_watermarks(hw);
2552 }
2553
2554 /**
2555  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2556  *  @hw: pointer to the HW structure
2557  *
2558  *  Configures the kumeran interface to the PHY to wait the appropriate time
2559  *  when polling the PHY, then call the generic setup_copper_link to finish
2560  *  configuring the copper link.
2561  **/
2562 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2563 {
2564         u32 ctrl;
2565         s32 ret_val;
2566         u16 reg_data;
2567
2568         ctrl = er32(CTRL);
2569         ctrl |= E1000_CTRL_SLU;
2570         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2571         ew32(CTRL, ctrl);
2572
2573         /*
2574          * Set the mac to wait the maximum time between each iteration
2575          * and increase the max iterations when polling the phy;
2576          * this fixes erroneous timeouts at 10Mbps.
2577          */
2578         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2579         if (ret_val)
2580                 return ret_val;
2581         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2582         if (ret_val)
2583                 return ret_val;
2584         reg_data |= 0x3F;
2585         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2586         if (ret_val)
2587                 return ret_val;
2588
2589         switch (hw->phy.type) {
2590         case e1000_phy_igp_3:
2591                 ret_val = e1000e_copper_link_setup_igp(hw);
2592                 if (ret_val)
2593                         return ret_val;
2594                 break;
2595         case e1000_phy_bm:
2596         case e1000_phy_82578:
2597                 ret_val = e1000e_copper_link_setup_m88(hw);
2598                 if (ret_val)
2599                         return ret_val;
2600                 break;
2601         case e1000_phy_82577:
2602                 ret_val = e1000_copper_link_setup_82577(hw);
2603                 if (ret_val)
2604                         return ret_val;
2605                 break;
2606         case e1000_phy_ife:
2607                 ret_val = hw->phy.ops.read_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2608                                                &reg_data);
2609                 if (ret_val)
2610                         return ret_val;
2611
2612                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2613
2614                 switch (hw->phy.mdix) {
2615                 case 1:
2616                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2617                         break;
2618                 case 2:
2619                         reg_data |= IFE_PMC_FORCE_MDIX;
2620                         break;
2621                 case 0:
2622                 default:
2623                         reg_data |= IFE_PMC_AUTO_MDIX;
2624                         break;
2625                 }
2626                 ret_val = hw->phy.ops.write_phy_reg(hw, IFE_PHY_MDIX_CONTROL,
2627                                                 reg_data);
2628                 if (ret_val)
2629                         return ret_val;
2630                 break;
2631         default:
2632                 break;
2633         }
2634         return e1000e_setup_copper_link(hw);
2635 }
2636
2637 /**
2638  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2639  *  @hw: pointer to the HW structure
2640  *  @speed: pointer to store current link speed
2641  *  @duplex: pointer to store the current link duplex
2642  *
2643  *  Calls the generic get_speed_and_duplex to retrieve the current link
2644  *  information and then calls the Kumeran lock loss workaround for links at
2645  *  gigabit speeds.
2646  **/
2647 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2648                                           u16 *duplex)
2649 {
2650         s32 ret_val;
2651
2652         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2653         if (ret_val)
2654                 return ret_val;
2655
2656         if ((hw->mac.type == e1000_pchlan) && (*speed == SPEED_1000)) {
2657                 ret_val = e1000e_write_kmrn_reg(hw,
2658                                                   E1000_KMRNCTRLSTA_K1_CONFIG,
2659                                                   E1000_KMRNCTRLSTA_K1_DISABLE);
2660                 if (ret_val)
2661                         return ret_val;
2662         }
2663
2664         if ((hw->mac.type == e1000_ich8lan) &&
2665             (hw->phy.type == e1000_phy_igp_3) &&
2666             (*speed == SPEED_1000)) {
2667                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2668         }
2669
2670         return ret_val;
2671 }
2672
2673 /**
2674  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2675  *  @hw: pointer to the HW structure
2676  *
2677  *  Work-around for 82566 Kumeran PCS lock loss:
2678  *  On link status change (i.e. PCI reset, speed change) and link is up and
2679  *  speed is gigabit-
2680  *    0) if workaround is optionally disabled do nothing
2681  *    1) wait 1ms for Kumeran link to come up
2682  *    2) check Kumeran Diagnostic register PCS lock loss bit
2683  *    3) if not set the link is locked (all is good), otherwise...
2684  *    4) reset the PHY
2685  *    5) repeat up to 10 times
2686  *  Note: this is only called for IGP3 copper when speed is 1gb.
2687  **/
2688 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2689 {
2690         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2691         u32 phy_ctrl;
2692         s32 ret_val;
2693         u16 i, data;
2694         bool link;
2695
2696         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2697                 return 0;
2698
2699         /*
2700          * Make sure link is up before proceeding.  If not just return.
2701          * Attempting this while link is negotiating fouled up link
2702          * stability
2703          */
2704         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2705         if (!link)
2706                 return 0;
2707
2708         for (i = 0; i < 10; i++) {
2709                 /* read once to clear */
2710                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2711                 if (ret_val)
2712                         return ret_val;
2713                 /* and again to get new status */
2714                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2715                 if (ret_val)
2716                         return ret_val;
2717
2718                 /* check for PCS lock */
2719                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2720                         return 0;
2721
2722                 /* Issue PHY reset */
2723                 e1000_phy_hw_reset(hw);
2724                 mdelay(5);
2725         }
2726         /* Disable GigE link negotiation */
2727         phy_ctrl = er32(PHY_CTRL);
2728         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2729                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2730         ew32(PHY_CTRL, phy_ctrl);
2731
2732         /*
2733          * Call gig speed drop workaround on Gig disable before accessing
2734          * any PHY registers
2735          */
2736         e1000e_gig_downshift_workaround_ich8lan(hw);
2737
2738         /* unable to acquire PCS lock */
2739         return -E1000_ERR_PHY;
2740 }
2741
2742 /**
2743  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2744  *  @hw: pointer to the HW structure
2745  *  @state: boolean value used to set the current Kumeran workaround state
2746  *
2747  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2748  *  /disabled - FALSE).
2749  **/
2750 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2751                                                  bool state)
2752 {
2753         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2754
2755         if (hw->mac.type != e1000_ich8lan) {
2756                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2757                 return;
2758         }
2759
2760         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2761 }
2762
2763 /**
2764  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2765  *  @hw: pointer to the HW structure
2766  *
2767  *  Workaround for 82566 power-down on D3 entry:
2768  *    1) disable gigabit link
2769  *    2) write VR power-down enable
2770  *    3) read it back
2771  *  Continue if successful, else issue LCD reset and repeat
2772  **/
2773 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2774 {
2775         u32 reg;
2776         u16 data;
2777         u8  retry = 0;
2778
2779         if (hw->phy.type != e1000_phy_igp_3)
2780                 return;
2781
2782         /* Try the workaround twice (if needed) */
2783         do {
2784                 /* Disable link */
2785                 reg = er32(PHY_CTRL);
2786                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2787                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2788                 ew32(PHY_CTRL, reg);
2789
2790                 /*
2791                  * Call gig speed drop workaround on Gig disable before
2792                  * accessing any PHY registers
2793                  */
2794                 if (hw->mac.type == e1000_ich8lan)
2795                         e1000e_gig_downshift_workaround_ich8lan(hw);
2796
2797                 /* Write VR power-down enable */
2798                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2799                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2800                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2801
2802                 /* Read it back and test */
2803                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2804                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2805                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2806                         break;
2807
2808                 /* Issue PHY reset and repeat at most one more time */
2809                 reg = er32(CTRL);
2810                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2811                 retry++;
2812         } while (retry);
2813 }
2814
2815 /**
2816  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2817  *  @hw: pointer to the HW structure
2818  *
2819  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2820  *  LPLU, Gig disable, MDIC PHY reset):
2821  *    1) Set Kumeran Near-end loopback
2822  *    2) Clear Kumeran Near-end loopback
2823  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2824  **/
2825 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2826 {
2827         s32 ret_val;
2828         u16 reg_data;
2829
2830         if ((hw->mac.type != e1000_ich8lan) ||
2831             (hw->phy.type != e1000_phy_igp_3))
2832                 return;
2833
2834         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2835                                       &reg_data);
2836         if (ret_val)
2837                 return;
2838         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2839         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2840                                        reg_data);
2841         if (ret_val)
2842                 return;
2843         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2844         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2845                                        reg_data);
2846 }
2847
2848 /**
2849  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2850  *  @hw: pointer to the HW structure
2851  *
2852  *  During S0 to Sx transition, it is possible the link remains at gig
2853  *  instead of negotiating to a lower speed.  Before going to Sx, set
2854  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2855  *  to a lower speed.
2856  *
2857  *  Should only be called for applicable parts.
2858  **/
2859 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2860 {
2861         u32 phy_ctrl;
2862
2863         switch (hw->mac.type) {
2864         case e1000_ich9lan:
2865         case e1000_ich10lan:
2866         case e1000_pchlan:
2867                 phy_ctrl = er32(PHY_CTRL);
2868                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2869                             E1000_PHY_CTRL_GBE_DISABLE;
2870                 ew32(PHY_CTRL, phy_ctrl);
2871
2872                 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2873                 if (hw->mac.type == e1000_pchlan)
2874                         udelay(500);
2875         default:
2876                 break;
2877         }
2878
2879         return;
2880 }
2881
2882 /**
2883  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2884  *  @hw: pointer to the HW structure
2885  *
2886  *  Return the LED back to the default configuration.
2887  **/
2888 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2889 {
2890         if (hw->phy.type == e1000_phy_ife)
2891                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2892
2893         ew32(LEDCTL, hw->mac.ledctl_default);
2894         return 0;
2895 }
2896
2897 /**
2898  *  e1000_led_on_ich8lan - Turn LEDs on
2899  *  @hw: pointer to the HW structure
2900  *
2901  *  Turn on the LEDs.
2902  **/
2903 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2904 {
2905         if (hw->phy.type == e1000_phy_ife)
2906                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2907                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2908
2909         ew32(LEDCTL, hw->mac.ledctl_mode2);
2910         return 0;
2911 }
2912
2913 /**
2914  *  e1000_led_off_ich8lan - Turn LEDs off
2915  *  @hw: pointer to the HW structure
2916  *
2917  *  Turn off the LEDs.
2918  **/
2919 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2920 {
2921         if (hw->phy.type == e1000_phy_ife)
2922                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2923                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2924
2925         ew32(LEDCTL, hw->mac.ledctl_mode1);
2926         return 0;
2927 }
2928
2929 /**
2930  *  e1000_setup_led_pchlan - Configures SW controllable LED
2931  *  @hw: pointer to the HW structure
2932  *
2933  *  This prepares the SW controllable LED for use.
2934  **/
2935 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
2936 {
2937         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2938                                         (u16)hw->mac.ledctl_mode1);
2939 }
2940
2941 /**
2942  *  e1000_cleanup_led_pchlan - Restore the default LED operation
2943  *  @hw: pointer to the HW structure
2944  *
2945  *  Return the LED back to the default configuration.
2946  **/
2947 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
2948 {
2949         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG,
2950                                         (u16)hw->mac.ledctl_default);
2951 }
2952
2953 /**
2954  *  e1000_led_on_pchlan - Turn LEDs on
2955  *  @hw: pointer to the HW structure
2956  *
2957  *  Turn on the LEDs.
2958  **/
2959 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
2960 {
2961         u16 data = (u16)hw->mac.ledctl_mode2;
2962         u32 i, led;
2963
2964         /*
2965          * If no link, then turn LED on by setting the invert bit
2966          * for each LED that's mode is "link_up" in ledctl_mode2.
2967          */
2968         if (!(er32(STATUS) & E1000_STATUS_LU)) {
2969                 for (i = 0; i < 3; i++) {
2970                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
2971                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
2972                             E1000_LEDCTL_MODE_LINK_UP)
2973                                 continue;
2974                         if (led & E1000_PHY_LED0_IVRT)
2975                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
2976                         else
2977                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
2978                 }
2979         }
2980
2981         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
2982 }
2983
2984 /**
2985  *  e1000_led_off_pchlan - Turn LEDs off
2986  *  @hw: pointer to the HW structure
2987  *
2988  *  Turn off the LEDs.
2989  **/
2990 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
2991 {
2992         u16 data = (u16)hw->mac.ledctl_mode1;
2993         u32 i, led;
2994
2995         /*
2996          * If no link, then turn LED off by clearing the invert bit
2997          * for each LED that's mode is "link_up" in ledctl_mode1.
2998          */
2999         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3000                 for (i = 0; i < 3; i++) {
3001                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3002                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3003                             E1000_LEDCTL_MODE_LINK_UP)
3004                                 continue;
3005                         if (led & E1000_PHY_LED0_IVRT)
3006                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3007                         else
3008                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3009                 }
3010         }
3011
3012         return hw->phy.ops.write_phy_reg(hw, HV_LED_CONFIG, data);
3013 }
3014
3015 /**
3016  *  e1000_get_cfg_done_ich8lan - Read config done bit
3017  *  @hw: pointer to the HW structure
3018  *
3019  *  Read the management control register for the config done bit for
3020  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
3021  *  to read the config done bit, so an error is *ONLY* logged and returns
3022  *  0.  If we were to return with error, EEPROM-less silicon
3023  *  would not be able to be reset or change link.
3024  **/
3025 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3026 {
3027         u32 bank = 0;
3028
3029         if (hw->mac.type >= e1000_pchlan) {
3030                 u32 status = er32(STATUS);
3031
3032                 if (status & E1000_STATUS_PHYRA)
3033                         ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3034                 else
3035                         hw_dbg(hw,
3036                                "PHY Reset Asserted not set - needs delay\n");
3037         }
3038
3039         e1000e_get_cfg_done(hw);
3040
3041         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3042         if ((hw->mac.type != e1000_ich10lan) &&
3043             (hw->mac.type != e1000_pchlan)) {
3044                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3045                     (hw->phy.type == e1000_phy_igp_3)) {
3046                         e1000e_phy_init_script_igp3(hw);
3047                 }
3048         } else {
3049                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3050                         /* Maybe we should do a basic PHY config */
3051                         hw_dbg(hw, "EEPROM not present\n");
3052                         return -E1000_ERR_CONFIG;
3053                 }
3054         }
3055
3056         return 0;
3057 }
3058
3059 /**
3060  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3061  *  @hw: pointer to the HW structure
3062  *
3063  *  Clears hardware counters specific to the silicon family and calls
3064  *  clear_hw_cntrs_generic to clear all general purpose counters.
3065  **/
3066 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3067 {
3068         u32 temp;
3069         u16 phy_data;
3070
3071         e1000e_clear_hw_cntrs_base(hw);
3072
3073         temp = er32(ALGNERRC);
3074         temp = er32(RXERRC);
3075         temp = er32(TNCRS);
3076         temp = er32(CEXTERR);
3077         temp = er32(TSCTC);
3078         temp = er32(TSCTFC);
3079
3080         temp = er32(MGTPRC);
3081         temp = er32(MGTPDC);
3082         temp = er32(MGTPTC);
3083
3084         temp = er32(IAC);
3085         temp = er32(ICRXOC);
3086
3087         /* Clear PHY statistics registers */
3088         if ((hw->phy.type == e1000_phy_82578) ||
3089             (hw->phy.type == e1000_phy_82577)) {
3090                 hw->phy.ops.read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
3091                 hw->phy.ops.read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
3092                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
3093                 hw->phy.ops.read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
3094                 hw->phy.ops.read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
3095                 hw->phy.ops.read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
3096                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
3097                 hw->phy.ops.read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
3098                 hw->phy.ops.read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
3099                 hw->phy.ops.read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
3100                 hw->phy.ops.read_phy_reg(hw, HV_DC_UPPER, &phy_data);
3101                 hw->phy.ops.read_phy_reg(hw, HV_DC_LOWER, &phy_data);
3102                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
3103                 hw->phy.ops.read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
3104         }
3105 }
3106
3107 static struct e1000_mac_operations ich8_mac_ops = {
3108         .id_led_init            = e1000e_id_led_init,
3109         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
3110         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3111         /* cleanup_led dependent on mac type */
3112         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3113         .get_bus_info           = e1000_get_bus_info_ich8lan,
3114         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3115         /* led_on dependent on mac type */
3116         /* led_off dependent on mac type */
3117         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3118         .reset_hw               = e1000_reset_hw_ich8lan,
3119         .init_hw                = e1000_init_hw_ich8lan,
3120         .setup_link             = e1000_setup_link_ich8lan,
3121         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3122         /* id_led_init dependent on mac type */
3123 };
3124
3125 static struct e1000_phy_operations ich8_phy_ops = {
3126         .acquire_phy            = e1000_acquire_swflag_ich8lan,
3127         .check_reset_block      = e1000_check_reset_block_ich8lan,
3128         .commit_phy             = NULL,
3129         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
3130         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3131         .get_cable_length       = e1000e_get_cable_length_igp_2,
3132         .get_phy_info           = e1000_get_phy_info_ich8lan,
3133         .read_phy_reg           = e1000e_read_phy_reg_igp,
3134         .release_phy            = e1000_release_swflag_ich8lan,
3135         .reset_phy              = e1000_phy_hw_reset_ich8lan,
3136         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3137         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3138         .write_phy_reg          = e1000e_write_phy_reg_igp,
3139 };
3140
3141 static struct e1000_nvm_operations ich8_nvm_ops = {
3142         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
3143         .read_nvm               = e1000_read_nvm_ich8lan,
3144         .release_nvm            = e1000_release_swflag_ich8lan,
3145         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
3146         .valid_led_default      = e1000_valid_led_default_ich8lan,
3147         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
3148         .write_nvm              = e1000_write_nvm_ich8lan,
3149 };
3150
3151 struct e1000_info e1000_ich8_info = {
3152         .mac                    = e1000_ich8lan,
3153         .flags                  = FLAG_HAS_WOL
3154                                   | FLAG_IS_ICH
3155                                   | FLAG_RX_CSUM_ENABLED
3156                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3157                                   | FLAG_HAS_AMT
3158                                   | FLAG_HAS_FLASH
3159                                   | FLAG_APME_IN_WUC,
3160         .pba                    = 8,
3161         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3162         .get_variants           = e1000_get_variants_ich8lan,
3163         .mac_ops                = &ich8_mac_ops,
3164         .phy_ops                = &ich8_phy_ops,
3165         .nvm_ops                = &ich8_nvm_ops,
3166 };
3167
3168 struct e1000_info e1000_ich9_info = {
3169         .mac                    = e1000_ich9lan,
3170         .flags                  = FLAG_HAS_JUMBO_FRAMES
3171                                   | FLAG_IS_ICH
3172                                   | FLAG_HAS_WOL
3173                                   | FLAG_RX_CSUM_ENABLED
3174                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3175                                   | FLAG_HAS_AMT
3176                                   | FLAG_HAS_ERT
3177                                   | FLAG_HAS_FLASH
3178                                   | FLAG_APME_IN_WUC,
3179         .pba                    = 10,
3180         .max_hw_frame_size      = DEFAULT_JUMBO,
3181         .get_variants           = e1000_get_variants_ich8lan,
3182         .mac_ops                = &ich8_mac_ops,
3183         .phy_ops                = &ich8_phy_ops,
3184         .nvm_ops                = &ich8_nvm_ops,
3185 };
3186
3187 struct e1000_info e1000_ich10_info = {
3188         .mac                    = e1000_ich10lan,
3189         .flags                  = FLAG_HAS_JUMBO_FRAMES
3190                                   | FLAG_IS_ICH
3191                                   | FLAG_HAS_WOL
3192                                   | FLAG_RX_CSUM_ENABLED
3193                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3194                                   | FLAG_HAS_AMT
3195                                   | FLAG_HAS_ERT
3196                                   | FLAG_HAS_FLASH
3197                                   | FLAG_APME_IN_WUC,
3198         .pba                    = 10,
3199         .max_hw_frame_size      = DEFAULT_JUMBO,
3200         .get_variants           = e1000_get_variants_ich8lan,
3201         .mac_ops                = &ich8_mac_ops,
3202         .phy_ops                = &ich8_phy_ops,
3203         .nvm_ops                = &ich8_nvm_ops,
3204 };
3205
3206 struct e1000_info e1000_pch_info = {
3207         .mac                    = e1000_pchlan,
3208         .flags                  = FLAG_IS_ICH
3209                                   | FLAG_HAS_WOL
3210                                   | FLAG_RX_CSUM_ENABLED
3211                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3212                                   | FLAG_HAS_AMT
3213                                   | FLAG_HAS_FLASH
3214                                   | FLAG_HAS_JUMBO_FRAMES
3215                                   | FLAG_APME_IN_WUC,
3216         .pba                    = 26,
3217         .max_hw_frame_size      = 4096,
3218         .get_variants           = e1000_get_variants_ich8lan,
3219         .mac_ops                = &ich8_mac_ops,
3220         .phy_ops                = &ich8_phy_ops,
3221         .nvm_ops                = &ich8_nvm_ops,
3222 };