1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
49 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at
103 static const u16 e1000_gg82563_cable_length_table[] =
104 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
106 ARRAY_SIZE(e1000_gg82563_cable_length_table)
108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
116 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
118 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
123 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
124 * @hw: pointer to the HW structure
126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
128 struct e1000_phy_info *phy = &hw->phy;
131 if (hw->phy.media_type != e1000_media_type_copper) {
132 phy->type = e1000_phy_none;
135 phy->ops.power_up = e1000_power_up_phy_copper;
136 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
140 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
141 phy->reset_delay_us = 100;
142 phy->type = e1000_phy_gg82563;
144 /* This can only be done after all function pointers are setup. */
145 ret_val = e1000e_get_phy_id(hw);
148 if (phy->id != GG82563_E_PHY_ID)
149 return -E1000_ERR_PHY;
155 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
156 * @hw: pointer to the HW structure
158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
160 struct e1000_nvm_info *nvm = &hw->nvm;
161 u32 eecd = er32(EECD);
164 nvm->opcode_bits = 8;
166 switch (nvm->override) {
167 case e1000_nvm_override_spi_large:
169 nvm->address_bits = 16;
171 case e1000_nvm_override_spi_small:
173 nvm->address_bits = 8;
176 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
177 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
181 nvm->type = e1000_nvm_eeprom_spi;
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
195 nvm->word_size = 1 << size;
201 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
202 * @hw: pointer to the HW structure
204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
206 struct e1000_hw *hw = &adapter->hw;
207 struct e1000_mac_info *mac = &hw->mac;
208 struct e1000_mac_operations *func = &mac->ops;
211 switch (adapter->pdev->device) {
212 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
213 hw->phy.media_type = e1000_media_type_internal_serdes;
216 hw->phy.media_type = e1000_media_type_copper;
220 /* Set mta register count */
221 mac->mta_reg_count = 128;
222 /* Set rar entry count */
223 mac->rar_entry_count = E1000_RAR_ENTRIES;
224 /* Set if manageability features are enabled. */
225 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
229 switch (hw->phy.media_type) {
230 case e1000_media_type_copper:
231 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
232 func->check_for_link = e1000e_check_for_copper_link;
234 case e1000_media_type_fiber:
235 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
236 func->check_for_link = e1000e_check_for_fiber_link;
238 case e1000_media_type_internal_serdes:
239 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
240 func->check_for_link = e1000e_check_for_serdes_link;
243 return -E1000_ERR_CONFIG;
250 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
252 struct e1000_hw *hw = &adapter->hw;
255 rc = e1000_init_mac_params_80003es2lan(adapter);
259 rc = e1000_init_nvm_params_80003es2lan(hw);
263 rc = e1000_init_phy_params_80003es2lan(hw);
271 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
272 * @hw: pointer to the HW structure
274 * A wrapper to acquire access rights to the correct PHY.
276 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
280 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
281 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
285 * e1000_release_phy_80003es2lan - Release rights to access PHY
286 * @hw: pointer to the HW structure
288 * A wrapper to release access rights to the correct PHY.
290 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
294 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
295 e1000_release_swfw_sync_80003es2lan(hw, mask);
299 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
300 * @hw: pointer to the HW structure
302 * Acquire the semaphore to access the Kumeran interface.
305 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
309 mask = E1000_SWFW_CSR_SM;
311 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
315 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
316 * @hw: pointer to the HW structure
318 * Release the semaphore used to access the Kumeran interface
320 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
324 mask = E1000_SWFW_CSR_SM;
326 e1000_release_swfw_sync_80003es2lan(hw, mask);
330 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
331 * @hw: pointer to the HW structure
333 * Acquire the semaphore to access the EEPROM.
335 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
339 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
343 ret_val = e1000e_acquire_nvm(hw);
346 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
352 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
353 * @hw: pointer to the HW structure
355 * Release the semaphore used to access the EEPROM.
357 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
359 e1000e_release_nvm(hw);
360 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
364 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
365 * @hw: pointer to the HW structure
366 * @mask: specifies which semaphore to acquire
368 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
369 * will also specify which port we're acquiring the lock for.
371 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
375 u32 fwmask = mask << 16;
379 while (i < timeout) {
380 if (e1000e_get_hw_semaphore(hw))
381 return -E1000_ERR_SWFW_SYNC;
383 swfw_sync = er32(SW_FW_SYNC);
384 if (!(swfw_sync & (fwmask | swmask)))
388 * Firmware currently using resource (fwmask)
389 * or other software thread using resource (swmask)
391 e1000e_put_hw_semaphore(hw);
397 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
398 return -E1000_ERR_SWFW_SYNC;
402 ew32(SW_FW_SYNC, swfw_sync);
404 e1000e_put_hw_semaphore(hw);
410 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
411 * @hw: pointer to the HW structure
412 * @mask: specifies which semaphore to acquire
414 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
415 * will also specify which port we're releasing the lock for.
417 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
421 while (e1000e_get_hw_semaphore(hw) != 0);
424 swfw_sync = er32(SW_FW_SYNC);
426 ew32(SW_FW_SYNC, swfw_sync);
428 e1000e_put_hw_semaphore(hw);
432 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
433 * @hw: pointer to the HW structure
434 * @offset: offset of the register to read
435 * @data: pointer to the data returned from the operation
437 * Read the GG82563 PHY register.
439 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
440 u32 offset, u16 *data)
446 ret_val = e1000_acquire_phy_80003es2lan(hw);
450 /* Select Configuration Page */
451 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
452 page_select = GG82563_PHY_PAGE_SELECT;
455 * Use Alternative Page Select register to access
456 * registers 30 and 31
458 page_select = GG82563_PHY_PAGE_SELECT_ALT;
461 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
462 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
464 e1000_release_phy_80003es2lan(hw);
468 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
470 * The "ready" bit in the MDIC register may be incorrectly set
471 * before the device has completed the "Page Select" MDI
472 * transaction. So we wait 200us after each MDI command...
476 /* ...and verify the command was successful. */
477 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
479 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
480 ret_val = -E1000_ERR_PHY;
481 e1000_release_phy_80003es2lan(hw);
487 ret_val = e1000e_read_phy_reg_mdic(hw,
488 MAX_PHY_REG_ADDRESS & offset,
493 ret_val = e1000e_read_phy_reg_mdic(hw,
494 MAX_PHY_REG_ADDRESS & offset,
498 e1000_release_phy_80003es2lan(hw);
504 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
505 * @hw: pointer to the HW structure
506 * @offset: offset of the register to read
507 * @data: value to write to the register
509 * Write to the GG82563 PHY register.
511 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
512 u32 offset, u16 data)
518 ret_val = e1000_acquire_phy_80003es2lan(hw);
522 /* Select Configuration Page */
523 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
524 page_select = GG82563_PHY_PAGE_SELECT;
527 * Use Alternative Page Select register to access
528 * registers 30 and 31
530 page_select = GG82563_PHY_PAGE_SELECT_ALT;
533 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
534 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
536 e1000_release_phy_80003es2lan(hw);
540 if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
542 * The "ready" bit in the MDIC register may be incorrectly set
543 * before the device has completed the "Page Select" MDI
544 * transaction. So we wait 200us after each MDI command...
548 /* ...and verify the command was successful. */
549 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
551 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
552 e1000_release_phy_80003es2lan(hw);
553 return -E1000_ERR_PHY;
558 ret_val = e1000e_write_phy_reg_mdic(hw,
559 MAX_PHY_REG_ADDRESS & offset,
564 ret_val = e1000e_write_phy_reg_mdic(hw,
565 MAX_PHY_REG_ADDRESS & offset,
569 e1000_release_phy_80003es2lan(hw);
575 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
576 * @hw: pointer to the HW structure
577 * @offset: offset of the register to read
578 * @words: number of words to write
579 * @data: buffer of data to write to the NVM
581 * Write "words" of data to the ESB2 NVM.
583 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
584 u16 words, u16 *data)
586 return e1000e_write_nvm_spi(hw, offset, words, data);
590 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
591 * @hw: pointer to the HW structure
593 * Wait a specific amount of time for manageability processes to complete.
594 * This is a function pointer entry point called by the phy module.
596 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
598 s32 timeout = PHY_CFG_TIMEOUT;
599 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
601 if (hw->bus.func == 1)
602 mask = E1000_NVM_CFG_DONE_PORT_1;
605 if (er32(EEMNGCTL) & mask)
611 e_dbg("MNG configuration cycle has not completed.\n");
612 return -E1000_ERR_RESET;
619 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
620 * @hw: pointer to the HW structure
622 * Force the speed and duplex settings onto the PHY. This is a
623 * function pointer entry point called by the phy module.
625 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
632 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
633 * forced whenever speed and duplex are forced.
635 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
639 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
640 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
644 e_dbg("GG82563 PSCR: %X\n", phy_data);
646 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
650 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
652 /* Reset the phy to commit changes. */
653 phy_data |= MII_CR_RESET;
655 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
661 if (hw->phy.autoneg_wait_to_complete) {
662 e_dbg("Waiting for forced speed/duplex link "
663 "on GG82563 phy.\n");
665 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
672 * We didn't get link.
673 * Reset the DSP and cross our fingers.
675 ret_val = e1000e_phy_reset_dsp(hw);
681 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
687 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
692 * Resetting the phy means we need to verify the TX_CLK corresponds
693 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
695 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
696 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
697 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
699 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
702 * In addition, we must re-enable CRS on Tx for both half and full
705 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
706 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
712 * e1000_get_cable_length_80003es2lan - Set approximate cable length
713 * @hw: pointer to the HW structure
715 * Find the approximate cable length as measured by the GG82563 PHY.
716 * This is a function pointer entry point called by the phy module.
718 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
720 struct e1000_phy_info *phy = &hw->phy;
724 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
728 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
730 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
731 ret_val = -E1000_ERR_PHY;
735 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
736 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
738 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
745 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
746 * @hw: pointer to the HW structure
747 * @speed: pointer to speed buffer
748 * @duplex: pointer to duplex buffer
750 * Retrieve the current speed and duplex configuration.
752 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
757 if (hw->phy.media_type == e1000_media_type_copper) {
758 ret_val = e1000e_get_speed_and_duplex_copper(hw,
761 hw->phy.ops.cfg_on_link_up(hw);
763 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
772 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
773 * @hw: pointer to the HW structure
775 * Perform a global reset to the ESB2 controller.
777 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
783 * Prevent the PCI-E bus from sticking if there is no TLP connection
784 * on the last TLP read/write transaction when MAC is reset.
786 ret_val = e1000e_disable_pcie_master(hw);
788 e_dbg("PCI-E Master disable polling has failed.\n");
790 e_dbg("Masking off all interrupts\n");
791 ew32(IMC, 0xffffffff);
794 ew32(TCTL, E1000_TCTL_PSP);
801 ret_val = e1000_acquire_phy_80003es2lan(hw);
802 e_dbg("Issuing a global reset to MAC\n");
803 ew32(CTRL, ctrl | E1000_CTRL_RST);
804 e1000_release_phy_80003es2lan(hw);
806 ret_val = e1000e_get_auto_rd_done(hw);
808 /* We don't want to continue accessing MAC registers. */
811 /* Clear any pending interrupt events. */
812 ew32(IMC, 0xffffffff);
819 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
820 * @hw: pointer to the HW structure
822 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
824 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
826 struct e1000_mac_info *mac = &hw->mac;
831 e1000_initialize_hw_bits_80003es2lan(hw);
833 /* Initialize identification LED */
834 ret_val = e1000e_id_led_init(hw);
836 e_dbg("Error initializing identification LED\n");
837 /* This is not fatal and we should not stop init due to this */
839 /* Disabling VLAN filtering */
840 e_dbg("Initializing the IEEE VLAN\n");
841 mac->ops.clear_vfta(hw);
843 /* Setup the receive address. */
844 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
846 /* Zero out the Multicast HASH table */
847 e_dbg("Zeroing the MTA\n");
848 for (i = 0; i < mac->mta_reg_count; i++)
849 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
851 /* Setup link and flow control */
852 ret_val = e1000e_setup_link(hw);
854 /* Set the transmit descriptor write-back policy */
855 reg_data = er32(TXDCTL(0));
856 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
857 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
858 ew32(TXDCTL(0), reg_data);
860 /* ...for both queues. */
861 reg_data = er32(TXDCTL(1));
862 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
863 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
864 ew32(TXDCTL(1), reg_data);
866 /* Enable retransmit on late collisions */
867 reg_data = er32(TCTL);
868 reg_data |= E1000_TCTL_RTLC;
869 ew32(TCTL, reg_data);
871 /* Configure Gigabit Carry Extend Padding */
872 reg_data = er32(TCTL_EXT);
873 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
874 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
875 ew32(TCTL_EXT, reg_data);
877 /* Configure Transmit Inter-Packet Gap */
878 reg_data = er32(TIPG);
879 reg_data &= ~E1000_TIPG_IPGT_MASK;
880 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
881 ew32(TIPG, reg_data);
883 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
884 reg_data &= ~0x00100000;
885 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
887 /* default to true to enable the MDIC W/A */
888 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
890 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
891 E1000_KMRNCTRLSTA_OFFSET >>
892 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
895 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
896 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
897 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
901 * Clear all of the statistics registers (clear on read). It is
902 * important that we do this after we have tried to establish link
903 * because the symbol error count will increment wildly if there
906 e1000_clear_hw_cntrs_80003es2lan(hw);
912 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
913 * @hw: pointer to the HW structure
915 * Initializes required hardware-dependent bits needed for normal operation.
917 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
921 /* Transmit Descriptor Control 0 */
922 reg = er32(TXDCTL(0));
924 ew32(TXDCTL(0), reg);
926 /* Transmit Descriptor Control 1 */
927 reg = er32(TXDCTL(1));
929 ew32(TXDCTL(1), reg);
931 /* Transmit Arbitration Control 0 */
933 reg &= ~(0xF << 27); /* 30:27 */
934 if (hw->phy.media_type != e1000_media_type_copper)
938 /* Transmit Arbitration Control 1 */
940 if (er32(TCTL) & E1000_TCTL_MULR)
948 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
949 * @hw: pointer to the HW structure
951 * Setup some GG82563 PHY registers for obtaining link
953 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
955 struct e1000_phy_info *phy = &hw->phy;
960 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
964 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
965 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
966 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
968 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
974 * MDI/MDI-X = 0 (default)
975 * 0 - Auto for all speeds
978 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
980 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
984 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
988 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
991 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
995 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1001 * disable_polarity_correction = 0 (default)
1002 * Automatic Correction for Reversed Cable Polarity
1006 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1007 if (phy->disable_polarity_correction)
1008 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1010 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1014 /* SW Reset the PHY so all changes take effect */
1015 ret_val = e1000e_commit_phy(hw);
1017 e_dbg("Error Resetting the PHY\n");
1021 /* Bypass Rx and Tx FIFO's */
1022 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1023 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1024 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1025 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1029 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1030 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1034 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1035 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1036 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1041 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1045 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1046 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1050 ctrl_ext = er32(CTRL_EXT);
1051 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1052 ew32(CTRL_EXT, ctrl_ext);
1054 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1059 * Do not init these registers when the HW is in IAMT mode, since the
1060 * firmware will have already initialized them. We only initialize
1061 * them if the HW is not in IAMT mode.
1063 if (!e1000e_check_mng_mode(hw)) {
1064 /* Enable Electrical Idle on the PHY */
1065 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1066 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1070 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1074 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1075 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1081 * Workaround: Disable padding in Kumeran interface in the MAC
1082 * and in the PHY to avoid CRC errors.
1084 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1088 data |= GG82563_ICR_DIS_PADDING;
1089 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1097 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1098 * @hw: pointer to the HW structure
1100 * Essentially a wrapper for setting up all things "copper" related.
1101 * This is a function pointer entry point called by the mac module.
1103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1110 ctrl |= E1000_CTRL_SLU;
1111 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1115 * Set the mac to wait the maximum time between each
1116 * iteration and increase the max iterations when
1117 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1119 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1123 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1128 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1132 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1133 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1137 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1138 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1139 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1144 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1148 ret_val = e1000e_setup_copper_link(hw);
1154 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1155 * @hw: pointer to the HW structure
1156 * @duplex: current duplex setting
1158 * Configure the KMRN interface by applying last minute quirks for
1161 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1167 if (hw->phy.media_type == e1000_media_type_copper) {
1168 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1173 if (speed == SPEED_1000)
1174 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1176 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1183 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1184 * @hw: pointer to the HW structure
1185 * @duplex: current duplex setting
1187 * Configure the KMRN interface by applying last minute quirks for
1190 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1195 u16 reg_data, reg_data2;
1197 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1198 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1199 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1204 /* Configure Transmit Inter-Packet Gap */
1206 tipg &= ~E1000_TIPG_IPGT_MASK;
1207 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1211 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1215 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1219 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1221 if (duplex == HALF_DUPLEX)
1222 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1224 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1226 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1232 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1233 * @hw: pointer to the HW structure
1235 * Configure the KMRN interface by applying last minute quirks for
1236 * gigabit operation.
1238 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1241 u16 reg_data, reg_data2;
1245 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1246 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1247 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1252 /* Configure Transmit Inter-Packet Gap */
1254 tipg &= ~E1000_TIPG_IPGT_MASK;
1255 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1259 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1263 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1267 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1269 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1270 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1276 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1277 * @hw: pointer to the HW structure
1278 * @offset: register offset to be read
1279 * @data: pointer to the read data
1281 * Acquire semaphore, then read the PHY register at offset
1282 * using the kumeran interface. The information retrieved is stored in data.
1283 * Release the semaphore before exiting.
1285 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1291 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1295 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1296 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1297 ew32(KMRNCTRLSTA, kmrnctrlsta);
1301 kmrnctrlsta = er32(KMRNCTRLSTA);
1302 *data = (u16)kmrnctrlsta;
1304 e1000_release_mac_csr_80003es2lan(hw);
1310 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1311 * @hw: pointer to the HW structure
1312 * @offset: register offset to write to
1313 * @data: data to write at register offset
1315 * Acquire semaphore, then write the data to PHY register
1316 * at the offset using the kumeran interface. Release semaphore
1319 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1325 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1329 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1330 E1000_KMRNCTRLSTA_OFFSET) | data;
1331 ew32(KMRNCTRLSTA, kmrnctrlsta);
1335 e1000_release_mac_csr_80003es2lan(hw);
1341 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1342 * @hw: pointer to the HW structure
1344 * In the case of a PHY power down to save power, or to turn off link during a
1345 * driver unload, or wake on lan is not enabled, remove the link.
1347 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1349 /* If the management interface is not enabled, then power down */
1350 if (!(hw->mac.ops.check_mng_mode(hw) ||
1351 hw->phy.ops.check_reset_block(hw)))
1352 e1000_power_down_phy_copper(hw);
1358 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1359 * @hw: pointer to the HW structure
1361 * Clears the hardware counters by reading the counter registers.
1363 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1365 e1000e_clear_hw_cntrs_base(hw);
1403 static struct e1000_mac_operations es2_mac_ops = {
1404 .id_led_init = e1000e_id_led_init,
1405 .check_mng_mode = e1000e_check_mng_mode_generic,
1406 /* check_for_link dependent on media type */
1407 .cleanup_led = e1000e_cleanup_led_generic,
1408 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1409 .get_bus_info = e1000e_get_bus_info_pcie,
1410 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1411 .led_on = e1000e_led_on_generic,
1412 .led_off = e1000e_led_off_generic,
1413 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1414 .write_vfta = e1000_write_vfta_generic,
1415 .clear_vfta = e1000_clear_vfta_generic,
1416 .reset_hw = e1000_reset_hw_80003es2lan,
1417 .init_hw = e1000_init_hw_80003es2lan,
1418 .setup_link = e1000e_setup_link,
1419 /* setup_physical_interface dependent on media type */
1420 .setup_led = e1000e_setup_led_generic,
1423 static struct e1000_phy_operations es2_phy_ops = {
1424 .acquire = e1000_acquire_phy_80003es2lan,
1425 .check_polarity = e1000_check_polarity_m88,
1426 .check_reset_block = e1000e_check_reset_block_generic,
1427 .commit = e1000e_phy_sw_reset,
1428 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1429 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1430 .get_cable_length = e1000_get_cable_length_80003es2lan,
1431 .get_info = e1000e_get_phy_info_m88,
1432 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1433 .release = e1000_release_phy_80003es2lan,
1434 .reset = e1000e_phy_hw_reset_generic,
1435 .set_d0_lplu_state = NULL,
1436 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1437 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1438 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1441 static struct e1000_nvm_operations es2_nvm_ops = {
1442 .acquire = e1000_acquire_nvm_80003es2lan,
1443 .read = e1000e_read_nvm_eerd,
1444 .release = e1000_release_nvm_80003es2lan,
1445 .update = e1000e_update_nvm_checksum_generic,
1446 .valid_led_default = e1000e_valid_led_default,
1447 .validate = e1000e_validate_nvm_checksum_generic,
1448 .write = e1000_write_nvm_80003es2lan,
1451 struct e1000_info e1000_es2_info = {
1452 .mac = e1000_80003es2lan,
1453 .flags = FLAG_HAS_HW_VLAN_FILTER
1454 | FLAG_HAS_JUMBO_FRAMES
1456 | FLAG_APME_IN_CTRL3
1457 | FLAG_RX_CSUM_ENABLED
1458 | FLAG_HAS_CTRLEXT_ON_LOAD
1459 | FLAG_RX_NEEDS_RESTART /* errata */
1460 | FLAG_TARC_SET_BIT_ZERO /* errata */
1461 | FLAG_APME_CHECK_PORT_B
1462 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1463 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1465 .max_hw_frame_size = DEFAULT_JUMBO,
1466 .get_variants = e1000_get_variants_80003es2lan,
1467 .mac_ops = &es2_mac_ops,
1468 .phy_ops = &es2_phy_ops,
1469 .nvm_ops = &es2_nvm_ops,