drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  50 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  51
  52 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  53 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  54
  55 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  56 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  57 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  58 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  59 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  60 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  61
  62 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  63 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  64                                                 /* 1=Reverse Auto-Negotiation */
  65
  66 /* MAC Specific Control Register (Page 2, Register 21) */
  67 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  68 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  69 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  70 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  71 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  72
  73 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  74
  75 /* DSP Distance Register (Page 5, Register 26) */
  76 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  77                                                            1 = 50-80M
  78                                                            2 = 80-110M
  79                                                            3 = 110-140M
  80                                                            4 = >140M */
  81
  82 /* Kumeran Mode Control Register (Page 193, Register 16) */
  83 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  84
  85 /* Max number of times Kumeran read/write should be validated */
  86 #define GG82563_MAX_KMRN_RETRY  0x5
  87
  88 /* Power Management Control Register (Page 193, Register 20) */
  89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  90                                            /* 1=Enable SERDES Electrical Idle */
  91
  92 /* In-Band Control Register (Page 194, Register 18) */
  93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  94
  95 /*
  96  * A table for the GG82563 cable length where the range is defined
  97  * with a lower bound at "index" and the upper bound at
  98  * "index + 5".
  99  */
 100 static const u16 e1000_gg82563_cable_length_table[] =
 101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 102
 103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 110 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 111 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 112                                             u16 *data);
 113 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 114                                              u16 data);
 115
 116 /**
 117  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 118  *  @hw: pointer to the HW structure
 119  *
 120  *  This is a function pointer entry point called by the api module.
 121  **/
 122 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 123 {
 124         struct e1000_phy_info *phy = &hw->phy;
 125         s32 ret_val;
 126
 127         if (hw->phy.media_type != e1000_media_type_copper) {
 128                 phy->type       = e1000_phy_none;
 129                 return 0;
 130         }
 131
 132         phy->addr               = 1;
 133         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 134         phy->reset_delay_us      = 100;
 135         phy->type               = e1000_phy_gg82563;
 136
 137         /* This can only be done after all function pointers are setup. */
 138         ret_val = e1000e_get_phy_id(hw);
 139
 140         /* Verify phy id */
 141         if (phy->id != GG82563_E_PHY_ID)
 142                 return -E1000_ERR_PHY;
 143
 144         return ret_val;
 145 }
 146
 147 /**
 148  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 149  *  @hw: pointer to the HW structure
 150  *
 151  *  This is a function pointer entry point called by the api module.
 152  **/
 153 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 154 {
 155         struct e1000_nvm_info *nvm = &hw->nvm;
 156         u32 eecd = er32(EECD);
 157         u16 size;
 158
 159         nvm->opcode_bits        = 8;
 160         nvm->delay_usec  = 1;
 161         switch (nvm->override) {
 162         case e1000_nvm_override_spi_large:
 163                 nvm->page_size    = 32;
 164                 nvm->address_bits = 16;
 165                 break;
 166         case e1000_nvm_override_spi_small:
 167                 nvm->page_size    = 8;
 168                 nvm->address_bits = 8;
 169                 break;
 170         default:
 171                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 172                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 173                 break;
 174         }
 175
 176         nvm->type = e1000_nvm_eeprom_spi;
 177
 178         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 179                           E1000_EECD_SIZE_EX_SHIFT);
 180
 181         /*
 182          * Added to a constant, "size" becomes the left-shift value
 183          * for setting word_size.
 184          */
 185         size += NVM_WORD_SIZE_BASE_SHIFT;
 186
 187         /* EEPROM access above 16k is unsupported */
 188         if (size > 14)
 189                 size = 14;
 190         nvm->word_size  = 1 << size;
 191
 192         return 0;
 193 }
 194
 195 /**
 196  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 197  *  @hw: pointer to the HW structure
 198  *
 199  *  This is a function pointer entry point called by the api module.
 200  **/
 201 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 202 {
 203         struct e1000_hw *hw = &adapter->hw;
 204         struct e1000_mac_info *mac = &hw->mac;
 205         struct e1000_mac_operations *func = &mac->ops;
 206
 207         /* Set media type */
 208         switch (adapter->pdev->device) {
 209         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 210                 hw->phy.media_type = e1000_media_type_internal_serdes;
 211                 break;
 212         default:
 213                 hw->phy.media_type = e1000_media_type_copper;
 214                 break;
 215         }
 216
 217         /* Set mta register count */
 218         mac->mta_reg_count = 128;
 219         /* Set rar entry count */
 220         mac->rar_entry_count = E1000_RAR_ENTRIES;
 221         /* Set if manageability features are enabled. */
 222         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 223
 224         /* check for link */
 225         switch (hw->phy.media_type) {
 226         case e1000_media_type_copper:
 227                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 228                 func->check_for_link = e1000e_check_for_copper_link;
 229                 break;
 230         case e1000_media_type_fiber:
 231                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 232                 func->check_for_link = e1000e_check_for_fiber_link;
 233                 break;
 234         case e1000_media_type_internal_serdes:
 235                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 236                 func->check_for_link = e1000e_check_for_serdes_link;
 237                 break;
 238         default:
 239                 return -E1000_ERR_CONFIG;
 240                 break;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 247 {
 248         struct e1000_hw *hw = &adapter->hw;
 249         s32 rc;
 250
 251         rc = e1000_init_mac_params_80003es2lan(adapter);
 252         if (rc)
 253                 return rc;
 254
 255         rc = e1000_init_nvm_params_80003es2lan(hw);
 256         if (rc)
 257                 return rc;
 258
 259         rc = e1000_init_phy_params_80003es2lan(hw);
 260         if (rc)
 261                 return rc;
 262
 263         return 0;
 264 }
 265
 266 /**
 267  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  A wrapper to acquire access rights to the correct PHY.  This is a
 271  *  function pointer entry point called by the api module.
 272  **/
 273 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 274 {
 275         u16 mask;
 276
 277         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 278         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 279 }
 280
 281 /**
 282  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  A wrapper to release access rights to the correct PHY.  This is a
 286  *  function pointer entry point called by the api module.
 287  **/
 288 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 289 {
 290         u16 mask;
 291
 292         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 293         e1000_release_swfw_sync_80003es2lan(hw, mask);
 294 }
 295
 296 /**
 297  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 298  *  @hw: pointer to the HW structure
 299  *
 300  *  Acquire the semaphore to access the Kumeran interface.
 301  *
 302  **/
 303 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 304 {
 305         u16 mask;
 306
 307         mask = E1000_SWFW_CSR_SM;
 308
 309         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 310 }
 311
 312 /**
 313  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 314  *  @hw: pointer to the HW structure
 315  *
 316  *  Release the semaphore used to access the Kumeran interface
 317  **/
 318 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 319 {
 320         u16 mask;
 321
 322         mask = E1000_SWFW_CSR_SM;
 323
 324         e1000_release_swfw_sync_80003es2lan(hw, mask);
 325 }
 326
 327 /**
 328  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 329  *  @hw: pointer to the HW structure
 330  *
 331  *  Acquire the semaphore to access the EEPROM.  This is a function
 332  *  pointer entry point called by the api module.
 333  **/
 334 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 335 {
 336         s32 ret_val;
 337
 338         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 339         if (ret_val)
 340                 return ret_val;
 341
 342         ret_val = e1000e_acquire_nvm(hw);
 343
 344         if (ret_val)
 345                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 346
 347         return ret_val;
 348 }
 349
 350 /**
 351  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 352  *  @hw: pointer to the HW structure
 353  *
 354  *  Release the semaphore used to access the EEPROM.  This is a
 355  *  function pointer entry point called by the api module.
 356  **/
 357 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 358 {
 359         e1000e_release_nvm(hw);
 360         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 361 }
 362
 363 /**
 364  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 365  *  @hw: pointer to the HW structure
 366  *  @mask: specifies which semaphore to acquire
 367  *
 368  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 369  *  will also specify which port we're acquiring the lock for.
 370  **/
 371 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 372 {
 373         u32 swfw_sync;
 374         u32 swmask = mask;
 375         u32 fwmask = mask << 16;
 376         s32 i = 0;
 377         s32 timeout = 50;
 378
 379         while (i < timeout) {
 380                 if (e1000e_get_hw_semaphore(hw))
 381                         return -E1000_ERR_SWFW_SYNC;
 382
 383                 swfw_sync = er32(SW_FW_SYNC);
 384                 if (!(swfw_sync & (fwmask | swmask)))
 385                         break;
 386
 387                 /*
 388                  * Firmware currently using resource (fwmask)
 389                  * or other software thread using resource (swmask)
 390                  */
 391                 e1000e_put_hw_semaphore(hw);
 392                 mdelay(5);
 393                 i++;
 394         }
 395
 396         if (i == timeout) {
 397                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 398                 return -E1000_ERR_SWFW_SYNC;
 399         }
 400
 401         swfw_sync |= swmask;
 402         ew32(SW_FW_SYNC, swfw_sync);
 403
 404         e1000e_put_hw_semaphore(hw);
 405
 406         return 0;
 407 }
 408
 409 /**
 410  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 411  *  @hw: pointer to the HW structure
 412  *  @mask: specifies which semaphore to acquire
 413  *
 414  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 415  *  will also specify which port we're releasing the lock for.
 416  **/
 417 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 418 {
 419         u32 swfw_sync;
 420
 421         while (e1000e_get_hw_semaphore(hw) != 0);
 422         /* Empty */
 423
 424         swfw_sync = er32(SW_FW_SYNC);
 425         swfw_sync &= ~mask;
 426         ew32(SW_FW_SYNC, swfw_sync);
 427
 428         e1000e_put_hw_semaphore(hw);
 429 }
 430
 431 /**
 432  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 433  *  @hw: pointer to the HW structure
 434  *  @offset: offset of the register to read
 435  *  @data: pointer to the data returned from the operation
 436  *
 437  *  Read the GG82563 PHY register.  This is a function pointer entry
 438  *  point called by the api module.
 439  **/
 440 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 441                                                   u32 offset, u16 *data)
 442 {
 443         s32 ret_val;
 444         u32 page_select;
 445         u16 temp;
 446
 447         ret_val = e1000_acquire_phy_80003es2lan(hw);
 448         if (ret_val)
 449                 return ret_val;
 450
 451         /* Select Configuration Page */
 452         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 453                 page_select = GG82563_PHY_PAGE_SELECT;
 454         } else {
 455                 /*
 456                  * Use Alternative Page Select register to access
 457                  * registers 30 and 31
 458                  */
 459                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 460         }
 461
 462         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 463         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 464         if (ret_val) {
 465                 e1000_release_phy_80003es2lan(hw);
 466                 return ret_val;
 467         }
 468
 469         /*
 470          * The "ready" bit in the MDIC register may be incorrectly set
 471          * before the device has completed the "Page Select" MDI
 472          * transaction.  So we wait 200us after each MDI command...
 473          */
 474         udelay(200);
 475
 476         /* ...and verify the command was successful. */
 477         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 478
 479         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 480                 ret_val = -E1000_ERR_PHY;
 481                 e1000_release_phy_80003es2lan(hw);
 482                 return ret_val;
 483         }
 484
 485         udelay(200);
 486
 487         ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 488                                            data);
 489
 490         udelay(200);
 491         e1000_release_phy_80003es2lan(hw);
 492
 493         return ret_val;
 494 }
 495
 496 /**
 497  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 498  *  @hw: pointer to the HW structure
 499  *  @offset: offset of the register to read
 500  *  @data: value to write to the register
 501  *
 502  *  Write to the GG82563 PHY register.  This is a function pointer entry
 503  *  point called by the api module.
 504  **/
 505 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 506                                                    u32 offset, u16 data)
 507 {
 508         s32 ret_val;
 509         u32 page_select;
 510         u16 temp;
 511
 512         ret_val = e1000_acquire_phy_80003es2lan(hw);
 513         if (ret_val)
 514                 return ret_val;
 515
 516         /* Select Configuration Page */
 517         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 518                 page_select = GG82563_PHY_PAGE_SELECT;
 519         } else {
 520                 /*
 521                  * Use Alternative Page Select register to access
 522                  * registers 30 and 31
 523                  */
 524                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 525         }
 526
 527         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 528         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 529         if (ret_val) {
 530                 e1000_release_phy_80003es2lan(hw);
 531                 return ret_val;
 532         }
 533
 534
 535         /*
 536          * The "ready" bit in the MDIC register may be incorrectly set
 537          * before the device has completed the "Page Select" MDI
 538          * transaction.  So we wait 200us after each MDI command...
 539          */
 540         udelay(200);
 541
 542         /* ...and verify the command was successful. */
 543         ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 544
 545         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 546                 e1000_release_phy_80003es2lan(hw);
 547                 return -E1000_ERR_PHY;
 548         }
 549
 550         udelay(200);
 551
 552         ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
 553                                             data);
 554
 555         udelay(200);
 556         e1000_release_phy_80003es2lan(hw);
 557
 558         return ret_val;
 559 }
 560
 561 /**
 562  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 563  *  @hw: pointer to the HW structure
 564  *  @offset: offset of the register to read
 565  *  @words: number of words to write
 566  *  @data: buffer of data to write to the NVM
 567  *
 568  *  Write "words" of data to the ESB2 NVM.  This is a function
 569  *  pointer entry point called by the api module.
 570  **/
 571 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 572                                        u16 words, u16 *data)
 573 {
 574         return e1000e_write_nvm_spi(hw, offset, words, data);
 575 }
 576
 577 /**
 578  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 579  *  @hw: pointer to the HW structure
 580  *
 581  *  Wait a specific amount of time for manageability processes to complete.
 582  *  This is a function pointer entry point called by the phy module.
 583  **/
 584 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 585 {
 586         s32 timeout = PHY_CFG_TIMEOUT;
 587         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 588
 589         if (hw->bus.func == 1)
 590                 mask = E1000_NVM_CFG_DONE_PORT_1;
 591
 592         while (timeout) {
 593                 if (er32(EEMNGCTL) & mask)
 594                         break;
 595                 msleep(1);
 596                 timeout--;
 597         }
 598         if (!timeout) {
 599                 e_dbg("MNG configuration cycle has not completed.\n");
 600                 return -E1000_ERR_RESET;
 601         }
 602
 603         return 0;
 604 }
 605
 606 /**
 607  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 608  *  @hw: pointer to the HW structure
 609  *
 610  *  Force the speed and duplex settings onto the PHY.  This is a
 611  *  function pointer entry point called by the phy module.
 612  **/
 613 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 614 {
 615         s32 ret_val;
 616         u16 phy_data;
 617         bool link;
 618
 619         /*
 620          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 621          * forced whenever speed and duplex are forced.
 622          */
 623         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 624         if (ret_val)
 625                 return ret_val;
 626
 627         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 628         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 629         if (ret_val)
 630                 return ret_val;
 631
 632         e_dbg("GG82563 PSCR: %X\n", phy_data);
 633
 634         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 635         if (ret_val)
 636                 return ret_val;
 637
 638         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 639
 640         /* Reset the phy to commit changes. */
 641         phy_data |= MII_CR_RESET;
 642
 643         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 644         if (ret_val)
 645                 return ret_val;
 646
 647         udelay(1);
 648
 649         if (hw->phy.autoneg_wait_to_complete) {
 650                 e_dbg("Waiting for forced speed/duplex link "
 651                          "on GG82563 phy.\n");
 652
 653                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 654                                                      100000, &link);
 655                 if (ret_val)
 656                         return ret_val;
 657
 658                 if (!link) {
 659                         /*
 660                          * We didn't get link.
 661                          * Reset the DSP and cross our fingers.
 662                          */
 663                         ret_val = e1000e_phy_reset_dsp(hw);
 664                         if (ret_val)
 665                                 return ret_val;
 666                 }
 667
 668                 /* Try once more */
 669                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 670                                                      100000, &link);
 671                 if (ret_val)
 672                         return ret_val;
 673         }
 674
 675         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 676         if (ret_val)
 677                 return ret_val;
 678
 679         /*
 680          * Resetting the phy means we need to verify the TX_CLK corresponds
 681          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 682          */
 683         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 684         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 685                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 686         else
 687                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 688
 689         /*
 690          * In addition, we must re-enable CRS on Tx for both half and full
 691          * duplex.
 692          */
 693         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 694         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 695
 696         return ret_val;
 697 }
 698
 699 /**
 700  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 701  *  @hw: pointer to the HW structure
 702  *
 703  *  Find the approximate cable length as measured by the GG82563 PHY.
 704  *  This is a function pointer entry point called by the phy module.
 705  **/
 706 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 707 {
 708         struct e1000_phy_info *phy = &hw->phy;
 709         s32 ret_val;
 710         u16 phy_data;
 711         u16 index;
 712
 713         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 718         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 719         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 720
 721         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 722
 723         return 0;
 724 }
 725
 726 /**
 727  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 728  *  @hw: pointer to the HW structure
 729  *  @speed: pointer to speed buffer
 730  *  @duplex: pointer to duplex buffer
 731  *
 732  *  Retrieve the current speed and duplex configuration.
 733  *  This is a function pointer entry point called by the api module.
 734  **/
 735 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 736                                               u16 *duplex)
 737 {
 738         s32 ret_val;
 739
 740         if (hw->phy.media_type == e1000_media_type_copper) {
 741                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 742                                                                     speed,
 743                                                                     duplex);
 744                 hw->phy.ops.cfg_on_link_up(hw);
 745         } else {
 746                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 747                                                                   speed,
 748                                                                   duplex);
 749         }
 750
 751         return ret_val;
 752 }
 753
 754 /**
 755  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 756  *  @hw: pointer to the HW structure
 757  *
 758  *  Perform a global reset to the ESB2 controller.
 759  *  This is a function pointer entry point called by the api module.
 760  **/
 761 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 762 {
 763         u32 ctrl;
 764         u32 icr;
 765         s32 ret_val;
 766
 767         /*
 768          * Prevent the PCI-E bus from sticking if there is no TLP connection
 769          * on the last TLP read/write transaction when MAC is reset.
 770          */
 771         ret_val = e1000e_disable_pcie_master(hw);
 772         if (ret_val)
 773                 e_dbg("PCI-E Master disable polling has failed.\n");
 774
 775         e_dbg("Masking off all interrupts\n");
 776         ew32(IMC, 0xffffffff);
 777
 778         ew32(RCTL, 0);
 779         ew32(TCTL, E1000_TCTL_PSP);
 780         e1e_flush();
 781
 782         msleep(10);
 783
 784         ctrl = er32(CTRL);
 785
 786         ret_val = e1000_acquire_phy_80003es2lan(hw);
 787         e_dbg("Issuing a global reset to MAC\n");
 788         ew32(CTRL, ctrl | E1000_CTRL_RST);
 789         e1000_release_phy_80003es2lan(hw);
 790
 791         ret_val = e1000e_get_auto_rd_done(hw);
 792         if (ret_val)
 793                 /* We don't want to continue accessing MAC registers. */
 794                 return ret_val;
 795
 796         /* Clear any pending interrupt events. */
 797         ew32(IMC, 0xffffffff);
 798         icr = er32(ICR);
 799
 800         return 0;
 801 }
 802
 803 /**
 804  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 805  *  @hw: pointer to the HW structure
 806  *
 807  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 808  *  This is a function pointer entry point called by the api module.
 809  **/
 810 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 811 {
 812         struct e1000_mac_info *mac = &hw->mac;
 813         u32 reg_data;
 814         s32 ret_val;
 815         u16 i;
 816
 817         e1000_initialize_hw_bits_80003es2lan(hw);
 818
 819         /* Initialize identification LED */
 820         ret_val = e1000e_id_led_init(hw);
 821         if (ret_val) {
 822                 e_dbg("Error initializing identification LED\n");
 823                 return ret_val;
 824         }
 825
 826         /* Disabling VLAN filtering */
 827         e_dbg("Initializing the IEEE VLAN\n");
 828         e1000e_clear_vfta(hw);
 829
 830         /* Setup the receive address. */
 831         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 832
 833         /* Zero out the Multicast HASH table */
 834         e_dbg("Zeroing the MTA\n");
 835         for (i = 0; i < mac->mta_reg_count; i++)
 836                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 837
 838         /* Setup link and flow control */
 839         ret_val = e1000e_setup_link(hw);
 840
 841         /* Set the transmit descriptor write-back policy */
 842         reg_data = er32(TXDCTL(0));
 843         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 844                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 845         ew32(TXDCTL(0), reg_data);
 846
 847         /* ...for both queues. */
 848         reg_data = er32(TXDCTL(1));
 849         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 850                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 851         ew32(TXDCTL(1), reg_data);
 852
 853         /* Enable retransmit on late collisions */
 854         reg_data = er32(TCTL);
 855         reg_data |= E1000_TCTL_RTLC;
 856         ew32(TCTL, reg_data);
 857
 858         /* Configure Gigabit Carry Extend Padding */
 859         reg_data = er32(TCTL_EXT);
 860         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 861         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 862         ew32(TCTL_EXT, reg_data);
 863
 864         /* Configure Transmit Inter-Packet Gap */
 865         reg_data = er32(TIPG);
 866         reg_data &= ~E1000_TIPG_IPGT_MASK;
 867         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 868         ew32(TIPG, reg_data);
 869
 870         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 871         reg_data &= ~0x00100000;
 872         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 873
 874         /*
 875          * Clear all of the statistics registers (clear on read).  It is
 876          * important that we do this after we have tried to establish link
 877          * because the symbol error count will increment wildly if there
 878          * is no link.
 879          */
 880         e1000_clear_hw_cntrs_80003es2lan(hw);
 881
 882         return ret_val;
 883 }
 884
 885 /**
 886  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 887  *  @hw: pointer to the HW structure
 888  *
 889  *  Initializes required hardware-dependent bits needed for normal operation.
 890  **/
 891 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 892 {
 893         u32 reg;
 894
 895         /* Transmit Descriptor Control 0 */
 896         reg = er32(TXDCTL(0));
 897         reg |= (1 << 22);
 898         ew32(TXDCTL(0), reg);
 899
 900         /* Transmit Descriptor Control 1 */
 901         reg = er32(TXDCTL(1));
 902         reg |= (1 << 22);
 903         ew32(TXDCTL(1), reg);
 904
 905         /* Transmit Arbitration Control 0 */
 906         reg = er32(TARC(0));
 907         reg &= ~(0xF << 27); /* 30:27 */
 908         if (hw->phy.media_type != e1000_media_type_copper)
 909                 reg &= ~(1 << 20);
 910         ew32(TARC(0), reg);
 911
 912         /* Transmit Arbitration Control 1 */
 913         reg = er32(TARC(1));
 914         if (er32(TCTL) & E1000_TCTL_MULR)
 915                 reg &= ~(1 << 28);
 916         else
 917                 reg |= (1 << 28);
 918         ew32(TARC(1), reg);
 919 }
 920
 921 /**
 922  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 923  *  @hw: pointer to the HW structure
 924  *
 925  *  Setup some GG82563 PHY registers for obtaining link
 926  **/
 927 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 928 {
 929         struct e1000_phy_info *phy = &hw->phy;
 930         s32 ret_val;
 931         u32 ctrl_ext;
 932         u16 data;
 933
 934         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 935         if (ret_val)
 936                 return ret_val;
 937
 938         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 939         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 940         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 941
 942         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 943         if (ret_val)
 944                 return ret_val;
 945
 946         /*
 947          * Options:
 948          *   MDI/MDI-X = 0 (default)
 949          *   0 - Auto for all speeds
 950          *   1 - MDI mode
 951          *   2 - MDI-X mode
 952          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 953          */
 954         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 955         if (ret_val)
 956                 return ret_val;
 957
 958         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 959
 960         switch (phy->mdix) {
 961         case 1:
 962                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 963                 break;
 964         case 2:
 965                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 966                 break;
 967         case 0:
 968         default:
 969                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 970                 break;
 971         }
 972
 973         /*
 974          * Options:
 975          *   disable_polarity_correction = 0 (default)
 976          *       Automatic Correction for Reversed Cable Polarity
 977          *   0 - Disabled
 978          *   1 - Enabled
 979          */
 980         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 981         if (phy->disable_polarity_correction)
 982                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 983
 984         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 985         if (ret_val)
 986                 return ret_val;
 987
 988         /* SW Reset the PHY so all changes take effect */
 989         ret_val = e1000e_commit_phy(hw);
 990         if (ret_val) {
 991                 e_dbg("Error Resetting the PHY\n");
 992                 return ret_val;
 993         }
 994
 995         /* Bypass Rx and Tx FIFO's */
 996         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 997                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
 998                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 999                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1000         if (ret_val)
1001                 return ret_val;
1002
1003         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1004                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1005                                        &data);
1006         if (ret_val)
1007                 return ret_val;
1008         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1009         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1010                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1011                                         data);
1012         if (ret_val)
1013                 return ret_val;
1014
1015         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1016         if (ret_val)
1017                 return ret_val;
1018
1019         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1020         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1021         if (ret_val)
1022                 return ret_val;
1023
1024         ctrl_ext = er32(CTRL_EXT);
1025         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1026         ew32(CTRL_EXT, ctrl_ext);
1027
1028         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1029         if (ret_val)
1030                 return ret_val;
1031
1032         /*
1033          * Do not init these registers when the HW is in IAMT mode, since the
1034          * firmware will have already initialized them.  We only initialize
1035          * them if the HW is not in IAMT mode.
1036          */
1037         if (!e1000e_check_mng_mode(hw)) {
1038                 /* Enable Electrical Idle on the PHY */
1039                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1040                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1041                 if (ret_val)
1042                         return ret_val;
1043
1044                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1045                 if (ret_val)
1046                         return ret_val;
1047
1048                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1049                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1050                 if (ret_val)
1051                         return ret_val;
1052         }
1053
1054         /*
1055          * Workaround: Disable padding in Kumeran interface in the MAC
1056          * and in the PHY to avoid CRC errors.
1057          */
1058         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1059         if (ret_val)
1060                 return ret_val;
1061
1062         data |= GG82563_ICR_DIS_PADDING;
1063         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1064         if (ret_val)
1065                 return ret_val;
1066
1067         return 0;
1068 }
1069
1070 /**
1071  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1072  *  @hw: pointer to the HW structure
1073  *
1074  *  Essentially a wrapper for setting up all things "copper" related.
1075  *  This is a function pointer entry point called by the mac module.
1076  **/
1077 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1078 {
1079         u32 ctrl;
1080         s32 ret_val;
1081         u16 reg_data;
1082
1083         ctrl = er32(CTRL);
1084         ctrl |= E1000_CTRL_SLU;
1085         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1086         ew32(CTRL, ctrl);
1087
1088         /*
1089          * Set the mac to wait the maximum time between each
1090          * iteration and increase the max iterations when
1091          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1092          */
1093         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1094                                                    0xFFFF);
1095         if (ret_val)
1096                 return ret_val;
1097         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1098                                                   &reg_data);
1099         if (ret_val)
1100                 return ret_val;
1101         reg_data |= 0x3F;
1102         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1103                                                    reg_data);
1104         if (ret_val)
1105                 return ret_val;
1106         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1107                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1108                                       &reg_data);
1109         if (ret_val)
1110                 return ret_val;
1111         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1112         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1113                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1114                                         reg_data);
1115         if (ret_val)
1116                 return ret_val;
1117
1118         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1119         if (ret_val)
1120                 return ret_val;
1121
1122         ret_val = e1000e_setup_copper_link(hw);
1123
1124         return 0;
1125 }
1126
1127 /**
1128  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1129  *  @hw: pointer to the HW structure
1130  *  @duplex: current duplex setting
1131  *
1132  *  Configure the KMRN interface by applying last minute quirks for
1133  *  10/100 operation.
1134  **/
1135 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1136 {
1137         s32 ret_val = 0;
1138         u16 speed;
1139         u16 duplex;
1140
1141         if (hw->phy.media_type == e1000_media_type_copper) {
1142                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1143                                                              &duplex);
1144                 if (ret_val)
1145                         return ret_val;
1146
1147                 if (speed == SPEED_1000)
1148                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1149                 else
1150                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1151         }
1152
1153         return ret_val;
1154 }
1155
1156 /**
1157  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1158  *  @hw: pointer to the HW structure
1159  *  @duplex: current duplex setting
1160  *
1161  *  Configure the KMRN interface by applying last minute quirks for
1162  *  10/100 operation.
1163  **/
1164 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1165 {
1166         s32 ret_val;
1167         u32 tipg;
1168         u32 i = 0;
1169         u16 reg_data, reg_data2;
1170
1171         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1172         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1173                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1174                                        reg_data);
1175         if (ret_val)
1176                 return ret_val;
1177
1178         /* Configure Transmit Inter-Packet Gap */
1179         tipg = er32(TIPG);
1180         tipg &= ~E1000_TIPG_IPGT_MASK;
1181         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1182         ew32(TIPG, tipg);
1183
1184         do {
1185                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1186                 if (ret_val)
1187                         return ret_val;
1188
1189                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1190                 if (ret_val)
1191                         return ret_val;
1192                 i++;
1193         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1194
1195         if (duplex == HALF_DUPLEX)
1196                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1197         else
1198                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1199
1200         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1201
1202         return 0;
1203 }
1204
1205 /**
1206  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1207  *  @hw: pointer to the HW structure
1208  *
1209  *  Configure the KMRN interface by applying last minute quirks for
1210  *  gigabit operation.
1211  **/
1212 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1213 {
1214         s32 ret_val;
1215         u16 reg_data, reg_data2;
1216         u32 tipg;
1217         u32 i = 0;
1218
1219         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1220         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1221                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1222                                        reg_data);
1223         if (ret_val)
1224                 return ret_val;
1225
1226         /* Configure Transmit Inter-Packet Gap */
1227         tipg = er32(TIPG);
1228         tipg &= ~E1000_TIPG_IPGT_MASK;
1229         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1230         ew32(TIPG, tipg);
1231
1232         do {
1233                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1234                 if (ret_val)
1235                         return ret_val;
1236
1237                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1238                 if (ret_val)
1239                         return ret_val;
1240                 i++;
1241         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1242
1243         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1244         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1245
1246         return ret_val;
1247 }
1248
1249 /**
1250  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1251  *  @hw: pointer to the HW structure
1252  *  @offset: register offset to be read
1253  *  @data: pointer to the read data
1254  *
1255  *  Acquire semaphore, then read the PHY register at offset
1256  *  using the kumeran interface.  The information retrieved is stored in data.
1257  *  Release the semaphore before exiting.
1258  **/
1259 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1260                                            u16 *data)
1261 {
1262         u32 kmrnctrlsta;
1263         s32 ret_val = 0;
1264
1265         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1266         if (ret_val)
1267                 return ret_val;
1268
1269         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1270                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1271         ew32(KMRNCTRLSTA, kmrnctrlsta);
1272
1273         udelay(2);
1274
1275         kmrnctrlsta = er32(KMRNCTRLSTA);
1276         *data = (u16)kmrnctrlsta;
1277
1278         e1000_release_mac_csr_80003es2lan(hw);
1279
1280         return ret_val;
1281 }
1282
1283 /**
1284  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1285  *  @hw: pointer to the HW structure
1286  *  @offset: register offset to write to
1287  *  @data: data to write at register offset
1288  *
1289  *  Acquire semaphore, then write the data to PHY register
1290  *  at the offset using the kumeran interface.  Release semaphore
1291  *  before exiting.
1292  **/
1293 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1294                                             u16 data)
1295 {
1296         u32 kmrnctrlsta;
1297         s32 ret_val = 0;
1298
1299         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1300         if (ret_val)
1301                 return ret_val;
1302
1303         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1304                        E1000_KMRNCTRLSTA_OFFSET) | data;
1305         ew32(KMRNCTRLSTA, kmrnctrlsta);
1306
1307         udelay(2);
1308
1309         e1000_release_mac_csr_80003es2lan(hw);
1310
1311         return ret_val;
1312 }
1313
1314 /**
1315  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1316  *  @hw: pointer to the HW structure
1317  *
1318  *  Clears the hardware counters by reading the counter registers.
1319  **/
1320 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1321 {
1322         u32 temp;
1323
1324         e1000e_clear_hw_cntrs_base(hw);
1325
1326         temp = er32(PRC64);
1327         temp = er32(PRC127);
1328         temp = er32(PRC255);
1329         temp = er32(PRC511);
1330         temp = er32(PRC1023);
1331         temp = er32(PRC1522);
1332         temp = er32(PTC64);
1333         temp = er32(PTC127);
1334         temp = er32(PTC255);
1335         temp = er32(PTC511);
1336         temp = er32(PTC1023);
1337         temp = er32(PTC1522);
1338
1339         temp = er32(ALGNERRC);
1340         temp = er32(RXERRC);
1341         temp = er32(TNCRS);
1342         temp = er32(CEXTERR);
1343         temp = er32(TSCTC);
1344         temp = er32(TSCTFC);
1345
1346         temp = er32(MGTPRC);
1347         temp = er32(MGTPDC);
1348         temp = er32(MGTPTC);
1349
1350         temp = er32(IAC);
1351         temp = er32(ICRXOC);
1352
1353         temp = er32(ICRXPTC);
1354         temp = er32(ICRXATC);
1355         temp = er32(ICTXPTC);
1356         temp = er32(ICTXATC);
1357         temp = er32(ICTXQEC);
1358         temp = er32(ICTXQMTC);
1359         temp = er32(ICRXDMTC);
1360 }
1361
1362 static struct e1000_mac_operations es2_mac_ops = {
1363         .id_led_init            = e1000e_id_led_init,
1364         .check_mng_mode         = e1000e_check_mng_mode_generic,
1365         /* check_for_link dependent on media type */
1366         .cleanup_led            = e1000e_cleanup_led_generic,
1367         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1368         .get_bus_info           = e1000e_get_bus_info_pcie,
1369         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1370         .led_on                 = e1000e_led_on_generic,
1371         .led_off                = e1000e_led_off_generic,
1372         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1373         .reset_hw               = e1000_reset_hw_80003es2lan,
1374         .init_hw                = e1000_init_hw_80003es2lan,
1375         .setup_link             = e1000e_setup_link,
1376         /* setup_physical_interface dependent on media type */
1377         .setup_led              = e1000e_setup_led_generic,
1378 };
1379
1380 static struct e1000_phy_operations es2_phy_ops = {
1381         .acquire                = e1000_acquire_phy_80003es2lan,
1382         .check_reset_block      = e1000e_check_reset_block_generic,
1383         .commit                 = e1000e_phy_sw_reset,
1384         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1385         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1386         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1387         .get_info               = e1000e_get_phy_info_m88,
1388         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1389         .release                = e1000_release_phy_80003es2lan,
1390         .reset                  = e1000e_phy_hw_reset_generic,
1391         .set_d0_lplu_state      = NULL,
1392         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1393         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1394         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1395 };
1396
1397 static struct e1000_nvm_operations es2_nvm_ops = {
1398         .acquire                = e1000_acquire_nvm_80003es2lan,
1399         .read                   = e1000e_read_nvm_eerd,
1400         .release                = e1000_release_nvm_80003es2lan,
1401         .update                 = e1000e_update_nvm_checksum_generic,
1402         .valid_led_default      = e1000e_valid_led_default,
1403         .validate               = e1000e_validate_nvm_checksum_generic,
1404         .write                  = e1000_write_nvm_80003es2lan,
1405 };
1406
1407 struct e1000_info e1000_es2_info = {
1408         .mac                    = e1000_80003es2lan,
1409         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1410                                   | FLAG_HAS_JUMBO_FRAMES
1411                                   | FLAG_HAS_WOL
1412                                   | FLAG_APME_IN_CTRL3
1413                                   | FLAG_RX_CSUM_ENABLED
1414                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1415                                   | FLAG_RX_NEEDS_RESTART /* errata */
1416                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1417                                   | FLAG_APME_CHECK_PORT_B
1418                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1419                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1420         .pba                    = 38,
1421         .max_hw_frame_size      = DEFAULT_JUMBO,
1422         .get_variants           = e1000_get_variants_80003es2lan,
1423         .mac_ops                = &es2_mac_ops,
1424         .phy_ops                = &es2_phy_ops,
1425         .nvm_ops                = &es2_nvm_ops,
1426 };
1427