1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
63 u16 words, u16 *data);
64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
75 * e1000_init_phy_params_82571 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
80 struct e1000_phy_info *phy = &hw->phy;
83 if (hw->phy.media_type != e1000_media_type_copper) {
84 phy->type = e1000_phy_none;
89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
90 phy->reset_delay_us = 100;
92 phy->ops.power_up = e1000_power_up_phy_copper;
93 phy->ops.power_down = e1000_power_down_phy_copper_82571;
95 switch (hw->mac.type) {
98 phy->type = e1000_phy_igp_2;
101 phy->type = e1000_phy_m88;
105 phy->type = e1000_phy_bm;
108 return -E1000_ERR_PHY;
112 /* This can only be done after all function pointers are setup. */
113 ret_val = e1000_get_phy_id_82571(hw);
116 switch (hw->mac.type) {
119 if (phy->id != IGP01E1000_I_PHY_ID)
120 return -E1000_ERR_PHY;
123 if (phy->id != M88E1111_I_PHY_ID)
124 return -E1000_ERR_PHY;
128 if (phy->id != BME1000_E_PHY_ID_R2)
129 return -E1000_ERR_PHY;
132 return -E1000_ERR_PHY;
140 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
141 * @hw: pointer to the HW structure
143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = er32(EECD);
149 nvm->opcode_bits = 8;
151 switch (nvm->override) {
152 case e1000_nvm_override_spi_large:
154 nvm->address_bits = 16;
156 case e1000_nvm_override_spi_small:
158 nvm->address_bits = 8;
161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
166 switch (hw->mac.type) {
170 if (((eecd >> 15) & 0x3) == 0x3) {
171 nvm->type = e1000_nvm_flash_hw;
172 nvm->word_size = 2048;
174 * Autonomous Flash update bit must be cleared due
175 * to Flash update issue.
177 eecd &= ~E1000_EECD_AUPDEN;
183 nvm->type = e1000_nvm_eeprom_spi;
184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
185 E1000_EECD_SIZE_EX_SHIFT);
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
190 size += NVM_WORD_SIZE_BASE_SHIFT;
192 /* EEPROM access above 16k is unsupported */
195 nvm->word_size = 1 << size;
203 * e1000_init_mac_params_82571 - Init MAC func ptrs.
204 * @hw: pointer to the HW structure
206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_mac_info *mac = &hw->mac;
210 struct e1000_mac_operations *func = &mac->ops;
213 bool force_clear_smbi = false;
216 switch (adapter->pdev->device) {
217 case E1000_DEV_ID_82571EB_FIBER:
218 case E1000_DEV_ID_82572EI_FIBER:
219 case E1000_DEV_ID_82571EB_QUAD_FIBER:
220 hw->phy.media_type = e1000_media_type_fiber;
222 case E1000_DEV_ID_82571EB_SERDES:
223 case E1000_DEV_ID_82572EI_SERDES:
224 case E1000_DEV_ID_82571EB_SERDES_DUAL:
225 case E1000_DEV_ID_82571EB_SERDES_QUAD:
226 hw->phy.media_type = e1000_media_type_internal_serdes;
229 hw->phy.media_type = e1000_media_type_copper;
233 /* Set mta register count */
234 mac->mta_reg_count = 128;
235 /* Set rar entry count */
236 mac->rar_entry_count = E1000_RAR_ENTRIES;
237 /* Set if manageability features are enabled. */
238 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
240 /* Adaptive IFS supported */
241 mac->adaptive_ifs = true;
244 switch (hw->phy.media_type) {
245 case e1000_media_type_copper:
246 func->setup_physical_interface = e1000_setup_copper_link_82571;
247 func->check_for_link = e1000e_check_for_copper_link;
248 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
250 case e1000_media_type_fiber:
251 func->setup_physical_interface =
252 e1000_setup_fiber_serdes_link_82571;
253 func->check_for_link = e1000e_check_for_fiber_link;
254 func->get_link_up_info =
255 e1000e_get_speed_and_duplex_fiber_serdes;
257 case e1000_media_type_internal_serdes:
258 func->setup_physical_interface =
259 e1000_setup_fiber_serdes_link_82571;
260 func->check_for_link = e1000_check_for_serdes_link_82571;
261 func->get_link_up_info =
262 e1000e_get_speed_and_duplex_fiber_serdes;
265 return -E1000_ERR_CONFIG;
269 switch (hw->mac.type) {
271 func->set_lan_id = e1000_set_lan_id_single_port;
272 func->check_mng_mode = e1000e_check_mng_mode_generic;
273 func->led_on = e1000e_led_on_generic;
277 func->set_lan_id = e1000_set_lan_id_single_port;
278 func->check_mng_mode = e1000_check_mng_mode_82574;
279 func->led_on = e1000_led_on_82574;
282 func->check_mng_mode = e1000e_check_mng_mode_generic;
283 func->led_on = e1000e_led_on_generic;
288 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
289 * first NVM or PHY acess. This should be done for single-port
290 * devices, and for one port only on dual-port devices so that
291 * for those devices we can still use the SMBI lock to synchronize
292 * inter-port accesses to the PHY & NVM.
294 switch (hw->mac.type) {
299 if (!(swsm2 & E1000_SWSM2_LOCK)) {
300 /* Only do this for the first interface on this card */
302 swsm2 | E1000_SWSM2_LOCK);
303 force_clear_smbi = true;
305 force_clear_smbi = false;
308 force_clear_smbi = true;
312 if (force_clear_smbi) {
313 /* Make sure SWSM.SMBI is clear */
315 if (swsm & E1000_SWSM_SMBI) {
316 /* This bit should not be set on a first interface, and
317 * indicates that the bootagent or EFI code has
318 * improperly left this bit enabled
320 e_dbg("Please update your 82571 Bootagent\n");
322 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
326 * Initialze device specific counter of SMBI acquisition
329 hw->dev_spec.e82571.smb_counter = 0;
334 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
336 struct e1000_hw *hw = &adapter->hw;
337 static int global_quad_port_a; /* global port a indication */
338 struct pci_dev *pdev = adapter->pdev;
340 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
343 rc = e1000_init_mac_params_82571(adapter);
347 rc = e1000_init_nvm_params_82571(hw);
351 rc = e1000_init_phy_params_82571(hw);
355 /* tag quad port adapters first, it's used below */
356 switch (pdev->device) {
357 case E1000_DEV_ID_82571EB_QUAD_COPPER:
358 case E1000_DEV_ID_82571EB_QUAD_FIBER:
359 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
360 case E1000_DEV_ID_82571PT_QUAD_COPPER:
361 adapter->flags |= FLAG_IS_QUAD_PORT;
362 /* mark the first port */
363 if (global_quad_port_a == 0)
364 adapter->flags |= FLAG_IS_QUAD_PORT_A;
365 /* Reset for multiple quad port adapters */
366 global_quad_port_a++;
367 if (global_quad_port_a == 4)
368 global_quad_port_a = 0;
374 switch (adapter->hw.mac.type) {
376 /* these dual ports don't have WoL on port B at all */
377 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
378 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
379 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
381 adapter->flags &= ~FLAG_HAS_WOL;
382 /* quad ports only support WoL on port A */
383 if (adapter->flags & FLAG_IS_QUAD_PORT &&
384 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
385 adapter->flags &= ~FLAG_HAS_WOL;
386 /* Does not support WoL on any port */
387 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
388 adapter->flags &= ~FLAG_HAS_WOL;
392 if (pdev->device == E1000_DEV_ID_82573L) {
393 if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
396 if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
397 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
398 adapter->max_hw_frame_size = DEFAULT_JUMBO;
410 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
411 * @hw: pointer to the HW structure
413 * Reads the PHY registers and stores the PHY ID and possibly the PHY
414 * revision in the hardware structure.
416 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
418 struct e1000_phy_info *phy = &hw->phy;
422 switch (hw->mac.type) {
426 * The 82571 firmware may still be configuring the PHY.
427 * In this case, we cannot access the PHY until the
428 * configuration is done. So we explicitly set the
431 phy->id = IGP01E1000_I_PHY_ID;
434 return e1000e_get_phy_id(hw);
438 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
442 phy->id = (u32)(phy_id << 16);
444 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
448 phy->id |= (u32)(phy_id);
449 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
452 return -E1000_ERR_PHY;
460 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
461 * @hw: pointer to the HW structure
463 * Acquire the HW semaphore to access the PHY or NVM
465 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
468 s32 sw_timeout = hw->nvm.word_size + 1;
469 s32 fw_timeout = hw->nvm.word_size + 1;
473 * If we have timedout 3 times on trying to acquire
474 * the inter-port SMBI semaphore, there is old code
475 * operating on the other port, and it is not
476 * releasing SMBI. Modify the number of times that
477 * we try for the semaphore to interwork with this
480 if (hw->dev_spec.e82571.smb_counter > 2)
483 /* Get the SW semaphore */
484 while (i < sw_timeout) {
486 if (!(swsm & E1000_SWSM_SMBI))
493 if (i == sw_timeout) {
494 e_dbg("Driver can't access device - SMBI bit is set.\n");
495 hw->dev_spec.e82571.smb_counter++;
497 /* Get the FW semaphore. */
498 for (i = 0; i < fw_timeout; i++) {
500 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
502 /* Semaphore acquired if bit latched */
503 if (er32(SWSM) & E1000_SWSM_SWESMBI)
509 if (i == fw_timeout) {
510 /* Release semaphores */
511 e1000_put_hw_semaphore_82571(hw);
512 e_dbg("Driver can't access the NVM\n");
513 return -E1000_ERR_NVM;
520 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
521 * @hw: pointer to the HW structure
523 * Release hardware semaphore used to access the PHY or NVM
525 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
530 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
535 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
536 * @hw: pointer to the HW structure
538 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
539 * Then for non-82573 hardware, set the EEPROM access request bit and wait
540 * for EEPROM access grant bit. If the access grant bit is not set, release
541 * hardware semaphore.
543 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
547 ret_val = e1000_get_hw_semaphore_82571(hw);
551 switch (hw->mac.type) {
557 ret_val = e1000e_acquire_nvm(hw);
562 e1000_put_hw_semaphore_82571(hw);
568 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
569 * @hw: pointer to the HW structure
571 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
573 static void e1000_release_nvm_82571(struct e1000_hw *hw)
575 e1000e_release_nvm(hw);
576 e1000_put_hw_semaphore_82571(hw);
580 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
581 * @hw: pointer to the HW structure
582 * @offset: offset within the EEPROM to be written to
583 * @words: number of words to write
584 * @data: 16 bit word(s) to be written to the EEPROM
586 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
588 * If e1000e_update_nvm_checksum is not called after this function, the
589 * EEPROM will most likely contain an invalid checksum.
591 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
596 switch (hw->mac.type) {
600 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
604 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
607 ret_val = -E1000_ERR_NVM;
615 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
616 * @hw: pointer to the HW structure
618 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
619 * up to the checksum. Then calculates the EEPROM checksum and writes the
620 * value to the EEPROM.
622 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
628 ret_val = e1000e_update_nvm_checksum_generic(hw);
633 * If our nvm is an EEPROM, then we're done
634 * otherwise, commit the checksum to the flash NVM.
636 if (hw->nvm.type != e1000_nvm_flash_hw)
639 /* Check for pending operations. */
640 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
642 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
646 if (i == E1000_FLASH_UPDATES)
647 return -E1000_ERR_NVM;
649 /* Reset the firmware if using STM opcode. */
650 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
652 * The enabling of and the actual reset must be done
653 * in two write cycles.
655 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
657 ew32(HICR, E1000_HICR_FW_RESET);
660 /* Commit the write to flash */
661 eecd = er32(EECD) | E1000_EECD_FLUPD;
664 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
666 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
670 if (i == E1000_FLASH_UPDATES)
671 return -E1000_ERR_NVM;
677 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
678 * @hw: pointer to the HW structure
680 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
681 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
683 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
685 if (hw->nvm.type == e1000_nvm_flash_hw)
686 e1000_fix_nvm_checksum_82571(hw);
688 return e1000e_validate_nvm_checksum_generic(hw);
692 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
693 * @hw: pointer to the HW structure
694 * @offset: offset within the EEPROM to be written to
695 * @words: number of words to write
696 * @data: 16 bit word(s) to be written to the EEPROM
698 * After checking for invalid values, poll the EEPROM to ensure the previous
699 * command has completed before trying to write the next word. After write
700 * poll for completion.
702 * If e1000e_update_nvm_checksum is not called after this function, the
703 * EEPROM will most likely contain an invalid checksum.
705 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
706 u16 words, u16 *data)
708 struct e1000_nvm_info *nvm = &hw->nvm;
713 * A check for invalid values: offset too large, too many words,
714 * and not enough words.
716 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
718 e_dbg("nvm parameter(s) out of bounds\n");
719 return -E1000_ERR_NVM;
722 for (i = 0; i < words; i++) {
723 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
724 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
725 E1000_NVM_RW_REG_START;
727 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
733 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
742 * e1000_get_cfg_done_82571 - Poll for configuration done
743 * @hw: pointer to the HW structure
745 * Reads the management control register for the config done bit to be set.
747 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
749 s32 timeout = PHY_CFG_TIMEOUT;
753 E1000_NVM_CFG_DONE_PORT_0)
759 e_dbg("MNG configuration cycle has not completed.\n");
760 return -E1000_ERR_RESET;
767 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
768 * @hw: pointer to the HW structure
769 * @active: true to enable LPLU, false to disable
771 * Sets the LPLU D0 state according to the active flag. When activating LPLU
772 * this function also disables smart speed and vice versa. LPLU will not be
773 * activated unless the device autonegotiation advertisement meets standards
774 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
775 * pointer entry point only called by PHY setup routines.
777 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
779 struct e1000_phy_info *phy = &hw->phy;
783 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
788 data |= IGP02E1000_PM_D0_LPLU;
789 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
793 /* When LPLU is enabled, we should disable SmartSpeed */
794 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
795 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
796 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
800 data &= ~IGP02E1000_PM_D0_LPLU;
801 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
803 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
804 * during Dx states where the power conservation is most
805 * important. During driver activity we should enable
806 * SmartSpeed, so performance is maintained.
808 if (phy->smart_speed == e1000_smart_speed_on) {
809 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
814 data |= IGP01E1000_PSCFR_SMART_SPEED;
815 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
819 } else if (phy->smart_speed == e1000_smart_speed_off) {
820 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
825 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
826 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
837 * e1000_reset_hw_82571 - Reset hardware
838 * @hw: pointer to the HW structure
840 * This resets the hardware into a known state.
842 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
844 u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
849 * Prevent the PCI-E bus from sticking if there is no TLP connection
850 * on the last TLP read/write transaction when MAC is reset.
852 ret_val = e1000e_disable_pcie_master(hw);
854 e_dbg("PCI-E Master disable polling has failed.\n");
856 e_dbg("Masking off all interrupts\n");
857 ew32(IMC, 0xffffffff);
860 ew32(TCTL, E1000_TCTL_PSP);
866 * Must acquire the MDIO ownership before MAC reset.
867 * Ownership defaults to firmware after a reset.
869 switch (hw->mac.type) {
873 extcnf_ctrl = er32(EXTCNF_CTRL);
874 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
877 ew32(EXTCNF_CTRL, extcnf_ctrl);
878 extcnf_ctrl = er32(EXTCNF_CTRL);
880 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
883 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
887 } while (i < MDIO_OWNERSHIP_TIMEOUT);
895 e_dbg("Issuing a global reset to MAC\n");
896 ew32(CTRL, ctrl | E1000_CTRL_RST);
898 if (hw->nvm.type == e1000_nvm_flash_hw) {
900 ctrl_ext = er32(CTRL_EXT);
901 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
902 ew32(CTRL_EXT, ctrl_ext);
906 ret_val = e1000e_get_auto_rd_done(hw);
908 /* We don't want to continue accessing MAC registers. */
912 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
913 * Need to wait for Phy configuration completion before accessing
917 switch (hw->mac.type) {
927 /* Clear any pending interrupt events. */
928 ew32(IMC, 0xffffffff);
931 /* Install any alternate MAC address into RAR0 */
932 ret_val = e1000_check_alt_mac_addr_generic(hw);
936 e1000e_set_laa_state_82571(hw, true);
938 /* Reinitialize the 82571 serdes link state machine */
939 if (hw->phy.media_type == e1000_media_type_internal_serdes)
940 hw->mac.serdes_link_state = e1000_serdes_link_down;
946 * e1000_init_hw_82571 - Initialize hardware
947 * @hw: pointer to the HW structure
949 * This inits the hardware readying it for operation.
951 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
953 struct e1000_mac_info *mac = &hw->mac;
956 u16 i, rar_count = mac->rar_entry_count;
958 e1000_initialize_hw_bits_82571(hw);
960 /* Initialize identification LED */
961 ret_val = e1000e_id_led_init(hw);
963 e_dbg("Error initializing identification LED\n");
964 /* This is not fatal and we should not stop init due to this */
966 /* Disabling VLAN filtering */
967 e_dbg("Initializing the IEEE VLAN\n");
968 mac->ops.clear_vfta(hw);
970 /* Setup the receive address. */
972 * If, however, a locally administered address was assigned to the
973 * 82571, we must reserve a RAR for it to work around an issue where
974 * resetting one port will reload the MAC on the other port.
976 if (e1000e_get_laa_state_82571(hw))
978 e1000e_init_rx_addrs(hw, rar_count);
980 /* Zero out the Multicast HASH table */
981 e_dbg("Zeroing the MTA\n");
982 for (i = 0; i < mac->mta_reg_count; i++)
983 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
985 /* Setup link and flow control */
986 ret_val = e1000_setup_link_82571(hw);
988 /* Set the transmit descriptor write-back policy */
989 reg_data = er32(TXDCTL(0));
990 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
991 E1000_TXDCTL_FULL_TX_DESC_WB |
992 E1000_TXDCTL_COUNT_DESC;
993 ew32(TXDCTL(0), reg_data);
995 /* ...for both queues. */
1000 e1000e_enable_tx_pkt_filtering(hw);
1001 reg_data = er32(GCR);
1002 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1003 ew32(GCR, reg_data);
1006 reg_data = er32(TXDCTL(1));
1007 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1008 E1000_TXDCTL_FULL_TX_DESC_WB |
1009 E1000_TXDCTL_COUNT_DESC;
1010 ew32(TXDCTL(1), reg_data);
1015 * Clear all of the statistics registers (clear on read). It is
1016 * important that we do this after we have tried to establish link
1017 * because the symbol error count will increment wildly if there
1020 e1000_clear_hw_cntrs_82571(hw);
1026 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1027 * @hw: pointer to the HW structure
1029 * Initializes required hardware-dependent bits needed for normal operation.
1031 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1035 /* Transmit Descriptor Control 0 */
1036 reg = er32(TXDCTL(0));
1038 ew32(TXDCTL(0), reg);
1040 /* Transmit Descriptor Control 1 */
1041 reg = er32(TXDCTL(1));
1043 ew32(TXDCTL(1), reg);
1045 /* Transmit Arbitration Control 0 */
1046 reg = er32(TARC(0));
1047 reg &= ~(0xF << 27); /* 30:27 */
1048 switch (hw->mac.type) {
1051 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1058 /* Transmit Arbitration Control 1 */
1059 reg = er32(TARC(1));
1060 switch (hw->mac.type) {
1063 reg &= ~((1 << 29) | (1 << 30));
1064 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1065 if (er32(TCTL) & E1000_TCTL_MULR)
1075 /* Device Control */
1076 switch (hw->mac.type) {
1088 /* Extended Device Control */
1089 switch (hw->mac.type) {
1093 reg = er32(CTRL_EXT);
1096 ew32(CTRL_EXT, reg);
1102 if (hw->mac.type == e1000_82571) {
1103 reg = er32(PBA_ECC);
1104 reg |= E1000_PBA_ECC_CORR_EN;
1108 * Workaround for hardware errata.
1109 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1112 if ((hw->mac.type == e1000_82571) ||
1113 (hw->mac.type == e1000_82572)) {
1114 reg = er32(CTRL_EXT);
1115 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1116 ew32(CTRL_EXT, reg);
1120 /* PCI-Ex Control Registers */
1121 switch (hw->mac.type) {
1129 * Workaround for hardware errata.
1130 * apply workaround for hardware errata documented in errata
1131 * docs Fixes issue where some error prone or unreliable PCIe
1132 * completions are occurring, particularly with ASPM enabled.
1133 * Without fix, issue can cause tx timeouts.
1147 * e1000_clear_vfta_82571 - Clear VLAN filter table
1148 * @hw: pointer to the HW structure
1150 * Clears the register array which contains the VLAN filter table by
1151 * setting all the values to 0.
1153 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1157 u32 vfta_offset = 0;
1158 u32 vfta_bit_in_reg = 0;
1160 switch (hw->mac.type) {
1164 if (hw->mng_cookie.vlan_id != 0) {
1166 * The VFTA is a 4096b bit-field, each identifying
1167 * a single VLAN ID. The following operations
1168 * determine which 32b entry (i.e. offset) into the
1169 * array we want to set the VLAN ID (i.e. bit) of
1170 * the manageability unit.
1172 vfta_offset = (hw->mng_cookie.vlan_id >>
1173 E1000_VFTA_ENTRY_SHIFT) &
1174 E1000_VFTA_ENTRY_MASK;
1175 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1176 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1182 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1184 * If the offset we want to clear is the same offset of the
1185 * manageability VLAN ID, then clear all bits except that of
1186 * the manageability unit.
1188 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1189 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1195 * e1000_check_mng_mode_82574 - Check manageability is enabled
1196 * @hw: pointer to the HW structure
1198 * Reads the NVM Initialization Control Word 2 and returns true
1199 * (>0) if any manageability is enabled, else false (0).
1201 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1205 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1206 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1210 * e1000_led_on_82574 - Turn LED on
1211 * @hw: pointer to the HW structure
1215 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1220 ctrl = hw->mac.ledctl_mode2;
1221 if (!(E1000_STATUS_LU & er32(STATUS))) {
1223 * If no link, then turn LED on by setting the invert bit
1224 * for each LED that's "on" (0x0E) in ledctl_mode2.
1226 for (i = 0; i < 4; i++)
1227 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1228 E1000_LEDCTL_MODE_LED_ON)
1229 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1237 * e1000_setup_link_82571 - Setup flow control and link settings
1238 * @hw: pointer to the HW structure
1240 * Determines which flow control settings to use, then configures flow
1241 * control. Calls the appropriate media-specific link configuration
1242 * function. Assuming the adapter has a valid link partner, a valid link
1243 * should be established. Assumes the hardware has previously been reset
1244 * and the transmitter and receiver are not enabled.
1246 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1249 * 82573 does not have a word in the NVM to determine
1250 * the default flow control setting, so we explicitly
1253 switch (hw->mac.type) {
1257 if (hw->fc.requested_mode == e1000_fc_default)
1258 hw->fc.requested_mode = e1000_fc_full;
1264 return e1000e_setup_link(hw);
1268 * e1000_setup_copper_link_82571 - Configure copper link settings
1269 * @hw: pointer to the HW structure
1271 * Configures the link for auto-neg or forced speed and duplex. Then we check
1272 * for link, once link is established calls to configure collision distance
1273 * and flow control are called.
1275 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1281 ctrl |= E1000_CTRL_SLU;
1282 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1285 switch (hw->phy.type) {
1288 ret_val = e1000e_copper_link_setup_m88(hw);
1290 case e1000_phy_igp_2:
1291 ret_val = e1000e_copper_link_setup_igp(hw);
1294 return -E1000_ERR_PHY;
1301 ret_val = e1000e_setup_copper_link(hw);
1307 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1308 * @hw: pointer to the HW structure
1310 * Configures collision distance and flow control for fiber and serdes links.
1311 * Upon successful setup, poll for link.
1313 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1315 switch (hw->mac.type) {
1319 * If SerDes loopback mode is entered, there is no form
1320 * of reset to take the adapter out of that mode. So we
1321 * have to explicitly take the adapter out of loopback
1322 * mode. This prevents drivers from twiddling their thumbs
1323 * if another tool failed to take it out of loopback mode.
1325 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1331 return e1000e_setup_fiber_serdes_link(hw);
1335 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1336 * @hw: pointer to the HW structure
1338 * Reports the link state as up or down.
1340 * If autonegotiation is supported by the link partner, the link state is
1341 * determined by the result of autonegotiation. This is the most likely case.
1342 * If autonegotiation is not supported by the link partner, and the link
1343 * has a valid signal, force the link up.
1345 * The link state is represented internally here by 4 states:
1348 * 2) autoneg_progress
1349 * 3) autoneg_complete (the link successfully autonegotiated)
1350 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1353 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1355 struct e1000_mac_info *mac = &hw->mac;
1362 status = er32(STATUS);
1365 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1367 /* Receiver is synchronized with no invalid bits. */
1368 switch (mac->serdes_link_state) {
1369 case e1000_serdes_link_autoneg_complete:
1370 if (!(status & E1000_STATUS_LU)) {
1372 * We have lost link, retry autoneg before
1373 * reporting link failure
1375 mac->serdes_link_state =
1376 e1000_serdes_link_autoneg_progress;
1377 mac->serdes_has_link = false;
1378 e_dbg("AN_UP -> AN_PROG\n");
1382 case e1000_serdes_link_forced_up:
1384 * If we are receiving /C/ ordered sets, re-enable
1385 * auto-negotiation in the TXCW register and disable
1386 * forced link in the Device Control register in an
1387 * attempt to auto-negotiate with our link partner.
1389 if (rxcw & E1000_RXCW_C) {
1390 /* Enable autoneg, and unforce link up */
1391 ew32(TXCW, mac->txcw);
1392 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1393 mac->serdes_link_state =
1394 e1000_serdes_link_autoneg_progress;
1395 mac->serdes_has_link = false;
1396 e_dbg("FORCED_UP -> AN_PROG\n");
1400 case e1000_serdes_link_autoneg_progress:
1401 if (rxcw & E1000_RXCW_C) {
1403 * We received /C/ ordered sets, meaning the
1404 * link partner has autonegotiated, and we can
1405 * trust the Link Up (LU) status bit.
1407 if (status & E1000_STATUS_LU) {
1408 mac->serdes_link_state =
1409 e1000_serdes_link_autoneg_complete;
1410 e_dbg("AN_PROG -> AN_UP\n");
1411 mac->serdes_has_link = true;
1413 /* Autoneg completed, but failed. */
1414 mac->serdes_link_state =
1415 e1000_serdes_link_down;
1416 e_dbg("AN_PROG -> DOWN\n");
1420 * The link partner did not autoneg.
1421 * Force link up and full duplex, and change
1424 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1425 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1428 /* Configure Flow Control after link up. */
1429 ret_val = e1000e_config_fc_after_link_up(hw);
1431 e_dbg("Error config flow control\n");
1434 mac->serdes_link_state =
1435 e1000_serdes_link_forced_up;
1436 mac->serdes_has_link = true;
1437 e_dbg("AN_PROG -> FORCED_UP\n");
1441 case e1000_serdes_link_down:
1444 * The link was down but the receiver has now gained
1445 * valid sync, so lets see if we can bring the link
1448 ew32(TXCW, mac->txcw);
1449 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1450 mac->serdes_link_state =
1451 e1000_serdes_link_autoneg_progress;
1452 e_dbg("DOWN -> AN_PROG\n");
1456 if (!(rxcw & E1000_RXCW_SYNCH)) {
1457 mac->serdes_has_link = false;
1458 mac->serdes_link_state = e1000_serdes_link_down;
1459 e_dbg("ANYSTATE -> DOWN\n");
1462 * We have sync, and can tolerate one invalid (IV)
1463 * codeword before declaring link down, so reread
1468 if (rxcw & E1000_RXCW_IV) {
1469 mac->serdes_link_state = e1000_serdes_link_down;
1470 mac->serdes_has_link = false;
1471 e_dbg("ANYSTATE -> DOWN\n");
1480 * e1000_valid_led_default_82571 - Verify a valid default LED config
1481 * @hw: pointer to the HW structure
1482 * @data: pointer to the NVM (EEPROM)
1484 * Read the EEPROM for the current default LED configuration. If the
1485 * LED configuration is not valid, set to a valid LED configuration.
1487 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1491 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1493 e_dbg("NVM Read Error\n");
1497 switch (hw->mac.type) {
1501 if (*data == ID_LED_RESERVED_F746)
1502 *data = ID_LED_DEFAULT_82573;
1505 if (*data == ID_LED_RESERVED_0000 ||
1506 *data == ID_LED_RESERVED_FFFF)
1507 *data = ID_LED_DEFAULT;
1515 * e1000e_get_laa_state_82571 - Get locally administered address state
1516 * @hw: pointer to the HW structure
1518 * Retrieve and return the current locally administered address state.
1520 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1522 if (hw->mac.type != e1000_82571)
1525 return hw->dev_spec.e82571.laa_is_present;
1529 * e1000e_set_laa_state_82571 - Set locally administered address state
1530 * @hw: pointer to the HW structure
1531 * @state: enable/disable locally administered address
1533 * Enable/Disable the current locally administered address state.
1535 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1537 if (hw->mac.type != e1000_82571)
1540 hw->dev_spec.e82571.laa_is_present = state;
1542 /* If workaround is activated... */
1545 * Hold a copy of the LAA in RAR[14] This is done so that
1546 * between the time RAR[0] gets clobbered and the time it
1547 * gets fixed, the actual LAA is in one of the RARs and no
1548 * incoming packets directed to this port are dropped.
1549 * Eventually the LAA will be in RAR[0] and RAR[14].
1551 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1555 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1556 * @hw: pointer to the HW structure
1558 * Verifies that the EEPROM has completed the update. After updating the
1559 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1560 * the checksum fix is not implemented, we need to set the bit and update
1561 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1562 * we need to return bad checksum.
1564 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1566 struct e1000_nvm_info *nvm = &hw->nvm;
1570 if (nvm->type != e1000_nvm_flash_hw)
1574 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1575 * 10h-12h. Checksum may need to be fixed.
1577 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1581 if (!(data & 0x10)) {
1583 * Read 0x23 and check bit 15. This bit is a 1
1584 * when the checksum has already been fixed. If
1585 * the checksum is still wrong and this bit is a
1586 * 1, we need to return bad checksum. Otherwise,
1587 * we need to set this bit to a 1 and update the
1590 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1594 if (!(data & 0x8000)) {
1596 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1599 ret_val = e1000e_update_nvm_checksum(hw);
1607 * e1000_read_mac_addr_82571 - Read device MAC address
1608 * @hw: pointer to the HW structure
1610 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1615 * If there's an alternate MAC address place it in RAR0
1616 * so that it will override the Si installed default perm
1619 ret_val = e1000_check_alt_mac_addr_generic(hw);
1623 ret_val = e1000_read_mac_addr_generic(hw);
1630 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1631 * @hw: pointer to the HW structure
1633 * In the case of a PHY power down to save power, or to turn off link during a
1634 * driver unload, or wake on lan is not enabled, remove the link.
1636 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1638 struct e1000_phy_info *phy = &hw->phy;
1639 struct e1000_mac_info *mac = &hw->mac;
1641 if (!(phy->ops.check_reset_block))
1644 /* If the management interface is not enabled, then power down */
1645 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1646 e1000_power_down_phy_copper(hw);
1652 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1653 * @hw: pointer to the HW structure
1655 * Clears the hardware counters by reading the counter registers.
1657 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1659 e1000e_clear_hw_cntrs_base(hw);
1697 static struct e1000_mac_operations e82571_mac_ops = {
1698 /* .check_mng_mode: mac type dependent */
1699 /* .check_for_link: media type dependent */
1700 .id_led_init = e1000e_id_led_init,
1701 .cleanup_led = e1000e_cleanup_led_generic,
1702 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1703 .get_bus_info = e1000e_get_bus_info_pcie,
1704 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1705 /* .get_link_up_info: media type dependent */
1706 /* .led_on: mac type dependent */
1707 .led_off = e1000e_led_off_generic,
1708 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1709 .write_vfta = e1000_write_vfta_generic,
1710 .clear_vfta = e1000_clear_vfta_82571,
1711 .reset_hw = e1000_reset_hw_82571,
1712 .init_hw = e1000_init_hw_82571,
1713 .setup_link = e1000_setup_link_82571,
1714 /* .setup_physical_interface: media type dependent */
1715 .setup_led = e1000e_setup_led_generic,
1716 .read_mac_addr = e1000_read_mac_addr_82571,
1719 static struct e1000_phy_operations e82_phy_ops_igp = {
1720 .acquire = e1000_get_hw_semaphore_82571,
1721 .check_polarity = e1000_check_polarity_igp,
1722 .check_reset_block = e1000e_check_reset_block_generic,
1724 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1725 .get_cfg_done = e1000_get_cfg_done_82571,
1726 .get_cable_length = e1000e_get_cable_length_igp_2,
1727 .get_info = e1000e_get_phy_info_igp,
1728 .read_reg = e1000e_read_phy_reg_igp,
1729 .release = e1000_put_hw_semaphore_82571,
1730 .reset = e1000e_phy_hw_reset_generic,
1731 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1732 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1733 .write_reg = e1000e_write_phy_reg_igp,
1734 .cfg_on_link_up = NULL,
1737 static struct e1000_phy_operations e82_phy_ops_m88 = {
1738 .acquire = e1000_get_hw_semaphore_82571,
1739 .check_polarity = e1000_check_polarity_m88,
1740 .check_reset_block = e1000e_check_reset_block_generic,
1741 .commit = e1000e_phy_sw_reset,
1742 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1743 .get_cfg_done = e1000e_get_cfg_done,
1744 .get_cable_length = e1000e_get_cable_length_m88,
1745 .get_info = e1000e_get_phy_info_m88,
1746 .read_reg = e1000e_read_phy_reg_m88,
1747 .release = e1000_put_hw_semaphore_82571,
1748 .reset = e1000e_phy_hw_reset_generic,
1749 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1750 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1751 .write_reg = e1000e_write_phy_reg_m88,
1752 .cfg_on_link_up = NULL,
1755 static struct e1000_phy_operations e82_phy_ops_bm = {
1756 .acquire = e1000_get_hw_semaphore_82571,
1757 .check_polarity = e1000_check_polarity_m88,
1758 .check_reset_block = e1000e_check_reset_block_generic,
1759 .commit = e1000e_phy_sw_reset,
1760 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1761 .get_cfg_done = e1000e_get_cfg_done,
1762 .get_cable_length = e1000e_get_cable_length_m88,
1763 .get_info = e1000e_get_phy_info_m88,
1764 .read_reg = e1000e_read_phy_reg_bm2,
1765 .release = e1000_put_hw_semaphore_82571,
1766 .reset = e1000e_phy_hw_reset_generic,
1767 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1768 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1769 .write_reg = e1000e_write_phy_reg_bm2,
1770 .cfg_on_link_up = NULL,
1773 static struct e1000_nvm_operations e82571_nvm_ops = {
1774 .acquire = e1000_acquire_nvm_82571,
1775 .read = e1000e_read_nvm_eerd,
1776 .release = e1000_release_nvm_82571,
1777 .update = e1000_update_nvm_checksum_82571,
1778 .valid_led_default = e1000_valid_led_default_82571,
1779 .validate = e1000_validate_nvm_checksum_82571,
1780 .write = e1000_write_nvm_82571,
1783 struct e1000_info e1000_82571_info = {
1785 .flags = FLAG_HAS_HW_VLAN_FILTER
1786 | FLAG_HAS_JUMBO_FRAMES
1788 | FLAG_APME_IN_CTRL3
1789 | FLAG_RX_CSUM_ENABLED
1790 | FLAG_HAS_CTRLEXT_ON_LOAD
1791 | FLAG_HAS_SMART_POWER_DOWN
1792 | FLAG_RESET_OVERWRITES_LAA /* errata */
1793 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1794 | FLAG_APME_CHECK_PORT_B,
1796 .max_hw_frame_size = DEFAULT_JUMBO,
1797 .get_variants = e1000_get_variants_82571,
1798 .mac_ops = &e82571_mac_ops,
1799 .phy_ops = &e82_phy_ops_igp,
1800 .nvm_ops = &e82571_nvm_ops,
1803 struct e1000_info e1000_82572_info = {
1805 .flags = FLAG_HAS_HW_VLAN_FILTER
1806 | FLAG_HAS_JUMBO_FRAMES
1808 | FLAG_APME_IN_CTRL3
1809 | FLAG_RX_CSUM_ENABLED
1810 | FLAG_HAS_CTRLEXT_ON_LOAD
1811 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1813 .max_hw_frame_size = DEFAULT_JUMBO,
1814 .get_variants = e1000_get_variants_82571,
1815 .mac_ops = &e82571_mac_ops,
1816 .phy_ops = &e82_phy_ops_igp,
1817 .nvm_ops = &e82571_nvm_ops,
1820 struct e1000_info e1000_82573_info = {
1822 .flags = FLAG_HAS_HW_VLAN_FILTER
1823 | FLAG_HAS_JUMBO_FRAMES
1825 | FLAG_APME_IN_CTRL3
1826 | FLAG_RX_CSUM_ENABLED
1827 | FLAG_HAS_SMART_POWER_DOWN
1830 | FLAG_HAS_SWSM_ON_LOAD,
1832 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1833 .get_variants = e1000_get_variants_82571,
1834 .mac_ops = &e82571_mac_ops,
1835 .phy_ops = &e82_phy_ops_m88,
1836 .nvm_ops = &e82571_nvm_ops,
1839 struct e1000_info e1000_82574_info = {
1841 .flags = FLAG_HAS_HW_VLAN_FILTER
1843 | FLAG_HAS_JUMBO_FRAMES
1845 | FLAG_APME_IN_CTRL3
1846 | FLAG_RX_CSUM_ENABLED
1847 | FLAG_HAS_SMART_POWER_DOWN
1849 | FLAG_HAS_CTRLEXT_ON_LOAD,
1851 .max_hw_frame_size = DEFAULT_JUMBO,
1852 .get_variants = e1000_get_variants_82571,
1853 .mac_ops = &e82571_mac_ops,
1854 .phy_ops = &e82_phy_ops_bm,
1855 .nvm_ops = &e82571_nvm_ops,
1858 struct e1000_info e1000_82583_info = {
1860 .flags = FLAG_HAS_HW_VLAN_FILTER
1862 | FLAG_APME_IN_CTRL3
1863 | FLAG_RX_CSUM_ENABLED
1864 | FLAG_HAS_SMART_POWER_DOWN
1866 | FLAG_HAS_CTRLEXT_ON_LOAD,
1868 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1869 .get_variants = e1000_get_variants_82571,
1870 .mac_ops = &e82571_mac_ops,
1871 .phy_ops = &e82_phy_ops_bm,
1872 .nvm_ops = &e82571_nvm_ops,