1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55 #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */
56 #define E1000_BASE1000T_STATUS 10
57 #define E1000_IDLE_ERROR_COUNT_MASK 0xFF
58 #define E1000_RECEIVE_ERROR_COUNTER 21
59 #define E1000_RECEIVE_ERROR_MAX 0xFFFF
61 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
63 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
64 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
65 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
66 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
67 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
68 u16 words, u16 *data);
69 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
70 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
71 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
74 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
75 static s32 e1000_led_on_82574(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
78 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
79 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
80 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
81 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
85 * e1000_init_phy_params_82571 - Init PHY func ptrs.
86 * @hw: pointer to the HW structure
88 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
90 struct e1000_phy_info *phy = &hw->phy;
93 if (hw->phy.media_type != e1000_media_type_copper) {
94 phy->type = e1000_phy_none;
99 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
100 phy->reset_delay_us = 100;
102 phy->ops.power_up = e1000_power_up_phy_copper;
103 phy->ops.power_down = e1000_power_down_phy_copper_82571;
105 switch (hw->mac.type) {
108 phy->type = e1000_phy_igp_2;
111 phy->type = e1000_phy_m88;
115 phy->type = e1000_phy_bm;
116 phy->ops.acquire = e1000_get_hw_semaphore_82574;
117 phy->ops.release = e1000_put_hw_semaphore_82574;
118 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
119 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
122 return -E1000_ERR_PHY;
126 /* This can only be done after all function pointers are setup. */
127 ret_val = e1000_get_phy_id_82571(hw);
129 e_dbg("Error getting PHY ID\n");
134 switch (hw->mac.type) {
137 if (phy->id != IGP01E1000_I_PHY_ID)
138 ret_val = -E1000_ERR_PHY;
141 if (phy->id != M88E1111_I_PHY_ID)
142 ret_val = -E1000_ERR_PHY;
146 if (phy->id != BME1000_E_PHY_ID_R2)
147 ret_val = -E1000_ERR_PHY;
150 ret_val = -E1000_ERR_PHY;
155 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
161 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
162 * @hw: pointer to the HW structure
164 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
166 struct e1000_nvm_info *nvm = &hw->nvm;
167 u32 eecd = er32(EECD);
170 nvm->opcode_bits = 8;
172 switch (nvm->override) {
173 case e1000_nvm_override_spi_large:
175 nvm->address_bits = 16;
177 case e1000_nvm_override_spi_small:
179 nvm->address_bits = 8;
182 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
183 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
187 switch (hw->mac.type) {
191 if (((eecd >> 15) & 0x3) == 0x3) {
192 nvm->type = e1000_nvm_flash_hw;
193 nvm->word_size = 2048;
195 * Autonomous Flash update bit must be cleared due
196 * to Flash update issue.
198 eecd &= ~E1000_EECD_AUPDEN;
204 nvm->type = e1000_nvm_eeprom_spi;
205 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
206 E1000_EECD_SIZE_EX_SHIFT);
208 * Added to a constant, "size" becomes the left-shift value
209 * for setting word_size.
211 size += NVM_WORD_SIZE_BASE_SHIFT;
213 /* EEPROM access above 16k is unsupported */
216 nvm->word_size = 1 << size;
220 /* Function Pointers */
221 switch (hw->mac.type) {
224 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
225 nvm->ops.release = e1000_put_hw_semaphore_82574;
235 * e1000_init_mac_params_82571 - Init MAC func ptrs.
236 * @hw: pointer to the HW structure
238 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
240 struct e1000_hw *hw = &adapter->hw;
241 struct e1000_mac_info *mac = &hw->mac;
242 struct e1000_mac_operations *func = &mac->ops;
245 bool force_clear_smbi = false;
248 switch (adapter->pdev->device) {
249 case E1000_DEV_ID_82571EB_FIBER:
250 case E1000_DEV_ID_82572EI_FIBER:
251 case E1000_DEV_ID_82571EB_QUAD_FIBER:
252 hw->phy.media_type = e1000_media_type_fiber;
254 case E1000_DEV_ID_82571EB_SERDES:
255 case E1000_DEV_ID_82572EI_SERDES:
256 case E1000_DEV_ID_82571EB_SERDES_DUAL:
257 case E1000_DEV_ID_82571EB_SERDES_QUAD:
258 hw->phy.media_type = e1000_media_type_internal_serdes;
261 hw->phy.media_type = e1000_media_type_copper;
265 /* Set mta register count */
266 mac->mta_reg_count = 128;
267 /* Set rar entry count */
268 mac->rar_entry_count = E1000_RAR_ENTRIES;
269 /* Adaptive IFS supported */
270 mac->adaptive_ifs = true;
273 switch (hw->phy.media_type) {
274 case e1000_media_type_copper:
275 func->setup_physical_interface = e1000_setup_copper_link_82571;
276 func->check_for_link = e1000e_check_for_copper_link;
277 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
279 case e1000_media_type_fiber:
280 func->setup_physical_interface =
281 e1000_setup_fiber_serdes_link_82571;
282 func->check_for_link = e1000e_check_for_fiber_link;
283 func->get_link_up_info =
284 e1000e_get_speed_and_duplex_fiber_serdes;
286 case e1000_media_type_internal_serdes:
287 func->setup_physical_interface =
288 e1000_setup_fiber_serdes_link_82571;
289 func->check_for_link = e1000_check_for_serdes_link_82571;
290 func->get_link_up_info =
291 e1000e_get_speed_and_duplex_fiber_serdes;
294 return -E1000_ERR_CONFIG;
298 switch (hw->mac.type) {
300 func->set_lan_id = e1000_set_lan_id_single_port;
301 func->check_mng_mode = e1000e_check_mng_mode_generic;
302 func->led_on = e1000e_led_on_generic;
305 mac->has_fwsm = true;
307 * ARC supported; valid only if manageability features are
310 mac->arc_subsystem_valid =
311 (er32(FWSM) & E1000_FWSM_MODE_MASK)
316 func->set_lan_id = e1000_set_lan_id_single_port;
317 func->check_mng_mode = e1000_check_mng_mode_82574;
318 func->led_on = e1000_led_on_82574;
321 func->check_mng_mode = e1000e_check_mng_mode_generic;
322 func->led_on = e1000e_led_on_generic;
325 mac->has_fwsm = true;
330 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
331 * first NVM or PHY access. This should be done for single-port
332 * devices, and for one port only on dual-port devices so that
333 * for those devices we can still use the SMBI lock to synchronize
334 * inter-port accesses to the PHY & NVM.
336 switch (hw->mac.type) {
341 if (!(swsm2 & E1000_SWSM2_LOCK)) {
342 /* Only do this for the first interface on this card */
344 swsm2 | E1000_SWSM2_LOCK);
345 force_clear_smbi = true;
347 force_clear_smbi = false;
350 force_clear_smbi = true;
354 if (force_clear_smbi) {
355 /* Make sure SWSM.SMBI is clear */
357 if (swsm & E1000_SWSM_SMBI) {
358 /* This bit should not be set on a first interface, and
359 * indicates that the bootagent or EFI code has
360 * improperly left this bit enabled
362 e_dbg("Please update your 82571 Bootagent\n");
364 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
368 * Initialize device specific counter of SMBI acquisition
371 hw->dev_spec.e82571.smb_counter = 0;
376 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
378 struct e1000_hw *hw = &adapter->hw;
379 static int global_quad_port_a; /* global port a indication */
380 struct pci_dev *pdev = adapter->pdev;
381 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
384 rc = e1000_init_mac_params_82571(adapter);
388 rc = e1000_init_nvm_params_82571(hw);
392 rc = e1000_init_phy_params_82571(hw);
396 /* tag quad port adapters first, it's used below */
397 switch (pdev->device) {
398 case E1000_DEV_ID_82571EB_QUAD_COPPER:
399 case E1000_DEV_ID_82571EB_QUAD_FIBER:
400 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
401 case E1000_DEV_ID_82571PT_QUAD_COPPER:
402 adapter->flags |= FLAG_IS_QUAD_PORT;
403 /* mark the first port */
404 if (global_quad_port_a == 0)
405 adapter->flags |= FLAG_IS_QUAD_PORT_A;
406 /* Reset for multiple quad port adapters */
407 global_quad_port_a++;
408 if (global_quad_port_a == 4)
409 global_quad_port_a = 0;
415 switch (adapter->hw.mac.type) {
417 /* these dual ports don't have WoL on port B at all */
418 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
419 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
420 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
422 adapter->flags &= ~FLAG_HAS_WOL;
423 /* quad ports only support WoL on port A */
424 if (adapter->flags & FLAG_IS_QUAD_PORT &&
425 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
426 adapter->flags &= ~FLAG_HAS_WOL;
427 /* Does not support WoL on any port */
428 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
429 adapter->flags &= ~FLAG_HAS_WOL;
434 /* Disable ASPM L0s due to hardware errata */
435 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S);
437 if (pdev->device == E1000_DEV_ID_82573L) {
438 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
439 adapter->max_hw_frame_size = DEFAULT_JUMBO;
450 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
451 * @hw: pointer to the HW structure
453 * Reads the PHY registers and stores the PHY ID and possibly the PHY
454 * revision in the hardware structure.
456 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
458 struct e1000_phy_info *phy = &hw->phy;
462 switch (hw->mac.type) {
466 * The 82571 firmware may still be configuring the PHY.
467 * In this case, we cannot access the PHY until the
468 * configuration is done. So we explicitly set the
471 phy->id = IGP01E1000_I_PHY_ID;
474 return e1000e_get_phy_id(hw);
478 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
482 phy->id = (u32)(phy_id << 16);
484 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
488 phy->id |= (u32)(phy_id);
489 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
492 return -E1000_ERR_PHY;
500 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
501 * @hw: pointer to the HW structure
503 * Acquire the HW semaphore to access the PHY or NVM
505 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
508 s32 sw_timeout = hw->nvm.word_size + 1;
509 s32 fw_timeout = hw->nvm.word_size + 1;
513 * If we have timedout 3 times on trying to acquire
514 * the inter-port SMBI semaphore, there is old code
515 * operating on the other port, and it is not
516 * releasing SMBI. Modify the number of times that
517 * we try for the semaphore to interwork with this
520 if (hw->dev_spec.e82571.smb_counter > 2)
523 /* Get the SW semaphore */
524 while (i < sw_timeout) {
526 if (!(swsm & E1000_SWSM_SMBI))
533 if (i == sw_timeout) {
534 e_dbg("Driver can't access device - SMBI bit is set.\n");
535 hw->dev_spec.e82571.smb_counter++;
537 /* Get the FW semaphore. */
538 for (i = 0; i < fw_timeout; i++) {
540 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
542 /* Semaphore acquired if bit latched */
543 if (er32(SWSM) & E1000_SWSM_SWESMBI)
549 if (i == fw_timeout) {
550 /* Release semaphores */
551 e1000_put_hw_semaphore_82571(hw);
552 e_dbg("Driver can't access the NVM\n");
553 return -E1000_ERR_NVM;
560 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
561 * @hw: pointer to the HW structure
563 * Release hardware semaphore used to access the PHY or NVM
565 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
570 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
574 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
575 * @hw: pointer to the HW structure
577 * Acquire the HW semaphore during reset.
580 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
586 extcnf_ctrl = er32(EXTCNF_CTRL);
587 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
589 ew32(EXTCNF_CTRL, extcnf_ctrl);
590 extcnf_ctrl = er32(EXTCNF_CTRL);
592 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
595 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
599 } while (i < MDIO_OWNERSHIP_TIMEOUT);
601 if (i == MDIO_OWNERSHIP_TIMEOUT) {
602 /* Release semaphores */
603 e1000_put_hw_semaphore_82573(hw);
604 e_dbg("Driver can't access the PHY\n");
605 ret_val = -E1000_ERR_PHY;
614 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
615 * @hw: pointer to the HW structure
617 * Release hardware semaphore used during reset.
620 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
624 extcnf_ctrl = er32(EXTCNF_CTRL);
625 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
626 ew32(EXTCNF_CTRL, extcnf_ctrl);
629 static DEFINE_MUTEX(swflag_mutex);
632 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
633 * @hw: pointer to the HW structure
635 * Acquire the HW semaphore to access the PHY or NVM.
638 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
642 mutex_lock(&swflag_mutex);
643 ret_val = e1000_get_hw_semaphore_82573(hw);
645 mutex_unlock(&swflag_mutex);
650 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
651 * @hw: pointer to the HW structure
653 * Release hardware semaphore used to access the PHY or NVM
656 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
658 e1000_put_hw_semaphore_82573(hw);
659 mutex_unlock(&swflag_mutex);
663 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
664 * @hw: pointer to the HW structure
665 * @active: true to enable LPLU, false to disable
667 * Sets the LPLU D0 state according to the active flag.
668 * LPLU will not be activated unless the
669 * device autonegotiation advertisement meets standards of
670 * either 10 or 10/100 or 10/100/1000 at all duplexes.
671 * This is a function pointer entry point only called by
672 * PHY setup routines.
674 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
676 u16 data = er32(POEMB);
679 data |= E1000_PHY_CTRL_D0A_LPLU;
681 data &= ~E1000_PHY_CTRL_D0A_LPLU;
688 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
689 * @hw: pointer to the HW structure
690 * @active: boolean used to enable/disable lplu
692 * The low power link up (lplu) state is set to the power management level D3
693 * when active is true, else clear lplu for D3. LPLU
694 * is used during Dx states where the power conservation is most important.
695 * During driver activity, SmartSpeed should be enabled so performance is
698 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
700 u16 data = er32(POEMB);
703 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
704 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
705 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
706 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
707 data |= E1000_PHY_CTRL_NOND0A_LPLU;
715 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
716 * @hw: pointer to the HW structure
718 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
719 * Then for non-82573 hardware, set the EEPROM access request bit and wait
720 * for EEPROM access grant bit. If the access grant bit is not set, release
721 * hardware semaphore.
723 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
727 ret_val = e1000_get_hw_semaphore_82571(hw);
731 switch (hw->mac.type) {
735 ret_val = e1000e_acquire_nvm(hw);
740 e1000_put_hw_semaphore_82571(hw);
746 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
747 * @hw: pointer to the HW structure
749 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
751 static void e1000_release_nvm_82571(struct e1000_hw *hw)
753 e1000e_release_nvm(hw);
754 e1000_put_hw_semaphore_82571(hw);
758 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
759 * @hw: pointer to the HW structure
760 * @offset: offset within the EEPROM to be written to
761 * @words: number of words to write
762 * @data: 16 bit word(s) to be written to the EEPROM
764 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
766 * If e1000e_update_nvm_checksum is not called after this function, the
767 * EEPROM will most likely contain an invalid checksum.
769 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
774 switch (hw->mac.type) {
778 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
782 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
785 ret_val = -E1000_ERR_NVM;
793 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
794 * @hw: pointer to the HW structure
796 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
797 * up to the checksum. Then calculates the EEPROM checksum and writes the
798 * value to the EEPROM.
800 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
806 ret_val = e1000e_update_nvm_checksum_generic(hw);
811 * If our nvm is an EEPROM, then we're done
812 * otherwise, commit the checksum to the flash NVM.
814 if (hw->nvm.type != e1000_nvm_flash_hw)
817 /* Check for pending operations. */
818 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
820 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
824 if (i == E1000_FLASH_UPDATES)
825 return -E1000_ERR_NVM;
827 /* Reset the firmware if using STM opcode. */
828 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
830 * The enabling of and the actual reset must be done
831 * in two write cycles.
833 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
835 ew32(HICR, E1000_HICR_FW_RESET);
838 /* Commit the write to flash */
839 eecd = er32(EECD) | E1000_EECD_FLUPD;
842 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
844 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
848 if (i == E1000_FLASH_UPDATES)
849 return -E1000_ERR_NVM;
855 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
856 * @hw: pointer to the HW structure
858 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
859 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
861 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
863 if (hw->nvm.type == e1000_nvm_flash_hw)
864 e1000_fix_nvm_checksum_82571(hw);
866 return e1000e_validate_nvm_checksum_generic(hw);
870 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
871 * @hw: pointer to the HW structure
872 * @offset: offset within the EEPROM to be written to
873 * @words: number of words to write
874 * @data: 16 bit word(s) to be written to the EEPROM
876 * After checking for invalid values, poll the EEPROM to ensure the previous
877 * command has completed before trying to write the next word. After write
878 * poll for completion.
880 * If e1000e_update_nvm_checksum is not called after this function, the
881 * EEPROM will most likely contain an invalid checksum.
883 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
884 u16 words, u16 *data)
886 struct e1000_nvm_info *nvm = &hw->nvm;
891 * A check for invalid values: offset too large, too many words,
892 * and not enough words.
894 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
896 e_dbg("nvm parameter(s) out of bounds\n");
897 return -E1000_ERR_NVM;
900 for (i = 0; i < words; i++) {
901 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
902 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
903 E1000_NVM_RW_REG_START;
905 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
911 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
920 * e1000_get_cfg_done_82571 - Poll for configuration done
921 * @hw: pointer to the HW structure
923 * Reads the management control register for the config done bit to be set.
925 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
927 s32 timeout = PHY_CFG_TIMEOUT;
931 E1000_NVM_CFG_DONE_PORT_0)
937 e_dbg("MNG configuration cycle has not completed.\n");
938 return -E1000_ERR_RESET;
945 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
946 * @hw: pointer to the HW structure
947 * @active: true to enable LPLU, false to disable
949 * Sets the LPLU D0 state according to the active flag. When activating LPLU
950 * this function also disables smart speed and vice versa. LPLU will not be
951 * activated unless the device autonegotiation advertisement meets standards
952 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
953 * pointer entry point only called by PHY setup routines.
955 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
957 struct e1000_phy_info *phy = &hw->phy;
961 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
966 data |= IGP02E1000_PM_D0_LPLU;
967 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
971 /* When LPLU is enabled, we should disable SmartSpeed */
972 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
973 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
974 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
978 data &= ~IGP02E1000_PM_D0_LPLU;
979 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
981 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
982 * during Dx states where the power conservation is most
983 * important. During driver activity we should enable
984 * SmartSpeed, so performance is maintained.
986 if (phy->smart_speed == e1000_smart_speed_on) {
987 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
992 data |= IGP01E1000_PSCFR_SMART_SPEED;
993 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
997 } else if (phy->smart_speed == e1000_smart_speed_off) {
998 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1003 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1004 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1015 * e1000_reset_hw_82571 - Reset hardware
1016 * @hw: pointer to the HW structure
1018 * This resets the hardware into a known state.
1020 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1026 * Prevent the PCI-E bus from sticking if there is no TLP connection
1027 * on the last TLP read/write transaction when MAC is reset.
1029 ret_val = e1000e_disable_pcie_master(hw);
1031 e_dbg("PCI-E Master disable polling has failed.\n");
1033 e_dbg("Masking off all interrupts\n");
1034 ew32(IMC, 0xffffffff);
1037 ew32(TCTL, E1000_TCTL_PSP);
1043 * Must acquire the MDIO ownership before MAC reset.
1044 * Ownership defaults to firmware after a reset.
1046 switch (hw->mac.type) {
1048 ret_val = e1000_get_hw_semaphore_82573(hw);
1052 ret_val = e1000_get_hw_semaphore_82574(hw);
1058 e_dbg("Cannot acquire MDIO ownership\n");
1062 e_dbg("Issuing a global reset to MAC\n");
1063 ew32(CTRL, ctrl | E1000_CTRL_RST);
1065 /* Must release MDIO ownership and mutex after MAC reset. */
1066 switch (hw->mac.type) {
1069 e1000_put_hw_semaphore_82574(hw);
1075 if (hw->nvm.type == e1000_nvm_flash_hw) {
1077 ctrl_ext = er32(CTRL_EXT);
1078 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1079 ew32(CTRL_EXT, ctrl_ext);
1083 ret_val = e1000e_get_auto_rd_done(hw);
1085 /* We don't want to continue accessing MAC registers. */
1089 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1090 * Need to wait for Phy configuration completion before accessing
1094 switch (hw->mac.type) {
1104 /* Clear any pending interrupt events. */
1105 ew32(IMC, 0xffffffff);
1108 if (hw->mac.type == e1000_82571) {
1109 /* Install any alternate MAC address into RAR0 */
1110 ret_val = e1000_check_alt_mac_addr_generic(hw);
1114 e1000e_set_laa_state_82571(hw, true);
1117 /* Reinitialize the 82571 serdes link state machine */
1118 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1119 hw->mac.serdes_link_state = e1000_serdes_link_down;
1125 * e1000_init_hw_82571 - Initialize hardware
1126 * @hw: pointer to the HW structure
1128 * This inits the hardware readying it for operation.
1130 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1132 struct e1000_mac_info *mac = &hw->mac;
1135 u16 i, rar_count = mac->rar_entry_count;
1137 e1000_initialize_hw_bits_82571(hw);
1139 /* Initialize identification LED */
1140 ret_val = e1000e_id_led_init(hw);
1142 e_dbg("Error initializing identification LED\n");
1143 /* This is not fatal and we should not stop init due to this */
1145 /* Disabling VLAN filtering */
1146 e_dbg("Initializing the IEEE VLAN\n");
1147 mac->ops.clear_vfta(hw);
1149 /* Setup the receive address. */
1151 * If, however, a locally administered address was assigned to the
1152 * 82571, we must reserve a RAR for it to work around an issue where
1153 * resetting one port will reload the MAC on the other port.
1155 if (e1000e_get_laa_state_82571(hw))
1157 e1000e_init_rx_addrs(hw, rar_count);
1159 /* Zero out the Multicast HASH table */
1160 e_dbg("Zeroing the MTA\n");
1161 for (i = 0; i < mac->mta_reg_count; i++)
1162 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1164 /* Setup link and flow control */
1165 ret_val = e1000_setup_link_82571(hw);
1167 /* Set the transmit descriptor write-back policy */
1168 reg_data = er32(TXDCTL(0));
1169 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1170 E1000_TXDCTL_FULL_TX_DESC_WB |
1171 E1000_TXDCTL_COUNT_DESC;
1172 ew32(TXDCTL(0), reg_data);
1174 /* ...for both queues. */
1175 switch (mac->type) {
1177 e1000e_enable_tx_pkt_filtering(hw);
1181 reg_data = er32(GCR);
1182 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1183 ew32(GCR, reg_data);
1186 reg_data = er32(TXDCTL(1));
1187 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1188 E1000_TXDCTL_FULL_TX_DESC_WB |
1189 E1000_TXDCTL_COUNT_DESC;
1190 ew32(TXDCTL(1), reg_data);
1195 * Clear all of the statistics registers (clear on read). It is
1196 * important that we do this after we have tried to establish link
1197 * because the symbol error count will increment wildly if there
1200 e1000_clear_hw_cntrs_82571(hw);
1206 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1207 * @hw: pointer to the HW structure
1209 * Initializes required hardware-dependent bits needed for normal operation.
1211 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1215 /* Transmit Descriptor Control 0 */
1216 reg = er32(TXDCTL(0));
1218 ew32(TXDCTL(0), reg);
1220 /* Transmit Descriptor Control 1 */
1221 reg = er32(TXDCTL(1));
1223 ew32(TXDCTL(1), reg);
1225 /* Transmit Arbitration Control 0 */
1226 reg = er32(TARC(0));
1227 reg &= ~(0xF << 27); /* 30:27 */
1228 switch (hw->mac.type) {
1231 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1238 /* Transmit Arbitration Control 1 */
1239 reg = er32(TARC(1));
1240 switch (hw->mac.type) {
1243 reg &= ~((1 << 29) | (1 << 30));
1244 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1245 if (er32(TCTL) & E1000_TCTL_MULR)
1255 /* Device Control */
1256 switch (hw->mac.type) {
1268 /* Extended Device Control */
1269 switch (hw->mac.type) {
1273 reg = er32(CTRL_EXT);
1276 ew32(CTRL_EXT, reg);
1282 if (hw->mac.type == e1000_82571) {
1283 reg = er32(PBA_ECC);
1284 reg |= E1000_PBA_ECC_CORR_EN;
1288 * Workaround for hardware errata.
1289 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1292 if ((hw->mac.type == e1000_82571) ||
1293 (hw->mac.type == e1000_82572)) {
1294 reg = er32(CTRL_EXT);
1295 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1296 ew32(CTRL_EXT, reg);
1300 /* PCI-Ex Control Registers */
1301 switch (hw->mac.type) {
1309 * Workaround for hardware errata.
1310 * apply workaround for hardware errata documented in errata
1311 * docs Fixes issue where some error prone or unreliable PCIe
1312 * completions are occurring, particularly with ASPM enabled.
1313 * Without fix, issue can cause tx timeouts.
1325 * e1000_clear_vfta_82571 - Clear VLAN filter table
1326 * @hw: pointer to the HW structure
1328 * Clears the register array which contains the VLAN filter table by
1329 * setting all the values to 0.
1331 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1335 u32 vfta_offset = 0;
1336 u32 vfta_bit_in_reg = 0;
1338 switch (hw->mac.type) {
1342 if (hw->mng_cookie.vlan_id != 0) {
1344 * The VFTA is a 4096b bit-field, each identifying
1345 * a single VLAN ID. The following operations
1346 * determine which 32b entry (i.e. offset) into the
1347 * array we want to set the VLAN ID (i.e. bit) of
1348 * the manageability unit.
1350 vfta_offset = (hw->mng_cookie.vlan_id >>
1351 E1000_VFTA_ENTRY_SHIFT) &
1352 E1000_VFTA_ENTRY_MASK;
1353 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1354 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1360 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1362 * If the offset we want to clear is the same offset of the
1363 * manageability VLAN ID, then clear all bits except that of
1364 * the manageability unit.
1366 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1367 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1373 * e1000_check_mng_mode_82574 - Check manageability is enabled
1374 * @hw: pointer to the HW structure
1376 * Reads the NVM Initialization Control Word 2 and returns true
1377 * (>0) if any manageability is enabled, else false (0).
1379 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1383 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1384 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1388 * e1000_led_on_82574 - Turn LED on
1389 * @hw: pointer to the HW structure
1393 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1398 ctrl = hw->mac.ledctl_mode2;
1399 if (!(E1000_STATUS_LU & er32(STATUS))) {
1401 * If no link, then turn LED on by setting the invert bit
1402 * for each LED that's "on" (0x0E) in ledctl_mode2.
1404 for (i = 0; i < 4; i++)
1405 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1406 E1000_LEDCTL_MODE_LED_ON)
1407 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1415 * e1000_check_phy_82574 - check 82574 phy hung state
1416 * @hw: pointer to the HW structure
1418 * Returns whether phy is hung or not
1420 bool e1000_check_phy_82574(struct e1000_hw *hw)
1422 u16 status_1kbt = 0;
1423 u16 receive_errors = 0;
1424 bool phy_hung = false;
1428 * Read PHY Receive Error counter first, if its is max - all F's then
1429 * read the Base1000T status register If both are max then PHY is hung.
1431 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1435 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1436 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1439 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1440 E1000_IDLE_ERROR_COUNT_MASK)
1448 * e1000_setup_link_82571 - Setup flow control and link settings
1449 * @hw: pointer to the HW structure
1451 * Determines which flow control settings to use, then configures flow
1452 * control. Calls the appropriate media-specific link configuration
1453 * function. Assuming the adapter has a valid link partner, a valid link
1454 * should be established. Assumes the hardware has previously been reset
1455 * and the transmitter and receiver are not enabled.
1457 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1460 * 82573 does not have a word in the NVM to determine
1461 * the default flow control setting, so we explicitly
1464 switch (hw->mac.type) {
1468 if (hw->fc.requested_mode == e1000_fc_default)
1469 hw->fc.requested_mode = e1000_fc_full;
1475 return e1000e_setup_link(hw);
1479 * e1000_setup_copper_link_82571 - Configure copper link settings
1480 * @hw: pointer to the HW structure
1482 * Configures the link for auto-neg or forced speed and duplex. Then we check
1483 * for link, once link is established calls to configure collision distance
1484 * and flow control are called.
1486 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1492 ctrl |= E1000_CTRL_SLU;
1493 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1496 switch (hw->phy.type) {
1499 ret_val = e1000e_copper_link_setup_m88(hw);
1501 case e1000_phy_igp_2:
1502 ret_val = e1000e_copper_link_setup_igp(hw);
1505 return -E1000_ERR_PHY;
1512 ret_val = e1000e_setup_copper_link(hw);
1518 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1519 * @hw: pointer to the HW structure
1521 * Configures collision distance and flow control for fiber and serdes links.
1522 * Upon successful setup, poll for link.
1524 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1526 switch (hw->mac.type) {
1530 * If SerDes loopback mode is entered, there is no form
1531 * of reset to take the adapter out of that mode. So we
1532 * have to explicitly take the adapter out of loopback
1533 * mode. This prevents drivers from twiddling their thumbs
1534 * if another tool failed to take it out of loopback mode.
1536 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1542 return e1000e_setup_fiber_serdes_link(hw);
1546 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1547 * @hw: pointer to the HW structure
1549 * Reports the link state as up or down.
1551 * If autonegotiation is supported by the link partner, the link state is
1552 * determined by the result of autonegotiation. This is the most likely case.
1553 * If autonegotiation is not supported by the link partner, and the link
1554 * has a valid signal, force the link up.
1556 * The link state is represented internally here by 4 states:
1559 * 2) autoneg_progress
1560 * 3) autoneg_complete (the link successfully autonegotiated)
1561 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1564 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1566 struct e1000_mac_info *mac = &hw->mac;
1575 status = er32(STATUS);
1578 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1580 /* Receiver is synchronized with no invalid bits. */
1581 switch (mac->serdes_link_state) {
1582 case e1000_serdes_link_autoneg_complete:
1583 if (!(status & E1000_STATUS_LU)) {
1585 * We have lost link, retry autoneg before
1586 * reporting link failure
1588 mac->serdes_link_state =
1589 e1000_serdes_link_autoneg_progress;
1590 mac->serdes_has_link = false;
1591 e_dbg("AN_UP -> AN_PROG\n");
1593 mac->serdes_has_link = true;
1597 case e1000_serdes_link_forced_up:
1599 * If we are receiving /C/ ordered sets, re-enable
1600 * auto-negotiation in the TXCW register and disable
1601 * forced link in the Device Control register in an
1602 * attempt to auto-negotiate with our link partner.
1603 * If the partner code word is null, stop forcing
1604 * and restart auto negotiation.
1606 if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) {
1607 /* Enable autoneg, and unforce link up */
1608 ew32(TXCW, mac->txcw);
1609 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1610 mac->serdes_link_state =
1611 e1000_serdes_link_autoneg_progress;
1612 mac->serdes_has_link = false;
1613 e_dbg("FORCED_UP -> AN_PROG\n");
1615 mac->serdes_has_link = true;
1619 case e1000_serdes_link_autoneg_progress:
1620 if (rxcw & E1000_RXCW_C) {
1622 * We received /C/ ordered sets, meaning the
1623 * link partner has autonegotiated, and we can
1624 * trust the Link Up (LU) status bit.
1626 if (status & E1000_STATUS_LU) {
1627 mac->serdes_link_state =
1628 e1000_serdes_link_autoneg_complete;
1629 e_dbg("AN_PROG -> AN_UP\n");
1630 mac->serdes_has_link = true;
1632 /* Autoneg completed, but failed. */
1633 mac->serdes_link_state =
1634 e1000_serdes_link_down;
1635 e_dbg("AN_PROG -> DOWN\n");
1639 * The link partner did not autoneg.
1640 * Force link up and full duplex, and change
1643 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1644 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1647 /* Configure Flow Control after link up. */
1648 ret_val = e1000e_config_fc_after_link_up(hw);
1650 e_dbg("Error config flow control\n");
1653 mac->serdes_link_state =
1654 e1000_serdes_link_forced_up;
1655 mac->serdes_has_link = true;
1656 e_dbg("AN_PROG -> FORCED_UP\n");
1660 case e1000_serdes_link_down:
1663 * The link was down but the receiver has now gained
1664 * valid sync, so lets see if we can bring the link
1667 ew32(TXCW, mac->txcw);
1668 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1669 mac->serdes_link_state =
1670 e1000_serdes_link_autoneg_progress;
1671 mac->serdes_has_link = false;
1672 e_dbg("DOWN -> AN_PROG\n");
1676 if (!(rxcw & E1000_RXCW_SYNCH)) {
1677 mac->serdes_has_link = false;
1678 mac->serdes_link_state = e1000_serdes_link_down;
1679 e_dbg("ANYSTATE -> DOWN\n");
1682 * Check several times, if Sync and Config
1683 * both are consistently 1 then simply ignore
1684 * the Invalid bit and restart Autoneg
1686 for (i = 0; i < AN_RETRY_COUNT; i++) {
1689 if ((rxcw & E1000_RXCW_IV) &&
1690 !((rxcw & E1000_RXCW_SYNCH) &&
1691 (rxcw & E1000_RXCW_C))) {
1692 mac->serdes_has_link = false;
1693 mac->serdes_link_state =
1694 e1000_serdes_link_down;
1695 e_dbg("ANYSTATE -> DOWN\n");
1700 if (i == AN_RETRY_COUNT) {
1702 txcw |= E1000_TXCW_ANE;
1704 mac->serdes_link_state =
1705 e1000_serdes_link_autoneg_progress;
1706 mac->serdes_has_link = false;
1707 e_dbg("ANYSTATE -> AN_PROG\n");
1716 * e1000_valid_led_default_82571 - Verify a valid default LED config
1717 * @hw: pointer to the HW structure
1718 * @data: pointer to the NVM (EEPROM)
1720 * Read the EEPROM for the current default LED configuration. If the
1721 * LED configuration is not valid, set to a valid LED configuration.
1723 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1727 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1729 e_dbg("NVM Read Error\n");
1733 switch (hw->mac.type) {
1737 if (*data == ID_LED_RESERVED_F746)
1738 *data = ID_LED_DEFAULT_82573;
1741 if (*data == ID_LED_RESERVED_0000 ||
1742 *data == ID_LED_RESERVED_FFFF)
1743 *data = ID_LED_DEFAULT;
1751 * e1000e_get_laa_state_82571 - Get locally administered address state
1752 * @hw: pointer to the HW structure
1754 * Retrieve and return the current locally administered address state.
1756 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1758 if (hw->mac.type != e1000_82571)
1761 return hw->dev_spec.e82571.laa_is_present;
1765 * e1000e_set_laa_state_82571 - Set locally administered address state
1766 * @hw: pointer to the HW structure
1767 * @state: enable/disable locally administered address
1769 * Enable/Disable the current locally administered address state.
1771 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1773 if (hw->mac.type != e1000_82571)
1776 hw->dev_spec.e82571.laa_is_present = state;
1778 /* If workaround is activated... */
1781 * Hold a copy of the LAA in RAR[14] This is done so that
1782 * between the time RAR[0] gets clobbered and the time it
1783 * gets fixed, the actual LAA is in one of the RARs and no
1784 * incoming packets directed to this port are dropped.
1785 * Eventually the LAA will be in RAR[0] and RAR[14].
1787 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1791 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1792 * @hw: pointer to the HW structure
1794 * Verifies that the EEPROM has completed the update. After updating the
1795 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1796 * the checksum fix is not implemented, we need to set the bit and update
1797 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1798 * we need to return bad checksum.
1800 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1802 struct e1000_nvm_info *nvm = &hw->nvm;
1806 if (nvm->type != e1000_nvm_flash_hw)
1810 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1811 * 10h-12h. Checksum may need to be fixed.
1813 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1817 if (!(data & 0x10)) {
1819 * Read 0x23 and check bit 15. This bit is a 1
1820 * when the checksum has already been fixed. If
1821 * the checksum is still wrong and this bit is a
1822 * 1, we need to return bad checksum. Otherwise,
1823 * we need to set this bit to a 1 and update the
1826 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1830 if (!(data & 0x8000)) {
1832 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1835 ret_val = e1000e_update_nvm_checksum(hw);
1843 * e1000_read_mac_addr_82571 - Read device MAC address
1844 * @hw: pointer to the HW structure
1846 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1850 if (hw->mac.type == e1000_82571) {
1852 * If there's an alternate MAC address place it in RAR0
1853 * so that it will override the Si installed default perm
1856 ret_val = e1000_check_alt_mac_addr_generic(hw);
1861 ret_val = e1000_read_mac_addr_generic(hw);
1868 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1869 * @hw: pointer to the HW structure
1871 * In the case of a PHY power down to save power, or to turn off link during a
1872 * driver unload, or wake on lan is not enabled, remove the link.
1874 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1876 struct e1000_phy_info *phy = &hw->phy;
1877 struct e1000_mac_info *mac = &hw->mac;
1879 if (!(phy->ops.check_reset_block))
1882 /* If the management interface is not enabled, then power down */
1883 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1884 e1000_power_down_phy_copper(hw);
1888 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1889 * @hw: pointer to the HW structure
1891 * Clears the hardware counters by reading the counter registers.
1893 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1895 e1000e_clear_hw_cntrs_base(hw);
1933 static struct e1000_mac_operations e82571_mac_ops = {
1934 /* .check_mng_mode: mac type dependent */
1935 /* .check_for_link: media type dependent */
1936 .id_led_init = e1000e_id_led_init,
1937 .cleanup_led = e1000e_cleanup_led_generic,
1938 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1939 .get_bus_info = e1000e_get_bus_info_pcie,
1940 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1941 /* .get_link_up_info: media type dependent */
1942 /* .led_on: mac type dependent */
1943 .led_off = e1000e_led_off_generic,
1944 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1945 .write_vfta = e1000_write_vfta_generic,
1946 .clear_vfta = e1000_clear_vfta_82571,
1947 .reset_hw = e1000_reset_hw_82571,
1948 .init_hw = e1000_init_hw_82571,
1949 .setup_link = e1000_setup_link_82571,
1950 /* .setup_physical_interface: media type dependent */
1951 .setup_led = e1000e_setup_led_generic,
1952 .read_mac_addr = e1000_read_mac_addr_82571,
1955 static struct e1000_phy_operations e82_phy_ops_igp = {
1956 .acquire = e1000_get_hw_semaphore_82571,
1957 .check_polarity = e1000_check_polarity_igp,
1958 .check_reset_block = e1000e_check_reset_block_generic,
1960 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1961 .get_cfg_done = e1000_get_cfg_done_82571,
1962 .get_cable_length = e1000e_get_cable_length_igp_2,
1963 .get_info = e1000e_get_phy_info_igp,
1964 .read_reg = e1000e_read_phy_reg_igp,
1965 .release = e1000_put_hw_semaphore_82571,
1966 .reset = e1000e_phy_hw_reset_generic,
1967 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1968 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1969 .write_reg = e1000e_write_phy_reg_igp,
1970 .cfg_on_link_up = NULL,
1973 static struct e1000_phy_operations e82_phy_ops_m88 = {
1974 .acquire = e1000_get_hw_semaphore_82571,
1975 .check_polarity = e1000_check_polarity_m88,
1976 .check_reset_block = e1000e_check_reset_block_generic,
1977 .commit = e1000e_phy_sw_reset,
1978 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1979 .get_cfg_done = e1000e_get_cfg_done,
1980 .get_cable_length = e1000e_get_cable_length_m88,
1981 .get_info = e1000e_get_phy_info_m88,
1982 .read_reg = e1000e_read_phy_reg_m88,
1983 .release = e1000_put_hw_semaphore_82571,
1984 .reset = e1000e_phy_hw_reset_generic,
1985 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1986 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1987 .write_reg = e1000e_write_phy_reg_m88,
1988 .cfg_on_link_up = NULL,
1991 static struct e1000_phy_operations e82_phy_ops_bm = {
1992 .acquire = e1000_get_hw_semaphore_82571,
1993 .check_polarity = e1000_check_polarity_m88,
1994 .check_reset_block = e1000e_check_reset_block_generic,
1995 .commit = e1000e_phy_sw_reset,
1996 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1997 .get_cfg_done = e1000e_get_cfg_done,
1998 .get_cable_length = e1000e_get_cable_length_m88,
1999 .get_info = e1000e_get_phy_info_m88,
2000 .read_reg = e1000e_read_phy_reg_bm2,
2001 .release = e1000_put_hw_semaphore_82571,
2002 .reset = e1000e_phy_hw_reset_generic,
2003 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
2004 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
2005 .write_reg = e1000e_write_phy_reg_bm2,
2006 .cfg_on_link_up = NULL,
2009 static struct e1000_nvm_operations e82571_nvm_ops = {
2010 .acquire = e1000_acquire_nvm_82571,
2011 .read = e1000e_read_nvm_eerd,
2012 .release = e1000_release_nvm_82571,
2013 .update = e1000_update_nvm_checksum_82571,
2014 .valid_led_default = e1000_valid_led_default_82571,
2015 .validate = e1000_validate_nvm_checksum_82571,
2016 .write = e1000_write_nvm_82571,
2019 struct e1000_info e1000_82571_info = {
2021 .flags = FLAG_HAS_HW_VLAN_FILTER
2022 | FLAG_HAS_JUMBO_FRAMES
2024 | FLAG_APME_IN_CTRL3
2025 | FLAG_RX_CSUM_ENABLED
2026 | FLAG_HAS_CTRLEXT_ON_LOAD
2027 | FLAG_HAS_SMART_POWER_DOWN
2028 | FLAG_RESET_OVERWRITES_LAA /* errata */
2029 | FLAG_TARC_SPEED_MODE_BIT /* errata */
2030 | FLAG_APME_CHECK_PORT_B,
2031 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2034 .max_hw_frame_size = DEFAULT_JUMBO,
2035 .get_variants = e1000_get_variants_82571,
2036 .mac_ops = &e82571_mac_ops,
2037 .phy_ops = &e82_phy_ops_igp,
2038 .nvm_ops = &e82571_nvm_ops,
2041 struct e1000_info e1000_82572_info = {
2043 .flags = FLAG_HAS_HW_VLAN_FILTER
2044 | FLAG_HAS_JUMBO_FRAMES
2046 | FLAG_APME_IN_CTRL3
2047 | FLAG_RX_CSUM_ENABLED
2048 | FLAG_HAS_CTRLEXT_ON_LOAD
2049 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
2050 .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2053 .max_hw_frame_size = DEFAULT_JUMBO,
2054 .get_variants = e1000_get_variants_82571,
2055 .mac_ops = &e82571_mac_ops,
2056 .phy_ops = &e82_phy_ops_igp,
2057 .nvm_ops = &e82571_nvm_ops,
2060 struct e1000_info e1000_82573_info = {
2062 .flags = FLAG_HAS_HW_VLAN_FILTER
2064 | FLAG_APME_IN_CTRL3
2065 | FLAG_RX_CSUM_ENABLED
2066 | FLAG_HAS_SMART_POWER_DOWN
2068 | FLAG_HAS_SWSM_ON_LOAD,
2069 .flags2 = FLAG2_DISABLE_ASPM_L1,
2071 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2072 .get_variants = e1000_get_variants_82571,
2073 .mac_ops = &e82571_mac_ops,
2074 .phy_ops = &e82_phy_ops_m88,
2075 .nvm_ops = &e82571_nvm_ops,
2078 struct e1000_info e1000_82574_info = {
2080 .flags = FLAG_HAS_HW_VLAN_FILTER
2082 | FLAG_HAS_JUMBO_FRAMES
2084 | FLAG_APME_IN_CTRL3
2085 | FLAG_RX_CSUM_ENABLED
2086 | FLAG_HAS_SMART_POWER_DOWN
2088 | FLAG_HAS_CTRLEXT_ON_LOAD,
2089 .flags2 = FLAG2_CHECK_PHY_HANG,
2091 .max_hw_frame_size = DEFAULT_JUMBO,
2092 .get_variants = e1000_get_variants_82571,
2093 .mac_ops = &e82571_mac_ops,
2094 .phy_ops = &e82_phy_ops_bm,
2095 .nvm_ops = &e82571_nvm_ops,
2098 struct e1000_info e1000_82583_info = {
2100 .flags = FLAG_HAS_HW_VLAN_FILTER
2102 | FLAG_APME_IN_CTRL3
2103 | FLAG_RX_CSUM_ENABLED
2104 | FLAG_HAS_SMART_POWER_DOWN
2106 | FLAG_HAS_CTRLEXT_ON_LOAD,
2108 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
2109 .get_variants = e1000_get_variants_82571,
2110 .mac_ops = &e82571_mac_ops,
2111 .phy_ops = &e82_phy_ops_bm,
2112 .nvm_ops = &e82571_nvm_ops,