drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  * 82583V Gigabit Network Connection
  44  */
  45
  46 #include "e1000.h"
  47
  48 #define ID_LED_RESERVED_F746 0xF746
  49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  50                               (ID_LED_OFF1_ON2  <<  8) | \
  51                               (ID_LED_DEF1_DEF2 <<  4) | \
  52                               (ID_LED_DEF1_DEF2))
  53
  54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  55
  56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  57
  58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  63                                       u16 words, u16 *data);
  64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  73
  74 /**
  75  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  76  *  @hw: pointer to the HW structure
  77  **/
  78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  79 {
  80         struct e1000_phy_info *phy = &hw->phy;
  81         s32 ret_val;
  82
  83         if (hw->phy.media_type != e1000_media_type_copper) {
  84                 phy->type = e1000_phy_none;
  85                 return 0;
  86         }
  87
  88         phy->addr                        = 1;
  89         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  90         phy->reset_delay_us              = 100;
  91
  92         phy->ops.power_up                = e1000_power_up_phy_copper;
  93         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82571:
  97         case e1000_82572:
  98                 phy->type                = e1000_phy_igp_2;
  99                 break;
 100         case e1000_82573:
 101                 phy->type                = e1000_phy_m88;
 102                 break;
 103         case e1000_82574:
 104         case e1000_82583:
 105                 phy->type                = e1000_phy_bm;
 106                 break;
 107         default:
 108                 return -E1000_ERR_PHY;
 109                 break;
 110         }
 111
 112         /* This can only be done after all function pointers are setup. */
 113         ret_val = e1000_get_phy_id_82571(hw);
 114
 115         /* Verify phy id */
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 if (phy->id != IGP01E1000_I_PHY_ID)
 120                         return -E1000_ERR_PHY;
 121                 break;
 122         case e1000_82573:
 123                 if (phy->id != M88E1111_I_PHY_ID)
 124                         return -E1000_ERR_PHY;
 125                 break;
 126         case e1000_82574:
 127         case e1000_82583:
 128                 if (phy->id != BME1000_E_PHY_ID_R2)
 129                         return -E1000_ERR_PHY;
 130                 break;
 131         default:
 132                 return -E1000_ERR_PHY;
 133                 break;
 134         }
 135
 136         return 0;
 137 }
 138
 139 /**
 140  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 141  *  @hw: pointer to the HW structure
 142  **/
 143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 144 {
 145         struct e1000_nvm_info *nvm = &hw->nvm;
 146         u32 eecd = er32(EECD);
 147         u16 size;
 148
 149         nvm->opcode_bits = 8;
 150         nvm->delay_usec = 1;
 151         switch (nvm->override) {
 152         case e1000_nvm_override_spi_large:
 153                 nvm->page_size = 32;
 154                 nvm->address_bits = 16;
 155                 break;
 156         case e1000_nvm_override_spi_small:
 157                 nvm->page_size = 8;
 158                 nvm->address_bits = 8;
 159                 break;
 160         default:
 161                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 162                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 163                 break;
 164         }
 165
 166         switch (hw->mac.type) {
 167         case e1000_82573:
 168         case e1000_82574:
 169         case e1000_82583:
 170                 if (((eecd >> 15) & 0x3) == 0x3) {
 171                         nvm->type = e1000_nvm_flash_hw;
 172                         nvm->word_size = 2048;
 173                         /*
 174                          * Autonomous Flash update bit must be cleared due
 175                          * to Flash update issue.
 176                          */
 177                         eecd &= ~E1000_EECD_AUPDEN;
 178                         ew32(EECD, eecd);
 179                         break;
 180                 }
 181                 /* Fall Through */
 182         default:
 183                 nvm->type = e1000_nvm_eeprom_spi;
 184                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 185                                   E1000_EECD_SIZE_EX_SHIFT);
 186                 /*
 187                  * Added to a constant, "size" becomes the left-shift value
 188                  * for setting word_size.
 189                  */
 190                 size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192                 /* EEPROM access above 16k is unsupported */
 193                 if (size > 14)
 194                         size = 14;
 195                 nvm->word_size  = 1 << size;
 196                 break;
 197         }
 198
 199         return 0;
 200 }
 201
 202 /**
 203  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 204  *  @hw: pointer to the HW structure
 205  **/
 206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 207 {
 208         struct e1000_hw *hw = &adapter->hw;
 209         struct e1000_mac_info *mac = &hw->mac;
 210         struct e1000_mac_operations *func = &mac->ops;
 211         u32 swsm = 0;
 212         u32 swsm2 = 0;
 213         bool force_clear_smbi = false;
 214
 215         /* Set media type */
 216         switch (adapter->pdev->device) {
 217         case E1000_DEV_ID_82571EB_FIBER:
 218         case E1000_DEV_ID_82572EI_FIBER:
 219         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 220                 hw->phy.media_type = e1000_media_type_fiber;
 221                 break;
 222         case E1000_DEV_ID_82571EB_SERDES:
 223         case E1000_DEV_ID_82572EI_SERDES:
 224         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 225         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 226                 hw->phy.media_type = e1000_media_type_internal_serdes;
 227                 break;
 228         default:
 229                 hw->phy.media_type = e1000_media_type_copper;
 230                 break;
 231         }
 232
 233         /* Set mta register count */
 234         mac->mta_reg_count = 128;
 235         /* Set rar entry count */
 236         mac->rar_entry_count = E1000_RAR_ENTRIES;
 237         /* Set if manageability features are enabled. */
 238         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
 239                         ? true : false;
 240         /* Adaptive IFS supported */
 241         mac->adaptive_ifs = true;
 242
 243         /* check for link */
 244         switch (hw->phy.media_type) {
 245         case e1000_media_type_copper:
 246                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 247                 func->check_for_link = e1000e_check_for_copper_link;
 248                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 249                 break;
 250         case e1000_media_type_fiber:
 251                 func->setup_physical_interface =
 252                         e1000_setup_fiber_serdes_link_82571;
 253                 func->check_for_link = e1000e_check_for_fiber_link;
 254                 func->get_link_up_info =
 255                         e1000e_get_speed_and_duplex_fiber_serdes;
 256                 break;
 257         case e1000_media_type_internal_serdes:
 258                 func->setup_physical_interface =
 259                         e1000_setup_fiber_serdes_link_82571;
 260                 func->check_for_link = e1000_check_for_serdes_link_82571;
 261                 func->get_link_up_info =
 262                         e1000e_get_speed_and_duplex_fiber_serdes;
 263                 break;
 264         default:
 265                 return -E1000_ERR_CONFIG;
 266                 break;
 267         }
 268
 269         switch (hw->mac.type) {
 270         case e1000_82574:
 271         case e1000_82583:
 272                 func->check_mng_mode = e1000_check_mng_mode_82574;
 273                 func->led_on = e1000_led_on_82574;
 274                 break;
 275         default:
 276                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 277                 func->led_on = e1000e_led_on_generic;
 278                 break;
 279         }
 280
 281         /*
 282          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 283          * first NVM or PHY acess. This should be done for single-port
 284          * devices, and for one port only on dual-port devices so that
 285          * for those devices we can still use the SMBI lock to synchronize
 286          * inter-port accesses to the PHY & NVM.
 287          */
 288         switch (hw->mac.type) {
 289         case e1000_82571:
 290         case e1000_82572:
 291                 swsm2 = er32(SWSM2);
 292
 293                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 294                         /* Only do this for the first interface on this card */
 295                         ew32(SWSM2,
 296                             swsm2 | E1000_SWSM2_LOCK);
 297                         force_clear_smbi = true;
 298                 } else
 299                         force_clear_smbi = false;
 300                 break;
 301         default:
 302                 force_clear_smbi = true;
 303                 break;
 304         }
 305
 306         if (force_clear_smbi) {
 307                 /* Make sure SWSM.SMBI is clear */
 308                 swsm = er32(SWSM);
 309                 if (swsm & E1000_SWSM_SMBI) {
 310                         /* This bit should not be set on a first interface, and
 311                          * indicates that the bootagent or EFI code has
 312                          * improperly left this bit enabled
 313                          */
 314                         e_dbg("Please update your 82571 Bootagent\n");
 315                 }
 316                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 317         }
 318
 319         /*
 320          * Initialze device specific counter of SMBI acquisition
 321          * timeouts.
 322          */
 323          hw->dev_spec.e82571.smb_counter = 0;
 324
 325         return 0;
 326 }
 327
 328 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 329 {
 330         struct e1000_hw *hw = &adapter->hw;
 331         static int global_quad_port_a; /* global port a indication */
 332         struct pci_dev *pdev = adapter->pdev;
 333         u16 eeprom_data = 0;
 334         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 335         s32 rc;
 336
 337         rc = e1000_init_mac_params_82571(adapter);
 338         if (rc)
 339                 return rc;
 340
 341         rc = e1000_init_nvm_params_82571(hw);
 342         if (rc)
 343                 return rc;
 344
 345         rc = e1000_init_phy_params_82571(hw);
 346         if (rc)
 347                 return rc;
 348
 349         /* tag quad port adapters first, it's used below */
 350         switch (pdev->device) {
 351         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 352         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 353         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 354         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 355                 adapter->flags |= FLAG_IS_QUAD_PORT;
 356                 /* mark the first port */
 357                 if (global_quad_port_a == 0)
 358                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 359                 /* Reset for multiple quad port adapters */
 360                 global_quad_port_a++;
 361                 if (global_quad_port_a == 4)
 362                         global_quad_port_a = 0;
 363                 break;
 364         default:
 365                 break;
 366         }
 367
 368         switch (adapter->hw.mac.type) {
 369         case e1000_82571:
 370                 /* these dual ports don't have WoL on port B at all */
 371                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 372                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 373                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 374                     (is_port_b))
 375                         adapter->flags &= ~FLAG_HAS_WOL;
 376                 /* quad ports only support WoL on port A */
 377                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 378                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 379                         adapter->flags &= ~FLAG_HAS_WOL;
 380                 /* Does not support WoL on any port */
 381                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 382                         adapter->flags &= ~FLAG_HAS_WOL;
 383                 break;
 384
 385         case e1000_82573:
 386                 if (pdev->device == E1000_DEV_ID_82573L) {
 387                         if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
 388                                        &eeprom_data) < 0)
 389                                 break;
 390                         if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
 391                                 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 392                                 adapter->max_hw_frame_size = DEFAULT_JUMBO;
 393                         }
 394                 }
 395                 break;
 396         default:
 397                 break;
 398         }
 399
 400         return 0;
 401 }
 402
 403 /**
 404  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 405  *  @hw: pointer to the HW structure
 406  *
 407  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 408  *  revision in the hardware structure.
 409  **/
 410 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 411 {
 412         struct e1000_phy_info *phy = &hw->phy;
 413         s32 ret_val;
 414         u16 phy_id = 0;
 415
 416         switch (hw->mac.type) {
 417         case e1000_82571:
 418         case e1000_82572:
 419                 /*
 420                  * The 82571 firmware may still be configuring the PHY.
 421                  * In this case, we cannot access the PHY until the
 422                  * configuration is done.  So we explicitly set the
 423                  * PHY ID.
 424                  */
 425                 phy->id = IGP01E1000_I_PHY_ID;
 426                 break;
 427         case e1000_82573:
 428                 return e1000e_get_phy_id(hw);
 429                 break;
 430         case e1000_82574:
 431         case e1000_82583:
 432                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 433                 if (ret_val)
 434                         return ret_val;
 435
 436                 phy->id = (u32)(phy_id << 16);
 437                 udelay(20);
 438                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 439                 if (ret_val)
 440                         return ret_val;
 441
 442                 phy->id |= (u32)(phy_id);
 443                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 444                 break;
 445         default:
 446                 return -E1000_ERR_PHY;
 447                 break;
 448         }
 449
 450         return 0;
 451 }
 452
 453 /**
 454  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 455  *  @hw: pointer to the HW structure
 456  *
 457  *  Acquire the HW semaphore to access the PHY or NVM
 458  **/
 459 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 460 {
 461         u32 swsm;
 462         s32 sw_timeout = hw->nvm.word_size + 1;
 463         s32 fw_timeout = hw->nvm.word_size + 1;
 464         s32 i = 0;
 465
 466         /*
 467          * If we have timedout 3 times on trying to acquire
 468          * the inter-port SMBI semaphore, there is old code
 469          * operating on the other port, and it is not
 470          * releasing SMBI. Modify the number of times that
 471          * we try for the semaphore to interwork with this
 472          * older code.
 473          */
 474         if (hw->dev_spec.e82571.smb_counter > 2)
 475                 sw_timeout = 1;
 476
 477         /* Get the SW semaphore */
 478         while (i < sw_timeout) {
 479                 swsm = er32(SWSM);
 480                 if (!(swsm & E1000_SWSM_SMBI))
 481                         break;
 482
 483                 udelay(50);
 484                 i++;
 485         }
 486
 487         if (i == sw_timeout) {
 488                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 489                 hw->dev_spec.e82571.smb_counter++;
 490         }
 491         /* Get the FW semaphore. */
 492         for (i = 0; i < fw_timeout; i++) {
 493                 swsm = er32(SWSM);
 494                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 495
 496                 /* Semaphore acquired if bit latched */
 497                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 498                         break;
 499
 500                 udelay(50);
 501         }
 502
 503         if (i == fw_timeout) {
 504                 /* Release semaphores */
 505                 e1000_put_hw_semaphore_82571(hw);
 506                 e_dbg("Driver can't access the NVM\n");
 507                 return -E1000_ERR_NVM;
 508         }
 509
 510         return 0;
 511 }
 512
 513 /**
 514  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 515  *  @hw: pointer to the HW structure
 516  *
 517  *  Release hardware semaphore used to access the PHY or NVM
 518  **/
 519 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 520 {
 521         u32 swsm;
 522
 523         swsm = er32(SWSM);
 524         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 525         ew32(SWSM, swsm);
 526 }
 527
 528 /**
 529  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 530  *  @hw: pointer to the HW structure
 531  *
 532  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 533  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 534  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 535  *  hardware semaphore.
 536  **/
 537 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 538 {
 539         s32 ret_val;
 540
 541         ret_val = e1000_get_hw_semaphore_82571(hw);
 542         if (ret_val)
 543                 return ret_val;
 544
 545         switch (hw->mac.type) {
 546         case e1000_82573:
 547         case e1000_82574:
 548         case e1000_82583:
 549                 break;
 550         default:
 551                 ret_val = e1000e_acquire_nvm(hw);
 552                 break;
 553         }
 554
 555         if (ret_val)
 556                 e1000_put_hw_semaphore_82571(hw);
 557
 558         return ret_val;
 559 }
 560
 561 /**
 562  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 566  **/
 567 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 568 {
 569         e1000e_release_nvm(hw);
 570         e1000_put_hw_semaphore_82571(hw);
 571 }
 572
 573 /**
 574  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 575  *  @hw: pointer to the HW structure
 576  *  @offset: offset within the EEPROM to be written to
 577  *  @words: number of words to write
 578  *  @data: 16 bit word(s) to be written to the EEPROM
 579  *
 580  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 581  *
 582  *  If e1000e_update_nvm_checksum is not called after this function, the
 583  *  EEPROM will most likely contain an invalid checksum.
 584  **/
 585 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 586                                  u16 *data)
 587 {
 588         s32 ret_val;
 589
 590         switch (hw->mac.type) {
 591         case e1000_82573:
 592         case e1000_82574:
 593         case e1000_82583:
 594                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 595                 break;
 596         case e1000_82571:
 597         case e1000_82572:
 598                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 599                 break;
 600         default:
 601                 ret_val = -E1000_ERR_NVM;
 602                 break;
 603         }
 604
 605         return ret_val;
 606 }
 607
 608 /**
 609  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 610  *  @hw: pointer to the HW structure
 611  *
 612  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 613  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 614  *  value to the EEPROM.
 615  **/
 616 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 617 {
 618         u32 eecd;
 619         s32 ret_val;
 620         u16 i;
 621
 622         ret_val = e1000e_update_nvm_checksum_generic(hw);
 623         if (ret_val)
 624                 return ret_val;
 625
 626         /*
 627          * If our nvm is an EEPROM, then we're done
 628          * otherwise, commit the checksum to the flash NVM.
 629          */
 630         if (hw->nvm.type != e1000_nvm_flash_hw)
 631                 return ret_val;
 632
 633         /* Check for pending operations. */
 634         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 635                 msleep(1);
 636                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 637                         break;
 638         }
 639
 640         if (i == E1000_FLASH_UPDATES)
 641                 return -E1000_ERR_NVM;
 642
 643         /* Reset the firmware if using STM opcode. */
 644         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 645                 /*
 646                  * The enabling of and the actual reset must be done
 647                  * in two write cycles.
 648                  */
 649                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 650                 e1e_flush();
 651                 ew32(HICR, E1000_HICR_FW_RESET);
 652         }
 653
 654         /* Commit the write to flash */
 655         eecd = er32(EECD) | E1000_EECD_FLUPD;
 656         ew32(EECD, eecd);
 657
 658         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 659                 msleep(1);
 660                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 661                         break;
 662         }
 663
 664         if (i == E1000_FLASH_UPDATES)
 665                 return -E1000_ERR_NVM;
 666
 667         return 0;
 668 }
 669
 670 /**
 671  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 672  *  @hw: pointer to the HW structure
 673  *
 674  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 675  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 676  **/
 677 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 678 {
 679         if (hw->nvm.type == e1000_nvm_flash_hw)
 680                 e1000_fix_nvm_checksum_82571(hw);
 681
 682         return e1000e_validate_nvm_checksum_generic(hw);
 683 }
 684
 685 /**
 686  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 687  *  @hw: pointer to the HW structure
 688  *  @offset: offset within the EEPROM to be written to
 689  *  @words: number of words to write
 690  *  @data: 16 bit word(s) to be written to the EEPROM
 691  *
 692  *  After checking for invalid values, poll the EEPROM to ensure the previous
 693  *  command has completed before trying to write the next word.  After write
 694  *  poll for completion.
 695  *
 696  *  If e1000e_update_nvm_checksum is not called after this function, the
 697  *  EEPROM will most likely contain an invalid checksum.
 698  **/
 699 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 700                                       u16 words, u16 *data)
 701 {
 702         struct e1000_nvm_info *nvm = &hw->nvm;
 703         u32 i, eewr = 0;
 704         s32 ret_val = 0;
 705
 706         /*
 707          * A check for invalid values:  offset too large, too many words,
 708          * and not enough words.
 709          */
 710         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 711             (words == 0)) {
 712                 e_dbg("nvm parameter(s) out of bounds\n");
 713                 return -E1000_ERR_NVM;
 714         }
 715
 716         for (i = 0; i < words; i++) {
 717                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 718                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 719                        E1000_NVM_RW_REG_START;
 720
 721                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 722                 if (ret_val)
 723                         break;
 724
 725                 ew32(EEWR, eewr);
 726
 727                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 728                 if (ret_val)
 729                         break;
 730         }
 731
 732         return ret_val;
 733 }
 734
 735 /**
 736  *  e1000_get_cfg_done_82571 - Poll for configuration done
 737  *  @hw: pointer to the HW structure
 738  *
 739  *  Reads the management control register for the config done bit to be set.
 740  **/
 741 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 742 {
 743         s32 timeout = PHY_CFG_TIMEOUT;
 744
 745         while (timeout) {
 746                 if (er32(EEMNGCTL) &
 747                     E1000_NVM_CFG_DONE_PORT_0)
 748                         break;
 749                 msleep(1);
 750                 timeout--;
 751         }
 752         if (!timeout) {
 753                 e_dbg("MNG configuration cycle has not completed.\n");
 754                 return -E1000_ERR_RESET;
 755         }
 756
 757         return 0;
 758 }
 759
 760 /**
 761  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 762  *  @hw: pointer to the HW structure
 763  *  @active: true to enable LPLU, false to disable
 764  *
 765  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 766  *  this function also disables smart speed and vice versa.  LPLU will not be
 767  *  activated unless the device autonegotiation advertisement meets standards
 768  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 769  *  pointer entry point only called by PHY setup routines.
 770  **/
 771 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 772 {
 773         struct e1000_phy_info *phy = &hw->phy;
 774         s32 ret_val;
 775         u16 data;
 776
 777         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 778         if (ret_val)
 779                 return ret_val;
 780
 781         if (active) {
 782                 data |= IGP02E1000_PM_D0_LPLU;
 783                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 784                 if (ret_val)
 785                         return ret_val;
 786
 787                 /* When LPLU is enabled, we should disable SmartSpeed */
 788                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 789                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 790                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 791                 if (ret_val)
 792                         return ret_val;
 793         } else {
 794                 data &= ~IGP02E1000_PM_D0_LPLU;
 795                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 796                 /*
 797                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 798                  * during Dx states where the power conservation is most
 799                  * important.  During driver activity we should enable
 800                  * SmartSpeed, so performance is maintained.
 801                  */
 802                 if (phy->smart_speed == e1000_smart_speed_on) {
 803                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 804                                            &data);
 805                         if (ret_val)
 806                                 return ret_val;
 807
 808                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 809                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 810                                            data);
 811                         if (ret_val)
 812                                 return ret_val;
 813                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 814                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 815                                            &data);
 816                         if (ret_val)
 817                                 return ret_val;
 818
 819                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 820                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 821                                            data);
 822                         if (ret_val)
 823                                 return ret_val;
 824                 }
 825         }
 826
 827         return 0;
 828 }
 829
 830 /**
 831  *  e1000_reset_hw_82571 - Reset hardware
 832  *  @hw: pointer to the HW structure
 833  *
 834  *  This resets the hardware into a known state.
 835  **/
 836 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 837 {
 838         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
 839         s32 ret_val;
 840         u16 i = 0;
 841
 842         /*
 843          * Prevent the PCI-E bus from sticking if there is no TLP connection
 844          * on the last TLP read/write transaction when MAC is reset.
 845          */
 846         ret_val = e1000e_disable_pcie_master(hw);
 847         if (ret_val)
 848                 e_dbg("PCI-E Master disable polling has failed.\n");
 849
 850         e_dbg("Masking off all interrupts\n");
 851         ew32(IMC, 0xffffffff);
 852
 853         ew32(RCTL, 0);
 854         ew32(TCTL, E1000_TCTL_PSP);
 855         e1e_flush();
 856
 857         msleep(10);
 858
 859         /*
 860          * Must acquire the MDIO ownership before MAC reset.
 861          * Ownership defaults to firmware after a reset.
 862          */
 863         switch (hw->mac.type) {
 864         case e1000_82573:
 865         case e1000_82574:
 866         case e1000_82583:
 867                 extcnf_ctrl = er32(EXTCNF_CTRL);
 868                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 869
 870                 do {
 871                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 872                         extcnf_ctrl = er32(EXTCNF_CTRL);
 873
 874                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 875                                 break;
 876
 877                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 878
 879                         msleep(2);
 880                         i++;
 881                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 882                 break;
 883         default:
 884                 break;
 885         }
 886
 887         ctrl = er32(CTRL);
 888
 889         e_dbg("Issuing a global reset to MAC\n");
 890         ew32(CTRL, ctrl | E1000_CTRL_RST);
 891
 892         if (hw->nvm.type == e1000_nvm_flash_hw) {
 893                 udelay(10);
 894                 ctrl_ext = er32(CTRL_EXT);
 895                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 896                 ew32(CTRL_EXT, ctrl_ext);
 897                 e1e_flush();
 898         }
 899
 900         ret_val = e1000e_get_auto_rd_done(hw);
 901         if (ret_val)
 902                 /* We don't want to continue accessing MAC registers. */
 903                 return ret_val;
 904
 905         /*
 906          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 907          * Need to wait for Phy configuration completion before accessing
 908          * NVM and Phy.
 909          */
 910
 911         switch (hw->mac.type) {
 912         case e1000_82573:
 913         case e1000_82574:
 914         case e1000_82583:
 915                 msleep(25);
 916                 break;
 917         default:
 918                 break;
 919         }
 920
 921         /* Clear any pending interrupt events. */
 922         ew32(IMC, 0xffffffff);
 923         icr = er32(ICR);
 924
 925         if (hw->mac.type == e1000_82571 &&
 926                 hw->dev_spec.e82571.alt_mac_addr_is_present)
 927                         e1000e_set_laa_state_82571(hw, true);
 928
 929         /* Reinitialize the 82571 serdes link state machine */
 930         if (hw->phy.media_type == e1000_media_type_internal_serdes)
 931                 hw->mac.serdes_link_state = e1000_serdes_link_down;
 932
 933         return 0;
 934 }
 935
 936 /**
 937  *  e1000_init_hw_82571 - Initialize hardware
 938  *  @hw: pointer to the HW structure
 939  *
 940  *  This inits the hardware readying it for operation.
 941  **/
 942 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 943 {
 944         struct e1000_mac_info *mac = &hw->mac;
 945         u32 reg_data;
 946         s32 ret_val;
 947         u16 i, rar_count = mac->rar_entry_count;
 948
 949         e1000_initialize_hw_bits_82571(hw);
 950
 951         /* Initialize identification LED */
 952         ret_val = e1000e_id_led_init(hw);
 953         if (ret_val)
 954                 e_dbg("Error initializing identification LED\n");
 955                 /* This is not fatal and we should not stop init due to this */
 956
 957         /* Disabling VLAN filtering */
 958         e_dbg("Initializing the IEEE VLAN\n");
 959         mac->ops.clear_vfta(hw);
 960
 961         /* Setup the receive address. */
 962         /*
 963          * If, however, a locally administered address was assigned to the
 964          * 82571, we must reserve a RAR for it to work around an issue where
 965          * resetting one port will reload the MAC on the other port.
 966          */
 967         if (e1000e_get_laa_state_82571(hw))
 968                 rar_count--;
 969         e1000e_init_rx_addrs(hw, rar_count);
 970
 971         /* Zero out the Multicast HASH table */
 972         e_dbg("Zeroing the MTA\n");
 973         for (i = 0; i < mac->mta_reg_count; i++)
 974                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 975
 976         /* Setup link and flow control */
 977         ret_val = e1000_setup_link_82571(hw);
 978
 979         /* Set the transmit descriptor write-back policy */
 980         reg_data = er32(TXDCTL(0));
 981         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 982                    E1000_TXDCTL_FULL_TX_DESC_WB |
 983                    E1000_TXDCTL_COUNT_DESC;
 984         ew32(TXDCTL(0), reg_data);
 985
 986         /* ...for both queues. */
 987         switch (mac->type) {
 988         case e1000_82573:
 989         case e1000_82574:
 990         case e1000_82583:
 991                 e1000e_enable_tx_pkt_filtering(hw);
 992                 reg_data = er32(GCR);
 993                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 994                 ew32(GCR, reg_data);
 995                 break;
 996         default:
 997                 reg_data = er32(TXDCTL(1));
 998                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 999                            E1000_TXDCTL_FULL_TX_DESC_WB |
1000                            E1000_TXDCTL_COUNT_DESC;
1001                 ew32(TXDCTL(1), reg_data);
1002                 break;
1003         }
1004
1005         /*
1006          * Clear all of the statistics registers (clear on read).  It is
1007          * important that we do this after we have tried to establish link
1008          * because the symbol error count will increment wildly if there
1009          * is no link.
1010          */
1011         e1000_clear_hw_cntrs_82571(hw);
1012
1013         return ret_val;
1014 }
1015
1016 /**
1017  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1018  *  @hw: pointer to the HW structure
1019  *
1020  *  Initializes required hardware-dependent bits needed for normal operation.
1021  **/
1022 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1023 {
1024         u32 reg;
1025
1026         /* Transmit Descriptor Control 0 */
1027         reg = er32(TXDCTL(0));
1028         reg |= (1 << 22);
1029         ew32(TXDCTL(0), reg);
1030
1031         /* Transmit Descriptor Control 1 */
1032         reg = er32(TXDCTL(1));
1033         reg |= (1 << 22);
1034         ew32(TXDCTL(1), reg);
1035
1036         /* Transmit Arbitration Control 0 */
1037         reg = er32(TARC(0));
1038         reg &= ~(0xF << 27); /* 30:27 */
1039         switch (hw->mac.type) {
1040         case e1000_82571:
1041         case e1000_82572:
1042                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1043                 break;
1044         default:
1045                 break;
1046         }
1047         ew32(TARC(0), reg);
1048
1049         /* Transmit Arbitration Control 1 */
1050         reg = er32(TARC(1));
1051         switch (hw->mac.type) {
1052         case e1000_82571:
1053         case e1000_82572:
1054                 reg &= ~((1 << 29) | (1 << 30));
1055                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1056                 if (er32(TCTL) & E1000_TCTL_MULR)
1057                         reg &= ~(1 << 28);
1058                 else
1059                         reg |= (1 << 28);
1060                 ew32(TARC(1), reg);
1061                 break;
1062         default:
1063                 break;
1064         }
1065
1066         /* Device Control */
1067         switch (hw->mac.type) {
1068         case e1000_82573:
1069         case e1000_82574:
1070         case e1000_82583:
1071                 reg = er32(CTRL);
1072                 reg &= ~(1 << 29);
1073                 ew32(CTRL, reg);
1074                 break;
1075         default:
1076                 break;
1077         }
1078
1079         /* Extended Device Control */
1080         switch (hw->mac.type) {
1081         case e1000_82573:
1082         case e1000_82574:
1083         case e1000_82583:
1084                 reg = er32(CTRL_EXT);
1085                 reg &= ~(1 << 23);
1086                 reg |= (1 << 22);
1087                 ew32(CTRL_EXT, reg);
1088                 break;
1089         default:
1090                 break;
1091         }
1092
1093         if (hw->mac.type == e1000_82571) {
1094                 reg = er32(PBA_ECC);
1095                 reg |= E1000_PBA_ECC_CORR_EN;
1096                 ew32(PBA_ECC, reg);
1097         }
1098         /*
1099          * Workaround for hardware errata.
1100          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1101          */
1102
1103         if ((hw->mac.type == e1000_82571) ||
1104            (hw->mac.type == e1000_82572)) {
1105                 reg = er32(CTRL_EXT);
1106                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1107                 ew32(CTRL_EXT, reg);
1108         }
1109
1110
1111         /* PCI-Ex Control Registers */
1112         switch (hw->mac.type) {
1113         case e1000_82574:
1114         case e1000_82583:
1115                 reg = er32(GCR);
1116                 reg |= (1 << 22);
1117                 ew32(GCR, reg);
1118
1119                 /*
1120                  * Workaround for hardware errata.
1121                  * apply workaround for hardware errata documented in errata
1122                  * docs Fixes issue where some error prone or unreliable PCIe
1123                  * completions are occurring, particularly with ASPM enabled.
1124                  * Without fix, issue can cause tx timeouts.
1125                  */
1126                 reg = er32(GCR2);
1127                 reg |= 1;
1128                 ew32(GCR2, reg);
1129                 break;
1130         default:
1131                 break;
1132         }
1133
1134         return;
1135 }
1136
1137 /**
1138  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1139  *  @hw: pointer to the HW structure
1140  *
1141  *  Clears the register array which contains the VLAN filter table by
1142  *  setting all the values to 0.
1143  **/
1144 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1145 {
1146         u32 offset;
1147         u32 vfta_value = 0;
1148         u32 vfta_offset = 0;
1149         u32 vfta_bit_in_reg = 0;
1150
1151         switch (hw->mac.type) {
1152         case e1000_82573:
1153         case e1000_82574:
1154         case e1000_82583:
1155                 if (hw->mng_cookie.vlan_id != 0) {
1156                         /*
1157                          * The VFTA is a 4096b bit-field, each identifying
1158                          * a single VLAN ID.  The following operations
1159                          * determine which 32b entry (i.e. offset) into the
1160                          * array we want to set the VLAN ID (i.e. bit) of
1161                          * the manageability unit.
1162                          */
1163                         vfta_offset = (hw->mng_cookie.vlan_id >>
1164                                        E1000_VFTA_ENTRY_SHIFT) &
1165                                       E1000_VFTA_ENTRY_MASK;
1166                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1167                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1168                 }
1169                 break;
1170         default:
1171                 break;
1172         }
1173         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1174                 /*
1175                  * If the offset we want to clear is the same offset of the
1176                  * manageability VLAN ID, then clear all bits except that of
1177                  * the manageability unit.
1178                  */
1179                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1180                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1181                 e1e_flush();
1182         }
1183 }
1184
1185 /**
1186  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1187  *  @hw: pointer to the HW structure
1188  *
1189  *  Reads the NVM Initialization Control Word 2 and returns true
1190  *  (>0) if any manageability is enabled, else false (0).
1191  **/
1192 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1193 {
1194         u16 data;
1195
1196         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1197         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1198 }
1199
1200 /**
1201  *  e1000_led_on_82574 - Turn LED on
1202  *  @hw: pointer to the HW structure
1203  *
1204  *  Turn LED on.
1205  **/
1206 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1207 {
1208         u32 ctrl;
1209         u32 i;
1210
1211         ctrl = hw->mac.ledctl_mode2;
1212         if (!(E1000_STATUS_LU & er32(STATUS))) {
1213                 /*
1214                  * If no link, then turn LED on by setting the invert bit
1215                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1216                  */
1217                 for (i = 0; i < 4; i++)
1218                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1219                             E1000_LEDCTL_MODE_LED_ON)
1220                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1221         }
1222         ew32(LEDCTL, ctrl);
1223
1224         return 0;
1225 }
1226
1227 /**
1228  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1229  *  @hw: pointer to the HW structure
1230  *  @mc_addr_list: array of multicast addresses to program
1231  *  @mc_addr_count: number of multicast addresses to program
1232  *  @rar_used_count: the first RAR register free to program
1233  *  @rar_count: total number of supported Receive Address Registers
1234  *
1235  *  Updates the Receive Address Registers and Multicast Table Array.
1236  *  The caller must have a packed mc_addr_list of multicast addresses.
1237  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1238  *  unless there are workarounds that change this.
1239  **/
1240 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1241                                             u8 *mc_addr_list,
1242                                             u32 mc_addr_count,
1243                                             u32 rar_used_count,
1244                                             u32 rar_count)
1245 {
1246         if (e1000e_get_laa_state_82571(hw))
1247                 rar_count--;
1248
1249         e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1250                                            rar_used_count, rar_count);
1251 }
1252
1253 /**
1254  *  e1000_setup_link_82571 - Setup flow control and link settings
1255  *  @hw: pointer to the HW structure
1256  *
1257  *  Determines which flow control settings to use, then configures flow
1258  *  control.  Calls the appropriate media-specific link configuration
1259  *  function.  Assuming the adapter has a valid link partner, a valid link
1260  *  should be established.  Assumes the hardware has previously been reset
1261  *  and the transmitter and receiver are not enabled.
1262  **/
1263 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1264 {
1265         /*
1266          * 82573 does not have a word in the NVM to determine
1267          * the default flow control setting, so we explicitly
1268          * set it to full.
1269          */
1270         switch (hw->mac.type) {
1271         case e1000_82573:
1272         case e1000_82574:
1273         case e1000_82583:
1274                 if (hw->fc.requested_mode == e1000_fc_default)
1275                         hw->fc.requested_mode = e1000_fc_full;
1276                 break;
1277         default:
1278                 break;
1279         }
1280
1281         return e1000e_setup_link(hw);
1282 }
1283
1284 /**
1285  *  e1000_setup_copper_link_82571 - Configure copper link settings
1286  *  @hw: pointer to the HW structure
1287  *
1288  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1289  *  for link, once link is established calls to configure collision distance
1290  *  and flow control are called.
1291  **/
1292 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1293 {
1294         u32 ctrl;
1295         s32 ret_val;
1296
1297         ctrl = er32(CTRL);
1298         ctrl |= E1000_CTRL_SLU;
1299         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1300         ew32(CTRL, ctrl);
1301
1302         switch (hw->phy.type) {
1303         case e1000_phy_m88:
1304         case e1000_phy_bm:
1305                 ret_val = e1000e_copper_link_setup_m88(hw);
1306                 break;
1307         case e1000_phy_igp_2:
1308                 ret_val = e1000e_copper_link_setup_igp(hw);
1309                 break;
1310         default:
1311                 return -E1000_ERR_PHY;
1312                 break;
1313         }
1314
1315         if (ret_val)
1316                 return ret_val;
1317
1318         ret_val = e1000e_setup_copper_link(hw);
1319
1320         return ret_val;
1321 }
1322
1323 /**
1324  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1325  *  @hw: pointer to the HW structure
1326  *
1327  *  Configures collision distance and flow control for fiber and serdes links.
1328  *  Upon successful setup, poll for link.
1329  **/
1330 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1331 {
1332         switch (hw->mac.type) {
1333         case e1000_82571:
1334         case e1000_82572:
1335                 /*
1336                  * If SerDes loopback mode is entered, there is no form
1337                  * of reset to take the adapter out of that mode.  So we
1338                  * have to explicitly take the adapter out of loopback
1339                  * mode.  This prevents drivers from twiddling their thumbs
1340                  * if another tool failed to take it out of loopback mode.
1341                  */
1342                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1343                 break;
1344         default:
1345                 break;
1346         }
1347
1348         return e1000e_setup_fiber_serdes_link(hw);
1349 }
1350
1351 /**
1352  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1353  *  @hw: pointer to the HW structure
1354  *
1355  *  Reports the link state as up or down.
1356  *
1357  *  If autonegotiation is supported by the link partner, the link state is
1358  *  determined by the result of autonegotiation. This is the most likely case.
1359  *  If autonegotiation is not supported by the link partner, and the link
1360  *  has a valid signal, force the link up.
1361  *
1362  *  The link state is represented internally here by 4 states:
1363  *
1364  *  1) down
1365  *  2) autoneg_progress
1366  *  3) autoneg_complete (the link successfully autonegotiated)
1367  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1368  *
1369  **/
1370 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1371 {
1372         struct e1000_mac_info *mac = &hw->mac;
1373         u32 rxcw;
1374         u32 ctrl;
1375         u32 status;
1376         s32 ret_val = 0;
1377
1378         ctrl = er32(CTRL);
1379         status = er32(STATUS);
1380         rxcw = er32(RXCW);
1381
1382         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1383
1384                 /* Receiver is synchronized with no invalid bits.  */
1385                 switch (mac->serdes_link_state) {
1386                 case e1000_serdes_link_autoneg_complete:
1387                         if (!(status & E1000_STATUS_LU)) {
1388                                 /*
1389                                  * We have lost link, retry autoneg before
1390                                  * reporting link failure
1391                                  */
1392                                 mac->serdes_link_state =
1393                                     e1000_serdes_link_autoneg_progress;
1394                                 mac->serdes_has_link = false;
1395                                 e_dbg("AN_UP     -> AN_PROG\n");
1396                         }
1397                 break;
1398
1399                 case e1000_serdes_link_forced_up:
1400                         /*
1401                          * If we are receiving /C/ ordered sets, re-enable
1402                          * auto-negotiation in the TXCW register and disable
1403                          * forced link in the Device Control register in an
1404                          * attempt to auto-negotiate with our link partner.
1405                          */
1406                         if (rxcw & E1000_RXCW_C) {
1407                                 /* Enable autoneg, and unforce link up */
1408                                 ew32(TXCW, mac->txcw);
1409                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1410                                 mac->serdes_link_state =
1411                                     e1000_serdes_link_autoneg_progress;
1412                                 mac->serdes_has_link = false;
1413                                 e_dbg("FORCED_UP -> AN_PROG\n");
1414                         }
1415                         break;
1416
1417                 case e1000_serdes_link_autoneg_progress:
1418                         if (rxcw & E1000_RXCW_C) {
1419                                 /*
1420                                  * We received /C/ ordered sets, meaning the
1421                                  * link partner has autonegotiated, and we can
1422                                  * trust the Link Up (LU) status bit.
1423                                  */
1424                                 if (status & E1000_STATUS_LU) {
1425                                         mac->serdes_link_state =
1426                                             e1000_serdes_link_autoneg_complete;
1427                                         e_dbg("AN_PROG   -> AN_UP\n");
1428                                         mac->serdes_has_link = true;
1429                                 } else {
1430                                         /* Autoneg completed, but failed. */
1431                                         mac->serdes_link_state =
1432                                             e1000_serdes_link_down;
1433                                         e_dbg("AN_PROG   -> DOWN\n");
1434                                 }
1435                         } else {
1436                                 /*
1437                                  * The link partner did not autoneg.
1438                                  * Force link up and full duplex, and change
1439                                  * state to forced.
1440                                  */
1441                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1442                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1443                                 ew32(CTRL, ctrl);
1444
1445                                 /* Configure Flow Control after link up. */
1446                                 ret_val = e1000e_config_fc_after_link_up(hw);
1447                                 if (ret_val) {
1448                                         e_dbg("Error config flow control\n");
1449                                         break;
1450                                 }
1451                                 mac->serdes_link_state =
1452                                     e1000_serdes_link_forced_up;
1453                                 mac->serdes_has_link = true;
1454                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1455                         }
1456                         break;
1457
1458                 case e1000_serdes_link_down:
1459                 default:
1460                         /*
1461                          * The link was down but the receiver has now gained
1462                          * valid sync, so lets see if we can bring the link
1463                          * up.
1464                          */
1465                         ew32(TXCW, mac->txcw);
1466                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1467                         mac->serdes_link_state =
1468                             e1000_serdes_link_autoneg_progress;
1469                         e_dbg("DOWN      -> AN_PROG\n");
1470                         break;
1471                 }
1472         } else {
1473                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1474                         mac->serdes_has_link = false;
1475                         mac->serdes_link_state = e1000_serdes_link_down;
1476                         e_dbg("ANYSTATE  -> DOWN\n");
1477                 } else {
1478                         /*
1479                          * We have sync, and can tolerate one invalid (IV)
1480                          * codeword before declaring link down, so reread
1481                          * to look again.
1482                          */
1483                         udelay(10);
1484                         rxcw = er32(RXCW);
1485                         if (rxcw & E1000_RXCW_IV) {
1486                                 mac->serdes_link_state = e1000_serdes_link_down;
1487                                 mac->serdes_has_link = false;
1488                                 e_dbg("ANYSTATE  -> DOWN\n");
1489                         }
1490                 }
1491         }
1492
1493         return ret_val;
1494 }
1495
1496 /**
1497  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1498  *  @hw: pointer to the HW structure
1499  *  @data: pointer to the NVM (EEPROM)
1500  *
1501  *  Read the EEPROM for the current default LED configuration.  If the
1502  *  LED configuration is not valid, set to a valid LED configuration.
1503  **/
1504 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1505 {
1506         s32 ret_val;
1507
1508         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1509         if (ret_val) {
1510                 e_dbg("NVM Read Error\n");
1511                 return ret_val;
1512         }
1513
1514         switch (hw->mac.type) {
1515         case e1000_82573:
1516         case e1000_82574:
1517         case e1000_82583:
1518                 if (*data == ID_LED_RESERVED_F746)
1519                         *data = ID_LED_DEFAULT_82573;
1520                 break;
1521         default:
1522                 if (*data == ID_LED_RESERVED_0000 ||
1523                     *data == ID_LED_RESERVED_FFFF)
1524                         *data = ID_LED_DEFAULT;
1525                 break;
1526         }
1527
1528         return 0;
1529 }
1530
1531 /**
1532  *  e1000e_get_laa_state_82571 - Get locally administered address state
1533  *  @hw: pointer to the HW structure
1534  *
1535  *  Retrieve and return the current locally administered address state.
1536  **/
1537 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1538 {
1539         if (hw->mac.type != e1000_82571)
1540                 return false;
1541
1542         return hw->dev_spec.e82571.laa_is_present;
1543 }
1544
1545 /**
1546  *  e1000e_set_laa_state_82571 - Set locally administered address state
1547  *  @hw: pointer to the HW structure
1548  *  @state: enable/disable locally administered address
1549  *
1550  *  Enable/Disable the current locally administered address state.
1551  **/
1552 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1553 {
1554         if (hw->mac.type != e1000_82571)
1555                 return;
1556
1557         hw->dev_spec.e82571.laa_is_present = state;
1558
1559         /* If workaround is activated... */
1560         if (state)
1561                 /*
1562                  * Hold a copy of the LAA in RAR[14] This is done so that
1563                  * between the time RAR[0] gets clobbered and the time it
1564                  * gets fixed, the actual LAA is in one of the RARs and no
1565                  * incoming packets directed to this port are dropped.
1566                  * Eventually the LAA will be in RAR[0] and RAR[14].
1567                  */
1568                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1569 }
1570
1571 /**
1572  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1573  *  @hw: pointer to the HW structure
1574  *
1575  *  Verifies that the EEPROM has completed the update.  After updating the
1576  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1577  *  the checksum fix is not implemented, we need to set the bit and update
1578  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1579  *  we need to return bad checksum.
1580  **/
1581 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1582 {
1583         struct e1000_nvm_info *nvm = &hw->nvm;
1584         s32 ret_val;
1585         u16 data;
1586
1587         if (nvm->type != e1000_nvm_flash_hw)
1588                 return 0;
1589
1590         /*
1591          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1592          * 10h-12h.  Checksum may need to be fixed.
1593          */
1594         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1595         if (ret_val)
1596                 return ret_val;
1597
1598         if (!(data & 0x10)) {
1599                 /*
1600                  * Read 0x23 and check bit 15.  This bit is a 1
1601                  * when the checksum has already been fixed.  If
1602                  * the checksum is still wrong and this bit is a
1603                  * 1, we need to return bad checksum.  Otherwise,
1604                  * we need to set this bit to a 1 and update the
1605                  * checksum.
1606                  */
1607                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1608                 if (ret_val)
1609                         return ret_val;
1610
1611                 if (!(data & 0x8000)) {
1612                         data |= 0x8000;
1613                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1614                         if (ret_val)
1615                                 return ret_val;
1616                         ret_val = e1000e_update_nvm_checksum(hw);
1617                 }
1618         }
1619
1620         return 0;
1621 }
1622
1623 /**
1624  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1625  * @hw: pointer to the HW structure
1626  *
1627  * In the case of a PHY power down to save power, or to turn off link during a
1628  * driver unload, or wake on lan is not enabled, remove the link.
1629  **/
1630 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1631 {
1632         struct e1000_phy_info *phy = &hw->phy;
1633         struct e1000_mac_info *mac = &hw->mac;
1634
1635         if (!(phy->ops.check_reset_block))
1636                 return;
1637
1638         /* If the management interface is not enabled, then power down */
1639         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1640                 e1000_power_down_phy_copper(hw);
1641
1642         return;
1643 }
1644
1645 /**
1646  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1647  *  @hw: pointer to the HW structure
1648  *
1649  *  Clears the hardware counters by reading the counter registers.
1650  **/
1651 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1652 {
1653         e1000e_clear_hw_cntrs_base(hw);
1654
1655         er32(PRC64);
1656         er32(PRC127);
1657         er32(PRC255);
1658         er32(PRC511);
1659         er32(PRC1023);
1660         er32(PRC1522);
1661         er32(PTC64);
1662         er32(PTC127);
1663         er32(PTC255);
1664         er32(PTC511);
1665         er32(PTC1023);
1666         er32(PTC1522);
1667
1668         er32(ALGNERRC);
1669         er32(RXERRC);
1670         er32(TNCRS);
1671         er32(CEXTERR);
1672         er32(TSCTC);
1673         er32(TSCTFC);
1674
1675         er32(MGTPRC);
1676         er32(MGTPDC);
1677         er32(MGTPTC);
1678
1679         er32(IAC);
1680         er32(ICRXOC);
1681
1682         er32(ICRXPTC);
1683         er32(ICRXATC);
1684         er32(ICTXPTC);
1685         er32(ICTXATC);
1686         er32(ICTXQEC);
1687         er32(ICTXQMTC);
1688         er32(ICRXDMTC);
1689 }
1690
1691 static struct e1000_mac_operations e82571_mac_ops = {
1692         /* .check_mng_mode: mac type dependent */
1693         /* .check_for_link: media type dependent */
1694         .id_led_init            = e1000e_id_led_init,
1695         .cleanup_led            = e1000e_cleanup_led_generic,
1696         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1697         .get_bus_info           = e1000e_get_bus_info_pcie,
1698         /* .get_link_up_info: media type dependent */
1699         /* .led_on: mac type dependent */
1700         .led_off                = e1000e_led_off_generic,
1701         .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
1702         .write_vfta             = e1000_write_vfta_generic,
1703         .clear_vfta             = e1000_clear_vfta_82571,
1704         .reset_hw               = e1000_reset_hw_82571,
1705         .init_hw                = e1000_init_hw_82571,
1706         .setup_link             = e1000_setup_link_82571,
1707         /* .setup_physical_interface: media type dependent */
1708         .setup_led              = e1000e_setup_led_generic,
1709 };
1710
1711 static struct e1000_phy_operations e82_phy_ops_igp = {
1712         .acquire                = e1000_get_hw_semaphore_82571,
1713         .check_polarity         = e1000_check_polarity_igp,
1714         .check_reset_block      = e1000e_check_reset_block_generic,
1715         .commit                 = NULL,
1716         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1717         .get_cfg_done           = e1000_get_cfg_done_82571,
1718         .get_cable_length       = e1000e_get_cable_length_igp_2,
1719         .get_info               = e1000e_get_phy_info_igp,
1720         .read_reg               = e1000e_read_phy_reg_igp,
1721         .release                = e1000_put_hw_semaphore_82571,
1722         .reset                  = e1000e_phy_hw_reset_generic,
1723         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1724         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1725         .write_reg              = e1000e_write_phy_reg_igp,
1726         .cfg_on_link_up         = NULL,
1727 };
1728
1729 static struct e1000_phy_operations e82_phy_ops_m88 = {
1730         .acquire                = e1000_get_hw_semaphore_82571,
1731         .check_polarity         = e1000_check_polarity_m88,
1732         .check_reset_block      = e1000e_check_reset_block_generic,
1733         .commit                 = e1000e_phy_sw_reset,
1734         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1735         .get_cfg_done           = e1000e_get_cfg_done,
1736         .get_cable_length       = e1000e_get_cable_length_m88,
1737         .get_info               = e1000e_get_phy_info_m88,
1738         .read_reg               = e1000e_read_phy_reg_m88,
1739         .release                = e1000_put_hw_semaphore_82571,
1740         .reset                  = e1000e_phy_hw_reset_generic,
1741         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1742         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1743         .write_reg              = e1000e_write_phy_reg_m88,
1744         .cfg_on_link_up         = NULL,
1745 };
1746
1747 static struct e1000_phy_operations e82_phy_ops_bm = {
1748         .acquire                = e1000_get_hw_semaphore_82571,
1749         .check_polarity         = e1000_check_polarity_m88,
1750         .check_reset_block      = e1000e_check_reset_block_generic,
1751         .commit                 = e1000e_phy_sw_reset,
1752         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1753         .get_cfg_done           = e1000e_get_cfg_done,
1754         .get_cable_length       = e1000e_get_cable_length_m88,
1755         .get_info               = e1000e_get_phy_info_m88,
1756         .read_reg               = e1000e_read_phy_reg_bm2,
1757         .release                = e1000_put_hw_semaphore_82571,
1758         .reset                  = e1000e_phy_hw_reset_generic,
1759         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1760         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1761         .write_reg              = e1000e_write_phy_reg_bm2,
1762         .cfg_on_link_up         = NULL,
1763 };
1764
1765 static struct e1000_nvm_operations e82571_nvm_ops = {
1766         .acquire                = e1000_acquire_nvm_82571,
1767         .read                   = e1000e_read_nvm_eerd,
1768         .release                = e1000_release_nvm_82571,
1769         .update                 = e1000_update_nvm_checksum_82571,
1770         .valid_led_default      = e1000_valid_led_default_82571,
1771         .validate               = e1000_validate_nvm_checksum_82571,
1772         .write                  = e1000_write_nvm_82571,
1773 };
1774
1775 struct e1000_info e1000_82571_info = {
1776         .mac                    = e1000_82571,
1777         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1778                                   | FLAG_HAS_JUMBO_FRAMES
1779                                   | FLAG_HAS_WOL
1780                                   | FLAG_APME_IN_CTRL3
1781                                   | FLAG_RX_CSUM_ENABLED
1782                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1783                                   | FLAG_HAS_SMART_POWER_DOWN
1784                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1785                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1786                                   | FLAG_APME_CHECK_PORT_B,
1787         .pba                    = 38,
1788         .max_hw_frame_size      = DEFAULT_JUMBO,
1789         .get_variants           = e1000_get_variants_82571,
1790         .mac_ops                = &e82571_mac_ops,
1791         .phy_ops                = &e82_phy_ops_igp,
1792         .nvm_ops                = &e82571_nvm_ops,
1793 };
1794
1795 struct e1000_info e1000_82572_info = {
1796         .mac                    = e1000_82572,
1797         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1798                                   | FLAG_HAS_JUMBO_FRAMES
1799                                   | FLAG_HAS_WOL
1800                                   | FLAG_APME_IN_CTRL3
1801                                   | FLAG_RX_CSUM_ENABLED
1802                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1803                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1804         .pba                    = 38,
1805         .max_hw_frame_size      = DEFAULT_JUMBO,
1806         .get_variants           = e1000_get_variants_82571,
1807         .mac_ops                = &e82571_mac_ops,
1808         .phy_ops                = &e82_phy_ops_igp,
1809         .nvm_ops                = &e82571_nvm_ops,
1810 };
1811
1812 struct e1000_info e1000_82573_info = {
1813         .mac                    = e1000_82573,
1814         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1815                                   | FLAG_HAS_JUMBO_FRAMES
1816                                   | FLAG_HAS_WOL
1817                                   | FLAG_APME_IN_CTRL3
1818                                   | FLAG_RX_CSUM_ENABLED
1819                                   | FLAG_HAS_SMART_POWER_DOWN
1820                                   | FLAG_HAS_AMT
1821                                   | FLAG_HAS_ERT
1822                                   | FLAG_HAS_SWSM_ON_LOAD,
1823         .pba                    = 20,
1824         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1825         .get_variants           = e1000_get_variants_82571,
1826         .mac_ops                = &e82571_mac_ops,
1827         .phy_ops                = &e82_phy_ops_m88,
1828         .nvm_ops                = &e82571_nvm_ops,
1829 };
1830
1831 struct e1000_info e1000_82574_info = {
1832         .mac                    = e1000_82574,
1833         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1834                                   | FLAG_HAS_MSIX
1835                                   | FLAG_HAS_JUMBO_FRAMES
1836                                   | FLAG_HAS_WOL
1837                                   | FLAG_APME_IN_CTRL3
1838                                   | FLAG_RX_CSUM_ENABLED
1839                                   | FLAG_HAS_SMART_POWER_DOWN
1840                                   | FLAG_HAS_AMT
1841                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1842         .pba                    = 20,
1843         .max_hw_frame_size      = DEFAULT_JUMBO,
1844         .get_variants           = e1000_get_variants_82571,
1845         .mac_ops                = &e82571_mac_ops,
1846         .phy_ops                = &e82_phy_ops_bm,
1847         .nvm_ops                = &e82571_nvm_ops,
1848 };
1849
1850 struct e1000_info e1000_82583_info = {
1851         .mac                    = e1000_82583,
1852         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1853                                   | FLAG_HAS_WOL
1854                                   | FLAG_APME_IN_CTRL3
1855                                   | FLAG_RX_CSUM_ENABLED
1856                                   | FLAG_HAS_SMART_POWER_DOWN
1857                                   | FLAG_HAS_AMT
1858                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1859         .pba                    = 20,
1860         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
1861         .get_variants           = e1000_get_variants_82571,
1862         .mac_ops                = &e82571_mac_ops,
1863         .phy_ops                = &e82_phy_ops_bm,
1864         .nvm_ops                = &e82571_nvm_ops,
1865 };
1866