1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 * Shared functions for accessing and configuring the MAC
35 static s32 e1000_check_downshift(struct e1000_hw *hw);
36 static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
38 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39 static void e1000_clear_vfta(struct e1000_hw *hw);
40 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
42 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
44 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
45 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
47 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
48 static s32 e1000_id_led_init(struct e1000_hw *hw);
49 static void e1000_init_rx_addrs(struct e1000_hw *hw);
50 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
52 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
54 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
55 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57 static s32 e1000_set_phy_type(struct e1000_hw *hw);
58 static void e1000_phy_init_script(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
66 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
67 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
70 u16 words, u16 *data);
71 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
73 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
76 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
77 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
79 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
81 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
83 static void e1000_release_eeprom(struct e1000_hw *hw);
84 static void e1000_standby_eeprom(struct e1000_hw *hw);
85 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
88 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
90 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
93 /* IGP cable length table */
95 u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
109 static DEFINE_SPINLOCK(e1000_eeprom_lock);
112 * e1000_set_phy_type - Set the phy type member in the hw struct.
113 * @hw: Struct containing variables accessed by shared code
115 static s32 e1000_set_phy_type(struct e1000_hw *hw)
117 e_dbg("e1000_set_phy_type");
119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
127 case M88E1118_E_PHY_ID:
128 hw->phy_type = e1000_phy_m88;
130 case IGP01E1000_I_PHY_ID:
131 if (hw->mac_type == e1000_82541 ||
132 hw->mac_type == e1000_82541_rev_2 ||
133 hw->mac_type == e1000_82547 ||
134 hw->mac_type == e1000_82547_rev_2)
135 hw->phy_type = e1000_phy_igp;
137 case RTL8211B_PHY_ID:
138 hw->phy_type = e1000_phy_8211;
140 case RTL8201N_PHY_ID:
141 hw->phy_type = e1000_phy_8201;
144 /* Should never have loaded on this device */
145 hw->phy_type = e1000_phy_undefined;
146 return -E1000_ERR_PHY_TYPE;
149 return E1000_SUCCESS;
153 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
154 * @hw: Struct containing variables accessed by shared code
156 static void e1000_phy_init_script(struct e1000_hw *hw)
161 e_dbg("e1000_phy_init_script");
163 if (hw->phy_init_script) {
166 /* Save off the current value of register 0x2F5B to be restored at
167 * the end of this routine. */
168 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
170 /* Disabled the PHY transmitter */
171 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
174 e1000_write_phy_reg(hw, 0x0000, 0x0140);
177 switch (hw->mac_type) {
180 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
183 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
184 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
185 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
186 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
187 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
188 e1000_write_phy_reg(hw, 0x2010, 0x0008);
191 case e1000_82541_rev_2:
192 case e1000_82547_rev_2:
193 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
199 e1000_write_phy_reg(hw, 0x0000, 0x3300);
202 /* Now enable the transmitter */
203 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
205 if (hw->mac_type == e1000_82547) {
206 u16 fused, fine, coarse;
208 /* Move to analog registers page */
209 e1000_read_phy_reg(hw,
210 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
213 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214 e1000_read_phy_reg(hw,
215 IGP01E1000_ANALOG_FUSE_STATUS,
218 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
220 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
223 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
225 IGP01E1000_ANALOG_FUSE_COARSE_10;
226 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
228 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
229 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
232 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
233 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
235 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
237 e1000_write_phy_reg(hw,
238 IGP01E1000_ANALOG_FUSE_CONTROL,
240 e1000_write_phy_reg(hw,
241 IGP01E1000_ANALOG_FUSE_BYPASS,
242 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
249 * e1000_set_mac_type - Set the mac type member in the hw struct.
250 * @hw: Struct containing variables accessed by shared code
252 s32 e1000_set_mac_type(struct e1000_hw *hw)
254 e_dbg("e1000_set_mac_type");
256 switch (hw->device_id) {
257 case E1000_DEV_ID_82542:
258 switch (hw->revision_id) {
259 case E1000_82542_2_0_REV_ID:
260 hw->mac_type = e1000_82542_rev2_0;
262 case E1000_82542_2_1_REV_ID:
263 hw->mac_type = e1000_82542_rev2_1;
266 /* Invalid 82542 revision ID */
267 return -E1000_ERR_MAC_TYPE;
270 case E1000_DEV_ID_82543GC_FIBER:
271 case E1000_DEV_ID_82543GC_COPPER:
272 hw->mac_type = e1000_82543;
274 case E1000_DEV_ID_82544EI_COPPER:
275 case E1000_DEV_ID_82544EI_FIBER:
276 case E1000_DEV_ID_82544GC_COPPER:
277 case E1000_DEV_ID_82544GC_LOM:
278 hw->mac_type = e1000_82544;
280 case E1000_DEV_ID_82540EM:
281 case E1000_DEV_ID_82540EM_LOM:
282 case E1000_DEV_ID_82540EP:
283 case E1000_DEV_ID_82540EP_LOM:
284 case E1000_DEV_ID_82540EP_LP:
285 hw->mac_type = e1000_82540;
287 case E1000_DEV_ID_82545EM_COPPER:
288 case E1000_DEV_ID_82545EM_FIBER:
289 hw->mac_type = e1000_82545;
291 case E1000_DEV_ID_82545GM_COPPER:
292 case E1000_DEV_ID_82545GM_FIBER:
293 case E1000_DEV_ID_82545GM_SERDES:
294 hw->mac_type = e1000_82545_rev_3;
296 case E1000_DEV_ID_82546EB_COPPER:
297 case E1000_DEV_ID_82546EB_FIBER:
298 case E1000_DEV_ID_82546EB_QUAD_COPPER:
299 hw->mac_type = e1000_82546;
301 case E1000_DEV_ID_82546GB_COPPER:
302 case E1000_DEV_ID_82546GB_FIBER:
303 case E1000_DEV_ID_82546GB_SERDES:
304 case E1000_DEV_ID_82546GB_PCIE:
305 case E1000_DEV_ID_82546GB_QUAD_COPPER:
306 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
307 hw->mac_type = e1000_82546_rev_3;
309 case E1000_DEV_ID_82541EI:
310 case E1000_DEV_ID_82541EI_MOBILE:
311 case E1000_DEV_ID_82541ER_LOM:
312 hw->mac_type = e1000_82541;
314 case E1000_DEV_ID_82541ER:
315 case E1000_DEV_ID_82541GI:
316 case E1000_DEV_ID_82541GI_LF:
317 case E1000_DEV_ID_82541GI_MOBILE:
318 hw->mac_type = e1000_82541_rev_2;
320 case E1000_DEV_ID_82547EI:
321 case E1000_DEV_ID_82547EI_MOBILE:
322 hw->mac_type = e1000_82547;
324 case E1000_DEV_ID_82547GI:
325 hw->mac_type = e1000_82547_rev_2;
327 case E1000_DEV_ID_INTEL_CE4100_GBE:
328 hw->mac_type = e1000_ce4100;
331 /* Should never have loaded on this device */
332 return -E1000_ERR_MAC_TYPE;
335 switch (hw->mac_type) {
338 case e1000_82541_rev_2:
339 case e1000_82547_rev_2:
340 hw->asf_firmware_present = true;
346 /* The 82543 chip does not count tx_carrier_errors properly in
349 if (hw->mac_type == e1000_82543)
350 hw->bad_tx_carr_stats_fd = true;
352 if (hw->mac_type > e1000_82544)
353 hw->has_smbus = true;
355 return E1000_SUCCESS;
359 * e1000_set_media_type - Set media type and TBI compatibility.
360 * @hw: Struct containing variables accessed by shared code
362 void e1000_set_media_type(struct e1000_hw *hw)
366 e_dbg("e1000_set_media_type");
368 if (hw->mac_type != e1000_82543) {
369 /* tbi_compatibility is only valid on 82543 */
370 hw->tbi_compatibility_en = false;
373 switch (hw->device_id) {
374 case E1000_DEV_ID_82545GM_SERDES:
375 case E1000_DEV_ID_82546GB_SERDES:
376 hw->media_type = e1000_media_type_internal_serdes;
379 switch (hw->mac_type) {
380 case e1000_82542_rev2_0:
381 case e1000_82542_rev2_1:
382 hw->media_type = e1000_media_type_fiber;
385 hw->media_type = e1000_media_type_copper;
388 status = er32(STATUS);
389 if (status & E1000_STATUS_TBIMODE) {
390 hw->media_type = e1000_media_type_fiber;
391 /* tbi_compatibility not valid on fiber */
392 hw->tbi_compatibility_en = false;
394 hw->media_type = e1000_media_type_copper;
402 * e1000_reset_hw: reset the hardware completely
403 * @hw: Struct containing variables accessed by shared code
405 * Reset the transmit and receive units; mask and clear all interrupts.
407 s32 e1000_reset_hw(struct e1000_hw *hw)
416 e_dbg("e1000_reset_hw");
418 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
419 if (hw->mac_type == e1000_82542_rev2_0) {
420 e_dbg("Disabling MWI on 82542 rev 2.0\n");
421 e1000_pci_clear_mwi(hw);
424 /* Clear interrupt mask to stop board from generating interrupts */
425 e_dbg("Masking off all interrupts\n");
426 ew32(IMC, 0xffffffff);
428 /* Disable the Transmit and Receive units. Then delay to allow
429 * any pending transactions to complete before we hit the MAC with
433 ew32(TCTL, E1000_TCTL_PSP);
436 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
437 hw->tbi_compatibility_on = false;
439 /* Delay to allow any outstanding PCI transactions to complete before
440 * resetting the device
446 /* Must reset the PHY before resetting the MAC */
447 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
448 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
452 /* Issue a global reset to the MAC. This will reset the chip's
453 * transmit, receive, DMA, and link units. It will not effect
454 * the current PCI configuration. The global reset bit is self-
455 * clearing, and should clear within a microsecond.
457 e_dbg("Issuing a global reset to MAC\n");
459 switch (hw->mac_type) {
465 case e1000_82541_rev_2:
466 /* These controllers can't ack the 64-bit write when issuing the
467 * reset, so use IO-mapping as a workaround to issue the reset */
468 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
470 case e1000_82545_rev_3:
471 case e1000_82546_rev_3:
472 /* Reset is performed on a shadow of the control register */
473 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
477 ew32(CTRL, (ctrl | E1000_CTRL_RST));
481 /* After MAC reset, force reload of EEPROM to restore power-on settings to
482 * device. Later controllers reload the EEPROM automatically, so just wait
483 * for reload to complete.
485 switch (hw->mac_type) {
486 case e1000_82542_rev2_0:
487 case e1000_82542_rev2_1:
490 /* Wait for reset to complete */
492 ctrl_ext = er32(CTRL_EXT);
493 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
494 ew32(CTRL_EXT, ctrl_ext);
496 /* Wait for EEPROM reload */
500 case e1000_82541_rev_2:
502 case e1000_82547_rev_2:
503 /* Wait for EEPROM reload */
507 /* Auto read done will delay 5ms or poll based on mac type */
508 ret_val = e1000_get_auto_rd_done(hw);
514 /* Disable HW ARPs on ASF enabled adapters */
515 if (hw->mac_type >= e1000_82540) {
517 manc &= ~(E1000_MANC_ARP_EN);
521 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
522 e1000_phy_init_script(hw);
524 /* Configure activity LED after PHY reset */
525 led_ctrl = er32(LEDCTL);
526 led_ctrl &= IGP_ACTIVITY_LED_MASK;
527 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
528 ew32(LEDCTL, led_ctrl);
531 /* Clear interrupt mask to stop board from generating interrupts */
532 e_dbg("Masking off all interrupts\n");
533 ew32(IMC, 0xffffffff);
535 /* Clear any pending interrupt events. */
538 /* If MWI was previously enabled, reenable it. */
539 if (hw->mac_type == e1000_82542_rev2_0) {
540 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
541 e1000_pci_set_mwi(hw);
544 return E1000_SUCCESS;
548 * e1000_init_hw: Performs basic configuration of the adapter.
549 * @hw: Struct containing variables accessed by shared code
551 * Assumes that the controller has previously been reset and is in a
552 * post-reset uninitialized state. Initializes the receive address registers,
553 * multicast table, and VLAN filter table. Calls routines to setup link
554 * configuration and flow control settings. Clears all on-chip counters. Leaves
555 * the transmit and receive units disabled and uninitialized.
557 s32 e1000_init_hw(struct e1000_hw *hw)
565 e_dbg("e1000_init_hw");
567 /* Initialize Identification LED */
568 ret_val = e1000_id_led_init(hw);
570 e_dbg("Error Initializing Identification LED\n");
574 /* Set the media type and TBI compatibility */
575 e1000_set_media_type(hw);
577 /* Disabling VLAN filtering. */
578 e_dbg("Initializing the IEEE VLAN\n");
579 if (hw->mac_type < e1000_82545_rev_3)
581 e1000_clear_vfta(hw);
583 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
584 if (hw->mac_type == e1000_82542_rev2_0) {
585 e_dbg("Disabling MWI on 82542 rev 2.0\n");
586 e1000_pci_clear_mwi(hw);
587 ew32(RCTL, E1000_RCTL_RST);
592 /* Setup the receive address. This involves initializing all of the Receive
593 * Address Registers (RARs 0 - 15).
595 e1000_init_rx_addrs(hw);
597 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
598 if (hw->mac_type == e1000_82542_rev2_0) {
602 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
603 e1000_pci_set_mwi(hw);
606 /* Zero out the Multicast HASH table */
607 e_dbg("Zeroing the MTA\n");
608 mta_size = E1000_MC_TBL_SIZE;
609 for (i = 0; i < mta_size; i++) {
610 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
611 /* use write flush to prevent Memory Write Block (MWB) from
612 * occurring when accessing our register space */
616 /* Set the PCI priority bit correctly in the CTRL register. This
617 * determines if the adapter gives priority to receives, or if it
618 * gives equal priority to transmits and receives. Valid only on
619 * 82542 and 82543 silicon.
621 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
623 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
626 switch (hw->mac_type) {
627 case e1000_82545_rev_3:
628 case e1000_82546_rev_3:
631 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
632 if (hw->bus_type == e1000_bus_type_pcix
633 && e1000_pcix_get_mmrbc(hw) > 2048)
634 e1000_pcix_set_mmrbc(hw, 2048);
638 /* Call a subroutine to configure the link and setup flow control. */
639 ret_val = e1000_setup_link(hw);
641 /* Set the transmit descriptor write-back policy */
642 if (hw->mac_type > e1000_82544) {
645 (ctrl & ~E1000_TXDCTL_WTHRESH) |
646 E1000_TXDCTL_FULL_TX_DESC_WB;
650 /* Clear all of the statistics registers (clear on read). It is
651 * important that we do this after we have tried to establish link
652 * because the symbol error count will increment wildly if there
655 e1000_clear_hw_cntrs(hw);
657 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
658 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
659 ctrl_ext = er32(CTRL_EXT);
660 /* Relaxed ordering must be disabled to avoid a parity
661 * error crash in a PCI slot. */
662 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
663 ew32(CTRL_EXT, ctrl_ext);
670 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
671 * @hw: Struct containing variables accessed by shared code.
673 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
678 e_dbg("e1000_adjust_serdes_amplitude");
680 if (hw->media_type != e1000_media_type_internal_serdes)
681 return E1000_SUCCESS;
683 switch (hw->mac_type) {
684 case e1000_82545_rev_3:
685 case e1000_82546_rev_3:
688 return E1000_SUCCESS;
691 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
697 if (eeprom_data != EEPROM_RESERVED_WORD) {
698 /* Adjust SERDES output amplitude only. */
699 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
701 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
706 return E1000_SUCCESS;
710 * e1000_setup_link - Configures flow control and link settings.
711 * @hw: Struct containing variables accessed by shared code
713 * Determines which flow control settings to use. Calls the appropriate media-
714 * specific link configuration function. Configures the flow control settings.
715 * Assuming the adapter has a valid link partner, a valid link should be
716 * established. Assumes the hardware has previously been reset and the
717 * transmitter and receiver are not enabled.
719 s32 e1000_setup_link(struct e1000_hw *hw)
725 e_dbg("e1000_setup_link");
727 /* Read and store word 0x0F of the EEPROM. This word contains bits
728 * that determine the hardware's default PAUSE (flow control) mode,
729 * a bit that determines whether the HW defaults to enabling or
730 * disabling auto-negotiation, and the direction of the
731 * SW defined pins. If there is no SW over-ride of the flow
732 * control setting, then the variable hw->fc will
733 * be initialized based on a value in the EEPROM.
735 if (hw->fc == E1000_FC_DEFAULT) {
736 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
739 e_dbg("EEPROM Read Error\n");
740 return -E1000_ERR_EEPROM;
742 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
743 hw->fc = E1000_FC_NONE;
744 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
745 EEPROM_WORD0F_ASM_DIR)
746 hw->fc = E1000_FC_TX_PAUSE;
748 hw->fc = E1000_FC_FULL;
751 /* We want to save off the original Flow Control configuration just
752 * in case we get disconnected and then reconnected into a different
753 * hub or switch with different Flow Control capabilities.
755 if (hw->mac_type == e1000_82542_rev2_0)
756 hw->fc &= (~E1000_FC_TX_PAUSE);
758 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
759 hw->fc &= (~E1000_FC_RX_PAUSE);
761 hw->original_fc = hw->fc;
763 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
765 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
766 * polarity value for the SW controlled pins, and setup the
767 * Extended Device Control reg with that info.
768 * This is needed because one of the SW controlled pins is used for
769 * signal detection. So this should be done before e1000_setup_pcs_link()
770 * or e1000_phy_setup() is called.
772 if (hw->mac_type == e1000_82543) {
773 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
776 e_dbg("EEPROM Read Error\n");
777 return -E1000_ERR_EEPROM;
779 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
781 ew32(CTRL_EXT, ctrl_ext);
784 /* Call the necessary subroutine to configure the link. */
785 ret_val = (hw->media_type == e1000_media_type_copper) ?
786 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
788 /* Initialize the flow control address, type, and PAUSE timer
789 * registers to their default values. This is done even if flow
790 * control is disabled, because it does not hurt anything to
791 * initialize these registers.
793 e_dbg("Initializing the Flow Control address, type and timer regs\n");
795 ew32(FCT, FLOW_CONTROL_TYPE);
796 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
797 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
799 ew32(FCTTV, hw->fc_pause_time);
801 /* Set the flow control receive threshold registers. Normally,
802 * these registers will be set to a default threshold that may be
803 * adjusted later by the driver's runtime code. However, if the
804 * ability to transmit pause frames in not enabled, then these
805 * registers will be set to 0.
807 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
811 /* We need to set up the Receive Threshold high and low water marks
812 * as well as (optionally) enabling the transmission of XON frames.
814 if (hw->fc_send_xon) {
815 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
816 ew32(FCRTH, hw->fc_high_water);
818 ew32(FCRTL, hw->fc_low_water);
819 ew32(FCRTH, hw->fc_high_water);
826 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
827 * @hw: Struct containing variables accessed by shared code
829 * Manipulates Physical Coding Sublayer functions in order to configure
830 * link. Assumes the hardware has been previously reset and the transmitter
831 * and receiver are not enabled.
833 static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
842 e_dbg("e1000_setup_fiber_serdes_link");
844 /* On adapters with a MAC newer than 82544, SWDP 1 will be
845 * set when the optics detect a signal. On older adapters, it will be
846 * cleared when there is a signal. This applies to fiber media only.
847 * If we're on serdes media, adjust the output amplitude to value
851 if (hw->media_type == e1000_media_type_fiber)
852 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
854 ret_val = e1000_adjust_serdes_amplitude(hw);
858 /* Take the link out of reset */
859 ctrl &= ~(E1000_CTRL_LRST);
861 /* Adjust VCO speed to improve BER performance */
862 ret_val = e1000_set_vco_speed(hw);
866 e1000_config_collision_dist(hw);
868 /* Check for a software override of the flow control settings, and setup
869 * the device accordingly. If auto-negotiation is enabled, then software
870 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
871 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
872 * auto-negotiation is disabled, then software will have to manually
873 * configure the two flow control enable bits in the CTRL register.
875 * The possible values of the "fc" parameter are:
876 * 0: Flow control is completely disabled
877 * 1: Rx flow control is enabled (we can receive pause frames, but
878 * not send pause frames).
879 * 2: Tx flow control is enabled (we can send pause frames but we do
880 * not support receiving pause frames).
881 * 3: Both Rx and TX flow control (symmetric) are enabled.
885 /* Flow control is completely disabled by a software over-ride. */
886 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
888 case E1000_FC_RX_PAUSE:
889 /* RX Flow control is enabled and TX Flow control is disabled by a
890 * software over-ride. Since there really isn't a way to advertise
891 * that we are capable of RX Pause ONLY, we will advertise that we
892 * support both symmetric and asymmetric RX PAUSE. Later, we will
893 * disable the adapter's ability to send PAUSE frames.
895 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
897 case E1000_FC_TX_PAUSE:
898 /* TX Flow control is enabled, and RX Flow control is disabled, by a
899 * software over-ride.
901 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
904 /* Flow control (both RX and TX) is enabled by a software over-ride. */
905 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
908 e_dbg("Flow control param set incorrectly\n");
909 return -E1000_ERR_CONFIG;
913 /* Since auto-negotiation is enabled, take the link out of reset (the link
914 * will be in reset, because we previously reset the chip). This will
915 * restart auto-negotiation. If auto-negotiation is successful then the
916 * link-up status bit will be set and the flow control enable bits (RFCE
917 * and TFCE) will be set according to their negotiated value.
919 e_dbg("Auto-negotiation enabled\n");
928 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
929 * indication in the Device Status Register. Time-out if a link isn't
930 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
931 * less than 500 milliseconds even if the other end is doing it in SW).
932 * For internal serdes, we just assume a signal is present, then poll.
934 if (hw->media_type == e1000_media_type_internal_serdes ||
935 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
936 e_dbg("Looking for Link\n");
937 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
939 status = er32(STATUS);
940 if (status & E1000_STATUS_LU)
943 if (i == (LINK_UP_TIMEOUT / 10)) {
944 e_dbg("Never got a valid link from auto-neg!!!\n");
945 hw->autoneg_failed = 1;
946 /* AutoNeg failed to achieve a link, so we'll call
947 * e1000_check_for_link. This routine will force the link up if
948 * we detect a signal. This will allow us to communicate with
949 * non-autonegotiating link partners.
951 ret_val = e1000_check_for_link(hw);
953 e_dbg("Error while checking for link\n");
956 hw->autoneg_failed = 0;
958 hw->autoneg_failed = 0;
959 e_dbg("Valid Link Found\n");
962 e_dbg("No Signal Detected\n");
964 return E1000_SUCCESS;
968 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
969 * @hw: Struct containing variables accessed by shared code
971 * Commits changes to PHY configuration by calling e1000_phy_reset().
973 static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
977 /* SW reset the PHY so all changes take effect */
978 ret_val = e1000_phy_reset(hw);
980 e_dbg("Error Resetting the PHY\n");
984 return E1000_SUCCESS;
987 static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
992 switch (hw->phy_type) {
994 ret_val = e1000_copper_link_rtl_setup(hw);
996 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1000 case e1000_phy_8201:
1002 ctrl_aux = er32(CTL_AUX);
1003 ctrl_aux |= E1000_CTL_AUX_RMII;
1004 ew32(CTL_AUX, ctrl_aux);
1005 E1000_WRITE_FLUSH();
1007 /* Disable the J/K bits required for receive */
1008 ctrl_aux = er32(CTL_AUX);
1011 ew32(CTL_AUX, ctrl_aux);
1012 E1000_WRITE_FLUSH();
1013 ret_val = e1000_copper_link_rtl_setup(hw);
1016 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1021 e_dbg("Error Resetting the PHY\n");
1022 return E1000_ERR_PHY_TYPE;
1025 return E1000_SUCCESS;
1029 * e1000_copper_link_preconfig - early configuration for copper
1030 * @hw: Struct containing variables accessed by shared code
1032 * Make sure we have a valid PHY and change PHY mode before link setup.
1034 static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1040 e_dbg("e1000_copper_link_preconfig");
1043 /* With 82543, we need to force speed and duplex on the MAC equal to what
1044 * the PHY speed and duplex configuration is. In addition, we need to
1045 * perform a hardware reset on the PHY to take it out of reset.
1047 if (hw->mac_type > e1000_82543) {
1048 ctrl |= E1000_CTRL_SLU;
1049 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1053 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1055 ret_val = e1000_phy_hw_reset(hw);
1060 /* Make sure we have a valid PHY */
1061 ret_val = e1000_detect_gig_phy(hw);
1063 e_dbg("Error, did not detect valid phy.\n");
1066 e_dbg("Phy ID = %x\n", hw->phy_id);
1068 /* Set PHY to class A mode (if necessary) */
1069 ret_val = e1000_set_phy_mode(hw);
1073 if ((hw->mac_type == e1000_82545_rev_3) ||
1074 (hw->mac_type == e1000_82546_rev_3)) {
1076 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1077 phy_data |= 0x00000008;
1079 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1082 if (hw->mac_type <= e1000_82543 ||
1083 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1084 hw->mac_type == e1000_82541_rev_2
1085 || hw->mac_type == e1000_82547_rev_2)
1086 hw->phy_reset_disable = false;
1088 return E1000_SUCCESS;
1092 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1093 * @hw: Struct containing variables accessed by shared code
1095 static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1101 e_dbg("e1000_copper_link_igp_setup");
1103 if (hw->phy_reset_disable)
1104 return E1000_SUCCESS;
1106 ret_val = e1000_phy_reset(hw);
1108 e_dbg("Error Resetting the PHY\n");
1112 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1114 /* Configure activity LED after PHY reset */
1115 led_ctrl = er32(LEDCTL);
1116 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1117 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1118 ew32(LEDCTL, led_ctrl);
1120 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1121 if (hw->phy_type == e1000_phy_igp) {
1122 /* disable lplu d3 during driver init */
1123 ret_val = e1000_set_d3_lplu_state(hw, false);
1125 e_dbg("Error Disabling LPLU D3\n");
1130 /* Configure mdi-mdix settings */
1131 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1135 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1136 hw->dsp_config_state = e1000_dsp_config_disabled;
1137 /* Force MDI for earlier revs of the IGP PHY */
1139 ~(IGP01E1000_PSCR_AUTO_MDIX |
1140 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1144 hw->dsp_config_state = e1000_dsp_config_enabled;
1145 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1149 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1152 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1156 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1160 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1164 /* set auto-master slave resolution settings */
1166 e1000_ms_type phy_ms_setting = hw->master_slave;
1168 if (hw->ffe_config_state == e1000_ffe_config_active)
1169 hw->ffe_config_state = e1000_ffe_config_enabled;
1171 if (hw->dsp_config_state == e1000_dsp_config_activated)
1172 hw->dsp_config_state = e1000_dsp_config_enabled;
1174 /* when autonegotiation advertisement is only 1000Mbps then we
1175 * should disable SmartSpeed and enable Auto MasterSlave
1176 * resolution as hardware default. */
1177 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1178 /* Disable SmartSpeed */
1180 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1184 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1186 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1190 /* Set auto Master/Slave resolution process */
1192 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1195 phy_data &= ~CR_1000T_MS_ENABLE;
1197 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1206 /* load defaults for future use */
1207 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1208 ((phy_data & CR_1000T_MS_VALUE) ?
1209 e1000_ms_force_master :
1210 e1000_ms_force_slave) : e1000_ms_auto;
1212 switch (phy_ms_setting) {
1213 case e1000_ms_force_master:
1214 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1216 case e1000_ms_force_slave:
1217 phy_data |= CR_1000T_MS_ENABLE;
1218 phy_data &= ~(CR_1000T_MS_VALUE);
1221 phy_data &= ~CR_1000T_MS_ENABLE;
1225 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1230 return E1000_SUCCESS;
1234 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1235 * @hw: Struct containing variables accessed by shared code
1237 static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1242 e_dbg("e1000_copper_link_mgp_setup");
1244 if (hw->phy_reset_disable)
1245 return E1000_SUCCESS;
1247 /* Enable CRS on TX. This must be set for half-duplex operation. */
1248 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1252 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1255 * MDI/MDI-X = 0 (default)
1256 * 0 - Auto for all speeds
1259 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1261 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1265 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1268 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1271 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1275 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1280 * disable_polarity_correction = 0 (default)
1281 * Automatic Correction for Reversed Cable Polarity
1285 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1286 if (hw->disable_polarity_correction == 1)
1287 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1288 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1292 if (hw->phy_revision < M88E1011_I_REV_4) {
1293 /* Force TX_CLK in the Extended PHY Specific Control Register
1297 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1302 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1304 if ((hw->phy_revision == E1000_REVISION_2) &&
1305 (hw->phy_id == M88E1111_I_PHY_ID)) {
1306 /* Vidalia Phy, set the downshift counter to 5x */
1307 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1308 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1309 ret_val = e1000_write_phy_reg(hw,
1310 M88E1000_EXT_PHY_SPEC_CTRL,
1315 /* Configure Master and Slave downshift values */
1316 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1317 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1318 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1319 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1320 ret_val = e1000_write_phy_reg(hw,
1321 M88E1000_EXT_PHY_SPEC_CTRL,
1328 /* SW Reset the PHY so all changes take effect */
1329 ret_val = e1000_phy_reset(hw);
1331 e_dbg("Error Resetting the PHY\n");
1335 return E1000_SUCCESS;
1339 * e1000_copper_link_autoneg - setup auto-neg
1340 * @hw: Struct containing variables accessed by shared code
1342 * Setup auto-negotiation and flow control advertisements,
1343 * and then perform auto-negotiation.
1345 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1350 e_dbg("e1000_copper_link_autoneg");
1352 /* Perform some bounds checking on the hw->autoneg_advertised
1353 * parameter. If this variable is zero, then set it to the default.
1355 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1357 /* If autoneg_advertised is zero, we assume it was not defaulted
1358 * by the calling code so we set to advertise full capability.
1360 if (hw->autoneg_advertised == 0)
1361 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1363 /* IFE/RTL8201N PHY only supports 10/100 */
1364 if (hw->phy_type == e1000_phy_8201)
1365 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1367 e_dbg("Reconfiguring auto-neg advertisement params\n");
1368 ret_val = e1000_phy_setup_autoneg(hw);
1370 e_dbg("Error Setting up Auto-Negotiation\n");
1373 e_dbg("Restarting Auto-Neg\n");
1375 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1376 * the Auto Neg Restart bit in the PHY control register.
1378 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1382 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1383 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1387 /* Does the user want to wait for Auto-Neg to complete here, or
1388 * check at a later time (for example, callback routine).
1390 if (hw->wait_autoneg_complete) {
1391 ret_val = e1000_wait_autoneg(hw);
1394 ("Error while waiting for autoneg to complete\n");
1399 hw->get_link_status = true;
1401 return E1000_SUCCESS;
1405 * e1000_copper_link_postconfig - post link setup
1406 * @hw: Struct containing variables accessed by shared code
1408 * Config the MAC and the PHY after link is up.
1409 * 1) Set up the MAC to the current PHY speed/duplex
1410 * if we are on 82543. If we
1411 * are on newer silicon, we only need to configure
1412 * collision distance in the Transmit Control Register.
1413 * 2) Set up flow control on the MAC to that established with
1415 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1417 static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1420 e_dbg("e1000_copper_link_postconfig");
1422 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1423 e1000_config_collision_dist(hw);
1425 ret_val = e1000_config_mac_to_phy(hw);
1427 e_dbg("Error configuring MAC to PHY settings\n");
1431 ret_val = e1000_config_fc_after_link_up(hw);
1433 e_dbg("Error Configuring Flow Control\n");
1437 /* Config DSP to improve Giga link quality */
1438 if (hw->phy_type == e1000_phy_igp) {
1439 ret_val = e1000_config_dsp_after_link_change(hw, true);
1441 e_dbg("Error Configuring DSP after link up\n");
1446 return E1000_SUCCESS;
1450 * e1000_setup_copper_link - phy/speed/duplex setting
1451 * @hw: Struct containing variables accessed by shared code
1453 * Detects which PHY is present and sets up the speed and duplex
1455 static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1461 e_dbg("e1000_setup_copper_link");
1463 /* Check if it is a valid PHY and set PHY mode if necessary. */
1464 ret_val = e1000_copper_link_preconfig(hw);
1468 if (hw->phy_type == e1000_phy_igp) {
1469 ret_val = e1000_copper_link_igp_setup(hw);
1472 } else if (hw->phy_type == e1000_phy_m88) {
1473 ret_val = e1000_copper_link_mgp_setup(hw);
1477 ret_val = gbe_dhg_phy_setup(hw);
1479 e_dbg("gbe_dhg_phy_setup failed!\n");
1485 /* Setup autoneg and flow control advertisement
1486 * and perform autonegotiation */
1487 ret_val = e1000_copper_link_autoneg(hw);
1491 /* PHY will be set to 10H, 10F, 100H,or 100F
1492 * depending on value from forced_speed_duplex. */
1493 e_dbg("Forcing speed and duplex\n");
1494 ret_val = e1000_phy_force_speed_duplex(hw);
1496 e_dbg("Error Forcing Speed and Duplex\n");
1501 /* Check link status. Wait up to 100 microseconds for link to become
1504 for (i = 0; i < 10; i++) {
1505 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1508 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1512 if (phy_data & MII_SR_LINK_STATUS) {
1513 /* Config the MAC and PHY after link is up */
1514 ret_val = e1000_copper_link_postconfig(hw);
1518 e_dbg("Valid link established!!!\n");
1519 return E1000_SUCCESS;
1524 e_dbg("Unable to establish link!!!\n");
1525 return E1000_SUCCESS;
1529 * e1000_phy_setup_autoneg - phy settings
1530 * @hw: Struct containing variables accessed by shared code
1532 * Configures PHY autoneg and flow control advertisement settings
1534 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1537 u16 mii_autoneg_adv_reg;
1538 u16 mii_1000t_ctrl_reg;
1540 e_dbg("e1000_phy_setup_autoneg");
1542 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1543 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1547 /* Read the MII 1000Base-T Control Register (Address 9). */
1548 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1551 else if (hw->phy_type == e1000_phy_8201)
1552 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1554 /* Need to parse both autoneg_advertised and fc and set up
1555 * the appropriate PHY registers. First we will parse for
1556 * autoneg_advertised software override. Since we can advertise
1557 * a plethora of combinations, we need to check each bit
1561 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1562 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1563 * the 1000Base-T Control Register (Address 9).
1565 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1566 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1568 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1570 /* Do we want to advertise 10 Mb Half Duplex? */
1571 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1572 e_dbg("Advertise 10mb Half duplex\n");
1573 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1576 /* Do we want to advertise 10 Mb Full Duplex? */
1577 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1578 e_dbg("Advertise 10mb Full duplex\n");
1579 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1582 /* Do we want to advertise 100 Mb Half Duplex? */
1583 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1584 e_dbg("Advertise 100mb Half duplex\n");
1585 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1588 /* Do we want to advertise 100 Mb Full Duplex? */
1589 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1590 e_dbg("Advertise 100mb Full duplex\n");
1591 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1594 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1595 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1597 ("Advertise 1000mb Half duplex requested, request denied!\n");
1600 /* Do we want to advertise 1000 Mb Full Duplex? */
1601 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1602 e_dbg("Advertise 1000mb Full duplex\n");
1603 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1606 /* Check for a software override of the flow control settings, and
1607 * setup the PHY advertisement registers accordingly. If
1608 * auto-negotiation is enabled, then software will have to set the
1609 * "PAUSE" bits to the correct value in the Auto-Negotiation
1610 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1612 * The possible values of the "fc" parameter are:
1613 * 0: Flow control is completely disabled
1614 * 1: Rx flow control is enabled (we can receive pause frames
1615 * but not send pause frames).
1616 * 2: Tx flow control is enabled (we can send pause frames
1617 * but we do not support receiving pause frames).
1618 * 3: Both Rx and TX flow control (symmetric) are enabled.
1619 * other: No software override. The flow control configuration
1620 * in the EEPROM is used.
1623 case E1000_FC_NONE: /* 0 */
1624 /* Flow control (RX & TX) is completely disabled by a
1625 * software over-ride.
1627 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1629 case E1000_FC_RX_PAUSE: /* 1 */
1630 /* RX Flow control is enabled, and TX Flow control is
1631 * disabled, by a software over-ride.
1633 /* Since there really isn't a way to advertise that we are
1634 * capable of RX Pause ONLY, we will advertise that we
1635 * support both symmetric and asymmetric RX PAUSE. Later
1636 * (in e1000_config_fc_after_link_up) we will disable the
1637 *hw's ability to send PAUSE frames.
1639 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1641 case E1000_FC_TX_PAUSE: /* 2 */
1642 /* TX Flow control is enabled, and RX Flow control is
1643 * disabled, by a software over-ride.
1645 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1646 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1648 case E1000_FC_FULL: /* 3 */
1649 /* Flow control (both RX and TX) is enabled by a software
1652 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1655 e_dbg("Flow control param set incorrectly\n");
1656 return -E1000_ERR_CONFIG;
1659 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1663 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1665 if (hw->phy_type == e1000_phy_8201) {
1666 mii_1000t_ctrl_reg = 0;
1668 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1669 mii_1000t_ctrl_reg);
1674 return E1000_SUCCESS;
1678 * e1000_phy_force_speed_duplex - force link settings
1679 * @hw: Struct containing variables accessed by shared code
1681 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1683 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1692 e_dbg("e1000_phy_force_speed_duplex");
1694 /* Turn off Flow control if we are forcing speed and duplex. */
1695 hw->fc = E1000_FC_NONE;
1697 e_dbg("hw->fc = %d\n", hw->fc);
1699 /* Read the Device Control Register. */
1702 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1703 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1704 ctrl &= ~(DEVICE_SPEED_MASK);
1706 /* Clear the Auto Speed Detect Enable bit. */
1707 ctrl &= ~E1000_CTRL_ASDE;
1709 /* Read the MII Control Register. */
1710 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1714 /* We need to disable autoneg in order to force link and duplex. */
1716 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1718 /* Are we forcing Full or Half Duplex? */
1719 if (hw->forced_speed_duplex == e1000_100_full ||
1720 hw->forced_speed_duplex == e1000_10_full) {
1721 /* We want to force full duplex so we SET the full duplex bits in the
1722 * Device and MII Control Registers.
1724 ctrl |= E1000_CTRL_FD;
1725 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1726 e_dbg("Full Duplex\n");
1728 /* We want to force half duplex so we CLEAR the full duplex bits in
1729 * the Device and MII Control Registers.
1731 ctrl &= ~E1000_CTRL_FD;
1732 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1733 e_dbg("Half Duplex\n");
1736 /* Are we forcing 100Mbps??? */
1737 if (hw->forced_speed_duplex == e1000_100_full ||
1738 hw->forced_speed_duplex == e1000_100_half) {
1739 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1740 ctrl |= E1000_CTRL_SPD_100;
1741 mii_ctrl_reg |= MII_CR_SPEED_100;
1742 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1743 e_dbg("Forcing 100mb ");
1745 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1746 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1747 mii_ctrl_reg |= MII_CR_SPEED_10;
1748 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1749 e_dbg("Forcing 10mb ");
1752 e1000_config_collision_dist(hw);
1754 /* Write the configured values back to the Device Control Reg. */
1757 if (hw->phy_type == e1000_phy_m88) {
1759 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1763 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1764 * forced whenever speed are duplex are forced.
1766 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1768 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1772 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1774 /* Need to reset the PHY or these changes will be ignored */
1775 mii_ctrl_reg |= MII_CR_RESET;
1777 /* Disable MDI-X support for 10/100 */
1779 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1780 * forced whenever speed or duplex are forced.
1783 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1787 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1788 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1791 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1796 /* Write back the modified PHY MII control register. */
1797 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1803 /* The wait_autoneg_complete flag may be a little misleading here.
1804 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1805 * But we do want to delay for a period while forcing only so we
1806 * don't generate false No Link messages. So we will wait here
1807 * only if the user has set wait_autoneg_complete to 1, which is
1810 if (hw->wait_autoneg_complete) {
1811 /* We will wait for autoneg to complete. */
1812 e_dbg("Waiting for forced speed/duplex link.\n");
1815 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1816 for (i = PHY_FORCE_TIME; i > 0; i--) {
1817 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1821 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1826 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1830 if (mii_status_reg & MII_SR_LINK_STATUS)
1834 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1835 /* We didn't get link. Reset the DSP and wait again for link. */
1836 ret_val = e1000_phy_reset_dsp(hw);
1838 e_dbg("Error Resetting PHY DSP\n");
1842 /* This loop will early-out if the link condition has been met. */
1843 for (i = PHY_FORCE_TIME; i > 0; i--) {
1844 if (mii_status_reg & MII_SR_LINK_STATUS)
1847 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1851 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1856 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1862 if (hw->phy_type == e1000_phy_m88) {
1863 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1864 * Extended PHY Specific Control Register to 25MHz clock. This value
1865 * defaults back to a 2.5MHz clock when the PHY is reset.
1868 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1873 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1875 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1880 /* In addition, because of the s/w reset above, we need to enable CRS on
1881 * TX. This must be set for both full and half duplex operation.
1884 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1890 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1894 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1896 && (hw->forced_speed_duplex == e1000_10_full
1897 || hw->forced_speed_duplex == e1000_10_half)) {
1898 ret_val = e1000_polarity_reversal_workaround(hw);
1903 return E1000_SUCCESS;
1907 * e1000_config_collision_dist - set collision distance register
1908 * @hw: Struct containing variables accessed by shared code
1910 * Sets the collision distance in the Transmit Control register.
1911 * Link should have been established previously. Reads the speed and duplex
1912 * information from the Device Status register.
1914 void e1000_config_collision_dist(struct e1000_hw *hw)
1916 u32 tctl, coll_dist;
1918 e_dbg("e1000_config_collision_dist");
1920 if (hw->mac_type < e1000_82543)
1921 coll_dist = E1000_COLLISION_DISTANCE_82542;
1923 coll_dist = E1000_COLLISION_DISTANCE;
1927 tctl &= ~E1000_TCTL_COLD;
1928 tctl |= coll_dist << E1000_COLD_SHIFT;
1931 E1000_WRITE_FLUSH();
1935 * e1000_config_mac_to_phy - sync phy and mac settings
1936 * @hw: Struct containing variables accessed by shared code
1937 * @mii_reg: data to write to the MII control register
1939 * Sets MAC speed and duplex settings to reflect the those in the PHY
1940 * The contents of the PHY register containing the needed information need to
1943 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1949 e_dbg("e1000_config_mac_to_phy");
1951 /* 82544 or newer MAC, Auto Speed Detection takes care of
1952 * MAC speed/duplex configuration.*/
1953 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1954 return E1000_SUCCESS;
1956 /* Read the Device Control Register and set the bits to Force Speed
1960 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1961 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1963 switch (hw->phy_type) {
1964 case e1000_phy_8201:
1965 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1969 if (phy_data & RTL_PHY_CTRL_FD)
1970 ctrl |= E1000_CTRL_FD;
1972 ctrl &= ~E1000_CTRL_FD;
1974 if (phy_data & RTL_PHY_CTRL_SPD_100)
1975 ctrl |= E1000_CTRL_SPD_100;
1977 ctrl |= E1000_CTRL_SPD_10;
1979 e1000_config_collision_dist(hw);
1982 /* Set up duplex in the Device Control and Transmit Control
1983 * registers depending on negotiated values.
1985 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1990 if (phy_data & M88E1000_PSSR_DPLX)
1991 ctrl |= E1000_CTRL_FD;
1993 ctrl &= ~E1000_CTRL_FD;
1995 e1000_config_collision_dist(hw);
1997 /* Set up speed in the Device Control register depending on
1998 * negotiated values.
2000 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2001 ctrl |= E1000_CTRL_SPD_1000;
2002 else if ((phy_data & M88E1000_PSSR_SPEED) ==
2003 M88E1000_PSSR_100MBS)
2004 ctrl |= E1000_CTRL_SPD_100;
2007 /* Write the configured values back to the Device Control Reg. */
2009 return E1000_SUCCESS;
2013 * e1000_force_mac_fc - force flow control settings
2014 * @hw: Struct containing variables accessed by shared code
2016 * Forces the MAC's flow control settings.
2017 * Sets the TFCE and RFCE bits in the device control register to reflect
2018 * the adapter settings. TFCE and RFCE need to be explicitly set by
2019 * software when a Copper PHY is used because autonegotiation is managed
2020 * by the PHY rather than the MAC. Software must also configure these
2021 * bits when link is forced on a fiber connection.
2023 s32 e1000_force_mac_fc(struct e1000_hw *hw)
2027 e_dbg("e1000_force_mac_fc");
2029 /* Get the current configuration of the Device Control Register */
2032 /* Because we didn't get link via the internal auto-negotiation
2033 * mechanism (we either forced link or we got link via PHY
2034 * auto-neg), we have to manually enable/disable transmit an
2035 * receive flow control.
2037 * The "Case" statement below enables/disable flow control
2038 * according to the "hw->fc" parameter.
2040 * The possible values of the "fc" parameter are:
2041 * 0: Flow control is completely disabled
2042 * 1: Rx flow control is enabled (we can receive pause
2043 * frames but not send pause frames).
2044 * 2: Tx flow control is enabled (we can send pause frames
2045 * frames but we do not receive pause frames).
2046 * 3: Both Rx and TX flow control (symmetric) is enabled.
2047 * other: No other values should be possible at this point.
2052 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2054 case E1000_FC_RX_PAUSE:
2055 ctrl &= (~E1000_CTRL_TFCE);
2056 ctrl |= E1000_CTRL_RFCE;
2058 case E1000_FC_TX_PAUSE:
2059 ctrl &= (~E1000_CTRL_RFCE);
2060 ctrl |= E1000_CTRL_TFCE;
2063 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2066 e_dbg("Flow control param set incorrectly\n");
2067 return -E1000_ERR_CONFIG;
2070 /* Disable TX Flow Control for 82542 (rev 2.0) */
2071 if (hw->mac_type == e1000_82542_rev2_0)
2072 ctrl &= (~E1000_CTRL_TFCE);
2075 return E1000_SUCCESS;
2079 * e1000_config_fc_after_link_up - configure flow control after autoneg
2080 * @hw: Struct containing variables accessed by shared code
2082 * Configures flow control settings after link is established
2083 * Should be called immediately after a valid link has been established.
2084 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2085 * and autonegotiation is enabled, the MAC flow control settings will be set
2086 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2087 * and RFCE bits will be automatically set to the negotiated flow control mode.
2089 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2093 u16 mii_nway_adv_reg;
2094 u16 mii_nway_lp_ability_reg;
2098 e_dbg("e1000_config_fc_after_link_up");
2100 /* Check for the case where we have fiber media and auto-neg failed
2101 * so we had to force link. In this case, we need to force the
2102 * configuration of the MAC to match the "fc" parameter.
2104 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2105 || ((hw->media_type == e1000_media_type_internal_serdes)
2106 && (hw->autoneg_failed))
2107 || ((hw->media_type == e1000_media_type_copper)
2108 && (!hw->autoneg))) {
2109 ret_val = e1000_force_mac_fc(hw);
2111 e_dbg("Error forcing flow control settings\n");
2116 /* Check for the case where we have copper media and auto-neg is
2117 * enabled. In this case, we need to check and see if Auto-Neg
2118 * has completed, and if so, how the PHY and link partner has
2119 * flow control configured.
2121 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2122 /* Read the MII Status Register and check to see if AutoNeg
2123 * has completed. We read this twice because this reg has
2124 * some "sticky" (latched) bits.
2126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2133 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2134 /* The AutoNeg process has completed, so we now need to
2135 * read both the Auto Negotiation Advertisement Register
2136 * (Address 4) and the Auto_Negotiation Base Page Ability
2137 * Register (Address 5) to determine how flow control was
2140 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2144 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2145 &mii_nway_lp_ability_reg);
2149 /* Two bits in the Auto Negotiation Advertisement Register
2150 * (Address 4) and two bits in the Auto Negotiation Base
2151 * Page Ability Register (Address 5) determine flow control
2152 * for both the PHY and the link partner. The following
2153 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2154 * 1999, describes these PAUSE resolution bits and how flow
2155 * control is determined based upon these settings.
2156 * NOTE: DC = Don't Care
2158 * LOCAL DEVICE | LINK PARTNER
2159 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2160 *-------|---------|-------|---------|--------------------
2161 * 0 | 0 | DC | DC | E1000_FC_NONE
2162 * 0 | 1 | 0 | DC | E1000_FC_NONE
2163 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2164 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2165 * 1 | 0 | 0 | DC | E1000_FC_NONE
2166 * 1 | DC | 1 | DC | E1000_FC_FULL
2167 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2168 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2171 /* Are both PAUSE bits set to 1? If so, this implies
2172 * Symmetric Flow Control is enabled at both ends. The
2173 * ASM_DIR bits are irrelevant per the spec.
2175 * For Symmetric Flow Control:
2177 * LOCAL DEVICE | LINK PARTNER
2178 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2179 *-------|---------|-------|---------|--------------------
2180 * 1 | DC | 1 | DC | E1000_FC_FULL
2183 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2184 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2185 /* Now we need to check if the user selected RX ONLY
2186 * of pause frames. In this case, we had to advertise
2187 * FULL flow control because we could not advertise RX
2188 * ONLY. Hence, we must now check to see if we need to
2189 * turn OFF the TRANSMISSION of PAUSE frames.
2191 if (hw->original_fc == E1000_FC_FULL) {
2192 hw->fc = E1000_FC_FULL;
2193 e_dbg("Flow Control = FULL.\n");
2195 hw->fc = E1000_FC_RX_PAUSE;
2197 ("Flow Control = RX PAUSE frames only.\n");
2200 /* For receiving PAUSE frames ONLY.
2202 * LOCAL DEVICE | LINK PARTNER
2203 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2204 *-------|---------|-------|---------|--------------------
2205 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2208 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2209 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2210 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2211 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2213 hw->fc = E1000_FC_TX_PAUSE;
2215 ("Flow Control = TX PAUSE frames only.\n");
2217 /* For transmitting PAUSE frames ONLY.
2219 * LOCAL DEVICE | LINK PARTNER
2220 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2221 *-------|---------|-------|---------|--------------------
2222 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2225 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2226 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2227 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2228 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2230 hw->fc = E1000_FC_RX_PAUSE;
2232 ("Flow Control = RX PAUSE frames only.\n");
2234 /* Per the IEEE spec, at this point flow control should be
2235 * disabled. However, we want to consider that we could
2236 * be connected to a legacy switch that doesn't advertise
2237 * desired flow control, but can be forced on the link
2238 * partner. So if we advertised no flow control, that is
2239 * what we will resolve to. If we advertised some kind of
2240 * receive capability (Rx Pause Only or Full Flow Control)
2241 * and the link partner advertised none, we will configure
2242 * ourselves to enable Rx Flow Control only. We can do
2243 * this safely for two reasons: If the link partner really
2244 * didn't want flow control enabled, and we enable Rx, no
2245 * harm done since we won't be receiving any PAUSE frames
2246 * anyway. If the intent on the link partner was to have
2247 * flow control enabled, then by us enabling RX only, we
2248 * can at least receive pause frames and process them.
2249 * This is a good idea because in most cases, since we are
2250 * predominantly a server NIC, more times than not we will
2251 * be asked to delay transmission of packets than asking
2252 * our link partner to pause transmission of frames.
2254 else if ((hw->original_fc == E1000_FC_NONE ||
2255 hw->original_fc == E1000_FC_TX_PAUSE) ||
2256 hw->fc_strict_ieee) {
2257 hw->fc = E1000_FC_NONE;
2258 e_dbg("Flow Control = NONE.\n");
2260 hw->fc = E1000_FC_RX_PAUSE;
2262 ("Flow Control = RX PAUSE frames only.\n");
2265 /* Now we need to do one last check... If we auto-
2266 * negotiated to HALF DUPLEX, flow control should not be
2267 * enabled per IEEE 802.3 spec.
2270 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2273 ("Error getting link speed and duplex\n");
2277 if (duplex == HALF_DUPLEX)
2278 hw->fc = E1000_FC_NONE;
2280 /* Now we call a subroutine to actually force the MAC
2281 * controller to use the correct flow control settings.
2283 ret_val = e1000_force_mac_fc(hw);
2286 ("Error forcing flow control settings\n");
2291 ("Copper PHY and Auto Neg has not completed.\n");
2294 return E1000_SUCCESS;
2298 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2299 * @hw: pointer to the HW structure
2301 * Checks for link up on the hardware. If link is not up and we have
2302 * a signal, then we need to force link up.
2304 static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2309 s32 ret_val = E1000_SUCCESS;
2311 e_dbg("e1000_check_for_serdes_link_generic");
2314 status = er32(STATUS);
2318 * If we don't have link (auto-negotiation failed or link partner
2319 * cannot auto-negotiate), and our link partner is not trying to
2320 * auto-negotiate with us (we are receiving idles or data),
2321 * we need to force link up. We also need to give auto-negotiation
2324 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2325 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2326 if (hw->autoneg_failed == 0) {
2327 hw->autoneg_failed = 1;
2330 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2332 /* Disable auto-negotiation in the TXCW register */
2333 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2335 /* Force link-up and also force full-duplex. */
2337 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2340 /* Configure Flow Control after forcing link up. */
2341 ret_val = e1000_config_fc_after_link_up(hw);
2343 e_dbg("Error configuring flow control\n");
2346 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2348 * If we are forcing link and we are receiving /C/ ordered
2349 * sets, re-enable auto-negotiation in the TXCW register
2350 * and disable forced link in the Device Control register
2351 * in an attempt to auto-negotiate with our link partner.
2353 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2354 ew32(TXCW, hw->txcw);
2355 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2357 hw->serdes_has_link = true;
2358 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2360 * If we force link for non-auto-negotiation switch, check
2361 * link status based on MAC synchronization for internal
2362 * serdes media type.
2364 /* SYNCH bit and IV bit are sticky. */
2367 if (rxcw & E1000_RXCW_SYNCH) {
2368 if (!(rxcw & E1000_RXCW_IV)) {
2369 hw->serdes_has_link = true;
2370 e_dbg("SERDES: Link up - forced.\n");
2373 hw->serdes_has_link = false;
2374 e_dbg("SERDES: Link down - force failed.\n");
2378 if (E1000_TXCW_ANE & er32(TXCW)) {
2379 status = er32(STATUS);
2380 if (status & E1000_STATUS_LU) {
2381 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2384 if (rxcw & E1000_RXCW_SYNCH) {
2385 if (!(rxcw & E1000_RXCW_IV)) {
2386 hw->serdes_has_link = true;
2387 e_dbg("SERDES: Link up - autoneg "
2388 "completed successfully.\n");
2390 hw->serdes_has_link = false;
2391 e_dbg("SERDES: Link down - invalid"
2392 "codewords detected in autoneg.\n");
2395 hw->serdes_has_link = false;
2396 e_dbg("SERDES: Link down - no sync.\n");
2399 hw->serdes_has_link = false;
2400 e_dbg("SERDES: Link down - autoneg failed\n");
2409 * e1000_check_for_link
2410 * @hw: Struct containing variables accessed by shared code
2412 * Checks to see if the link status of the hardware has changed.
2413 * Called by any function that needs to check the link status of the adapter.
2415 s32 e1000_check_for_link(struct e1000_hw *hw)
2426 e_dbg("e1000_check_for_link");
2429 status = er32(STATUS);
2431 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2432 * set when the optics detect a signal. On older adapters, it will be
2433 * cleared when there is a signal. This applies to fiber media only.
2435 if ((hw->media_type == e1000_media_type_fiber) ||
2436 (hw->media_type == e1000_media_type_internal_serdes)) {
2439 if (hw->media_type == e1000_media_type_fiber) {
2442 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2443 if (status & E1000_STATUS_LU)
2444 hw->get_link_status = false;
2448 /* If we have a copper PHY then we only want to go out to the PHY
2449 * registers to see if Auto-Neg has completed and/or if our link
2450 * status has changed. The get_link_status flag will be set if we
2451 * receive a Link Status Change interrupt or we have Rx Sequence
2454 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2455 /* First we want to see if the MII Status Register reports
2456 * link. If so, then we want to get the current speed/duplex
2458 * Read the register twice since the link bit is sticky.
2460 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2467 if (phy_data & MII_SR_LINK_STATUS) {
2468 hw->get_link_status = false;
2469 /* Check if there was DownShift, must be checked immediately after
2471 e1000_check_downshift(hw);
2473 /* If we are on 82544 or 82543 silicon and speed/duplex
2474 * are forced to 10H or 10F, then we will implement the polarity
2475 * reversal workaround. We disable interrupts first, and upon
2476 * returning, place the devices interrupt state to its previous
2477 * value except for the link status change interrupt which will
2478 * happen due to the execution of this workaround.
2481 if ((hw->mac_type == e1000_82544
2482 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2483 && (hw->forced_speed_duplex == e1000_10_full
2484 || hw->forced_speed_duplex == e1000_10_half)) {
2485 ew32(IMC, 0xffffffff);
2487 e1000_polarity_reversal_workaround(hw);
2489 ew32(ICS, (icr & ~E1000_ICS_LSC));
2490 ew32(IMS, IMS_ENABLE_MASK);
2494 /* No link detected */
2495 e1000_config_dsp_after_link_change(hw, false);
2499 /* If we are forcing speed/duplex, then we simply return since
2500 * we have already determined whether we have link or not.
2503 return -E1000_ERR_CONFIG;
2505 /* optimize the dsp settings for the igp phy */
2506 e1000_config_dsp_after_link_change(hw, true);
2508 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2509 * have Si on board that is 82544 or newer, Auto
2510 * Speed Detection takes care of MAC speed/duplex
2511 * configuration. So we only need to configure Collision
2512 * Distance in the MAC. Otherwise, we need to force
2513 * speed/duplex on the MAC to the current PHY speed/duplex
2516 if ((hw->mac_type >= e1000_82544) &&
2517 (hw->mac_type != e1000_ce4100))
2518 e1000_config_collision_dist(hw);
2520 ret_val = e1000_config_mac_to_phy(hw);
2523 ("Error configuring MAC to PHY settings\n");
2528 /* Configure Flow Control now that Auto-Neg has completed. First, we
2529 * need to restore the desired flow control settings because we may
2530 * have had to re-autoneg with a different link partner.
2532 ret_val = e1000_config_fc_after_link_up(hw);
2534 e_dbg("Error configuring flow control\n");
2538 /* At this point we know that we are on copper and we have
2539 * auto-negotiated link. These are conditions for checking the link
2540 * partner capability register. We use the link speed to determine if
2541 * TBI compatibility needs to be turned on or off. If the link is not
2542 * at gigabit speed, then TBI compatibility is not needed. If we are
2543 * at gigabit speed, we turn on TBI compatibility.
2545 if (hw->tbi_compatibility_en) {
2548 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2551 ("Error getting link speed and duplex\n");
2554 if (speed != SPEED_1000) {
2555 /* If link speed is not set to gigabit speed, we do not need
2556 * to enable TBI compatibility.
2558 if (hw->tbi_compatibility_on) {
2559 /* If we previously were in the mode, turn it off. */
2561 rctl &= ~E1000_RCTL_SBP;
2563 hw->tbi_compatibility_on = false;
2566 /* If TBI compatibility is was previously off, turn it on. For
2567 * compatibility with a TBI link partner, we will store bad
2568 * packets. Some frames have an additional byte on the end and
2569 * will look like CRC errors to to the hardware.
2571 if (!hw->tbi_compatibility_on) {
2572 hw->tbi_compatibility_on = true;
2574 rctl |= E1000_RCTL_SBP;
2581 if ((hw->media_type == e1000_media_type_fiber) ||
2582 (hw->media_type == e1000_media_type_internal_serdes))
2583 e1000_check_for_serdes_link_generic(hw);
2585 return E1000_SUCCESS;
2589 * e1000_get_speed_and_duplex
2590 * @hw: Struct containing variables accessed by shared code
2591 * @speed: Speed of the connection
2592 * @duplex: Duplex setting of the connection
2594 * Detects the current speed and duplex settings of the hardware.
2596 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2602 e_dbg("e1000_get_speed_and_duplex");
2604 if (hw->mac_type >= e1000_82543) {
2605 status = er32(STATUS);
2606 if (status & E1000_STATUS_SPEED_1000) {
2607 *speed = SPEED_1000;
2608 e_dbg("1000 Mbs, ");
2609 } else if (status & E1000_STATUS_SPEED_100) {
2617 if (status & E1000_STATUS_FD) {
2618 *duplex = FULL_DUPLEX;
2619 e_dbg("Full Duplex\n");
2621 *duplex = HALF_DUPLEX;
2622 e_dbg(" Half Duplex\n");
2625 e_dbg("1000 Mbs, Full Duplex\n");
2626 *speed = SPEED_1000;
2627 *duplex = FULL_DUPLEX;
2630 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2631 * if it is operating at half duplex. Here we set the duplex settings to
2632 * match the duplex in the link partner's capabilities.
2634 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2635 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2639 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2640 *duplex = HALF_DUPLEX;
2643 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2646 if ((*speed == SPEED_100
2647 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2648 || (*speed == SPEED_10
2649 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2650 *duplex = HALF_DUPLEX;
2654 return E1000_SUCCESS;
2658 * e1000_wait_autoneg
2659 * @hw: Struct containing variables accessed by shared code
2661 * Blocks until autoneg completes or times out (~4.5 seconds)
2663 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2669 e_dbg("e1000_wait_autoneg");
2670 e_dbg("Waiting for Auto-Neg to complete.\n");
2672 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2673 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2674 /* Read the MII Status Register and wait for Auto-Neg
2675 * Complete bit to be set.
2677 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2680 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2683 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2684 return E1000_SUCCESS;
2688 return E1000_SUCCESS;
2692 * e1000_raise_mdi_clk - Raises the Management Data Clock
2693 * @hw: Struct containing variables accessed by shared code
2694 * @ctrl: Device control register's current value
2696 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2698 /* Raise the clock input to the Management Data Clock (by setting the MDC
2699 * bit), and then delay 10 microseconds.
2701 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2702 E1000_WRITE_FLUSH();
2707 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2708 * @hw: Struct containing variables accessed by shared code
2709 * @ctrl: Device control register's current value
2711 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2713 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2714 * bit), and then delay 10 microseconds.
2716 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2717 E1000_WRITE_FLUSH();
2722 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2723 * @hw: Struct containing variables accessed by shared code
2724 * @data: Data to send out to the PHY
2725 * @count: Number of bits to shift out
2727 * Bits are shifted out in MSB to LSB order.
2729 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2734 /* We need to shift "count" number of bits out to the PHY. So, the value
2735 * in the "data" parameter will be shifted out to the PHY one bit at a
2736 * time. In order to do this, "data" must be broken down into bits.
2739 mask <<= (count - 1);
2743 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2744 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2747 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2748 * then raising and lowering the Management Data Clock. A "0" is
2749 * shifted out to the PHY by setting the MDIO bit to "0" and then
2750 * raising and lowering the clock.
2753 ctrl |= E1000_CTRL_MDIO;
2755 ctrl &= ~E1000_CTRL_MDIO;
2758 E1000_WRITE_FLUSH();
2762 e1000_raise_mdi_clk(hw, &ctrl);
2763 e1000_lower_mdi_clk(hw, &ctrl);
2770 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2771 * @hw: Struct containing variables accessed by shared code
2773 * Bits are shifted in in MSB to LSB order.
2775 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2781 /* In order to read a register from the PHY, we need to shift in a total
2782 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2783 * to avoid contention on the MDIO pin when a read operation is performed.
2784 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2785 * by raising the input to the Management Data Clock (setting the MDC bit),
2786 * and then reading the value of the MDIO bit.
2790 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2791 ctrl &= ~E1000_CTRL_MDIO_DIR;
2792 ctrl &= ~E1000_CTRL_MDIO;
2795 E1000_WRITE_FLUSH();
2797 /* Raise and Lower the clock before reading in the data. This accounts for
2798 * the turnaround bits. The first clock occurred when we clocked out the
2799 * last bit of the Register Address.
2801 e1000_raise_mdi_clk(hw, &ctrl);
2802 e1000_lower_mdi_clk(hw, &ctrl);
2804 for (data = 0, i = 0; i < 16; i++) {
2806 e1000_raise_mdi_clk(hw, &ctrl);
2808 /* Check to see if we shifted in a "1". */
2809 if (ctrl & E1000_CTRL_MDIO)
2811 e1000_lower_mdi_clk(hw, &ctrl);
2814 e1000_raise_mdi_clk(hw, &ctrl);
2815 e1000_lower_mdi_clk(hw, &ctrl);
2822 * e1000_read_phy_reg - read a phy register
2823 * @hw: Struct containing variables accessed by shared code
2824 * @reg_addr: address of the PHY register to read
2826 * Reads the value from a PHY register, if the value is on a specific non zero
2827 * page, sets the page first.
2829 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2833 e_dbg("e1000_read_phy_reg");
2835 if ((hw->phy_type == e1000_phy_igp) &&
2836 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2837 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2843 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2849 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2854 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2856 e_dbg("e1000_read_phy_reg_ex");
2858 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2859 e_dbg("PHY Address %d is out of range\n", reg_addr);
2860 return -E1000_ERR_PARAM;
2863 if (hw->mac_type > e1000_82543) {
2864 /* Set up Op-code, Phy Address, and register address in the MDI
2865 * Control register. The MAC will take care of interfacing with the
2866 * PHY to retrieve the desired data.
2868 if (hw->mac_type == e1000_ce4100) {
2869 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2870 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2871 (INTEL_CE_GBE_MDIC_OP_READ) |
2872 (INTEL_CE_GBE_MDIC_GO));
2874 writel(mdic, E1000_MDIO_CMD);
2876 /* Poll the ready bit to see if the MDI read
2879 for (i = 0; i < 64; i++) {
2881 mdic = readl(E1000_MDIO_CMD);
2882 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2886 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2887 e_dbg("MDI Read did not complete\n");
2888 return -E1000_ERR_PHY;
2891 mdic = readl(E1000_MDIO_STS);
2892 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2893 e_dbg("MDI Read Error\n");
2894 return -E1000_ERR_PHY;
2896 *phy_data = (u16) mdic;
2898 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2899 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2900 (E1000_MDIC_OP_READ));
2904 /* Poll the ready bit to see if the MDI read
2907 for (i = 0; i < 64; i++) {
2910 if (mdic & E1000_MDIC_READY)
2913 if (!(mdic & E1000_MDIC_READY)) {
2914 e_dbg("MDI Read did not complete\n");
2915 return -E1000_ERR_PHY;
2917 if (mdic & E1000_MDIC_ERROR) {
2918 e_dbg("MDI Error\n");
2919 return -E1000_ERR_PHY;
2921 *phy_data = (u16) mdic;
2924 /* We must first send a preamble through the MDIO pin to signal the
2925 * beginning of an MII instruction. This is done by sending 32
2926 * consecutive "1" bits.
2928 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2930 /* Now combine the next few fields that are required for a read
2931 * operation. We use this method instead of calling the
2932 * e1000_shift_out_mdi_bits routine five different times. The format of
2933 * a MII read instruction consists of a shift out of 14 bits and is
2934 * defined as follows:
2935 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2936 * followed by a shift in of 18 bits. This first two bits shifted in
2937 * are TurnAround bits used to avoid contention on the MDIO pin when a
2938 * READ operation is performed. These two bits are thrown away
2939 * followed by a shift in of 16 bits which contains the desired data.
2941 mdic = ((reg_addr) | (phy_addr << 5) |
2942 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2944 e1000_shift_out_mdi_bits(hw, mdic, 14);
2946 /* Now that we've shifted out the read command to the MII, we need to
2947 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2950 *phy_data = e1000_shift_in_mdi_bits(hw);
2952 return E1000_SUCCESS;
2956 * e1000_write_phy_reg - write a phy register
2958 * @hw: Struct containing variables accessed by shared code
2959 * @reg_addr: address of the PHY register to write
2960 * @data: data to write to the PHY
2962 * Writes a value to a PHY register
2964 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2968 e_dbg("e1000_write_phy_reg");
2970 if ((hw->phy_type == e1000_phy_igp) &&
2971 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2972 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2978 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2984 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2989 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2991 e_dbg("e1000_write_phy_reg_ex");
2993 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2994 e_dbg("PHY Address %d is out of range\n", reg_addr);
2995 return -E1000_ERR_PARAM;
2998 if (hw->mac_type > e1000_82543) {
2999 /* Set up Op-code, Phy Address, register address, and data
3000 * intended for the PHY register in the MDI Control register.
3001 * The MAC will take care of interfacing with the PHY to send
3004 if (hw->mac_type == e1000_ce4100) {
3005 mdic = (((u32) phy_data) |
3006 (reg_addr << E1000_MDIC_REG_SHIFT) |
3007 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3008 (INTEL_CE_GBE_MDIC_OP_WRITE) |
3009 (INTEL_CE_GBE_MDIC_GO));
3011 writel(mdic, E1000_MDIO_CMD);
3013 /* Poll the ready bit to see if the MDI read
3016 for (i = 0; i < 640; i++) {
3018 mdic = readl(E1000_MDIO_CMD);
3019 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3022 if (mdic & INTEL_CE_GBE_MDIC_GO) {
3023 e_dbg("MDI Write did not complete\n");
3024 return -E1000_ERR_PHY;
3027 mdic = (((u32) phy_data) |
3028 (reg_addr << E1000_MDIC_REG_SHIFT) |
3029 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3030 (E1000_MDIC_OP_WRITE));
3034 /* Poll the ready bit to see if the MDI read
3037 for (i = 0; i < 641; i++) {
3040 if (mdic & E1000_MDIC_READY)
3043 if (!(mdic & E1000_MDIC_READY)) {
3044 e_dbg("MDI Write did not complete\n");
3045 return -E1000_ERR_PHY;
3049 /* We'll need to use the SW defined pins to shift the write command
3050 * out to the PHY. We first send a preamble to the PHY to signal the
3051 * beginning of the MII instruction. This is done by sending 32
3052 * consecutive "1" bits.
3054 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3056 /* Now combine the remaining required fields that will indicate a
3057 * write operation. We use this method instead of calling the
3058 * e1000_shift_out_mdi_bits routine for each field in the command. The
3059 * format of a MII write instruction is as follows:
3060 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3062 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3063 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3065 mdic |= (u32) phy_data;
3067 e1000_shift_out_mdi_bits(hw, mdic, 32);
3070 return E1000_SUCCESS;
3074 * e1000_phy_hw_reset - reset the phy, hardware style
3075 * @hw: Struct containing variables accessed by shared code
3077 * Returns the PHY to the power-on reset state
3079 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3084 e_dbg("e1000_phy_hw_reset");
3086 e_dbg("Resetting Phy...\n");
3088 if (hw->mac_type > e1000_82543) {
3089 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3090 * bit. Then, take it out of reset.
3091 * For e1000 hardware, we delay for 10ms between the assert
3095 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3096 E1000_WRITE_FLUSH();
3101 E1000_WRITE_FLUSH();
3104 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3105 * bit to put the PHY into reset. Then, take it out of reset.
3107 ctrl_ext = er32(CTRL_EXT);
3108 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3109 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3110 ew32(CTRL_EXT, ctrl_ext);
3111 E1000_WRITE_FLUSH();
3113 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3114 ew32(CTRL_EXT, ctrl_ext);
3115 E1000_WRITE_FLUSH();
3119 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3120 /* Configure activity LED after PHY reset */
3121 led_ctrl = er32(LEDCTL);
3122 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3123 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3124 ew32(LEDCTL, led_ctrl);
3127 /* Wait for FW to finish PHY configuration. */
3128 return e1000_get_phy_cfg_done(hw);
3132 * e1000_phy_reset - reset the phy to commit settings
3133 * @hw: Struct containing variables accessed by shared code
3136 * Sets bit 15 of the MII Control register
3138 s32 e1000_phy_reset(struct e1000_hw *hw)
3143 e_dbg("e1000_phy_reset");
3145 switch (hw->phy_type) {
3147 ret_val = e1000_phy_hw_reset(hw);
3152 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3156 phy_data |= MII_CR_RESET;
3157 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3165 if (hw->phy_type == e1000_phy_igp)
3166 e1000_phy_init_script(hw);
3168 return E1000_SUCCESS;
3172 * e1000_detect_gig_phy - check the phy type
3173 * @hw: Struct containing variables accessed by shared code
3175 * Probes the expected PHY address for known PHY IDs
3177 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3179 s32 phy_init_status, ret_val;
3180 u16 phy_id_high, phy_id_low;
3183 e_dbg("e1000_detect_gig_phy");
3185 if (hw->phy_id != 0)
3186 return E1000_SUCCESS;
3188 /* Read the PHY ID Registers to identify which PHY is onboard. */
3189 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3193 hw->phy_id = (u32) (phy_id_high << 16);
3195 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3199 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3200 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3202 switch (hw->mac_type) {
3204 if (hw->phy_id == M88E1000_E_PHY_ID)
3208 if (hw->phy_id == M88E1000_I_PHY_ID)
3213 case e1000_82545_rev_3:
3215 case e1000_82546_rev_3:
3216 if (hw->phy_id == M88E1011_I_PHY_ID)
3220 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3221 (hw->phy_id == RTL8201N_PHY_ID) ||
3222 (hw->phy_id == M88E1118_E_PHY_ID))
3226 case e1000_82541_rev_2:
3228 case e1000_82547_rev_2:
3229 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3233 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3234 return -E1000_ERR_CONFIG;
3236 phy_init_status = e1000_set_phy_type(hw);
3238 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3239 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3240 return E1000_SUCCESS;
3242 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3243 return -E1000_ERR_PHY;
3247 * e1000_phy_reset_dsp - reset DSP
3248 * @hw: Struct containing variables accessed by shared code
3250 * Resets the PHY's DSP
3252 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3255 e_dbg("e1000_phy_reset_dsp");
3258 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3261 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3264 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3267 ret_val = E1000_SUCCESS;
3274 * e1000_phy_igp_get_info - get igp specific registers
3275 * @hw: Struct containing variables accessed by shared code
3276 * @phy_info: PHY information structure
3278 * Get PHY information from various PHY registers for igp PHY only.
3280 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3281 struct e1000_phy_info *phy_info)
3284 u16 phy_data, min_length, max_length, average;
3285 e1000_rev_polarity polarity;
3287 e_dbg("e1000_phy_igp_get_info");
3289 /* The downshift status is checked only once, after link is established,
3290 * and it stored in the hw->speed_downgraded parameter. */
3291 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3293 /* IGP01E1000 does not need to support it. */
3294 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3296 /* IGP01E1000 always correct polarity reversal */
3297 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3299 /* Check polarity status */
3300 ret_val = e1000_check_polarity(hw, &polarity);
3304 phy_info->cable_polarity = polarity;
3306 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3310 phy_info->mdix_mode =
3311 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3312 IGP01E1000_PSSR_MDIX_SHIFT);
3314 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3315 IGP01E1000_PSSR_SPEED_1000MBPS) {
3316 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3317 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3321 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3322 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3323 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3324 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3325 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3326 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3328 /* Get cable length */
3329 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3333 /* Translate to old method */
3334 average = (max_length + min_length) / 2;
3336 if (average <= e1000_igp_cable_length_50)
3337 phy_info->cable_length = e1000_cable_length_50;
3338 else if (average <= e1000_igp_cable_length_80)
3339 phy_info->cable_length = e1000_cable_length_50_80;
3340 else if (average <= e1000_igp_cable_length_110)
3341 phy_info->cable_length = e1000_cable_length_80_110;
3342 else if (average <= e1000_igp_cable_length_140)
3343 phy_info->cable_length = e1000_cable_length_110_140;
3345 phy_info->cable_length = e1000_cable_length_140;
3348 return E1000_SUCCESS;
3352 * e1000_phy_m88_get_info - get m88 specific registers
3353 * @hw: Struct containing variables accessed by shared code
3354 * @phy_info: PHY information structure
3356 * Get PHY information from various PHY registers for m88 PHY only.
3358 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3359 struct e1000_phy_info *phy_info)
3363 e1000_rev_polarity polarity;
3365 e_dbg("e1000_phy_m88_get_info");
3367 /* The downshift status is checked only once, after link is established,
3368 * and it stored in the hw->speed_downgraded parameter. */
3369 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3371 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3375 phy_info->extended_10bt_distance =
3376 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3377 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3378 e1000_10bt_ext_dist_enable_lower :
3379 e1000_10bt_ext_dist_enable_normal;
3381 phy_info->polarity_correction =
3382 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3383 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3384 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3386 /* Check polarity status */
3387 ret_val = e1000_check_polarity(hw, &polarity);
3390 phy_info->cable_polarity = polarity;
3392 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3396 phy_info->mdix_mode =
3397 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3398 M88E1000_PSSR_MDIX_SHIFT);
3400 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3401 /* Cable Length Estimation and Local/Remote Receiver Information
3402 * are only valid at 1000 Mbps.
3404 phy_info->cable_length =
3405 (e1000_cable_length) ((phy_data &
3406 M88E1000_PSSR_CABLE_LENGTH) >>
3407 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3409 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3413 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3414 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3415 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3416 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3417 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3418 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3422 return E1000_SUCCESS;
3426 * e1000_phy_get_info - request phy info
3427 * @hw: Struct containing variables accessed by shared code
3428 * @phy_info: PHY information structure
3430 * Get PHY information from various PHY registers
3432 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3437 e_dbg("e1000_phy_get_info");
3439 phy_info->cable_length = e1000_cable_length_undefined;
3440 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3441 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3442 phy_info->downshift = e1000_downshift_undefined;
3443 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3444 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3445 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3446 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3448 if (hw->media_type != e1000_media_type_copper) {
3449 e_dbg("PHY info is only valid for copper media\n");
3450 return -E1000_ERR_CONFIG;
3453 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3457 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3461 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3462 e_dbg("PHY info is only valid if link is up\n");
3463 return -E1000_ERR_CONFIG;
3466 if (hw->phy_type == e1000_phy_igp)
3467 return e1000_phy_igp_get_info(hw, phy_info);
3468 else if ((hw->phy_type == e1000_phy_8211) ||
3469 (hw->phy_type == e1000_phy_8201))
3470 return E1000_SUCCESS;
3472 return e1000_phy_m88_get_info(hw, phy_info);
3475 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3477 e_dbg("e1000_validate_mdi_settings");
3479 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3480 e_dbg("Invalid MDI setting detected\n");
3482 return -E1000_ERR_CONFIG;
3484 return E1000_SUCCESS;
3488 * e1000_init_eeprom_params - initialize sw eeprom vars
3489 * @hw: Struct containing variables accessed by shared code
3491 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3494 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3496 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3497 u32 eecd = er32(EECD);
3498 s32 ret_val = E1000_SUCCESS;
3501 e_dbg("e1000_init_eeprom_params");
3503 switch (hw->mac_type) {
3504 case e1000_82542_rev2_0:
3505 case e1000_82542_rev2_1:
3508 eeprom->type = e1000_eeprom_microwire;
3509 eeprom->word_size = 64;
3510 eeprom->opcode_bits = 3;
3511 eeprom->address_bits = 6;
3512 eeprom->delay_usec = 50;
3516 case e1000_82545_rev_3:
3518 case e1000_82546_rev_3:
3519 eeprom->type = e1000_eeprom_microwire;
3520 eeprom->opcode_bits = 3;
3521 eeprom->delay_usec = 50;
3522 if (eecd & E1000_EECD_SIZE) {
3523 eeprom->word_size = 256;
3524 eeprom->address_bits = 8;
3526 eeprom->word_size = 64;
3527 eeprom->address_bits = 6;
3531 case e1000_82541_rev_2:
3533 case e1000_82547_rev_2:
3534 if (eecd & E1000_EECD_TYPE) {
3535 eeprom->type = e1000_eeprom_spi;
3536 eeprom->opcode_bits = 8;
3537 eeprom->delay_usec = 1;
3538 if (eecd & E1000_EECD_ADDR_BITS) {
3539 eeprom->page_size = 32;
3540 eeprom->address_bits = 16;
3542 eeprom->page_size = 8;
3543 eeprom->address_bits = 8;
3546 eeprom->type = e1000_eeprom_microwire;
3547 eeprom->opcode_bits = 3;
3548 eeprom->delay_usec = 50;
3549 if (eecd & E1000_EECD_ADDR_BITS) {
3550 eeprom->word_size = 256;
3551 eeprom->address_bits = 8;
3553 eeprom->word_size = 64;
3554 eeprom->address_bits = 6;
3562 if (eeprom->type == e1000_eeprom_spi) {
3563 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3564 * 32KB (incremented by powers of 2).
3566 /* Set to default value for initial eeprom read. */
3567 eeprom->word_size = 64;
3568 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3572 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3573 /* 256B eeprom size was not supported in earlier hardware, so we
3574 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3575 * is never the result used in the shifting logic below. */
3579 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3585 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3586 * @hw: Struct containing variables accessed by shared code
3587 * @eecd: EECD's current value
3589 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3591 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3592 * wait <delay> microseconds.
3594 *eecd = *eecd | E1000_EECD_SK;
3596 E1000_WRITE_FLUSH();
3597 udelay(hw->eeprom.delay_usec);
3601 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3602 * @hw: Struct containing variables accessed by shared code
3603 * @eecd: EECD's current value
3605 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3607 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3608 * wait 50 microseconds.
3610 *eecd = *eecd & ~E1000_EECD_SK;
3612 E1000_WRITE_FLUSH();
3613 udelay(hw->eeprom.delay_usec);
3617 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3618 * @hw: Struct containing variables accessed by shared code
3619 * @data: data to send to the EEPROM
3620 * @count: number of bits to shift out
3622 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3624 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3628 /* We need to shift "count" bits out to the EEPROM. So, value in the
3629 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3630 * In order to do this, "data" must be broken down into bits.
3632 mask = 0x01 << (count - 1);
3634 if (eeprom->type == e1000_eeprom_microwire) {
3635 eecd &= ~E1000_EECD_DO;
3636 } else if (eeprom->type == e1000_eeprom_spi) {
3637 eecd |= E1000_EECD_DO;
3640 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3641 * and then raising and then lowering the clock (the SK bit controls
3642 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3643 * by setting "DI" to "0" and then raising and then lowering the clock.
3645 eecd &= ~E1000_EECD_DI;
3648 eecd |= E1000_EECD_DI;
3651 E1000_WRITE_FLUSH();
3653 udelay(eeprom->delay_usec);
3655 e1000_raise_ee_clk(hw, &eecd);
3656 e1000_lower_ee_clk(hw, &eecd);
3662 /* We leave the "DI" bit set to "0" when we leave this routine. */
3663 eecd &= ~E1000_EECD_DI;
3668 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3669 * @hw: Struct containing variables accessed by shared code
3670 * @count: number of bits to shift in
3672 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3678 /* In order to read a register from the EEPROM, we need to shift 'count'
3679 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3680 * input to the EEPROM (setting the SK bit), and then reading the value of
3681 * the "DO" bit. During this "shifting in" process the "DI" bit should
3687 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3690 for (i = 0; i < count; i++) {
3692 e1000_raise_ee_clk(hw, &eecd);
3696 eecd &= ~(E1000_EECD_DI);
3697 if (eecd & E1000_EECD_DO)
3700 e1000_lower_ee_clk(hw, &eecd);
3707 * e1000_acquire_eeprom - Prepares EEPROM for access
3708 * @hw: Struct containing variables accessed by shared code
3710 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3711 * function should be called before issuing a command to the EEPROM.
3713 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3715 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3718 e_dbg("e1000_acquire_eeprom");
3722 /* Request EEPROM Access */
3723 if (hw->mac_type > e1000_82544) {
3724 eecd |= E1000_EECD_REQ;
3727 while ((!(eecd & E1000_EECD_GNT)) &&
3728 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3733 if (!(eecd & E1000_EECD_GNT)) {
3734 eecd &= ~E1000_EECD_REQ;
3736 e_dbg("Could not acquire EEPROM grant\n");
3737 return -E1000_ERR_EEPROM;
3741 /* Setup EEPROM for Read/Write */
3743 if (eeprom->type == e1000_eeprom_microwire) {
3744 /* Clear SK and DI */
3745 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3749 eecd |= E1000_EECD_CS;
3751 } else if (eeprom->type == e1000_eeprom_spi) {
3752 /* Clear SK and CS */
3753 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3758 return E1000_SUCCESS;
3762 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3763 * @hw: Struct containing variables accessed by shared code
3765 static void e1000_standby_eeprom(struct e1000_hw *hw)
3767 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3772 if (eeprom->type == e1000_eeprom_microwire) {
3773 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3775 E1000_WRITE_FLUSH();
3776 udelay(eeprom->delay_usec);
3779 eecd |= E1000_EECD_SK;
3781 E1000_WRITE_FLUSH();
3782 udelay(eeprom->delay_usec);
3785 eecd |= E1000_EECD_CS;
3787 E1000_WRITE_FLUSH();
3788 udelay(eeprom->delay_usec);
3791 eecd &= ~E1000_EECD_SK;
3793 E1000_WRITE_FLUSH();
3794 udelay(eeprom->delay_usec);
3795 } else if (eeprom->type == e1000_eeprom_spi) {
3796 /* Toggle CS to flush commands */
3797 eecd |= E1000_EECD_CS;
3799 E1000_WRITE_FLUSH();
3800 udelay(eeprom->delay_usec);
3801 eecd &= ~E1000_EECD_CS;
3803 E1000_WRITE_FLUSH();
3804 udelay(eeprom->delay_usec);
3809 * e1000_release_eeprom - drop chip select
3810 * @hw: Struct containing variables accessed by shared code
3812 * Terminates a command by inverting the EEPROM's chip select pin
3814 static void e1000_release_eeprom(struct e1000_hw *hw)
3818 e_dbg("e1000_release_eeprom");
3822 if (hw->eeprom.type == e1000_eeprom_spi) {
3823 eecd |= E1000_EECD_CS; /* Pull CS high */
3824 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3828 udelay(hw->eeprom.delay_usec);
3829 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3830 /* cleanup eeprom */
3832 /* CS on Microwire is active-high */
3833 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3837 /* Rising edge of clock */
3838 eecd |= E1000_EECD_SK;
3840 E1000_WRITE_FLUSH();
3841 udelay(hw->eeprom.delay_usec);
3843 /* Falling edge of clock */
3844 eecd &= ~E1000_EECD_SK;
3846 E1000_WRITE_FLUSH();
3847 udelay(hw->eeprom.delay_usec);
3850 /* Stop requesting EEPROM access */
3851 if (hw->mac_type > e1000_82544) {
3852 eecd &= ~E1000_EECD_REQ;
3858 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3859 * @hw: Struct containing variables accessed by shared code
3861 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3863 u16 retry_count = 0;
3866 e_dbg("e1000_spi_eeprom_ready");
3868 /* Read "Status Register" repeatedly until the LSB is cleared. The
3869 * EEPROM will signal that the command has been completed by clearing
3870 * bit 0 of the internal status register. If it's not cleared within
3871 * 5 milliseconds, then error out.
3875 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3876 hw->eeprom.opcode_bits);
3877 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3878 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3884 e1000_standby_eeprom(hw);
3885 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3887 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3888 * only 0-5mSec on 5V devices)
3890 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3891 e_dbg("SPI EEPROM Status error\n");
3892 return -E1000_ERR_EEPROM;
3895 return E1000_SUCCESS;
3899 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3900 * @hw: Struct containing variables accessed by shared code
3901 * @offset: offset of word in the EEPROM to read
3902 * @data: word read from the EEPROM
3903 * @words: number of words to read
3905 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3908 spin_lock(&e1000_eeprom_lock);
3909 ret = e1000_do_read_eeprom(hw, offset, words, data);
3910 spin_unlock(&e1000_eeprom_lock);
3914 static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3917 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3920 e_dbg("e1000_read_eeprom");
3922 if (hw->mac_type == e1000_ce4100) {
3923 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3925 return E1000_SUCCESS;
3928 /* If eeprom is not yet detected, do so now */
3929 if (eeprom->word_size == 0)
3930 e1000_init_eeprom_params(hw);
3932 /* A check for invalid values: offset too large, too many words, and not
3935 if ((offset >= eeprom->word_size)
3936 || (words > eeprom->word_size - offset) || (words == 0)) {
3937 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3938 "size = %d\n", offset, eeprom->word_size);
3939 return -E1000_ERR_EEPROM;
3942 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3943 * directly. In this case, we need to acquire the EEPROM so that
3944 * FW or other port software does not interrupt.
3946 /* Prepare the EEPROM for bit-bang reading */
3947 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3948 return -E1000_ERR_EEPROM;
3950 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3951 * acquired the EEPROM at this point, so any returns should release it */
3952 if (eeprom->type == e1000_eeprom_spi) {
3954 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3956 if (e1000_spi_eeprom_ready(hw)) {
3957 e1000_release_eeprom(hw);
3958 return -E1000_ERR_EEPROM;
3961 e1000_standby_eeprom(hw);
3963 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3964 if ((eeprom->address_bits == 8) && (offset >= 128))
3965 read_opcode |= EEPROM_A8_OPCODE_SPI;
3967 /* Send the READ command (opcode + addr) */
3968 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3969 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3970 eeprom->address_bits);
3972 /* Read the data. The address of the eeprom internally increments with
3973 * each byte (spi) being read, saving on the overhead of eeprom setup
3974 * and tear-down. The address counter will roll over if reading beyond
3975 * the size of the eeprom, thus allowing the entire memory to be read
3976 * starting from any offset. */
3977 for (i = 0; i < words; i++) {
3978 word_in = e1000_shift_in_ee_bits(hw, 16);
3979 data[i] = (word_in >> 8) | (word_in << 8);
3981 } else if (eeprom->type == e1000_eeprom_microwire) {
3982 for (i = 0; i < words; i++) {
3983 /* Send the READ command (opcode + addr) */
3984 e1000_shift_out_ee_bits(hw,
3985 EEPROM_READ_OPCODE_MICROWIRE,
3986 eeprom->opcode_bits);
3987 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3988 eeprom->address_bits);
3990 /* Read the data. For microwire, each word requires the overhead
3991 * of eeprom setup and tear-down. */
3992 data[i] = e1000_shift_in_ee_bits(hw, 16);
3993 e1000_standby_eeprom(hw);
3997 /* End this read operation */
3998 e1000_release_eeprom(hw);
4000 return E1000_SUCCESS;
4004 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
4005 * @hw: Struct containing variables accessed by shared code
4007 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4008 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4011 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4016 e_dbg("e1000_validate_eeprom_checksum");
4018 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4019 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4020 e_dbg("EEPROM Read Error\n");
4021 return -E1000_ERR_EEPROM;
4023 checksum += eeprom_data;
4026 if (checksum == (u16) EEPROM_SUM)
4027 return E1000_SUCCESS;
4029 e_dbg("EEPROM Checksum Invalid\n");
4030 return -E1000_ERR_EEPROM;
4035 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
4036 * @hw: Struct containing variables accessed by shared code
4038 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4039 * Writes the difference to word offset 63 of the EEPROM.
4041 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4046 e_dbg("e1000_update_eeprom_checksum");
4048 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4049 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4050 e_dbg("EEPROM Read Error\n");
4051 return -E1000_ERR_EEPROM;
4053 checksum += eeprom_data;
4055 checksum = (u16) EEPROM_SUM - checksum;
4056 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4057 e_dbg("EEPROM Write Error\n");
4058 return -E1000_ERR_EEPROM;
4060 return E1000_SUCCESS;
4064 * e1000_write_eeprom - write words to the different EEPROM types.
4065 * @hw: Struct containing variables accessed by shared code
4066 * @offset: offset within the EEPROM to be written to
4067 * @words: number of words to write
4068 * @data: 16 bit word to be written to the EEPROM
4070 * If e1000_update_eeprom_checksum is not called after this function, the
4071 * EEPROM will most likely contain an invalid checksum.
4073 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4076 spin_lock(&e1000_eeprom_lock);
4077 ret = e1000_do_write_eeprom(hw, offset, words, data);
4078 spin_unlock(&e1000_eeprom_lock);
4082 static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4085 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4088 e_dbg("e1000_write_eeprom");
4090 if (hw->mac_type == e1000_ce4100) {
4091 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4093 return E1000_SUCCESS;
4096 /* If eeprom is not yet detected, do so now */
4097 if (eeprom->word_size == 0)
4098 e1000_init_eeprom_params(hw);
4100 /* A check for invalid values: offset too large, too many words, and not
4103 if ((offset >= eeprom->word_size)
4104 || (words > eeprom->word_size - offset) || (words == 0)) {
4105 e_dbg("\"words\" parameter out of bounds\n");
4106 return -E1000_ERR_EEPROM;
4109 /* Prepare the EEPROM for writing */
4110 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4111 return -E1000_ERR_EEPROM;
4113 if (eeprom->type == e1000_eeprom_microwire) {
4114 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4116 status = e1000_write_eeprom_spi(hw, offset, words, data);
4120 /* Done with writing */
4121 e1000_release_eeprom(hw);
4127 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4128 * @hw: Struct containing variables accessed by shared code
4129 * @offset: offset within the EEPROM to be written to
4130 * @words: number of words to write
4131 * @data: pointer to array of 8 bit words to be written to the EEPROM
4133 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4136 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4139 e_dbg("e1000_write_eeprom_spi");
4141 while (widx < words) {
4142 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4144 if (e1000_spi_eeprom_ready(hw))
4145 return -E1000_ERR_EEPROM;
4147 e1000_standby_eeprom(hw);
4149 /* Send the WRITE ENABLE command (8 bit opcode ) */
4150 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4151 eeprom->opcode_bits);
4153 e1000_standby_eeprom(hw);
4155 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4156 if ((eeprom->address_bits == 8) && (offset >= 128))
4157 write_opcode |= EEPROM_A8_OPCODE_SPI;
4159 /* Send the Write command (8-bit opcode + addr) */
4160 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4162 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4163 eeprom->address_bits);
4167 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4168 while (widx < words) {
4169 u16 word_out = data[widx];
4170 word_out = (word_out >> 8) | (word_out << 8);
4171 e1000_shift_out_ee_bits(hw, word_out, 16);
4174 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4175 * operation, while the smaller eeproms are capable of an 8-byte
4176 * PAGE WRITE operation. Break the inner loop to pass new address
4178 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4179 e1000_standby_eeprom(hw);
4185 return E1000_SUCCESS;
4189 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4190 * @hw: Struct containing variables accessed by shared code
4191 * @offset: offset within the EEPROM to be written to
4192 * @words: number of words to write
4193 * @data: pointer to array of 8 bit words to be written to the EEPROM
4195 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4196 u16 words, u16 *data)
4198 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4200 u16 words_written = 0;
4203 e_dbg("e1000_write_eeprom_microwire");
4205 /* Send the write enable command to the EEPROM (3-bit opcode plus
4206 * 6/8-bit dummy address beginning with 11). It's less work to include
4207 * the 11 of the dummy address as part of the opcode than it is to shift
4208 * it over the correct number of bits for the address. This puts the
4209 * EEPROM into write/erase mode.
4211 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4212 (u16) (eeprom->opcode_bits + 2));
4214 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4216 /* Prepare the EEPROM */
4217 e1000_standby_eeprom(hw);
4219 while (words_written < words) {
4220 /* Send the Write command (3-bit opcode + addr) */
4221 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4222 eeprom->opcode_bits);
4224 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4225 eeprom->address_bits);
4228 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4230 /* Toggle the CS line. This in effect tells the EEPROM to execute
4231 * the previous command.
4233 e1000_standby_eeprom(hw);
4235 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4236 * signal that the command has been completed by raising the DO signal.
4237 * If DO does not go high in 10 milliseconds, then error out.
4239 for (i = 0; i < 200; i++) {
4241 if (eecd & E1000_EECD_DO)
4246 e_dbg("EEPROM Write did not complete\n");
4247 return -E1000_ERR_EEPROM;
4250 /* Recover from write */
4251 e1000_standby_eeprom(hw);
4256 /* Send the write disable command to the EEPROM (3-bit opcode plus
4257 * 6/8-bit dummy address beginning with 10). It's less work to include
4258 * the 10 of the dummy address as part of the opcode than it is to shift
4259 * it over the correct number of bits for the address. This takes the
4260 * EEPROM out of write/erase mode.
4262 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4263 (u16) (eeprom->opcode_bits + 2));
4265 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4267 return E1000_SUCCESS;
4271 * e1000_read_mac_addr - read the adapters MAC from eeprom
4272 * @hw: Struct containing variables accessed by shared code
4274 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4275 * second function of dual function devices
4277 s32 e1000_read_mac_addr(struct e1000_hw *hw)
4282 e_dbg("e1000_read_mac_addr");
4284 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4286 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4287 e_dbg("EEPROM Read Error\n");
4288 return -E1000_ERR_EEPROM;
4290 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4291 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4294 switch (hw->mac_type) {
4298 case e1000_82546_rev_3:
4299 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4300 hw->perm_mac_addr[5] ^= 0x01;
4304 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4305 hw->mac_addr[i] = hw->perm_mac_addr[i];
4306 return E1000_SUCCESS;
4310 * e1000_init_rx_addrs - Initializes receive address filters.
4311 * @hw: Struct containing variables accessed by shared code
4313 * Places the MAC address in receive address register 0 and clears the rest
4314 * of the receive address registers. Clears the multicast table. Assumes
4315 * the receiver is in reset when the routine is called.
4317 static void e1000_init_rx_addrs(struct e1000_hw *hw)
4322 e_dbg("e1000_init_rx_addrs");
4324 /* Setup the receive address. */
4325 e_dbg("Programming MAC Address into RAR[0]\n");
4327 e1000_rar_set(hw, hw->mac_addr, 0);
4329 rar_num = E1000_RAR_ENTRIES;
4331 /* Zero out the other 15 receive addresses. */
4332 e_dbg("Clearing RAR[1-15]\n");
4333 for (i = 1; i < rar_num; i++) {
4334 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4335 E1000_WRITE_FLUSH();
4336 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4337 E1000_WRITE_FLUSH();
4342 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4343 * @hw: Struct containing variables accessed by shared code
4344 * @mc_addr: the multicast address to hash
4346 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4350 /* The portion of the address that is used for the hash table is
4351 * determined by the mc_filter_type setting.
4353 switch (hw->mc_filter_type) {
4354 /* [0] [1] [2] [3] [4] [5]
4359 /* [47:36] i.e. 0x563 for above example address */
4360 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4363 /* [46:35] i.e. 0xAC6 for above example address */
4364 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4367 /* [45:34] i.e. 0x5D8 for above example address */
4368 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4371 /* [43:32] i.e. 0x634 for above example address */
4372 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4376 hash_value &= 0xFFF;
4381 * e1000_rar_set - Puts an ethernet address into a receive address register.
4382 * @hw: Struct containing variables accessed by shared code
4383 * @addr: Address to put into receive address register
4384 * @index: Receive address register to write
4386 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4388 u32 rar_low, rar_high;
4390 /* HW expects these in little endian so we reverse the byte order
4391 * from network order (big endian) to little endian
4393 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4394 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4395 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4397 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4401 * If there are any Rx frames queued up or otherwise present in the HW
4402 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4403 * hang. To work around this issue, we have to disable receives and
4404 * flush out all Rx frames before we enable RSS. To do so, we modify we
4405 * redirect all Rx traffic to manageability and then reset the HW.
4406 * This flushes away Rx frames, and (since the redirections to
4407 * manageability persists across resets) keeps new ones from coming in
4408 * while we work. Then, we clear the Address Valid AV bit for all MAC
4409 * addresses and undo the re-direction to manageability.
4410 * Now, frames are coming in again, but the MAC won't accept them, so
4411 * far so good. We now proceed to initialize RSS (if necessary) and
4412 * configure the Rx unit. Last, we re-enable the AV bits and continue
4415 switch (hw->mac_type) {
4417 /* Indicate to hardware the Address is Valid. */
4418 rar_high |= E1000_RAH_AV;
4422 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4423 E1000_WRITE_FLUSH();
4424 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4425 E1000_WRITE_FLUSH();
4429 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4430 * @hw: Struct containing variables accessed by shared code
4431 * @offset: Offset in VLAN filer table to write
4432 * @value: Value to write into VLAN filter table
4434 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4438 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4439 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4440 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4441 E1000_WRITE_FLUSH();
4442 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4443 E1000_WRITE_FLUSH();
4445 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4446 E1000_WRITE_FLUSH();
4451 * e1000_clear_vfta - Clears the VLAN filer table
4452 * @hw: Struct containing variables accessed by shared code
4454 static void e1000_clear_vfta(struct e1000_hw *hw)
4458 u32 vfta_offset = 0;
4459 u32 vfta_bit_in_reg = 0;
4461 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4462 /* If the offset we want to clear is the same offset of the
4463 * manageability VLAN ID, then clear all bits except that of the
4464 * manageability unit */
4465 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4466 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4467 E1000_WRITE_FLUSH();
4471 static s32 e1000_id_led_init(struct e1000_hw *hw)
4474 const u32 ledctl_mask = 0x000000FF;
4475 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4476 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4477 u16 eeprom_data, i, temp;
4478 const u16 led_mask = 0x0F;
4480 e_dbg("e1000_id_led_init");
4482 if (hw->mac_type < e1000_82540) {
4484 return E1000_SUCCESS;
4487 ledctl = er32(LEDCTL);
4488 hw->ledctl_default = ledctl;
4489 hw->ledctl_mode1 = hw->ledctl_default;
4490 hw->ledctl_mode2 = hw->ledctl_default;
4492 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4493 e_dbg("EEPROM Read Error\n");
4494 return -E1000_ERR_EEPROM;
4497 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4498 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4499 eeprom_data = ID_LED_DEFAULT;
4502 for (i = 0; i < 4; i++) {
4503 temp = (eeprom_data >> (i << 2)) & led_mask;
4505 case ID_LED_ON1_DEF2:
4506 case ID_LED_ON1_ON2:
4507 case ID_LED_ON1_OFF2:
4508 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4509 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4511 case ID_LED_OFF1_DEF2:
4512 case ID_LED_OFF1_ON2:
4513 case ID_LED_OFF1_OFF2:
4514 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4515 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4522 case ID_LED_DEF1_ON2:
4523 case ID_LED_ON1_ON2:
4524 case ID_LED_OFF1_ON2:
4525 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4526 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4528 case ID_LED_DEF1_OFF2:
4529 case ID_LED_ON1_OFF2:
4530 case ID_LED_OFF1_OFF2:
4531 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4532 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4539 return E1000_SUCCESS;
4544 * @hw: Struct containing variables accessed by shared code
4546 * Prepares SW controlable LED for use and saves the current state of the LED.
4548 s32 e1000_setup_led(struct e1000_hw *hw)
4551 s32 ret_val = E1000_SUCCESS;
4553 e_dbg("e1000_setup_led");
4555 switch (hw->mac_type) {
4556 case e1000_82542_rev2_0:
4557 case e1000_82542_rev2_1:
4560 /* No setup necessary */
4564 case e1000_82541_rev_2:
4565 case e1000_82547_rev_2:
4566 /* Turn off PHY Smart Power Down (if enabled) */
4567 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4568 &hw->phy_spd_default);
4571 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4572 (u16) (hw->phy_spd_default &
4573 ~IGP01E1000_GMII_SPD));
4578 if (hw->media_type == e1000_media_type_fiber) {
4579 ledctl = er32(LEDCTL);
4580 /* Save current LEDCTL settings */
4581 hw->ledctl_default = ledctl;
4583 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4584 E1000_LEDCTL_LED0_BLINK |
4585 E1000_LEDCTL_LED0_MODE_MASK);
4586 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4587 E1000_LEDCTL_LED0_MODE_SHIFT);
4588 ew32(LEDCTL, ledctl);
4589 } else if (hw->media_type == e1000_media_type_copper)
4590 ew32(LEDCTL, hw->ledctl_mode1);
4594 return E1000_SUCCESS;
4598 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4599 * @hw: Struct containing variables accessed by shared code
4601 s32 e1000_cleanup_led(struct e1000_hw *hw)
4603 s32 ret_val = E1000_SUCCESS;
4605 e_dbg("e1000_cleanup_led");
4607 switch (hw->mac_type) {
4608 case e1000_82542_rev2_0:
4609 case e1000_82542_rev2_1:
4612 /* No cleanup necessary */
4616 case e1000_82541_rev_2:
4617 case e1000_82547_rev_2:
4618 /* Turn on PHY Smart Power Down (if previously enabled) */
4619 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4620 hw->phy_spd_default);
4625 /* Restore LEDCTL settings */
4626 ew32(LEDCTL, hw->ledctl_default);
4630 return E1000_SUCCESS;
4634 * e1000_led_on - Turns on the software controllable LED
4635 * @hw: Struct containing variables accessed by shared code
4637 s32 e1000_led_on(struct e1000_hw *hw)
4639 u32 ctrl = er32(CTRL);
4641 e_dbg("e1000_led_on");
4643 switch (hw->mac_type) {
4644 case e1000_82542_rev2_0:
4645 case e1000_82542_rev2_1:
4647 /* Set SW Defineable Pin 0 to turn on the LED */
4648 ctrl |= E1000_CTRL_SWDPIN0;
4649 ctrl |= E1000_CTRL_SWDPIO0;
4652 if (hw->media_type == e1000_media_type_fiber) {
4653 /* Set SW Defineable Pin 0 to turn on the LED */
4654 ctrl |= E1000_CTRL_SWDPIN0;
4655 ctrl |= E1000_CTRL_SWDPIO0;
4657 /* Clear SW Defineable Pin 0 to turn on the LED */
4658 ctrl &= ~E1000_CTRL_SWDPIN0;
4659 ctrl |= E1000_CTRL_SWDPIO0;
4663 if (hw->media_type == e1000_media_type_fiber) {
4664 /* Clear SW Defineable Pin 0 to turn on the LED */
4665 ctrl &= ~E1000_CTRL_SWDPIN0;
4666 ctrl |= E1000_CTRL_SWDPIO0;
4667 } else if (hw->media_type == e1000_media_type_copper) {
4668 ew32(LEDCTL, hw->ledctl_mode2);
4669 return E1000_SUCCESS;
4676 return E1000_SUCCESS;
4680 * e1000_led_off - Turns off the software controllable LED
4681 * @hw: Struct containing variables accessed by shared code
4683 s32 e1000_led_off(struct e1000_hw *hw)
4685 u32 ctrl = er32(CTRL);
4687 e_dbg("e1000_led_off");
4689 switch (hw->mac_type) {
4690 case e1000_82542_rev2_0:
4691 case e1000_82542_rev2_1:
4693 /* Clear SW Defineable Pin 0 to turn off the LED */
4694 ctrl &= ~E1000_CTRL_SWDPIN0;
4695 ctrl |= E1000_CTRL_SWDPIO0;
4698 if (hw->media_type == e1000_media_type_fiber) {
4699 /* Clear SW Defineable Pin 0 to turn off the LED */
4700 ctrl &= ~E1000_CTRL_SWDPIN0;
4701 ctrl |= E1000_CTRL_SWDPIO0;
4703 /* Set SW Defineable Pin 0 to turn off the LED */
4704 ctrl |= E1000_CTRL_SWDPIN0;
4705 ctrl |= E1000_CTRL_SWDPIO0;
4709 if (hw->media_type == e1000_media_type_fiber) {
4710 /* Set SW Defineable Pin 0 to turn off the LED */
4711 ctrl |= E1000_CTRL_SWDPIN0;
4712 ctrl |= E1000_CTRL_SWDPIO0;
4713 } else if (hw->media_type == e1000_media_type_copper) {
4714 ew32(LEDCTL, hw->ledctl_mode1);
4715 return E1000_SUCCESS;
4722 return E1000_SUCCESS;
4726 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4727 * @hw: Struct containing variables accessed by shared code
4729 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4733 temp = er32(CRCERRS);
4734 temp = er32(SYMERRS);
4739 temp = er32(LATECOL);
4744 temp = er32(XONRXC);
4745 temp = er32(XONTXC);
4746 temp = er32(XOFFRXC);
4747 temp = er32(XOFFTXC);
4751 temp = er32(PRC127);
4752 temp = er32(PRC255);
4753 temp = er32(PRC511);
4754 temp = er32(PRC1023);
4755 temp = er32(PRC1522);
4778 temp = er32(PTC127);
4779 temp = er32(PTC255);
4780 temp = er32(PTC511);
4781 temp = er32(PTC1023);
4782 temp = er32(PTC1522);
4787 if (hw->mac_type < e1000_82543)
4790 temp = er32(ALGNERRC);
4791 temp = er32(RXERRC);
4793 temp = er32(CEXTERR);
4795 temp = er32(TSCTFC);
4797 if (hw->mac_type <= e1000_82544)
4800 temp = er32(MGTPRC);
4801 temp = er32(MGTPDC);
4802 temp = er32(MGTPTC);
4806 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4807 * @hw: Struct containing variables accessed by shared code
4809 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4810 * hw->ifs_params_forced to true. However, you must initialize hw->
4811 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4812 * before calling this function.
4814 void e1000_reset_adaptive(struct e1000_hw *hw)
4816 e_dbg("e1000_reset_adaptive");
4818 if (hw->adaptive_ifs) {
4819 if (!hw->ifs_params_forced) {
4820 hw->current_ifs_val = 0;
4821 hw->ifs_min_val = IFS_MIN;
4822 hw->ifs_max_val = IFS_MAX;
4823 hw->ifs_step_size = IFS_STEP;
4824 hw->ifs_ratio = IFS_RATIO;
4826 hw->in_ifs_mode = false;
4829 e_dbg("Not in Adaptive IFS mode!\n");
4834 * e1000_update_adaptive - update adaptive IFS
4835 * @hw: Struct containing variables accessed by shared code
4836 * @tx_packets: Number of transmits since last callback
4837 * @total_collisions: Number of collisions since last callback
4839 * Called during the callback/watchdog routine to update IFS value based on
4840 * the ratio of transmits to collisions.
4842 void e1000_update_adaptive(struct e1000_hw *hw)
4844 e_dbg("e1000_update_adaptive");
4846 if (hw->adaptive_ifs) {
4847 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4848 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4849 hw->in_ifs_mode = true;
4850 if (hw->current_ifs_val < hw->ifs_max_val) {
4851 if (hw->current_ifs_val == 0)
4852 hw->current_ifs_val =
4855 hw->current_ifs_val +=
4857 ew32(AIT, hw->current_ifs_val);
4862 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4863 hw->current_ifs_val = 0;
4864 hw->in_ifs_mode = false;
4869 e_dbg("Not in Adaptive IFS mode!\n");
4874 * e1000_tbi_adjust_stats
4875 * @hw: Struct containing variables accessed by shared code
4876 * @frame_len: The length of the frame in question
4877 * @mac_addr: The Ethernet destination address of the frame in question
4879 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4881 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4882 u32 frame_len, u8 *mac_addr)
4886 /* First adjust the frame length. */
4888 /* We need to adjust the statistics counters, since the hardware
4889 * counters overcount this packet as a CRC error and undercount
4890 * the packet as a good packet
4892 /* This packet should not be counted as a CRC error. */
4894 /* This packet does count as a Good Packet Received. */
4897 /* Adjust the Good Octets received counters */
4898 carry_bit = 0x80000000 & stats->gorcl;
4899 stats->gorcl += frame_len;
4900 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4901 * Received Count) was one before the addition,
4902 * AND it is zero after, then we lost the carry out,
4903 * need to add one to Gorch (Good Octets Received Count High).
4904 * This could be simplified if all environments supported
4907 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4909 /* Is this a broadcast or multicast? Check broadcast first,
4910 * since the test for a multicast frame will test positive on
4911 * a broadcast frame.
4913 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4914 /* Broadcast packet */
4916 else if (*mac_addr & 0x01)
4917 /* Multicast packet */
4920 if (frame_len == hw->max_frame_size) {
4921 /* In this case, the hardware has overcounted the number of
4928 /* Adjust the bin counters when the extra byte put the frame in the
4929 * wrong bin. Remember that the frame_len was adjusted above.
4931 if (frame_len == 64) {
4934 } else if (frame_len == 127) {
4937 } else if (frame_len == 255) {
4940 } else if (frame_len == 511) {
4943 } else if (frame_len == 1023) {
4946 } else if (frame_len == 1522) {
4952 * e1000_get_bus_info
4953 * @hw: Struct containing variables accessed by shared code
4955 * Gets the current PCI bus type, speed, and width of the hardware
4957 void e1000_get_bus_info(struct e1000_hw *hw)
4961 switch (hw->mac_type) {
4962 case e1000_82542_rev2_0:
4963 case e1000_82542_rev2_1:
4964 hw->bus_type = e1000_bus_type_pci;
4965 hw->bus_speed = e1000_bus_speed_unknown;
4966 hw->bus_width = e1000_bus_width_unknown;
4969 status = er32(STATUS);
4970 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4971 e1000_bus_type_pcix : e1000_bus_type_pci;
4973 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4974 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4975 e1000_bus_speed_66 : e1000_bus_speed_120;
4976 } else if (hw->bus_type == e1000_bus_type_pci) {
4977 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4978 e1000_bus_speed_66 : e1000_bus_speed_33;
4980 switch (status & E1000_STATUS_PCIX_SPEED) {
4981 case E1000_STATUS_PCIX_SPEED_66:
4982 hw->bus_speed = e1000_bus_speed_66;
4984 case E1000_STATUS_PCIX_SPEED_100:
4985 hw->bus_speed = e1000_bus_speed_100;
4987 case E1000_STATUS_PCIX_SPEED_133:
4988 hw->bus_speed = e1000_bus_speed_133;
4991 hw->bus_speed = e1000_bus_speed_reserved;
4995 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4996 e1000_bus_width_64 : e1000_bus_width_32;
5002 * e1000_write_reg_io
5003 * @hw: Struct containing variables accessed by shared code
5004 * @offset: offset to write to
5005 * @value: value to write
5007 * Writes a value to one of the devices registers using port I/O (as opposed to
5008 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5010 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
5012 unsigned long io_addr = hw->io_base;
5013 unsigned long io_data = hw->io_base + 4;
5015 e1000_io_write(hw, io_addr, offset);
5016 e1000_io_write(hw, io_data, value);
5020 * e1000_get_cable_length - Estimates the cable length.
5021 * @hw: Struct containing variables accessed by shared code
5022 * @min_length: The estimated minimum length
5023 * @max_length: The estimated maximum length
5025 * returns: - E1000_ERR_XXX
5028 * This function always returns a ranged length (minimum & maximum).
5029 * So for M88 phy's, this function interprets the one value returned from the
5030 * register to the minimum and maximum range.
5031 * For IGP phy's, the function calculates the range by the AGC registers.
5033 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
5041 e_dbg("e1000_get_cable_length");
5043 *min_length = *max_length = 0;
5045 /* Use old method for Phy older than IGP */
5046 if (hw->phy_type == e1000_phy_m88) {
5048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5052 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5053 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5055 /* Convert the enum value to ranged values */
5056 switch (cable_length) {
5057 case e1000_cable_length_50:
5059 *max_length = e1000_igp_cable_length_50;
5061 case e1000_cable_length_50_80:
5062 *min_length = e1000_igp_cable_length_50;
5063 *max_length = e1000_igp_cable_length_80;
5065 case e1000_cable_length_80_110:
5066 *min_length = e1000_igp_cable_length_80;
5067 *max_length = e1000_igp_cable_length_110;
5069 case e1000_cable_length_110_140:
5070 *min_length = e1000_igp_cable_length_110;
5071 *max_length = e1000_igp_cable_length_140;
5073 case e1000_cable_length_140:
5074 *min_length = e1000_igp_cable_length_140;
5075 *max_length = e1000_igp_cable_length_170;
5078 return -E1000_ERR_PHY;
5081 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5083 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5084 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5085 IGP01E1000_PHY_AGC_A,
5086 IGP01E1000_PHY_AGC_B,
5087 IGP01E1000_PHY_AGC_C,
5088 IGP01E1000_PHY_AGC_D
5090 /* Read the AGC registers for all channels */
5091 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5094 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5098 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5100 /* Value bound check. */
5101 if ((cur_agc_value >=
5102 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
5103 || (cur_agc_value == 0))
5104 return -E1000_ERR_PHY;
5106 agc_value += cur_agc_value;
5108 /* Update minimal AGC value. */
5109 if (min_agc_value > cur_agc_value)
5110 min_agc_value = cur_agc_value;
5113 /* Remove the minimal AGC result for length < 50m */
5115 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5116 agc_value -= min_agc_value;
5118 /* Get the average length of the remaining 3 channels */
5119 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5121 /* Get the average length of all the 4 channels. */
5122 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5125 /* Set the range of the calculated length. */
5126 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5127 IGP01E1000_AGC_RANGE) > 0) ?
5128 (e1000_igp_cable_length_table[agc_value] -
5129 IGP01E1000_AGC_RANGE) : 0;
5130 *max_length = e1000_igp_cable_length_table[agc_value] +
5131 IGP01E1000_AGC_RANGE;
5134 return E1000_SUCCESS;
5138 * e1000_check_polarity - Check the cable polarity
5139 * @hw: Struct containing variables accessed by shared code
5140 * @polarity: output parameter : 0 - Polarity is not reversed
5141 * 1 - Polarity is reversed.
5143 * returns: - E1000_ERR_XXX
5146 * For phy's older than IGP, this function simply reads the polarity bit in the
5147 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5148 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5149 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5150 * IGP01E1000_PHY_PCS_INIT_REG.
5152 static s32 e1000_check_polarity(struct e1000_hw *hw,
5153 e1000_rev_polarity *polarity)
5158 e_dbg("e1000_check_polarity");
5160 if (hw->phy_type == e1000_phy_m88) {
5161 /* return the Polarity bit in the Status register. */
5162 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5166 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5167 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5168 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5170 } else if (hw->phy_type == e1000_phy_igp) {
5171 /* Read the Status register to check the speed */
5172 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5177 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5178 * find the polarity status */
5179 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5180 IGP01E1000_PSSR_SPEED_1000MBPS) {
5182 /* Read the GIG initialization PCS register (0x00B4) */
5184 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5189 /* Check the polarity bits */
5190 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5191 e1000_rev_polarity_reversed :
5192 e1000_rev_polarity_normal;
5194 /* For 10 Mbps, read the polarity bit in the status register. (for
5195 * 100 Mbps this bit is always 0) */
5197 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5198 e1000_rev_polarity_reversed :
5199 e1000_rev_polarity_normal;
5202 return E1000_SUCCESS;
5206 * e1000_check_downshift - Check if Downshift occurred
5207 * @hw: Struct containing variables accessed by shared code
5208 * @downshift: output parameter : 0 - No Downshift occurred.
5209 * 1 - Downshift occurred.
5211 * returns: - E1000_ERR_XXX
5214 * For phy's older than IGP, this function reads the Downshift bit in the Phy
5215 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5216 * Link Health register. In IGP this bit is latched high, so the driver must
5217 * read it immediately after link is established.
5219 static s32 e1000_check_downshift(struct e1000_hw *hw)
5224 e_dbg("e1000_check_downshift");
5226 if (hw->phy_type == e1000_phy_igp) {
5227 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5232 hw->speed_downgraded =
5233 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5234 } else if (hw->phy_type == e1000_phy_m88) {
5235 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5240 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5241 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5244 return E1000_SUCCESS;
5248 * e1000_config_dsp_after_link_change
5249 * @hw: Struct containing variables accessed by shared code
5250 * @link_up: was link up at the time this was called
5252 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5253 * E1000_SUCCESS at any other case.
5255 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5256 * gigabit link is achieved to improve link quality.
5259 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5262 u16 phy_data, phy_saved_data, speed, duplex, i;
5263 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5264 IGP01E1000_PHY_AGC_PARAM_A,
5265 IGP01E1000_PHY_AGC_PARAM_B,
5266 IGP01E1000_PHY_AGC_PARAM_C,
5267 IGP01E1000_PHY_AGC_PARAM_D
5269 u16 min_length, max_length;
5271 e_dbg("e1000_config_dsp_after_link_change");
5273 if (hw->phy_type != e1000_phy_igp)
5274 return E1000_SUCCESS;
5277 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5279 e_dbg("Error getting link speed and duplex\n");
5283 if (speed == SPEED_1000) {
5286 e1000_get_cable_length(hw, &min_length,
5291 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5292 && min_length >= e1000_igp_cable_length_50) {
5294 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5296 e1000_read_phy_reg(hw,
5303 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5306 e1000_write_phy_reg(hw,
5312 hw->dsp_config_state =
5313 e1000_dsp_config_activated;
5316 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5317 && (min_length < e1000_igp_cable_length_50)) {
5319 u16 ffe_idle_err_timeout =
5320 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5323 /* clear previous idle error counts */
5325 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5330 for (i = 0; i < ffe_idle_err_timeout; i++) {
5333 e1000_read_phy_reg(hw,
5341 SR_1000T_IDLE_ERROR_CNT);
5343 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5345 hw->ffe_config_state =
5346 e1000_ffe_config_active;
5349 e1000_write_phy_reg(hw,
5350 IGP01E1000_PHY_DSP_FFE,
5351 IGP01E1000_PHY_DSP_FFE_CM_CP);
5358 ffe_idle_err_timeout =
5359 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5364 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5365 /* Save off the current value of register 0x2F5B to be restored at
5366 * the end of the routines. */
5368 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5373 /* Disable the PHY transmitter */
5374 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5381 ret_val = e1000_write_phy_reg(hw, 0x0000,
5382 IGP01E1000_IEEE_FORCE_GIGA);
5385 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5387 e1000_read_phy_reg(hw, dsp_reg_array[i],
5392 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5393 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5396 e1000_write_phy_reg(hw, dsp_reg_array[i],
5402 ret_val = e1000_write_phy_reg(hw, 0x0000,
5403 IGP01E1000_IEEE_RESTART_AUTONEG);
5409 /* Now enable the transmitter */
5411 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5416 hw->dsp_config_state = e1000_dsp_config_enabled;
5419 if (hw->ffe_config_state == e1000_ffe_config_active) {
5420 /* Save off the current value of register 0x2F5B to be restored at
5421 * the end of the routines. */
5423 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5428 /* Disable the PHY transmitter */
5429 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5436 ret_val = e1000_write_phy_reg(hw, 0x0000,
5437 IGP01E1000_IEEE_FORCE_GIGA);
5441 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5442 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5446 ret_val = e1000_write_phy_reg(hw, 0x0000,
5447 IGP01E1000_IEEE_RESTART_AUTONEG);
5453 /* Now enable the transmitter */
5455 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5460 hw->ffe_config_state = e1000_ffe_config_enabled;
5463 return E1000_SUCCESS;
5467 * e1000_set_phy_mode - Set PHY to class A mode
5468 * @hw: Struct containing variables accessed by shared code
5470 * Assumes the following operations will follow to enable the new class mode.
5471 * 1. Do a PHY soft reset
5472 * 2. Restart auto-negotiation or force link.
5474 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5479 e_dbg("e1000_set_phy_mode");
5481 if ((hw->mac_type == e1000_82545_rev_3) &&
5482 (hw->media_type == e1000_media_type_copper)) {
5484 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5490 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5491 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5493 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5498 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5503 hw->phy_reset_disable = false;
5507 return E1000_SUCCESS;
5511 * e1000_set_d3_lplu_state - set d3 link power state
5512 * @hw: Struct containing variables accessed by shared code
5513 * @active: true to enable lplu false to disable lplu.
5515 * This function sets the lplu state according to the active flag. When
5516 * activating lplu this function also disables smart speed and vise versa.
5517 * lplu will not be activated unless the device autonegotiation advertisement
5518 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5520 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5521 * E1000_SUCCESS at any other case.
5523 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5527 e_dbg("e1000_set_d3_lplu_state");
5529 if (hw->phy_type != e1000_phy_igp)
5530 return E1000_SUCCESS;
5532 /* During driver activity LPLU should not be used or it will attain link
5533 * from the lowest speeds starting from 10Mbps. The capability is used for
5534 * Dx transitions and states */
5535 if (hw->mac_type == e1000_82541_rev_2
5536 || hw->mac_type == e1000_82547_rev_2) {
5538 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5544 if (hw->mac_type == e1000_82541_rev_2 ||
5545 hw->mac_type == e1000_82547_rev_2) {
5546 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5548 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5554 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5555 * Dx states where the power conservation is most important. During
5556 * driver activity we should enable SmartSpeed, so performance is
5558 if (hw->smart_speed == e1000_smart_speed_on) {
5560 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5565 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5567 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5571 } else if (hw->smart_speed == e1000_smart_speed_off) {
5573 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5578 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5580 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5585 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5586 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5587 || (hw->autoneg_advertised ==
5588 AUTONEG_ADVERTISE_10_100_ALL)) {
5590 if (hw->mac_type == e1000_82541_rev_2 ||
5591 hw->mac_type == e1000_82547_rev_2) {
5592 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5594 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5600 /* When LPLU is enabled we should disable SmartSpeed */
5602 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5607 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5609 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5615 return E1000_SUCCESS;
5619 * e1000_set_vco_speed
5620 * @hw: Struct containing variables accessed by shared code
5622 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5624 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5627 u16 default_page = 0;
5630 e_dbg("e1000_set_vco_speed");
5632 switch (hw->mac_type) {
5633 case e1000_82545_rev_3:
5634 case e1000_82546_rev_3:
5637 return E1000_SUCCESS;
5640 /* Set PHY register 30, page 5, bit 8 to 0 */
5643 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5647 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5651 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5655 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5656 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5660 /* Set PHY register 30, page 4, bit 11 to 1 */
5662 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5666 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5670 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5671 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5676 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5680 return E1000_SUCCESS;
5685 * e1000_enable_mng_pass_thru - check for bmc pass through
5686 * @hw: Struct containing variables accessed by shared code
5688 * Verifies the hardware needs to allow ARPs to be processed by the host
5689 * returns: - true/false
5691 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5695 if (hw->asf_firmware_present) {
5698 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5699 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5701 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5707 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5713 /* Polarity reversal workaround for forced 10F/10H links. */
5715 /* Disable the transmitter on the PHY */
5717 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5720 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5724 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5728 /* This loop will early-out if the NO link condition has been met. */
5729 for (i = PHY_FORCE_TIME; i > 0; i--) {
5730 /* Read the MII Status Register and wait for Link Status bit
5734 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5738 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5742 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5747 /* Recommended delay time after link has been lost */
5750 /* Now we will re-enable th transmitter on the PHY */
5752 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5756 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5760 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5764 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5768 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5772 /* This loop will early-out if the link condition has been met. */
5773 for (i = PHY_FORCE_TIME; i > 0; i--) {
5774 /* Read the MII Status Register and wait for Link Status bit
5778 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5782 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5786 if (mii_status_reg & MII_SR_LINK_STATUS)
5790 return E1000_SUCCESS;
5794 * e1000_get_auto_rd_done
5795 * @hw: Struct containing variables accessed by shared code
5797 * Check for EEPROM Auto Read bit done.
5798 * returns: - E1000_ERR_RESET if fail to reset MAC
5799 * E1000_SUCCESS at any other case.
5801 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5803 e_dbg("e1000_get_auto_rd_done");
5805 return E1000_SUCCESS;
5809 * e1000_get_phy_cfg_done
5810 * @hw: Struct containing variables accessed by shared code
5812 * Checks if the PHY configuration is done
5813 * returns: - E1000_ERR_RESET if fail to reset MAC
5814 * E1000_SUCCESS at any other case.
5816 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5818 e_dbg("e1000_get_phy_cfg_done");
5820 return E1000_SUCCESS;