1 /*******************************************************************************
4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *******************************************************************************/
31 * Shared functions for accessing and configuring the MAC
36 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
37 static void e1000_phy_init_script(struct e1000_hw *hw);
38 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
39 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
40 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
41 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
42 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
43 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
45 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
47 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
48 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
49 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
50 uint16_t words, uint16_t *data);
51 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
52 uint16_t offset, uint16_t words,
54 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
55 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
57 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
59 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
61 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
63 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
64 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
65 static void e1000_release_eeprom(struct e1000_hw *hw);
66 static void e1000_standby_eeprom(struct e1000_hw *hw);
67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
71 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
72 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
73 static int32_t e1000_check_downshift(struct e1000_hw *hw);
74 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
75 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
76 static void e1000_clear_vfta(struct e1000_hw *hw);
77 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
78 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
80 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
81 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
82 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
83 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
85 uint16_t *max_length);
86 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
87 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
88 static int32_t e1000_id_led_init(struct e1000_hw * hw);
89 static void e1000_init_rx_addrs(struct e1000_hw *hw);
90 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
91 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
92 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
93 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
94 uint16_t words, uint16_t *data);
95 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
97 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
99 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
102 #define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val)
104 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw);
105 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
107 /* IGP cable length table */
109 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
110 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
111 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
112 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
113 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
114 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
115 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
116 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
117 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
120 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
121 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
122 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
123 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
124 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
125 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
126 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
127 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
128 104, 109, 114, 118, 121, 124};
131 /******************************************************************************
132 * Set the phy type member in the hw struct.
134 * hw - Struct containing variables accessed by shared code
135 *****************************************************************************/
137 e1000_set_phy_type(struct e1000_hw *hw)
139 DEBUGFUNC("e1000_set_phy_type");
141 if(hw->mac_type == e1000_undefined)
142 return -E1000_ERR_PHY_TYPE;
145 case M88E1000_E_PHY_ID:
146 case M88E1000_I_PHY_ID:
147 case M88E1011_I_PHY_ID:
148 case M88E1111_I_PHY_ID:
149 hw->phy_type = e1000_phy_m88;
151 case IGP01E1000_I_PHY_ID:
152 if(hw->mac_type == e1000_82541 ||
153 hw->mac_type == e1000_82541_rev_2 ||
154 hw->mac_type == e1000_82547 ||
155 hw->mac_type == e1000_82547_rev_2) {
156 hw->phy_type = e1000_phy_igp;
159 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563;
166 /* Should never have loaded on this device */
167 hw->phy_type = e1000_phy_undefined;
168 return -E1000_ERR_PHY_TYPE;
171 return E1000_SUCCESS;
174 /******************************************************************************
175 * IGP phy init script - initializes the GbE PHY
177 * hw - Struct containing variables accessed by shared code
178 *****************************************************************************/
180 e1000_phy_init_script(struct e1000_hw *hw)
183 uint16_t phy_saved_data;
185 DEBUGFUNC("e1000_phy_init_script");
187 if(hw->phy_init_script) {
190 /* Save off the current value of register 0x2F5B to be restored at
191 * the end of this routine. */
192 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
194 /* Disabled the PHY transmitter */
195 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
199 e1000_write_phy_reg(hw,0x0000,0x0140);
203 switch(hw->mac_type) {
206 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
208 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
210 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
212 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
214 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
216 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
218 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
220 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
222 e1000_write_phy_reg(hw, 0x2010, 0x0008);
225 case e1000_82541_rev_2:
226 case e1000_82547_rev_2:
227 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
233 e1000_write_phy_reg(hw, 0x0000, 0x3300);
237 /* Now enable the transmitter */
238 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
240 if(hw->mac_type == e1000_82547) {
241 uint16_t fused, fine, coarse;
243 /* Move to analog registers page */
244 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
246 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
247 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
249 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
250 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
252 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
253 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
254 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
255 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
256 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
258 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
259 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
260 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
262 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
263 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
264 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
270 /******************************************************************************
271 * Set the mac type member in the hw struct.
273 * hw - Struct containing variables accessed by shared code
274 *****************************************************************************/
276 e1000_set_mac_type(struct e1000_hw *hw)
278 DEBUGFUNC("e1000_set_mac_type");
280 switch (hw->device_id) {
281 case E1000_DEV_ID_82542:
282 switch (hw->revision_id) {
283 case E1000_82542_2_0_REV_ID:
284 hw->mac_type = e1000_82542_rev2_0;
286 case E1000_82542_2_1_REV_ID:
287 hw->mac_type = e1000_82542_rev2_1;
290 /* Invalid 82542 revision ID */
291 return -E1000_ERR_MAC_TYPE;
294 case E1000_DEV_ID_82543GC_FIBER:
295 case E1000_DEV_ID_82543GC_COPPER:
296 hw->mac_type = e1000_82543;
298 case E1000_DEV_ID_82544EI_COPPER:
299 case E1000_DEV_ID_82544EI_FIBER:
300 case E1000_DEV_ID_82544GC_COPPER:
301 case E1000_DEV_ID_82544GC_LOM:
302 hw->mac_type = e1000_82544;
304 case E1000_DEV_ID_82540EM:
305 case E1000_DEV_ID_82540EM_LOM:
306 case E1000_DEV_ID_82540EP:
307 case E1000_DEV_ID_82540EP_LOM:
308 case E1000_DEV_ID_82540EP_LP:
309 hw->mac_type = e1000_82540;
311 case E1000_DEV_ID_82545EM_COPPER:
312 case E1000_DEV_ID_82545EM_FIBER:
313 hw->mac_type = e1000_82545;
315 case E1000_DEV_ID_82545GM_COPPER:
316 case E1000_DEV_ID_82545GM_FIBER:
317 case E1000_DEV_ID_82545GM_SERDES:
318 hw->mac_type = e1000_82545_rev_3;
320 case E1000_DEV_ID_82546EB_COPPER:
321 case E1000_DEV_ID_82546EB_FIBER:
322 case E1000_DEV_ID_82546EB_QUAD_COPPER:
323 hw->mac_type = e1000_82546;
325 case E1000_DEV_ID_82546GB_COPPER:
326 case E1000_DEV_ID_82546GB_FIBER:
327 case E1000_DEV_ID_82546GB_SERDES:
328 case E1000_DEV_ID_82546GB_PCIE:
329 case E1000_DEV_ID_82546GB_QUAD_COPPER:
330 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
331 hw->mac_type = e1000_82546_rev_3;
333 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE:
335 hw->mac_type = e1000_82541;
337 case E1000_DEV_ID_82541ER:
338 case E1000_DEV_ID_82541GI:
339 case E1000_DEV_ID_82541GI_LF:
340 case E1000_DEV_ID_82541GI_MOBILE:
341 hw->mac_type = e1000_82541_rev_2;
343 case E1000_DEV_ID_82547EI:
344 hw->mac_type = e1000_82547;
346 case E1000_DEV_ID_82547GI:
347 hw->mac_type = e1000_82547_rev_2;
349 case E1000_DEV_ID_82571EB_COPPER:
350 case E1000_DEV_ID_82571EB_FIBER:
351 case E1000_DEV_ID_82571EB_SERDES:
352 hw->mac_type = e1000_82571;
354 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES:
357 hw->mac_type = e1000_82572;
359 case E1000_DEV_ID_82573E:
360 case E1000_DEV_ID_82573E_IAMT:
361 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573;
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan;
369 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE;
373 switch(hw->mac_type) {
374 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE;
380 hw->eeprom_semaphore_present = TRUE;
384 case e1000_82541_rev_2:
385 case e1000_82547_rev_2:
386 hw->asf_firmware_present = TRUE;
392 return E1000_SUCCESS;
395 /*****************************************************************************
396 * Set media type and TBI compatibility.
398 * hw - Struct containing variables accessed by shared code
399 * **************************************************************************/
401 e1000_set_media_type(struct e1000_hw *hw)
405 DEBUGFUNC("e1000_set_media_type");
407 if(hw->mac_type != e1000_82543) {
408 /* tbi_compatibility is only valid on 82543 */
409 hw->tbi_compatibility_en = FALSE;
412 switch (hw->device_id) {
413 case E1000_DEV_ID_82545GM_SERDES:
414 case E1000_DEV_ID_82546GB_SERDES:
415 case E1000_DEV_ID_82571EB_SERDES:
416 case E1000_DEV_ID_82572EI_SERDES:
417 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
418 hw->media_type = e1000_media_type_internal_serdes;
421 switch (hw->mac_type) {
422 case e1000_82542_rev2_0:
423 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber;
427 /* The STATUS_TBIMODE bit is reserved or reused for the this
430 hw->media_type = e1000_media_type_copper;
433 status = E1000_READ_REG(hw, STATUS);
434 if (status & E1000_STATUS_TBIMODE) {
435 hw->media_type = e1000_media_type_fiber;
436 /* tbi_compatibility not valid on fiber */
437 hw->tbi_compatibility_en = FALSE;
439 hw->media_type = e1000_media_type_copper;
446 /******************************************************************************
447 * Reset the transmit and receive units; mask and clear all interrupts.
449 * hw - Struct containing variables accessed by shared code
450 *****************************************************************************/
452 e1000_reset_hw(struct e1000_hw *hw)
460 uint32_t extcnf_ctrl;
463 DEBUGFUNC("e1000_reset_hw");
465 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
466 if(hw->mac_type == e1000_82542_rev2_0) {
467 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
468 e1000_pci_clear_mwi(hw);
471 if(hw->bus_type == e1000_bus_type_pci_express) {
472 /* Prevent the PCI-E bus from sticking if there is no TLP connection
473 * on the last TLP read/write transaction when MAC is reset.
475 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
476 DEBUGOUT("PCI-E Master disable polling has failed.\n");
480 /* Clear interrupt mask to stop board from generating interrupts */
481 DEBUGOUT("Masking off all interrupts\n");
482 E1000_WRITE_REG(hw, IMC, 0xffffffff);
484 /* Disable the Transmit and Receive units. Then delay to allow
485 * any pending transactions to complete before we hit the MAC with
488 E1000_WRITE_REG(hw, RCTL, 0);
489 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
490 E1000_WRITE_FLUSH(hw);
492 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
493 hw->tbi_compatibility_on = FALSE;
495 /* Delay to allow any outstanding PCI transactions to complete before
496 * resetting the device
500 ctrl = E1000_READ_REG(hw, CTRL);
502 /* Must reset the PHY before resetting the MAC */
503 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
504 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
508 /* Must acquire the MDIO ownership before MAC reset.
509 * Ownership defaults to firmware after a reset. */
510 if(hw->mac_type == e1000_82573) {
513 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
514 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
517 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
518 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
520 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
523 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
530 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self-
533 * clearing, and should clear within a microsecond.
535 DEBUGOUT("Issuing a global reset to MAC\n");
537 switch(hw->mac_type) {
543 case e1000_82541_rev_2:
544 /* These controllers can't ack the 64-bit write when issuing the
545 * reset, so use IO-mapping as a workaround to issue the reset */
546 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
548 case e1000_82545_rev_3:
549 case e1000_82546_rev_3:
550 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
558 /* After MAC reset, force reload of EEPROM to restore power-on settings to
559 * device. Later controllers reload the EEPROM automatically, so just wait
560 * for reload to complete.
562 switch(hw->mac_type) {
563 case e1000_82542_rev2_0:
564 case e1000_82542_rev2_1:
567 /* Wait for reset to complete */
569 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
570 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
571 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
572 E1000_WRITE_FLUSH(hw);
573 /* Wait for EEPROM reload */
577 case e1000_82541_rev_2:
579 case e1000_82547_rev_2:
580 /* Wait for EEPROM reload */
584 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
586 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
587 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
588 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
589 E1000_WRITE_FLUSH(hw);
594 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw);
597 /* We don't want to continue accessing MAC registers. */
601 /* Wait for EEPROM reload (it happens automatically) */
606 /* Disable HW ARPs on ASF enabled adapters */
607 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
608 manc = E1000_READ_REG(hw, MANC);
609 manc &= ~(E1000_MANC_ARP_EN);
610 E1000_WRITE_REG(hw, MANC, manc);
613 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
614 e1000_phy_init_script(hw);
616 /* Configure activity LED after PHY reset */
617 led_ctrl = E1000_READ_REG(hw, LEDCTL);
618 led_ctrl &= IGP_ACTIVITY_LED_MASK;
619 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
620 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
623 /* Clear interrupt mask to stop board from generating interrupts */
624 DEBUGOUT("Masking off all interrupts\n");
625 E1000_WRITE_REG(hw, IMC, 0xffffffff);
627 /* Clear any pending interrupt events. */
628 icr = E1000_READ_REG(hw, ICR);
630 /* If MWI was previously enabled, reenable it. */
631 if(hw->mac_type == e1000_82542_rev2_0) {
632 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
633 e1000_pci_set_mwi(hw);
636 return E1000_SUCCESS;
639 /******************************************************************************
640 * Performs basic configuration of the adapter.
642 * hw - Struct containing variables accessed by shared code
644 * Assumes that the controller has previously been reset and is in a
645 * post-reset uninitialized state. Initializes the receive address registers,
646 * multicast table, and VLAN filter table. Calls routines to setup link
647 * configuration and flow control settings. Clears all on-chip counters. Leaves
648 * the transmit and receive units disabled and uninitialized.
649 *****************************************************************************/
651 e1000_init_hw(struct e1000_hw *hw)
656 uint16_t pcix_cmd_word;
657 uint16_t pcix_stat_hi_word;
664 DEBUGFUNC("e1000_init_hw");
666 /* Initialize Identification LED */
667 ret_val = e1000_id_led_init(hw);
669 DEBUGOUT("Error Initializing Identification LED\n");
673 /* Set the media type and TBI compatibility */
674 e1000_set_media_type(hw);
676 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3)
679 E1000_WRITE_REG(hw, VET, 0);
680 e1000_clear_vfta(hw);
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) {
684 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
685 e1000_pci_clear_mwi(hw);
686 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
687 E1000_WRITE_FLUSH(hw);
691 /* Setup the receive address. This involves initializing all of the Receive
692 * Address Registers (RARs 0 - 15).
694 e1000_init_rx_addrs(hw);
696 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
697 if(hw->mac_type == e1000_82542_rev2_0) {
698 E1000_WRITE_REG(hw, RCTL, 0);
699 E1000_WRITE_FLUSH(hw);
701 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
702 e1000_pci_set_mwi(hw);
705 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE;
708 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
710 /* use write flush to prevent Memory Write Block (MWB) from
711 * occuring when accessing our register space */
712 E1000_WRITE_FLUSH(hw);
715 /* Set the PCI priority bit correctly in the CTRL register. This
716 * determines if the adapter gives priority to receives, or if it
717 * gives equal priority to transmits and receives. Valid only on
718 * 82542 and 82543 silicon.
720 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
721 ctrl = E1000_READ_REG(hw, CTRL);
722 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
725 switch(hw->mac_type) {
726 case e1000_82545_rev_3:
727 case e1000_82546_rev_3:
730 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
731 if(hw->bus_type == e1000_bus_type_pcix) {
732 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
733 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
735 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
736 PCIX_COMMAND_MMRBC_SHIFT;
737 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
738 PCIX_STATUS_HI_MMRBC_SHIFT;
739 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
740 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
741 if(cmd_mmrbc > stat_mmrbc) {
742 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
743 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
744 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
751 /* Call a subroutine to configure the link and setup flow control. */
752 ret_val = e1000_setup_link(hw);
754 /* Set the transmit descriptor write-back policy */
755 if(hw->mac_type > e1000_82544) {
756 ctrl = E1000_READ_REG(hw, TXDCTL);
757 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
758 switch (hw->mac_type) {
764 case e1000_80003es2lan:
765 ctrl |= E1000_TXDCTL_COUNT_DESC;
768 E1000_WRITE_REG(hw, TXDCTL, ctrl);
771 if (hw->mac_type == e1000_82573) {
772 e1000_enable_tx_pkt_filtering(hw);
775 switch (hw->mac_type) {
778 case e1000_80003es2lan:
779 /* Enable retransmit on late collisions */
780 reg_data = E1000_READ_REG(hw, TCTL);
781 reg_data |= E1000_TCTL_RTLC;
782 E1000_WRITE_REG(hw, TCTL, reg_data);
784 /* Configure Gigabit Carry Extend Padding */
785 reg_data = E1000_READ_REG(hw, TCTL_EXT);
786 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
787 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
788 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
790 /* Configure Transmit Inter-Packet Gap */
791 reg_data = E1000_READ_REG(hw, TIPG);
792 reg_data &= ~E1000_TIPG_IPGT_MASK;
793 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
794 E1000_WRITE_REG(hw, TIPG, reg_data);
796 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
797 reg_data &= ~0x00100000;
798 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
802 ctrl = E1000_READ_REG(hw, TXDCTL1);
803 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
804 if(hw->mac_type >= e1000_82571)
805 ctrl |= E1000_TXDCTL_COUNT_DESC;
806 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
812 if (hw->mac_type == e1000_82573) {
813 uint32_t gcr = E1000_READ_REG(hw, GCR);
814 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
815 E1000_WRITE_REG(hw, GCR, gcr);
818 /* Clear all of the statistics registers (clear on read). It is
819 * important that we do this after we have tried to establish link
820 * because the symbol error count will increment wildly if there
823 e1000_clear_hw_cntrs(hw);
825 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
826 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
827 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
828 /* Relaxed ordering must be disabled to avoid a parity
829 * error crash in a PCI slot. */
830 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
831 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
837 /******************************************************************************
838 * Adjust SERDES output amplitude based on EEPROM setting.
840 * hw - Struct containing variables accessed by shared code.
841 *****************************************************************************/
843 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
845 uint16_t eeprom_data;
848 DEBUGFUNC("e1000_adjust_serdes_amplitude");
850 if(hw->media_type != e1000_media_type_internal_serdes)
851 return E1000_SUCCESS;
853 switch(hw->mac_type) {
854 case e1000_82545_rev_3:
855 case e1000_82546_rev_3:
858 return E1000_SUCCESS;
861 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
866 if(eeprom_data != EEPROM_RESERVED_WORD) {
867 /* Adjust SERDES output amplitude only. */
868 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
874 return E1000_SUCCESS;
877 /******************************************************************************
878 * Configures flow control and link settings.
880 * hw - Struct containing variables accessed by shared code
882 * Determines which flow control settings to use. Calls the apropriate media-
883 * specific link configuration function. Configures the flow control settings.
884 * Assuming the adapter has a valid link partner, a valid link should be
885 * established. Assumes the hardware has previously been reset and the
886 * transmitter and receiver are not enabled.
887 *****************************************************************************/
889 e1000_setup_link(struct e1000_hw *hw)
893 uint16_t eeprom_data;
895 DEBUGFUNC("e1000_setup_link");
897 /* In the case of the phy reset being blocked, we already have a link.
898 * We do not have to set it up again. */
899 if (e1000_check_phy_reset_block(hw))
900 return E1000_SUCCESS;
902 /* Read and store word 0x0F of the EEPROM. This word contains bits
903 * that determine the hardware's default PAUSE (flow control) mode,
904 * a bit that determines whether the HW defaults to enabling or
905 * disabling auto-negotiation, and the direction of the
906 * SW defined pins. If there is no SW over-ride of the flow
907 * control setting, then the variable hw->fc will
908 * be initialized based on a value in the EEPROM.
910 if (hw->fc == e1000_fc_default) {
911 switch (hw->mac_type) {
913 hw->fc = e1000_fc_full;
916 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
919 DEBUGOUT("EEPROM Read Error\n");
920 return -E1000_ERR_EEPROM;
922 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
923 hw->fc = e1000_fc_none;
924 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
925 EEPROM_WORD0F_ASM_DIR)
926 hw->fc = e1000_fc_tx_pause;
928 hw->fc = e1000_fc_full;
933 /* We want to save off the original Flow Control configuration just
934 * in case we get disconnected and then reconnected into a different
935 * hub or switch with different Flow Control capabilities.
937 if(hw->mac_type == e1000_82542_rev2_0)
938 hw->fc &= (~e1000_fc_tx_pause);
940 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
941 hw->fc &= (~e1000_fc_rx_pause);
943 hw->original_fc = hw->fc;
945 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
947 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
948 * polarity value for the SW controlled pins, and setup the
949 * Extended Device Control reg with that info.
950 * This is needed because one of the SW controlled pins is used for
951 * signal detection. So this should be done before e1000_setup_pcs_link()
952 * or e1000_phy_setup() is called.
954 if (hw->mac_type == e1000_82543) {
955 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
958 DEBUGOUT("EEPROM Read Error\n");
959 return -E1000_ERR_EEPROM;
961 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
963 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
966 /* Call the necessary subroutine to configure the link. */
967 ret_val = (hw->media_type == e1000_media_type_copper) ?
968 e1000_setup_copper_link(hw) :
969 e1000_setup_fiber_serdes_link(hw);
971 /* Initialize the flow control address, type, and PAUSE timer
972 * registers to their default values. This is done even if flow
973 * control is disabled, because it does not hurt anything to
974 * initialize these registers.
976 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
978 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
979 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
980 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
982 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
984 /* Set the flow control receive threshold registers. Normally,
985 * these registers will be set to a default threshold that may be
986 * adjusted later by the driver's runtime code. However, if the
987 * ability to transmit pause frames in not enabled, then these
988 * registers will be set to 0.
990 if(!(hw->fc & e1000_fc_tx_pause)) {
991 E1000_WRITE_REG(hw, FCRTL, 0);
992 E1000_WRITE_REG(hw, FCRTH, 0);
994 /* We need to set up the Receive Threshold high and low water marks
995 * as well as (optionally) enabling the transmission of XON frames.
997 if(hw->fc_send_xon) {
998 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
999 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1001 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1002 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1008 /******************************************************************************
1009 * Sets up link for a fiber based or serdes based adapter
1011 * hw - Struct containing variables accessed by shared code
1013 * Manipulates Physical Coding Sublayer functions in order to configure
1014 * link. Assumes the hardware has been previously reset and the transmitter
1015 * and receiver are not enabled.
1016 *****************************************************************************/
1018 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1024 uint32_t signal = 0;
1027 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1029 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1030 * until explicitly turned off or a power cycle is performed. A read to
1031 * the register does not indicate its status. Therefore, we ensure
1032 * loopback mode is disabled during initialization.
1034 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1035 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1037 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1038 * set when the optics detect a signal. On older adapters, it will be
1039 * cleared when there is a signal. This applies to fiber media only.
1040 * If we're on serdes media, adjust the output amplitude to value set in
1043 ctrl = E1000_READ_REG(hw, CTRL);
1044 if(hw->media_type == e1000_media_type_fiber)
1045 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1047 ret_val = e1000_adjust_serdes_amplitude(hw);
1051 /* Take the link out of reset */
1052 ctrl &= ~(E1000_CTRL_LRST);
1054 /* Adjust VCO speed to improve BER performance */
1055 ret_val = e1000_set_vco_speed(hw);
1059 e1000_config_collision_dist(hw);
1061 /* Check for a software override of the flow control settings, and setup
1062 * the device accordingly. If auto-negotiation is enabled, then software
1063 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1064 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1065 * auto-negotiation is disabled, then software will have to manually
1066 * configure the two flow control enable bits in the CTRL register.
1068 * The possible values of the "fc" parameter are:
1069 * 0: Flow control is completely disabled
1070 * 1: Rx flow control is enabled (we can receive pause frames, but
1071 * not send pause frames).
1072 * 2: Tx flow control is enabled (we can send pause frames but we do
1073 * not support receiving pause frames).
1074 * 3: Both Rx and TX flow control (symmetric) are enabled.
1078 /* Flow control is completely disabled by a software over-ride. */
1079 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1081 case e1000_fc_rx_pause:
1082 /* RX Flow control is enabled and TX Flow control is disabled by a
1083 * software over-ride. Since there really isn't a way to advertise
1084 * that we are capable of RX Pause ONLY, we will advertise that we
1085 * support both symmetric and asymmetric RX PAUSE. Later, we will
1086 * disable the adapter's ability to send PAUSE frames.
1088 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1090 case e1000_fc_tx_pause:
1091 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1092 * software over-ride.
1094 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1097 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1098 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1101 DEBUGOUT("Flow control param set incorrectly\n");
1102 return -E1000_ERR_CONFIG;
1106 /* Since auto-negotiation is enabled, take the link out of reset (the link
1107 * will be in reset, because we previously reset the chip). This will
1108 * restart auto-negotiation. If auto-neogtiation is successful then the
1109 * link-up status bit will be set and the flow control enable bits (RFCE
1110 * and TFCE) will be set according to their negotiated value.
1112 DEBUGOUT("Auto-negotiation enabled\n");
1114 E1000_WRITE_REG(hw, TXCW, txcw);
1115 E1000_WRITE_REG(hw, CTRL, ctrl);
1116 E1000_WRITE_FLUSH(hw);
1121 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1122 * indication in the Device Status Register. Time-out if a link isn't
1123 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1124 * less than 500 milliseconds even if the other end is doing it in SW).
1125 * For internal serdes, we just assume a signal is present, then poll.
1127 if(hw->media_type == e1000_media_type_internal_serdes ||
1128 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1129 DEBUGOUT("Looking for Link\n");
1130 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1132 status = E1000_READ_REG(hw, STATUS);
1133 if(status & E1000_STATUS_LU) break;
1135 if(i == (LINK_UP_TIMEOUT / 10)) {
1136 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1137 hw->autoneg_failed = 1;
1138 /* AutoNeg failed to achieve a link, so we'll call
1139 * e1000_check_for_link. This routine will force the link up if
1140 * we detect a signal. This will allow us to communicate with
1141 * non-autonegotiating link partners.
1143 ret_val = e1000_check_for_link(hw);
1145 DEBUGOUT("Error while checking for link\n");
1148 hw->autoneg_failed = 0;
1150 hw->autoneg_failed = 0;
1151 DEBUGOUT("Valid Link Found\n");
1154 DEBUGOUT("No Signal Detected\n");
1156 return E1000_SUCCESS;
1159 /******************************************************************************
1160 * Make sure we have a valid PHY and change PHY mode before link setup.
1162 * hw - Struct containing variables accessed by shared code
1163 ******************************************************************************/
1165 e1000_copper_link_preconfig(struct e1000_hw *hw)
1171 DEBUGFUNC("e1000_copper_link_preconfig");
1173 ctrl = E1000_READ_REG(hw, CTRL);
1174 /* With 82543, we need to force speed and duplex on the MAC equal to what
1175 * the PHY speed and duplex configuration is. In addition, we need to
1176 * perform a hardware reset on the PHY to take it out of reset.
1178 if(hw->mac_type > e1000_82543) {
1179 ctrl |= E1000_CTRL_SLU;
1180 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1181 E1000_WRITE_REG(hw, CTRL, ctrl);
1183 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1184 E1000_WRITE_REG(hw, CTRL, ctrl);
1185 ret_val = e1000_phy_hw_reset(hw);
1190 /* Make sure we have a valid PHY */
1191 ret_val = e1000_detect_gig_phy(hw);
1193 DEBUGOUT("Error, did not detect valid phy.\n");
1196 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1198 /* Set PHY to class A mode (if necessary) */
1199 ret_val = e1000_set_phy_mode(hw);
1203 if((hw->mac_type == e1000_82545_rev_3) ||
1204 (hw->mac_type == e1000_82546_rev_3)) {
1205 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1206 phy_data |= 0x00000008;
1207 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1210 if(hw->mac_type <= e1000_82543 ||
1211 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1212 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1213 hw->phy_reset_disable = FALSE;
1215 return E1000_SUCCESS;
1219 /********************************************************************
1220 * Copper link setup for e1000_phy_igp series.
1222 * hw - Struct containing variables accessed by shared code
1223 *********************************************************************/
1225 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1231 DEBUGFUNC("e1000_copper_link_igp_setup");
1233 if (hw->phy_reset_disable)
1234 return E1000_SUCCESS;
1236 ret_val = e1000_phy_reset(hw);
1238 DEBUGOUT("Error Resetting the PHY\n");
1242 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1245 /* Configure activity LED after PHY reset */
1246 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1247 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1248 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1249 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1251 /* disable lplu d3 during driver init */
1252 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1254 DEBUGOUT("Error Disabling LPLU D3\n");
1258 /* disable lplu d0 during driver init */
1259 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1261 DEBUGOUT("Error Disabling LPLU D0\n");
1264 /* Configure mdi-mdix settings */
1265 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1269 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1270 hw->dsp_config_state = e1000_dsp_config_disabled;
1271 /* Force MDI for earlier revs of the IGP PHY */
1272 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1276 hw->dsp_config_state = e1000_dsp_config_enabled;
1277 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1281 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1284 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1288 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1292 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1296 /* set auto-master slave resolution settings */
1298 e1000_ms_type phy_ms_setting = hw->master_slave;
1300 if(hw->ffe_config_state == e1000_ffe_config_active)
1301 hw->ffe_config_state = e1000_ffe_config_enabled;
1303 if(hw->dsp_config_state == e1000_dsp_config_activated)
1304 hw->dsp_config_state = e1000_dsp_config_enabled;
1306 /* when autonegotiation advertisment is only 1000Mbps then we
1307 * should disable SmartSpeed and enable Auto MasterSlave
1308 * resolution as hardware default. */
1309 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1310 /* Disable SmartSpeed */
1311 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1314 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1315 ret_val = e1000_write_phy_reg(hw,
1316 IGP01E1000_PHY_PORT_CONFIG,
1320 /* Set auto Master/Slave resolution process */
1321 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1324 phy_data &= ~CR_1000T_MS_ENABLE;
1325 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1330 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1334 /* load defaults for future use */
1335 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1336 ((phy_data & CR_1000T_MS_VALUE) ?
1337 e1000_ms_force_master :
1338 e1000_ms_force_slave) :
1341 switch (phy_ms_setting) {
1342 case e1000_ms_force_master:
1343 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1345 case e1000_ms_force_slave:
1346 phy_data |= CR_1000T_MS_ENABLE;
1347 phy_data &= ~(CR_1000T_MS_VALUE);
1350 phy_data &= ~CR_1000T_MS_ENABLE;
1354 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1359 return E1000_SUCCESS;
1362 /********************************************************************
1363 * Copper link setup for e1000_phy_gg82563 series.
1365 * hw - Struct containing variables accessed by shared code
1366 *********************************************************************/
1368 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1374 DEBUGFUNC("e1000_copper_link_ggp_setup");
1376 if(!hw->phy_reset_disable) {
1378 /* Enable CRS on TX for half-duplex operation. */
1379 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1384 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1385 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1386 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1388 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1394 * MDI/MDI-X = 0 (default)
1395 * 0 - Auto for all speeds
1398 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1400 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1404 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1408 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1411 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1415 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1420 * disable_polarity_correction = 0 (default)
1421 * Automatic Correction for Reversed Cable Polarity
1425 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1426 if(hw->disable_polarity_correction == 1)
1427 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1428 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1433 /* SW Reset the PHY so all changes take effect */
1434 ret_val = e1000_phy_reset(hw);
1436 DEBUGOUT("Error Resetting the PHY\n");
1439 } /* phy_reset_disable */
1441 if (hw->mac_type == e1000_80003es2lan) {
1442 /* Bypass RX and TX FIFO's */
1443 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1444 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1445 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1449 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1453 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1454 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1459 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1460 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1461 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1463 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1468 /* Do not init these registers when the HW is in IAMT mode, since the
1469 * firmware will have already initialized them. We only initialize
1470 * them if the HW is not in IAMT mode.
1472 if (e1000_check_mng_mode(hw) == FALSE) {
1473 /* Enable Electrical Idle on the PHY */
1474 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1475 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1480 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1485 /* Enable Pass False Carrier on the PHY */
1486 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1488 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1494 /* Workaround: Disable padding in Kumeran interface in the MAC
1495 * and in the PHY to avoid CRC errors.
1497 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1501 phy_data |= GG82563_ICR_DIS_PADDING;
1502 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1508 return E1000_SUCCESS;
1511 /********************************************************************
1512 * Copper link setup for e1000_phy_m88 series.
1514 * hw - Struct containing variables accessed by shared code
1515 *********************************************************************/
1517 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1522 DEBUGFUNC("e1000_copper_link_mgp_setup");
1524 if(hw->phy_reset_disable)
1525 return E1000_SUCCESS;
1527 /* Enable CRS on TX. This must be set for half-duplex operation. */
1528 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1532 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1535 * MDI/MDI-X = 0 (default)
1536 * 0 - Auto for all speeds
1539 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1541 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1545 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1548 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1551 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1555 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1560 * disable_polarity_correction = 0 (default)
1561 * Automatic Correction for Reversed Cable Polarity
1565 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1566 if(hw->disable_polarity_correction == 1)
1567 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1568 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1572 /* Force TX_CLK in the Extended PHY Specific Control Register
1575 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1579 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1581 if (hw->phy_revision < M88E1011_I_REV_4) {
1582 /* Configure Master and Slave downshift values */
1583 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1584 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1585 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1586 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1587 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1592 /* SW Reset the PHY so all changes take effect */
1593 ret_val = e1000_phy_reset(hw);
1595 DEBUGOUT("Error Resetting the PHY\n");
1599 return E1000_SUCCESS;
1602 /********************************************************************
1603 * Setup auto-negotiation and flow control advertisements,
1604 * and then perform auto-negotiation.
1606 * hw - Struct containing variables accessed by shared code
1607 *********************************************************************/
1609 e1000_copper_link_autoneg(struct e1000_hw *hw)
1614 DEBUGFUNC("e1000_copper_link_autoneg");
1616 /* Perform some bounds checking on the hw->autoneg_advertised
1617 * parameter. If this variable is zero, then set it to the default.
1619 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1621 /* If autoneg_advertised is zero, we assume it was not defaulted
1622 * by the calling code so we set to advertise full capability.
1624 if(hw->autoneg_advertised == 0)
1625 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1627 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1628 ret_val = e1000_phy_setup_autoneg(hw);
1630 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1633 DEBUGOUT("Restarting Auto-Neg\n");
1635 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1636 * the Auto Neg Restart bit in the PHY control register.
1638 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1642 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1643 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1647 /* Does the user want to wait for Auto-Neg to complete here, or
1648 * check at a later time (for example, callback routine).
1650 if(hw->wait_autoneg_complete) {
1651 ret_val = e1000_wait_autoneg(hw);
1653 DEBUGOUT("Error while waiting for autoneg to complete\n");
1658 hw->get_link_status = TRUE;
1660 return E1000_SUCCESS;
1664 /******************************************************************************
1665 * Config the MAC and the PHY after link is up.
1666 * 1) Set up the MAC to the current PHY speed/duplex
1667 * if we are on 82543. If we
1668 * are on newer silicon, we only need to configure
1669 * collision distance in the Transmit Control Register.
1670 * 2) Set up flow control on the MAC to that established with
1672 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1674 * hw - Struct containing variables accessed by shared code
1675 ******************************************************************************/
1677 e1000_copper_link_postconfig(struct e1000_hw *hw)
1680 DEBUGFUNC("e1000_copper_link_postconfig");
1682 if(hw->mac_type >= e1000_82544) {
1683 e1000_config_collision_dist(hw);
1685 ret_val = e1000_config_mac_to_phy(hw);
1687 DEBUGOUT("Error configuring MAC to PHY settings\n");
1691 ret_val = e1000_config_fc_after_link_up(hw);
1693 DEBUGOUT("Error Configuring Flow Control\n");
1697 /* Config DSP to improve Giga link quality */
1698 if(hw->phy_type == e1000_phy_igp) {
1699 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1701 DEBUGOUT("Error Configuring DSP after link up\n");
1706 return E1000_SUCCESS;
1709 /******************************************************************************
1710 * Detects which PHY is present and setup the speed and duplex
1712 * hw - Struct containing variables accessed by shared code
1713 ******************************************************************************/
1715 e1000_setup_copper_link(struct e1000_hw *hw)
1722 DEBUGFUNC("e1000_setup_copper_link");
1724 /* Check if it is a valid PHY and set PHY mode if necessary. */
1725 ret_val = e1000_copper_link_preconfig(hw);
1729 switch (hw->mac_type) {
1730 case e1000_80003es2lan:
1731 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1735 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1736 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1745 if (hw->phy_type == e1000_phy_igp ||
1746 hw->phy_type == e1000_phy_igp_2) {
1747 ret_val = e1000_copper_link_igp_setup(hw);
1750 } else if (hw->phy_type == e1000_phy_m88) {
1751 ret_val = e1000_copper_link_mgp_setup(hw);
1754 } else if (hw->phy_type == e1000_phy_gg82563) {
1755 ret_val = e1000_copper_link_ggp_setup(hw);
1761 /* Setup autoneg and flow control advertisement
1762 * and perform autonegotiation */
1763 ret_val = e1000_copper_link_autoneg(hw);
1767 /* PHY will be set to 10H, 10F, 100H,or 100F
1768 * depending on value from forced_speed_duplex. */
1769 DEBUGOUT("Forcing speed and duplex\n");
1770 ret_val = e1000_phy_force_speed_duplex(hw);
1772 DEBUGOUT("Error Forcing Speed and Duplex\n");
1777 /* Check link status. Wait up to 100 microseconds for link to become
1780 for(i = 0; i < 10; i++) {
1781 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1784 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1788 if(phy_data & MII_SR_LINK_STATUS) {
1789 /* Config the MAC and PHY after link is up */
1790 ret_val = e1000_copper_link_postconfig(hw);
1794 DEBUGOUT("Valid link established!!!\n");
1795 return E1000_SUCCESS;
1800 DEBUGOUT("Unable to establish link!!!\n");
1801 return E1000_SUCCESS;
1804 /******************************************************************************
1805 * Configure the MAC-to-PHY interface for 10/100Mbps
1807 * hw - Struct containing variables accessed by shared code
1808 ******************************************************************************/
1810 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1812 int32_t ret_val = E1000_SUCCESS;
1816 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1818 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1819 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1824 /* Configure Transmit Inter-Packet Gap */
1825 tipg = E1000_READ_REG(hw, TIPG);
1826 tipg &= ~E1000_TIPG_IPGT_MASK;
1827 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1828 E1000_WRITE_REG(hw, TIPG, tipg);
1834 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1836 int32_t ret_val = E1000_SUCCESS;
1840 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1842 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
1843 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1848 /* Configure Transmit Inter-Packet Gap */
1849 tipg = E1000_READ_REG(hw, TIPG);
1850 tipg &= ~E1000_TIPG_IPGT_MASK;
1851 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1852 E1000_WRITE_REG(hw, TIPG, tipg);
1857 /******************************************************************************
1858 * Configures PHY autoneg and flow control advertisement settings
1860 * hw - Struct containing variables accessed by shared code
1861 ******************************************************************************/
1863 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1866 uint16_t mii_autoneg_adv_reg;
1867 uint16_t mii_1000t_ctrl_reg;
1869 DEBUGFUNC("e1000_phy_setup_autoneg");
1871 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1872 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1876 /* Read the MII 1000Base-T Control Register (Address 9). */
1877 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1881 /* Need to parse both autoneg_advertised and fc and set up
1882 * the appropriate PHY registers. First we will parse for
1883 * autoneg_advertised software override. Since we can advertise
1884 * a plethora of combinations, we need to check each bit
1888 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1889 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1890 * the 1000Base-T Control Register (Address 9).
1892 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1893 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1895 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1897 /* Do we want to advertise 10 Mb Half Duplex? */
1898 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1899 DEBUGOUT("Advertise 10mb Half duplex\n");
1900 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1903 /* Do we want to advertise 10 Mb Full Duplex? */
1904 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1905 DEBUGOUT("Advertise 10mb Full duplex\n");
1906 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1909 /* Do we want to advertise 100 Mb Half Duplex? */
1910 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1911 DEBUGOUT("Advertise 100mb Half duplex\n");
1912 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1915 /* Do we want to advertise 100 Mb Full Duplex? */
1916 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1917 DEBUGOUT("Advertise 100mb Full duplex\n");
1918 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1921 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1922 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1923 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1926 /* Do we want to advertise 1000 Mb Full Duplex? */
1927 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1928 DEBUGOUT("Advertise 1000mb Full duplex\n");
1929 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1932 /* Check for a software override of the flow control settings, and
1933 * setup the PHY advertisement registers accordingly. If
1934 * auto-negotiation is enabled, then software will have to set the
1935 * "PAUSE" bits to the correct value in the Auto-Negotiation
1936 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1938 * The possible values of the "fc" parameter are:
1939 * 0: Flow control is completely disabled
1940 * 1: Rx flow control is enabled (we can receive pause frames
1941 * but not send pause frames).
1942 * 2: Tx flow control is enabled (we can send pause frames
1943 * but we do not support receiving pause frames).
1944 * 3: Both Rx and TX flow control (symmetric) are enabled.
1945 * other: No software override. The flow control configuration
1946 * in the EEPROM is used.
1949 case e1000_fc_none: /* 0 */
1950 /* Flow control (RX & TX) is completely disabled by a
1951 * software over-ride.
1953 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1955 case e1000_fc_rx_pause: /* 1 */
1956 /* RX Flow control is enabled, and TX Flow control is
1957 * disabled, by a software over-ride.
1959 /* Since there really isn't a way to advertise that we are
1960 * capable of RX Pause ONLY, we will advertise that we
1961 * support both symmetric and asymmetric RX PAUSE. Later
1962 * (in e1000_config_fc_after_link_up) we will disable the
1963 *hw's ability to send PAUSE frames.
1965 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1967 case e1000_fc_tx_pause: /* 2 */
1968 /* TX Flow control is enabled, and RX Flow control is
1969 * disabled, by a software over-ride.
1971 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1972 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1974 case e1000_fc_full: /* 3 */
1975 /* Flow control (both RX and TX) is enabled by a software
1978 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1981 DEBUGOUT("Flow control param set incorrectly\n");
1982 return -E1000_ERR_CONFIG;
1985 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1989 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1991 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1995 return E1000_SUCCESS;
1998 /******************************************************************************
1999 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2001 * hw - Struct containing variables accessed by shared code
2002 ******************************************************************************/
2004 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2008 uint16_t mii_ctrl_reg;
2009 uint16_t mii_status_reg;
2013 DEBUGFUNC("e1000_phy_force_speed_duplex");
2015 /* Turn off Flow control if we are forcing speed and duplex. */
2016 hw->fc = e1000_fc_none;
2018 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2020 /* Read the Device Control Register. */
2021 ctrl = E1000_READ_REG(hw, CTRL);
2023 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2024 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2025 ctrl &= ~(DEVICE_SPEED_MASK);
2027 /* Clear the Auto Speed Detect Enable bit. */
2028 ctrl &= ~E1000_CTRL_ASDE;
2030 /* Read the MII Control Register. */
2031 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2035 /* We need to disable autoneg in order to force link and duplex. */
2037 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2039 /* Are we forcing Full or Half Duplex? */
2040 if(hw->forced_speed_duplex == e1000_100_full ||
2041 hw->forced_speed_duplex == e1000_10_full) {
2042 /* We want to force full duplex so we SET the full duplex bits in the
2043 * Device and MII Control Registers.
2045 ctrl |= E1000_CTRL_FD;
2046 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2047 DEBUGOUT("Full Duplex\n");
2049 /* We want to force half duplex so we CLEAR the full duplex bits in
2050 * the Device and MII Control Registers.
2052 ctrl &= ~E1000_CTRL_FD;
2053 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2054 DEBUGOUT("Half Duplex\n");
2057 /* Are we forcing 100Mbps??? */
2058 if(hw->forced_speed_duplex == e1000_100_full ||
2059 hw->forced_speed_duplex == e1000_100_half) {
2060 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2061 ctrl |= E1000_CTRL_SPD_100;
2062 mii_ctrl_reg |= MII_CR_SPEED_100;
2063 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2064 DEBUGOUT("Forcing 100mb ");
2066 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2067 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2068 mii_ctrl_reg |= MII_CR_SPEED_10;
2069 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2070 DEBUGOUT("Forcing 10mb ");
2073 e1000_config_collision_dist(hw);
2075 /* Write the configured values back to the Device Control Reg. */
2076 E1000_WRITE_REG(hw, CTRL, ctrl);
2078 if ((hw->phy_type == e1000_phy_m88) ||
2079 (hw->phy_type == e1000_phy_gg82563)) {
2080 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2084 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2085 * forced whenever speed are duplex are forced.
2087 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2088 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2092 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2094 /* Need to reset the PHY or these changes will be ignored */
2095 mii_ctrl_reg |= MII_CR_RESET;
2097 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2098 * forced whenever speed or duplex are forced.
2100 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2104 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2105 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2107 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2112 /* Write back the modified PHY MII control register. */
2113 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2119 /* The wait_autoneg_complete flag may be a little misleading here.
2120 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2121 * But we do want to delay for a period while forcing only so we
2122 * don't generate false No Link messages. So we will wait here
2123 * only if the user has set wait_autoneg_complete to 1, which is
2126 if(hw->wait_autoneg_complete) {
2127 /* We will wait for autoneg to complete. */
2128 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2131 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2132 for(i = PHY_FORCE_TIME; i > 0; i--) {
2133 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2136 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2140 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2144 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2148 ((hw->phy_type == e1000_phy_m88) ||
2149 (hw->phy_type == e1000_phy_gg82563))) {
2150 /* We didn't get link. Reset the DSP and wait again for link. */
2151 ret_val = e1000_phy_reset_dsp(hw);
2153 DEBUGOUT("Error Resetting PHY DSP\n");
2157 /* This loop will early-out if the link condition has been met. */
2158 for(i = PHY_FORCE_TIME; i > 0; i--) {
2159 if(mii_status_reg & MII_SR_LINK_STATUS) break;
2161 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2164 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2168 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2174 if (hw->phy_type == e1000_phy_m88) {
2175 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2176 * Extended PHY Specific Control Register to 25MHz clock. This value
2177 * defaults back to a 2.5MHz clock when the PHY is reset.
2179 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2183 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2184 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2188 /* In addition, because of the s/w reset above, we need to enable CRS on
2189 * TX. This must be set for both full and half duplex operation.
2191 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2195 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2196 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2200 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2202 (hw->forced_speed_duplex == e1000_10_full ||
2203 hw->forced_speed_duplex == e1000_10_half)) {
2204 ret_val = e1000_polarity_reversal_workaround(hw);
2208 } else if (hw->phy_type == e1000_phy_gg82563) {
2209 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2210 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2211 * we're not in a forced 10/duplex configuration. */
2212 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2216 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2217 if ((hw->forced_speed_duplex == e1000_10_full) ||
2218 (hw->forced_speed_duplex == e1000_10_half))
2219 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2221 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2223 /* Also due to the reset, we need to enable CRS on Tx. */
2224 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2226 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2230 return E1000_SUCCESS;
2233 /******************************************************************************
2234 * Sets the collision distance in the Transmit Control register
2236 * hw - Struct containing variables accessed by shared code
2238 * Link should have been established previously. Reads the speed and duplex
2239 * information from the Device Status register.
2240 ******************************************************************************/
2242 e1000_config_collision_dist(struct e1000_hw *hw)
2244 uint32_t tctl, coll_dist;
2246 DEBUGFUNC("e1000_config_collision_dist");
2248 if (hw->mac_type < e1000_82543)
2249 coll_dist = E1000_COLLISION_DISTANCE_82542;
2251 coll_dist = E1000_COLLISION_DISTANCE;
2253 tctl = E1000_READ_REG(hw, TCTL);
2255 tctl &= ~E1000_TCTL_COLD;
2256 tctl |= coll_dist << E1000_COLD_SHIFT;
2258 E1000_WRITE_REG(hw, TCTL, tctl);
2259 E1000_WRITE_FLUSH(hw);
2262 /******************************************************************************
2263 * Sets MAC speed and duplex settings to reflect the those in the PHY
2265 * hw - Struct containing variables accessed by shared code
2266 * mii_reg - data to write to the MII control register
2268 * The contents of the PHY register containing the needed information need to
2270 ******************************************************************************/
2272 e1000_config_mac_to_phy(struct e1000_hw *hw)
2278 DEBUGFUNC("e1000_config_mac_to_phy");
2280 /* 82544 or newer MAC, Auto Speed Detection takes care of
2281 * MAC speed/duplex configuration.*/
2282 if (hw->mac_type >= e1000_82544)
2283 return E1000_SUCCESS;
2285 /* Read the Device Control Register and set the bits to Force Speed
2288 ctrl = E1000_READ_REG(hw, CTRL);
2289 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2290 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2292 /* Set up duplex in the Device Control and Transmit Control
2293 * registers depending on negotiated values.
2295 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2299 if(phy_data & M88E1000_PSSR_DPLX)
2300 ctrl |= E1000_CTRL_FD;
2302 ctrl &= ~E1000_CTRL_FD;
2304 e1000_config_collision_dist(hw);
2306 /* Set up speed in the Device Control register depending on
2307 * negotiated values.
2309 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2310 ctrl |= E1000_CTRL_SPD_1000;
2311 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2312 ctrl |= E1000_CTRL_SPD_100;
2314 /* Write the configured values back to the Device Control Reg. */
2315 E1000_WRITE_REG(hw, CTRL, ctrl);
2316 return E1000_SUCCESS;
2319 /******************************************************************************
2320 * Forces the MAC's flow control settings.
2322 * hw - Struct containing variables accessed by shared code
2324 * Sets the TFCE and RFCE bits in the device control register to reflect
2325 * the adapter settings. TFCE and RFCE need to be explicitly set by
2326 * software when a Copper PHY is used because autonegotiation is managed
2327 * by the PHY rather than the MAC. Software must also configure these
2328 * bits when link is forced on a fiber connection.
2329 *****************************************************************************/
2331 e1000_force_mac_fc(struct e1000_hw *hw)
2335 DEBUGFUNC("e1000_force_mac_fc");
2337 /* Get the current configuration of the Device Control Register */
2338 ctrl = E1000_READ_REG(hw, CTRL);
2340 /* Because we didn't get link via the internal auto-negotiation
2341 * mechanism (we either forced link or we got link via PHY
2342 * auto-neg), we have to manually enable/disable transmit an
2343 * receive flow control.
2345 * The "Case" statement below enables/disable flow control
2346 * according to the "hw->fc" parameter.
2348 * The possible values of the "fc" parameter are:
2349 * 0: Flow control is completely disabled
2350 * 1: Rx flow control is enabled (we can receive pause
2351 * frames but not send pause frames).
2352 * 2: Tx flow control is enabled (we can send pause frames
2353 * frames but we do not receive pause frames).
2354 * 3: Both Rx and TX flow control (symmetric) is enabled.
2355 * other: No other values should be possible at this point.
2360 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2362 case e1000_fc_rx_pause:
2363 ctrl &= (~E1000_CTRL_TFCE);
2364 ctrl |= E1000_CTRL_RFCE;
2366 case e1000_fc_tx_pause:
2367 ctrl &= (~E1000_CTRL_RFCE);
2368 ctrl |= E1000_CTRL_TFCE;
2371 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2374 DEBUGOUT("Flow control param set incorrectly\n");
2375 return -E1000_ERR_CONFIG;
2378 /* Disable TX Flow Control for 82542 (rev 2.0) */
2379 if(hw->mac_type == e1000_82542_rev2_0)
2380 ctrl &= (~E1000_CTRL_TFCE);
2382 E1000_WRITE_REG(hw, CTRL, ctrl);
2383 return E1000_SUCCESS;
2386 /******************************************************************************
2387 * Configures flow control settings after link is established
2389 * hw - Struct containing variables accessed by shared code
2391 * Should be called immediately after a valid link has been established.
2392 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2393 * and autonegotiation is enabled, the MAC flow control settings will be set
2394 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2395 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2396 *****************************************************************************/
2398 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2401 uint16_t mii_status_reg;
2402 uint16_t mii_nway_adv_reg;
2403 uint16_t mii_nway_lp_ability_reg;
2407 DEBUGFUNC("e1000_config_fc_after_link_up");
2409 /* Check for the case where we have fiber media and auto-neg failed
2410 * so we had to force link. In this case, we need to force the
2411 * configuration of the MAC to match the "fc" parameter.
2413 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2414 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2415 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2416 ret_val = e1000_force_mac_fc(hw);
2418 DEBUGOUT("Error forcing flow control settings\n");
2423 /* Check for the case where we have copper media and auto-neg is
2424 * enabled. In this case, we need to check and see if Auto-Neg
2425 * has completed, and if so, how the PHY and link partner has
2426 * flow control configured.
2428 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2429 /* Read the MII Status Register and check to see if AutoNeg
2430 * has completed. We read this twice because this reg has
2431 * some "sticky" (latched) bits.
2433 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2436 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2440 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2441 /* The AutoNeg process has completed, so we now need to
2442 * read both the Auto Negotiation Advertisement Register
2443 * (Address 4) and the Auto_Negotiation Base Page Ability
2444 * Register (Address 5) to determine how flow control was
2447 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2451 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2452 &mii_nway_lp_ability_reg);
2456 /* Two bits in the Auto Negotiation Advertisement Register
2457 * (Address 4) and two bits in the Auto Negotiation Base
2458 * Page Ability Register (Address 5) determine flow control
2459 * for both the PHY and the link partner. The following
2460 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2461 * 1999, describes these PAUSE resolution bits and how flow
2462 * control is determined based upon these settings.
2463 * NOTE: DC = Don't Care
2465 * LOCAL DEVICE | LINK PARTNER
2466 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2467 *-------|---------|-------|---------|--------------------
2468 * 0 | 0 | DC | DC | e1000_fc_none
2469 * 0 | 1 | 0 | DC | e1000_fc_none
2470 * 0 | 1 | 1 | 0 | e1000_fc_none
2471 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2472 * 1 | 0 | 0 | DC | e1000_fc_none
2473 * 1 | DC | 1 | DC | e1000_fc_full
2474 * 1 | 1 | 0 | 0 | e1000_fc_none
2475 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2478 /* Are both PAUSE bits set to 1? If so, this implies
2479 * Symmetric Flow Control is enabled at both ends. The
2480 * ASM_DIR bits are irrelevant per the spec.
2482 * For Symmetric Flow Control:
2484 * LOCAL DEVICE | LINK PARTNER
2485 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2486 *-------|---------|-------|---------|--------------------
2487 * 1 | DC | 1 | DC | e1000_fc_full
2490 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2491 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2492 /* Now we need to check if the user selected RX ONLY
2493 * of pause frames. In this case, we had to advertise
2494 * FULL flow control because we could not advertise RX
2495 * ONLY. Hence, we must now check to see if we need to
2496 * turn OFF the TRANSMISSION of PAUSE frames.
2498 if(hw->original_fc == e1000_fc_full) {
2499 hw->fc = e1000_fc_full;
2500 DEBUGOUT("Flow Control = FULL.\n");
2502 hw->fc = e1000_fc_rx_pause;
2503 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2506 /* For receiving PAUSE frames ONLY.
2508 * LOCAL DEVICE | LINK PARTNER
2509 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2510 *-------|---------|-------|---------|--------------------
2511 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2514 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2515 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2516 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2517 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2518 hw->fc = e1000_fc_tx_pause;
2519 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2521 /* For transmitting PAUSE frames ONLY.
2523 * LOCAL DEVICE | LINK PARTNER
2524 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2525 *-------|---------|-------|---------|--------------------
2526 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2529 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2530 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2531 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2532 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2533 hw->fc = e1000_fc_rx_pause;
2534 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2536 /* Per the IEEE spec, at this point flow control should be
2537 * disabled. However, we want to consider that we could
2538 * be connected to a legacy switch that doesn't advertise
2539 * desired flow control, but can be forced on the link
2540 * partner. So if we advertised no flow control, that is
2541 * what we will resolve to. If we advertised some kind of
2542 * receive capability (Rx Pause Only or Full Flow Control)
2543 * and the link partner advertised none, we will configure
2544 * ourselves to enable Rx Flow Control only. We can do
2545 * this safely for two reasons: If the link partner really
2546 * didn't want flow control enabled, and we enable Rx, no
2547 * harm done since we won't be receiving any PAUSE frames
2548 * anyway. If the intent on the link partner was to have
2549 * flow control enabled, then by us enabling RX only, we
2550 * can at least receive pause frames and process them.
2551 * This is a good idea because in most cases, since we are
2552 * predominantly a server NIC, more times than not we will
2553 * be asked to delay transmission of packets than asking
2554 * our link partner to pause transmission of frames.
2556 else if((hw->original_fc == e1000_fc_none ||
2557 hw->original_fc == e1000_fc_tx_pause) ||
2558 hw->fc_strict_ieee) {
2559 hw->fc = e1000_fc_none;
2560 DEBUGOUT("Flow Control = NONE.\n");
2562 hw->fc = e1000_fc_rx_pause;
2563 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2566 /* Now we need to do one last check... If we auto-
2567 * negotiated to HALF DUPLEX, flow control should not be
2568 * enabled per IEEE 802.3 spec.
2570 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2572 DEBUGOUT("Error getting link speed and duplex\n");
2576 if(duplex == HALF_DUPLEX)
2577 hw->fc = e1000_fc_none;
2579 /* Now we call a subroutine to actually force the MAC
2580 * controller to use the correct flow control settings.
2582 ret_val = e1000_force_mac_fc(hw);
2584 DEBUGOUT("Error forcing flow control settings\n");
2588 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2591 return E1000_SUCCESS;
2594 /******************************************************************************
2595 * Checks to see if the link status of the hardware has changed.
2597 * hw - Struct containing variables accessed by shared code
2599 * Called by any function that needs to check the link status of the adapter.
2600 *****************************************************************************/
2602 e1000_check_for_link(struct e1000_hw *hw)
2609 uint32_t signal = 0;
2613 DEBUGFUNC("e1000_check_for_link");
2615 ctrl = E1000_READ_REG(hw, CTRL);
2616 status = E1000_READ_REG(hw, STATUS);
2618 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2619 * set when the optics detect a signal. On older adapters, it will be
2620 * cleared when there is a signal. This applies to fiber media only.
2622 if((hw->media_type == e1000_media_type_fiber) ||
2623 (hw->media_type == e1000_media_type_internal_serdes)) {
2624 rxcw = E1000_READ_REG(hw, RXCW);
2626 if(hw->media_type == e1000_media_type_fiber) {
2627 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2628 if(status & E1000_STATUS_LU)
2629 hw->get_link_status = FALSE;
2633 /* If we have a copper PHY then we only want to go out to the PHY
2634 * registers to see if Auto-Neg has completed and/or if our link
2635 * status has changed. The get_link_status flag will be set if we
2636 * receive a Link Status Change interrupt or we have Rx Sequence
2639 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2640 /* First we want to see if the MII Status Register reports
2641 * link. If so, then we want to get the current speed/duplex
2643 * Read the register twice since the link bit is sticky.
2645 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2648 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2652 if(phy_data & MII_SR_LINK_STATUS) {
2653 hw->get_link_status = FALSE;
2654 /* Check if there was DownShift, must be checked immediately after
2656 e1000_check_downshift(hw);
2658 /* If we are on 82544 or 82543 silicon and speed/duplex
2659 * are forced to 10H or 10F, then we will implement the polarity
2660 * reversal workaround. We disable interrupts first, and upon
2661 * returning, place the devices interrupt state to its previous
2662 * value except for the link status change interrupt which will
2663 * happen due to the execution of this workaround.
2666 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2668 (hw->forced_speed_duplex == e1000_10_full ||
2669 hw->forced_speed_duplex == e1000_10_half)) {
2670 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2671 ret_val = e1000_polarity_reversal_workaround(hw);
2672 icr = E1000_READ_REG(hw, ICR);
2673 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2674 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2678 /* No link detected */
2679 e1000_config_dsp_after_link_change(hw, FALSE);
2683 /* If we are forcing speed/duplex, then we simply return since
2684 * we have already determined whether we have link or not.
2686 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2688 /* optimize the dsp settings for the igp phy */
2689 e1000_config_dsp_after_link_change(hw, TRUE);
2691 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2692 * have Si on board that is 82544 or newer, Auto
2693 * Speed Detection takes care of MAC speed/duplex
2694 * configuration. So we only need to configure Collision
2695 * Distance in the MAC. Otherwise, we need to force
2696 * speed/duplex on the MAC to the current PHY speed/duplex
2699 if(hw->mac_type >= e1000_82544)
2700 e1000_config_collision_dist(hw);
2702 ret_val = e1000_config_mac_to_phy(hw);
2704 DEBUGOUT("Error configuring MAC to PHY settings\n");
2709 /* Configure Flow Control now that Auto-Neg has completed. First, we
2710 * need to restore the desired flow control settings because we may
2711 * have had to re-autoneg with a different link partner.
2713 ret_val = e1000_config_fc_after_link_up(hw);
2715 DEBUGOUT("Error configuring flow control\n");
2719 /* At this point we know that we are on copper and we have
2720 * auto-negotiated link. These are conditions for checking the link
2721 * partner capability register. We use the link speed to determine if
2722 * TBI compatibility needs to be turned on or off. If the link is not
2723 * at gigabit speed, then TBI compatibility is not needed. If we are
2724 * at gigabit speed, we turn on TBI compatibility.
2726 if(hw->tbi_compatibility_en) {
2727 uint16_t speed, duplex;
2728 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2729 if(speed != SPEED_1000) {
2730 /* If link speed is not set to gigabit speed, we do not need
2731 * to enable TBI compatibility.
2733 if(hw->tbi_compatibility_on) {
2734 /* If we previously were in the mode, turn it off. */
2735 rctl = E1000_READ_REG(hw, RCTL);
2736 rctl &= ~E1000_RCTL_SBP;
2737 E1000_WRITE_REG(hw, RCTL, rctl);
2738 hw->tbi_compatibility_on = FALSE;
2741 /* If TBI compatibility is was previously off, turn it on. For
2742 * compatibility with a TBI link partner, we will store bad
2743 * packets. Some frames have an additional byte on the end and
2744 * will look like CRC errors to to the hardware.
2746 if(!hw->tbi_compatibility_on) {
2747 hw->tbi_compatibility_on = TRUE;
2748 rctl = E1000_READ_REG(hw, RCTL);
2749 rctl |= E1000_RCTL_SBP;
2750 E1000_WRITE_REG(hw, RCTL, rctl);
2755 /* If we don't have link (auto-negotiation failed or link partner cannot
2756 * auto-negotiate), the cable is plugged in (we have signal), and our
2757 * link partner is not trying to auto-negotiate with us (we are receiving
2758 * idles or data), we need to force link up. We also need to give
2759 * auto-negotiation time to complete, in case the cable was just plugged
2760 * in. The autoneg_failed flag does this.
2762 else if((((hw->media_type == e1000_media_type_fiber) &&
2763 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2764 (hw->media_type == e1000_media_type_internal_serdes)) &&
2765 (!(status & E1000_STATUS_LU)) &&
2766 (!(rxcw & E1000_RXCW_C))) {
2767 if(hw->autoneg_failed == 0) {
2768 hw->autoneg_failed = 1;
2771 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2773 /* Disable auto-negotiation in the TXCW register */
2774 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2776 /* Force link-up and also force full-duplex. */
2777 ctrl = E1000_READ_REG(hw, CTRL);
2778 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2779 E1000_WRITE_REG(hw, CTRL, ctrl);
2781 /* Configure Flow Control after forcing link up. */
2782 ret_val = e1000_config_fc_after_link_up(hw);
2784 DEBUGOUT("Error configuring flow control\n");
2788 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2789 * auto-negotiation in the TXCW register and disable forced link in the
2790 * Device Control register in an attempt to auto-negotiate with our link
2793 else if(((hw->media_type == e1000_media_type_fiber) ||
2794 (hw->media_type == e1000_media_type_internal_serdes)) &&
2795 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2796 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2797 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2798 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2800 hw->serdes_link_down = FALSE;
2802 /* If we force link for non-auto-negotiation switch, check link status
2803 * based on MAC synchronization for internal serdes media type.
2805 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2806 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2807 /* SYNCH bit and IV bit are sticky. */
2809 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2810 if(!(rxcw & E1000_RXCW_IV)) {
2811 hw->serdes_link_down = FALSE;
2812 DEBUGOUT("SERDES: Link is up.\n");
2815 hw->serdes_link_down = TRUE;
2816 DEBUGOUT("SERDES: Link is down.\n");
2819 if((hw->media_type == e1000_media_type_internal_serdes) &&
2820 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2821 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2823 return E1000_SUCCESS;
2826 /******************************************************************************
2827 * Detects the current speed and duplex settings of the hardware.
2829 * hw - Struct containing variables accessed by shared code
2830 * speed - Speed of the connection
2831 * duplex - Duplex setting of the connection
2832 *****************************************************************************/
2834 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2842 DEBUGFUNC("e1000_get_speed_and_duplex");
2844 if(hw->mac_type >= e1000_82543) {
2845 status = E1000_READ_REG(hw, STATUS);
2846 if(status & E1000_STATUS_SPEED_1000) {
2847 *speed = SPEED_1000;
2848 DEBUGOUT("1000 Mbs, ");
2849 } else if(status & E1000_STATUS_SPEED_100) {
2851 DEBUGOUT("100 Mbs, ");
2854 DEBUGOUT("10 Mbs, ");
2857 if(status & E1000_STATUS_FD) {
2858 *duplex = FULL_DUPLEX;
2859 DEBUGOUT("Full Duplex\n");
2861 *duplex = HALF_DUPLEX;
2862 DEBUGOUT(" Half Duplex\n");
2865 DEBUGOUT("1000 Mbs, Full Duplex\n");
2866 *speed = SPEED_1000;
2867 *duplex = FULL_DUPLEX;
2870 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2871 * if it is operating at half duplex. Here we set the duplex settings to
2872 * match the duplex in the link partner's capabilities.
2874 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2875 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2879 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2880 *duplex = HALF_DUPLEX;
2882 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2885 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2886 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2887 *duplex = HALF_DUPLEX;
2891 if ((hw->mac_type == e1000_80003es2lan) &&
2892 (hw->media_type == e1000_media_type_copper)) {
2893 if (*speed == SPEED_1000)
2894 ret_val = e1000_configure_kmrn_for_1000(hw);
2896 ret_val = e1000_configure_kmrn_for_10_100(hw);
2901 return E1000_SUCCESS;
2904 /******************************************************************************
2905 * Blocks until autoneg completes or times out (~4.5 seconds)
2907 * hw - Struct containing variables accessed by shared code
2908 ******************************************************************************/
2910 e1000_wait_autoneg(struct e1000_hw *hw)
2916 DEBUGFUNC("e1000_wait_autoneg");
2917 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2919 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2920 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2921 /* Read the MII Status Register and wait for Auto-Neg
2922 * Complete bit to be set.
2924 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2927 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2930 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2931 return E1000_SUCCESS;
2935 return E1000_SUCCESS;
2938 /******************************************************************************
2939 * Raises the Management Data Clock
2941 * hw - Struct containing variables accessed by shared code
2942 * ctrl - Device control register's current value
2943 ******************************************************************************/
2945 e1000_raise_mdi_clk(struct e1000_hw *hw,
2948 /* Raise the clock input to the Management Data Clock (by setting the MDC
2949 * bit), and then delay 10 microseconds.
2951 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2952 E1000_WRITE_FLUSH(hw);
2956 /******************************************************************************
2957 * Lowers the Management Data Clock
2959 * hw - Struct containing variables accessed by shared code
2960 * ctrl - Device control register's current value
2961 ******************************************************************************/
2963 e1000_lower_mdi_clk(struct e1000_hw *hw,
2966 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2967 * bit), and then delay 10 microseconds.
2969 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2970 E1000_WRITE_FLUSH(hw);
2974 /******************************************************************************
2975 * Shifts data bits out to the PHY
2977 * hw - Struct containing variables accessed by shared code
2978 * data - Data to send out to the PHY
2979 * count - Number of bits to shift out
2981 * Bits are shifted out in MSB to LSB order.
2982 ******************************************************************************/
2984 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2991 /* We need to shift "count" number of bits out to the PHY. So, the value
2992 * in the "data" parameter will be shifted out to the PHY one bit at a
2993 * time. In order to do this, "data" must be broken down into bits.
2996 mask <<= (count - 1);
2998 ctrl = E1000_READ_REG(hw, CTRL);
3000 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3001 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3004 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3005 * then raising and lowering the Management Data Clock. A "0" is
3006 * shifted out to the PHY by setting the MDIO bit to "0" and then
3007 * raising and lowering the clock.
3009 if(data & mask) ctrl |= E1000_CTRL_MDIO;
3010 else ctrl &= ~E1000_CTRL_MDIO;
3012 E1000_WRITE_REG(hw, CTRL, ctrl);
3013 E1000_WRITE_FLUSH(hw);
3017 e1000_raise_mdi_clk(hw, &ctrl);
3018 e1000_lower_mdi_clk(hw, &ctrl);
3024 /******************************************************************************
3025 * Shifts data bits in from the PHY
3027 * hw - Struct containing variables accessed by shared code
3029 * Bits are shifted in in MSB to LSB order.
3030 ******************************************************************************/
3032 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3038 /* In order to read a register from the PHY, we need to shift in a total
3039 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3040 * to avoid contention on the MDIO pin when a read operation is performed.
3041 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3042 * by raising the input to the Management Data Clock (setting the MDC bit),
3043 * and then reading the value of the MDIO bit.
3045 ctrl = E1000_READ_REG(hw, CTRL);
3047 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3048 ctrl &= ~E1000_CTRL_MDIO_DIR;
3049 ctrl &= ~E1000_CTRL_MDIO;
3051 E1000_WRITE_REG(hw, CTRL, ctrl);
3052 E1000_WRITE_FLUSH(hw);
3054 /* Raise and Lower the clock before reading in the data. This accounts for
3055 * the turnaround bits. The first clock occurred when we clocked out the
3056 * last bit of the Register Address.
3058 e1000_raise_mdi_clk(hw, &ctrl);
3059 e1000_lower_mdi_clk(hw, &ctrl);
3061 for(data = 0, i = 0; i < 16; i++) {
3063 e1000_raise_mdi_clk(hw, &ctrl);
3064 ctrl = E1000_READ_REG(hw, CTRL);
3065 /* Check to see if we shifted in a "1". */
3066 if(ctrl & E1000_CTRL_MDIO) data |= 1;
3067 e1000_lower_mdi_clk(hw, &ctrl);
3070 e1000_raise_mdi_clk(hw, &ctrl);
3071 e1000_lower_mdi_clk(hw, &ctrl);
3077 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3079 uint32_t swfw_sync = 0;
3080 uint32_t swmask = mask;
3081 uint32_t fwmask = mask << 16;
3082 int32_t timeout = 200;
3084 DEBUGFUNC("e1000_swfw_sync_acquire");
3086 if (!hw->swfw_sync_present)
3087 return e1000_get_hw_eeprom_semaphore(hw);
3090 if (e1000_get_hw_eeprom_semaphore(hw))
3091 return -E1000_ERR_SWFW_SYNC;
3093 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3094 if (!(swfw_sync & (fwmask | swmask))) {
3098 /* firmware currently using resource (fwmask) */
3099 /* or other software thread currently using resource (swmask) */
3100 e1000_put_hw_eeprom_semaphore(hw);
3106 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3107 return -E1000_ERR_SWFW_SYNC;
3110 swfw_sync |= swmask;
3111 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3113 e1000_put_hw_eeprom_semaphore(hw);
3114 return E1000_SUCCESS;
3118 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3121 uint32_t swmask = mask;
3123 DEBUGFUNC("e1000_swfw_sync_release");
3125 if (!hw->swfw_sync_present) {
3126 e1000_put_hw_eeprom_semaphore(hw);
3130 /* if (e1000_get_hw_eeprom_semaphore(hw))
3131 * return -E1000_ERR_SWFW_SYNC; */
3132 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3135 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3136 swfw_sync &= ~swmask;
3137 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3139 e1000_put_hw_eeprom_semaphore(hw);
3142 /*****************************************************************************
3143 * Reads the value from a PHY register, if the value is on a specific non zero
3144 * page, sets the page first.
3145 * hw - Struct containing variables accessed by shared code
3146 * reg_addr - address of the PHY register to read
3147 ******************************************************************************/
3149 e1000_read_phy_reg(struct e1000_hw *hw,
3156 DEBUGFUNC("e1000_read_phy_reg");
3158 if ((hw->mac_type == e1000_80003es2lan) &&
3159 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3160 swfw = E1000_SWFW_PHY1_SM;
3162 swfw = E1000_SWFW_PHY0_SM;
3164 if (e1000_swfw_sync_acquire(hw, swfw))
3165 return -E1000_ERR_SWFW_SYNC;
3167 if((hw->phy_type == e1000_phy_igp ||
3168 hw->phy_type == e1000_phy_igp_2) &&
3169 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3170 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3171 (uint16_t)reg_addr);
3173 e1000_swfw_sync_release(hw, swfw);
3176 } else if (hw->phy_type == e1000_phy_gg82563) {
3177 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3178 (hw->mac_type == e1000_80003es2lan)) {
3179 /* Select Configuration Page */
3180 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3181 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3182 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3184 /* Use Alternative Page Select register to access
3185 * registers 30 and 31
3187 ret_val = e1000_write_phy_reg_ex(hw,
3188 GG82563_PHY_PAGE_SELECT_ALT,
3189 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3193 e1000_swfw_sync_release(hw, swfw);
3199 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3202 e1000_swfw_sync_release(hw, swfw);
3207 e1000_read_phy_reg_ex(struct e1000_hw *hw,
3213 const uint32_t phy_addr = 1;
3215 DEBUGFUNC("e1000_read_phy_reg_ex");
3217 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3218 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3219 return -E1000_ERR_PARAM;
3222 if(hw->mac_type > e1000_82543) {
3223 /* Set up Op-code, Phy Address, and register address in the MDI
3224 * Control register. The MAC will take care of interfacing with the
3225 * PHY to retrieve the desired data.
3227 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3228 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3229 (E1000_MDIC_OP_READ));
3231 E1000_WRITE_REG(hw, MDIC, mdic);
3233 /* Poll the ready bit to see if the MDI read completed */
3234 for(i = 0; i < 64; i++) {
3236 mdic = E1000_READ_REG(hw, MDIC);
3237 if(mdic & E1000_MDIC_READY) break;
3239 if(!(mdic & E1000_MDIC_READY)) {
3240 DEBUGOUT("MDI Read did not complete\n");
3241 return -E1000_ERR_PHY;
3243 if(mdic & E1000_MDIC_ERROR) {
3244 DEBUGOUT("MDI Error\n");
3245 return -E1000_ERR_PHY;
3247 *phy_data = (uint16_t) mdic;
3249 /* We must first send a preamble through the MDIO pin to signal the
3250 * beginning of an MII instruction. This is done by sending 32
3251 * consecutive "1" bits.
3253 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3255 /* Now combine the next few fields that are required for a read
3256 * operation. We use this method instead of calling the
3257 * e1000_shift_out_mdi_bits routine five different times. The format of
3258 * a MII read instruction consists of a shift out of 14 bits and is
3259 * defined as follows:
3260 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3261 * followed by a shift in of 18 bits. This first two bits shifted in
3262 * are TurnAround bits used to avoid contention on the MDIO pin when a
3263 * READ operation is performed. These two bits are thrown away
3264 * followed by a shift in of 16 bits which contains the desired data.
3266 mdic = ((reg_addr) | (phy_addr << 5) |
3267 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3269 e1000_shift_out_mdi_bits(hw, mdic, 14);
3271 /* Now that we've shifted out the read command to the MII, we need to
3272 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3275 *phy_data = e1000_shift_in_mdi_bits(hw);
3277 return E1000_SUCCESS;
3280 /******************************************************************************
3281 * Writes a value to a PHY register
3283 * hw - Struct containing variables accessed by shared code
3284 * reg_addr - address of the PHY register to write
3285 * data - data to write to the PHY
3286 ******************************************************************************/
3288 e1000_write_phy_reg(struct e1000_hw *hw,
3295 DEBUGFUNC("e1000_write_phy_reg");
3297 if ((hw->mac_type == e1000_80003es2lan) &&
3298 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3299 swfw = E1000_SWFW_PHY1_SM;
3301 swfw = E1000_SWFW_PHY0_SM;
3303 if (e1000_swfw_sync_acquire(hw, swfw))
3304 return -E1000_ERR_SWFW_SYNC;
3306 if((hw->phy_type == e1000_phy_igp ||
3307 hw->phy_type == e1000_phy_igp_2) &&
3308 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3309 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3310 (uint16_t)reg_addr);
3312 e1000_swfw_sync_release(hw, swfw);
3315 } else if (hw->phy_type == e1000_phy_gg82563) {
3316 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3317 (hw->mac_type == e1000_80003es2lan)) {
3318 /* Select Configuration Page */
3319 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3320 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3321 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3323 /* Use Alternative Page Select register to access
3324 * registers 30 and 31
3326 ret_val = e1000_write_phy_reg_ex(hw,
3327 GG82563_PHY_PAGE_SELECT_ALT,
3328 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3332 e1000_swfw_sync_release(hw, swfw);
3338 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3341 e1000_swfw_sync_release(hw, swfw);
3346 e1000_write_phy_reg_ex(struct e1000_hw *hw,
3352 const uint32_t phy_addr = 1;
3354 DEBUGFUNC("e1000_write_phy_reg_ex");
3356 if(reg_addr > MAX_PHY_REG_ADDRESS) {
3357 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3358 return -E1000_ERR_PARAM;
3361 if(hw->mac_type > e1000_82543) {
3362 /* Set up Op-code, Phy Address, register address, and data intended
3363 * for the PHY register in the MDI Control register. The MAC will take
3364 * care of interfacing with the PHY to send the desired data.
3366 mdic = (((uint32_t) phy_data) |
3367 (reg_addr << E1000_MDIC_REG_SHIFT) |
3368 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3369 (E1000_MDIC_OP_WRITE));
3371 E1000_WRITE_REG(hw, MDIC, mdic);
3373 /* Poll the ready bit to see if the MDI read completed */
3374 for(i = 0; i < 640; i++) {
3376 mdic = E1000_READ_REG(hw, MDIC);
3377 if(mdic & E1000_MDIC_READY) break;
3379 if(!(mdic & E1000_MDIC_READY)) {
3380 DEBUGOUT("MDI Write did not complete\n");
3381 return -E1000_ERR_PHY;
3384 /* We'll need to use the SW defined pins to shift the write command
3385 * out to the PHY. We first send a preamble to the PHY to signal the
3386 * beginning of the MII instruction. This is done by sending 32
3387 * consecutive "1" bits.
3389 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3391 /* Now combine the remaining required fields that will indicate a
3392 * write operation. We use this method instead of calling the
3393 * e1000_shift_out_mdi_bits routine for each field in the command. The
3394 * format of a MII write instruction is as follows:
3395 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3397 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3398 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3400 mdic |= (uint32_t) phy_data;
3402 e1000_shift_out_mdi_bits(hw, mdic, 32);
3405 return E1000_SUCCESS;
3409 e1000_read_kmrn_reg(struct e1000_hw *hw,
3415 DEBUGFUNC("e1000_read_kmrn_reg");
3417 if ((hw->mac_type == e1000_80003es2lan) &&
3418 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3419 swfw = E1000_SWFW_PHY1_SM;
3421 swfw = E1000_SWFW_PHY0_SM;
3423 if (e1000_swfw_sync_acquire(hw, swfw))
3424 return -E1000_ERR_SWFW_SYNC;
3426 /* Write register address */
3427 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3428 E1000_KUMCTRLSTA_OFFSET) |
3429 E1000_KUMCTRLSTA_REN;
3430 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3433 /* Read the data returned */
3434 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3435 *data = (uint16_t)reg_val;
3437 e1000_swfw_sync_release(hw, swfw);
3438 return E1000_SUCCESS;
3442 e1000_write_kmrn_reg(struct e1000_hw *hw,
3448 DEBUGFUNC("e1000_write_kmrn_reg");
3450 if ((hw->mac_type == e1000_80003es2lan) &&
3451 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3452 swfw = E1000_SWFW_PHY1_SM;
3454 swfw = E1000_SWFW_PHY0_SM;
3456 if (e1000_swfw_sync_acquire(hw, swfw))
3457 return -E1000_ERR_SWFW_SYNC;
3459 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3460 E1000_KUMCTRLSTA_OFFSET) | data;
3461 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3464 e1000_swfw_sync_release(hw, swfw);
3465 return E1000_SUCCESS;
3468 /******************************************************************************
3469 * Returns the PHY to the power-on reset state
3471 * hw - Struct containing variables accessed by shared code
3472 ******************************************************************************/
3474 e1000_phy_hw_reset(struct e1000_hw *hw)
3476 uint32_t ctrl, ctrl_ext;
3481 DEBUGFUNC("e1000_phy_hw_reset");
3483 /* In the case of the phy reset being blocked, it's not an error, we
3484 * simply return success without performing the reset. */
3485 ret_val = e1000_check_phy_reset_block(hw);
3487 return E1000_SUCCESS;
3489 DEBUGOUT("Resetting Phy...\n");
3491 if(hw->mac_type > e1000_82543) {
3492 if ((hw->mac_type == e1000_80003es2lan) &&
3493 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3494 swfw = E1000_SWFW_PHY1_SM;
3496 swfw = E1000_SWFW_PHY0_SM;
3498 if (e1000_swfw_sync_acquire(hw, swfw)) {
3499 e1000_release_software_semaphore(hw);
3500 return -E1000_ERR_SWFW_SYNC;
3502 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3503 * bit. Then, take it out of reset.
3504 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3505 * and deassert. For e1000_82571 hardware and later, we instead delay
3506 * for 50us between and 10ms after the deassertion.
3508 ctrl = E1000_READ_REG(hw, CTRL);
3509 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3510 E1000_WRITE_FLUSH(hw);
3512 if (hw->mac_type < e1000_82571)
3517 E1000_WRITE_REG(hw, CTRL, ctrl);
3518 E1000_WRITE_FLUSH(hw);
3520 if (hw->mac_type >= e1000_82571)
3522 e1000_swfw_sync_release(hw, swfw);
3524 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3525 * bit to put the PHY into reset. Then, take it out of reset.
3527 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3528 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3529 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3530 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3531 E1000_WRITE_FLUSH(hw);
3533 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3534 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3535 E1000_WRITE_FLUSH(hw);
3539 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3540 /* Configure activity LED after PHY reset */
3541 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3542 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3543 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3544 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3547 /* Wait for FW to finish PHY configuration. */
3548 ret_val = e1000_get_phy_cfg_done(hw);
3549 e1000_release_software_semaphore(hw);
3554 /******************************************************************************
3557 * hw - Struct containing variables accessed by shared code
3559 * Sets bit 15 of the MII Control regiser
3560 ******************************************************************************/
3562 e1000_phy_reset(struct e1000_hw *hw)
3567 DEBUGFUNC("e1000_phy_reset");
3569 /* In the case of the phy reset being blocked, it's not an error, we
3570 * simply return success without performing the reset. */
3571 ret_val = e1000_check_phy_reset_block(hw);
3573 return E1000_SUCCESS;
3575 switch (hw->mac_type) {
3576 case e1000_82541_rev_2:
3579 ret_val = e1000_phy_hw_reset(hw);
3584 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3588 phy_data |= MII_CR_RESET;
3589 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3597 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3598 e1000_phy_init_script(hw);
3600 return E1000_SUCCESS;
3603 /******************************************************************************
3604 * Probes the expected PHY address for known PHY IDs
3606 * hw - Struct containing variables accessed by shared code
3607 ******************************************************************************/
3609 e1000_detect_gig_phy(struct e1000_hw *hw)
3611 int32_t phy_init_status, ret_val;
3612 uint16_t phy_id_high, phy_id_low;
3613 boolean_t match = FALSE;
3615 DEBUGFUNC("e1000_detect_gig_phy");
3617 /* The 82571 firmware may still be configuring the PHY. In this
3618 * case, we cannot access the PHY until the configuration is done. So
3619 * we explicitly set the PHY values. */
3620 if(hw->mac_type == e1000_82571 ||
3621 hw->mac_type == e1000_82572) {
3622 hw->phy_id = IGP01E1000_I_PHY_ID;
3623 hw->phy_type = e1000_phy_igp_2;
3624 return E1000_SUCCESS;
3627 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3628 * around that forces PHY page 0 to be set or the reads fail. The rest of
3629 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3630 * So for ESB-2 we need to have this set so our reads won't fail. If the
3631 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3632 * this out as well. */
3633 if (hw->mac_type == e1000_80003es2lan)
3634 hw->phy_type = e1000_phy_gg82563;
3636 /* Read the PHY ID Registers to identify which PHY is onboard. */
3637 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3641 hw->phy_id = (uint32_t) (phy_id_high << 16);
3643 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3647 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3648 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3650 switch(hw->mac_type) {
3652 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3655 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3659 case e1000_82545_rev_3:
3661 case e1000_82546_rev_3:
3662 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3665 case e1000_82541_rev_2:
3667 case e1000_82547_rev_2:
3668 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3671 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3673 case e1000_80003es2lan:
3674 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3677 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3678 return -E1000_ERR_CONFIG;
3680 phy_init_status = e1000_set_phy_type(hw);
3682 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3683 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3684 return E1000_SUCCESS;
3686 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3687 return -E1000_ERR_PHY;
3690 /******************************************************************************
3691 * Resets the PHY's DSP
3693 * hw - Struct containing variables accessed by shared code
3694 ******************************************************************************/
3696 e1000_phy_reset_dsp(struct e1000_hw *hw)
3699 DEBUGFUNC("e1000_phy_reset_dsp");
3702 if (hw->phy_type != e1000_phy_gg82563) {
3703 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3706 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3708 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3710 ret_val = E1000_SUCCESS;
3716 /******************************************************************************
3717 * Get PHY information from various PHY registers for igp PHY only.
3719 * hw - Struct containing variables accessed by shared code
3720 * phy_info - PHY information structure
3721 ******************************************************************************/
3723 e1000_phy_igp_get_info(struct e1000_hw *hw,
3724 struct e1000_phy_info *phy_info)
3727 uint16_t phy_data, polarity, min_length, max_length, average;
3729 DEBUGFUNC("e1000_phy_igp_get_info");
3731 /* The downshift status is checked only once, after link is established,
3732 * and it stored in the hw->speed_downgraded parameter. */
3733 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3735 /* IGP01E1000 does not need to support it. */
3736 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3738 /* IGP01E1000 always correct polarity reversal */
3739 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3741 /* Check polarity status */
3742 ret_val = e1000_check_polarity(hw, &polarity);
3746 phy_info->cable_polarity = polarity;
3748 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3752 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
3753 IGP01E1000_PSSR_MDIX_SHIFT;
3755 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3756 IGP01E1000_PSSR_SPEED_1000MBPS) {
3757 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3758 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3762 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3763 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3764 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3765 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3767 /* Get cable length */
3768 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3772 /* Translate to old method */
3773 average = (max_length + min_length) / 2;
3775 if(average <= e1000_igp_cable_length_50)
3776 phy_info->cable_length = e1000_cable_length_50;
3777 else if(average <= e1000_igp_cable_length_80)
3778 phy_info->cable_length = e1000_cable_length_50_80;
3779 else if(average <= e1000_igp_cable_length_110)
3780 phy_info->cable_length = e1000_cable_length_80_110;
3781 else if(average <= e1000_igp_cable_length_140)
3782 phy_info->cable_length = e1000_cable_length_110_140;
3784 phy_info->cable_length = e1000_cable_length_140;
3787 return E1000_SUCCESS;
3790 /******************************************************************************
3791 * Get PHY information from various PHY registers fot m88 PHY only.
3793 * hw - Struct containing variables accessed by shared code
3794 * phy_info - PHY information structure
3795 ******************************************************************************/
3797 e1000_phy_m88_get_info(struct e1000_hw *hw,
3798 struct e1000_phy_info *phy_info)
3801 uint16_t phy_data, polarity;
3803 DEBUGFUNC("e1000_phy_m88_get_info");
3805 /* The downshift status is checked only once, after link is established,
3806 * and it stored in the hw->speed_downgraded parameter. */
3807 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3809 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3813 phy_info->extended_10bt_distance =
3814 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3815 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
3816 phy_info->polarity_correction =
3817 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3818 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
3820 /* Check polarity status */
3821 ret_val = e1000_check_polarity(hw, &polarity);
3824 phy_info->cable_polarity = polarity;
3826 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3830 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
3831 M88E1000_PSSR_MDIX_SHIFT;
3833 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3834 /* Cable Length Estimation and Local/Remote Receiver Information
3835 * are only valid at 1000 Mbps.
3837 if (hw->phy_type != e1000_phy_gg82563) {
3838 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
3839 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3841 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
3846 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
3849 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3853 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3854 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3856 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3857 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3860 return E1000_SUCCESS;
3863 /******************************************************************************
3864 * Get PHY information from various PHY registers
3866 * hw - Struct containing variables accessed by shared code
3867 * phy_info - PHY information structure
3868 ******************************************************************************/
3870 e1000_phy_get_info(struct e1000_hw *hw,
3871 struct e1000_phy_info *phy_info)
3876 DEBUGFUNC("e1000_phy_get_info");
3878 phy_info->cable_length = e1000_cable_length_undefined;
3879 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3880 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3881 phy_info->downshift = e1000_downshift_undefined;
3882 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3883 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3884 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3885 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3887 if(hw->media_type != e1000_media_type_copper) {
3888 DEBUGOUT("PHY info is only valid for copper media\n");
3889 return -E1000_ERR_CONFIG;
3892 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3896 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3900 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3901 DEBUGOUT("PHY info is only valid if link is up\n");
3902 return -E1000_ERR_CONFIG;
3905 if(hw->phy_type == e1000_phy_igp ||
3906 hw->phy_type == e1000_phy_igp_2)
3907 return e1000_phy_igp_get_info(hw, phy_info);
3909 return e1000_phy_m88_get_info(hw, phy_info);
3913 e1000_validate_mdi_setting(struct e1000_hw *hw)
3915 DEBUGFUNC("e1000_validate_mdi_settings");
3917 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3918 DEBUGOUT("Invalid MDI setting detected\n");
3920 return -E1000_ERR_CONFIG;
3922 return E1000_SUCCESS;
3926 /******************************************************************************
3927 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3928 * is configured. Additionally, if this is ICH8, the flash controller GbE
3929 * registers must be mapped, or this will crash.
3931 * hw - Struct containing variables accessed by shared code
3932 *****************************************************************************/
3934 e1000_init_eeprom_params(struct e1000_hw *hw)
3936 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3937 uint32_t eecd = E1000_READ_REG(hw, EECD);
3938 int32_t ret_val = E1000_SUCCESS;
3939 uint16_t eeprom_size;
3941 DEBUGFUNC("e1000_init_eeprom_params");
3943 switch (hw->mac_type) {
3944 case e1000_82542_rev2_0:
3945 case e1000_82542_rev2_1:
3948 eeprom->type = e1000_eeprom_microwire;
3949 eeprom->word_size = 64;
3950 eeprom->opcode_bits = 3;
3951 eeprom->address_bits = 6;
3952 eeprom->delay_usec = 50;
3953 eeprom->use_eerd = FALSE;
3954 eeprom->use_eewr = FALSE;
3958 case e1000_82545_rev_3:
3960 case e1000_82546_rev_3:
3961 eeprom->type = e1000_eeprom_microwire;
3962 eeprom->opcode_bits = 3;
3963 eeprom->delay_usec = 50;
3964 if(eecd & E1000_EECD_SIZE) {
3965 eeprom->word_size = 256;
3966 eeprom->address_bits = 8;
3968 eeprom->word_size = 64;
3969 eeprom->address_bits = 6;
3971 eeprom->use_eerd = FALSE;
3972 eeprom->use_eewr = FALSE;
3975 case e1000_82541_rev_2:
3977 case e1000_82547_rev_2:
3978 if (eecd & E1000_EECD_TYPE) {
3979 eeprom->type = e1000_eeprom_spi;
3980 eeprom->opcode_bits = 8;
3981 eeprom->delay_usec = 1;
3982 if (eecd & E1000_EECD_ADDR_BITS) {
3983 eeprom->page_size = 32;
3984 eeprom->address_bits = 16;
3986 eeprom->page_size = 8;
3987 eeprom->address_bits = 8;
3990 eeprom->type = e1000_eeprom_microwire;
3991 eeprom->opcode_bits = 3;
3992 eeprom->delay_usec = 50;
3993 if (eecd & E1000_EECD_ADDR_BITS) {
3994 eeprom->word_size = 256;
3995 eeprom->address_bits = 8;
3997 eeprom->word_size = 64;
3998 eeprom->address_bits = 6;
4001 eeprom->use_eerd = FALSE;
4002 eeprom->use_eewr = FALSE;
4006 eeprom->type = e1000_eeprom_spi;
4007 eeprom->opcode_bits = 8;
4008 eeprom->delay_usec = 1;
4009 if (eecd & E1000_EECD_ADDR_BITS) {
4010 eeprom->page_size = 32;
4011 eeprom->address_bits = 16;
4013 eeprom->page_size = 8;
4014 eeprom->address_bits = 8;
4016 eeprom->use_eerd = FALSE;
4017 eeprom->use_eewr = FALSE;
4020 eeprom->type = e1000_eeprom_spi;
4021 eeprom->opcode_bits = 8;
4022 eeprom->delay_usec = 1;
4023 if (eecd & E1000_EECD_ADDR_BITS) {
4024 eeprom->page_size = 32;
4025 eeprom->address_bits = 16;
4027 eeprom->page_size = 8;
4028 eeprom->address_bits = 8;
4030 eeprom->use_eerd = TRUE;
4031 eeprom->use_eewr = TRUE;
4032 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4033 eeprom->type = e1000_eeprom_flash;
4034 eeprom->word_size = 2048;
4036 /* Ensure that the Autonomous FLASH update bit is cleared due to
4037 * Flash update issue on parts which use a FLASH for NVM. */
4038 eecd &= ~E1000_EECD_AUPDEN;
4039 E1000_WRITE_REG(hw, EECD, eecd);
4042 case e1000_80003es2lan:
4043 eeprom->type = e1000_eeprom_spi;
4044 eeprom->opcode_bits = 8;
4045 eeprom->delay_usec = 1;
4046 if (eecd & E1000_EECD_ADDR_BITS) {
4047 eeprom->page_size = 32;
4048 eeprom->address_bits = 16;
4050 eeprom->page_size = 8;
4051 eeprom->address_bits = 8;
4053 eeprom->use_eerd = TRUE;
4054 eeprom->use_eewr = FALSE;
4060 if (eeprom->type == e1000_eeprom_spi) {
4061 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4062 * 32KB (incremented by powers of 2).
4064 if(hw->mac_type <= e1000_82547_rev_2) {
4065 /* Set to default value for initial eeprom read. */
4066 eeprom->word_size = 64;
4067 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4070 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4071 /* 256B eeprom size was not supported in earlier hardware, so we
4072 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4073 * is never the result used in the shifting logic below. */
4077 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4078 E1000_EECD_SIZE_EX_SHIFT);
4081 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4086 /******************************************************************************
4087 * Raises the EEPROM's clock input.
4089 * hw - Struct containing variables accessed by shared code
4090 * eecd - EECD's current value
4091 *****************************************************************************/
4093 e1000_raise_ee_clk(struct e1000_hw *hw,
4096 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4097 * wait <delay> microseconds.
4099 *eecd = *eecd | E1000_EECD_SK;
4100 E1000_WRITE_REG(hw, EECD, *eecd);
4101 E1000_WRITE_FLUSH(hw);
4102 udelay(hw->eeprom.delay_usec);
4105 /******************************************************************************
4106 * Lowers the EEPROM's clock input.
4108 * hw - Struct containing variables accessed by shared code
4109 * eecd - EECD's current value
4110 *****************************************************************************/
4112 e1000_lower_ee_clk(struct e1000_hw *hw,
4115 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4116 * wait 50 microseconds.
4118 *eecd = *eecd & ~E1000_EECD_SK;
4119 E1000_WRITE_REG(hw, EECD, *eecd);
4120 E1000_WRITE_FLUSH(hw);
4121 udelay(hw->eeprom.delay_usec);
4124 /******************************************************************************
4125 * Shift data bits out to the EEPROM.
4127 * hw - Struct containing variables accessed by shared code
4128 * data - data to send to the EEPROM
4129 * count - number of bits to shift out
4130 *****************************************************************************/
4132 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4136 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4140 /* We need to shift "count" bits out to the EEPROM. So, value in the
4141 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4142 * In order to do this, "data" must be broken down into bits.
4144 mask = 0x01 << (count - 1);
4145 eecd = E1000_READ_REG(hw, EECD);
4146 if (eeprom->type == e1000_eeprom_microwire) {
4147 eecd &= ~E1000_EECD_DO;
4148 } else if (eeprom->type == e1000_eeprom_spi) {
4149 eecd |= E1000_EECD_DO;
4152 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4153 * and then raising and then lowering the clock (the SK bit controls
4154 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4155 * by setting "DI" to "0" and then raising and then lowering the clock.
4157 eecd &= ~E1000_EECD_DI;
4160 eecd |= E1000_EECD_DI;
4162 E1000_WRITE_REG(hw, EECD, eecd);
4163 E1000_WRITE_FLUSH(hw);
4165 udelay(eeprom->delay_usec);
4167 e1000_raise_ee_clk(hw, &eecd);
4168 e1000_lower_ee_clk(hw, &eecd);
4174 /* We leave the "DI" bit set to "0" when we leave this routine. */
4175 eecd &= ~E1000_EECD_DI;
4176 E1000_WRITE_REG(hw, EECD, eecd);
4179 /******************************************************************************
4180 * Shift data bits in from the EEPROM
4182 * hw - Struct containing variables accessed by shared code
4183 *****************************************************************************/
4185 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4192 /* In order to read a register from the EEPROM, we need to shift 'count'
4193 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4194 * input to the EEPROM (setting the SK bit), and then reading the value of
4195 * the "DO" bit. During this "shifting in" process the "DI" bit should
4199 eecd = E1000_READ_REG(hw, EECD);
4201 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4204 for(i = 0; i < count; i++) {
4206 e1000_raise_ee_clk(hw, &eecd);
4208 eecd = E1000_READ_REG(hw, EECD);
4210 eecd &= ~(E1000_EECD_DI);
4211 if(eecd & E1000_EECD_DO)
4214 e1000_lower_ee_clk(hw, &eecd);
4220 /******************************************************************************
4221 * Prepares EEPROM for access
4223 * hw - Struct containing variables accessed by shared code
4225 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4226 * function should be called before issuing a command to the EEPROM.
4227 *****************************************************************************/
4229 e1000_acquire_eeprom(struct e1000_hw *hw)
4231 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4234 DEBUGFUNC("e1000_acquire_eeprom");
4236 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4237 return -E1000_ERR_SWFW_SYNC;
4238 eecd = E1000_READ_REG(hw, EECD);
4240 if (hw->mac_type != e1000_82573) {
4241 /* Request EEPROM Access */
4242 if(hw->mac_type > e1000_82544) {
4243 eecd |= E1000_EECD_REQ;
4244 E1000_WRITE_REG(hw, EECD, eecd);
4245 eecd = E1000_READ_REG(hw, EECD);
4246 while((!(eecd & E1000_EECD_GNT)) &&
4247 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4250 eecd = E1000_READ_REG(hw, EECD);
4252 if(!(eecd & E1000_EECD_GNT)) {
4253 eecd &= ~E1000_EECD_REQ;
4254 E1000_WRITE_REG(hw, EECD, eecd);
4255 DEBUGOUT("Could not acquire EEPROM grant\n");
4256 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4257 return -E1000_ERR_EEPROM;
4262 /* Setup EEPROM for Read/Write */
4264 if (eeprom->type == e1000_eeprom_microwire) {
4265 /* Clear SK and DI */
4266 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4267 E1000_WRITE_REG(hw, EECD, eecd);
4270 eecd |= E1000_EECD_CS;
4271 E1000_WRITE_REG(hw, EECD, eecd);
4272 } else if (eeprom->type == e1000_eeprom_spi) {
4273 /* Clear SK and CS */
4274 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4275 E1000_WRITE_REG(hw, EECD, eecd);
4279 return E1000_SUCCESS;
4282 /******************************************************************************
4283 * Returns EEPROM to a "standby" state
4285 * hw - Struct containing variables accessed by shared code
4286 *****************************************************************************/
4288 e1000_standby_eeprom(struct e1000_hw *hw)
4290 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4293 eecd = E1000_READ_REG(hw, EECD);
4295 if(eeprom->type == e1000_eeprom_microwire) {
4296 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4297 E1000_WRITE_REG(hw, EECD, eecd);
4298 E1000_WRITE_FLUSH(hw);
4299 udelay(eeprom->delay_usec);
4302 eecd |= E1000_EECD_SK;
4303 E1000_WRITE_REG(hw, EECD, eecd);
4304 E1000_WRITE_FLUSH(hw);
4305 udelay(eeprom->delay_usec);
4308 eecd |= E1000_EECD_CS;
4309 E1000_WRITE_REG(hw, EECD, eecd);
4310 E1000_WRITE_FLUSH(hw);
4311 udelay(eeprom->delay_usec);
4314 eecd &= ~E1000_EECD_SK;
4315 E1000_WRITE_REG(hw, EECD, eecd);
4316 E1000_WRITE_FLUSH(hw);
4317 udelay(eeprom->delay_usec);
4318 } else if(eeprom->type == e1000_eeprom_spi) {
4319 /* Toggle CS to flush commands */
4320 eecd |= E1000_EECD_CS;
4321 E1000_WRITE_REG(hw, EECD, eecd);
4322 E1000_WRITE_FLUSH(hw);
4323 udelay(eeprom->delay_usec);
4324 eecd &= ~E1000_EECD_CS;
4325 E1000_WRITE_REG(hw, EECD, eecd);
4326 E1000_WRITE_FLUSH(hw);
4327 udelay(eeprom->delay_usec);
4331 /******************************************************************************
4332 * Terminates a command by inverting the EEPROM's chip select pin
4334 * hw - Struct containing variables accessed by shared code
4335 *****************************************************************************/
4337 e1000_release_eeprom(struct e1000_hw *hw)
4341 DEBUGFUNC("e1000_release_eeprom");
4343 eecd = E1000_READ_REG(hw, EECD);
4345 if (hw->eeprom.type == e1000_eeprom_spi) {
4346 eecd |= E1000_EECD_CS; /* Pull CS high */
4347 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4349 E1000_WRITE_REG(hw, EECD, eecd);
4351 udelay(hw->eeprom.delay_usec);
4352 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
4353 /* cleanup eeprom */
4355 /* CS on Microwire is active-high */
4356 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4358 E1000_WRITE_REG(hw, EECD, eecd);
4360 /* Rising edge of clock */
4361 eecd |= E1000_EECD_SK;
4362 E1000_WRITE_REG(hw, EECD, eecd);
4363 E1000_WRITE_FLUSH(hw);
4364 udelay(hw->eeprom.delay_usec);
4366 /* Falling edge of clock */
4367 eecd &= ~E1000_EECD_SK;
4368 E1000_WRITE_REG(hw, EECD, eecd);
4369 E1000_WRITE_FLUSH(hw);
4370 udelay(hw->eeprom.delay_usec);
4373 /* Stop requesting EEPROM access */
4374 if(hw->mac_type > e1000_82544) {
4375 eecd &= ~E1000_EECD_REQ;
4376 E1000_WRITE_REG(hw, EECD, eecd);
4379 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4382 /******************************************************************************
4383 * Reads a 16 bit word from the EEPROM.
4385 * hw - Struct containing variables accessed by shared code
4386 *****************************************************************************/
4388 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4390 uint16_t retry_count = 0;
4391 uint8_t spi_stat_reg;
4393 DEBUGFUNC("e1000_spi_eeprom_ready");
4395 /* Read "Status Register" repeatedly until the LSB is cleared. The
4396 * EEPROM will signal that the command has been completed by clearing
4397 * bit 0 of the internal status register. If it's not cleared within
4398 * 5 milliseconds, then error out.
4402 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4403 hw->eeprom.opcode_bits);
4404 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4405 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4411 e1000_standby_eeprom(hw);
4412 } while(retry_count < EEPROM_MAX_RETRY_SPI);
4414 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4415 * only 0-5mSec on 5V devices)
4417 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
4418 DEBUGOUT("SPI EEPROM Status error\n");
4419 return -E1000_ERR_EEPROM;
4422 return E1000_SUCCESS;
4425 /******************************************************************************
4426 * Reads a 16 bit word from the EEPROM.
4428 * hw - Struct containing variables accessed by shared code
4429 * offset - offset of word in the EEPROM to read
4430 * data - word read from the EEPROM
4431 * words - number of words to read
4432 *****************************************************************************/
4434 e1000_read_eeprom(struct e1000_hw *hw,
4439 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4443 DEBUGFUNC("e1000_read_eeprom");
4445 /* A check for invalid values: offset too large, too many words, and not
4448 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4450 DEBUGOUT("\"words\" parameter out of bounds\n");
4451 return -E1000_ERR_EEPROM;
4454 /* FLASH reads without acquiring the semaphore are safe */
4455 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4456 hw->eeprom.use_eerd == FALSE) {
4457 switch (hw->mac_type) {
4458 case e1000_80003es2lan:
4461 /* Prepare the EEPROM for reading */
4462 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4463 return -E1000_ERR_EEPROM;
4468 if (eeprom->use_eerd == TRUE) {
4469 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4470 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4471 (hw->mac_type != e1000_82573))
4472 e1000_release_eeprom(hw);
4476 if(eeprom->type == e1000_eeprom_spi) {
4478 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4480 if(e1000_spi_eeprom_ready(hw)) {
4481 e1000_release_eeprom(hw);
4482 return -E1000_ERR_EEPROM;
4485 e1000_standby_eeprom(hw);
4487 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4488 if((eeprom->address_bits == 8) && (offset >= 128))
4489 read_opcode |= EEPROM_A8_OPCODE_SPI;
4491 /* Send the READ command (opcode + addr) */
4492 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4493 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4495 /* Read the data. The address of the eeprom internally increments with
4496 * each byte (spi) being read, saving on the overhead of eeprom setup
4497 * and tear-down. The address counter will roll over if reading beyond
4498 * the size of the eeprom, thus allowing the entire memory to be read
4499 * starting from any offset. */
4500 for (i = 0; i < words; i++) {
4501 word_in = e1000_shift_in_ee_bits(hw, 16);
4502 data[i] = (word_in >> 8) | (word_in << 8);
4504 } else if(eeprom->type == e1000_eeprom_microwire) {
4505 for (i = 0; i < words; i++) {
4506 /* Send the READ command (opcode + addr) */
4507 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4508 eeprom->opcode_bits);
4509 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4510 eeprom->address_bits);
4512 /* Read the data. For microwire, each word requires the overhead
4513 * of eeprom setup and tear-down. */
4514 data[i] = e1000_shift_in_ee_bits(hw, 16);
4515 e1000_standby_eeprom(hw);
4519 /* End this read operation */
4520 e1000_release_eeprom(hw);
4522 return E1000_SUCCESS;
4525 /******************************************************************************
4526 * Reads a 16 bit word from the EEPROM using the EERD register.
4528 * hw - Struct containing variables accessed by shared code
4529 * offset - offset of word in the EEPROM to read
4530 * data - word read from the EEPROM
4531 * words - number of words to read
4532 *****************************************************************************/
4534 e1000_read_eeprom_eerd(struct e1000_hw *hw,
4539 uint32_t i, eerd = 0;
4542 for (i = 0; i < words; i++) {
4543 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4544 E1000_EEPROM_RW_REG_START;
4546 E1000_WRITE_REG(hw, EERD, eerd);
4547 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4552 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4559 /******************************************************************************
4560 * Writes a 16 bit word from the EEPROM using the EEWR register.
4562 * hw - Struct containing variables accessed by shared code
4563 * offset - offset of word in the EEPROM to read
4564 * data - word read from the EEPROM
4565 * words - number of words to read
4566 *****************************************************************************/
4568 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4573 uint32_t register_value = 0;
4577 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4578 return -E1000_ERR_SWFW_SYNC;
4580 for (i = 0; i < words; i++) {
4581 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
4582 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
4583 E1000_EEPROM_RW_REG_START;
4585 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4590 E1000_WRITE_REG(hw, EEWR, register_value);
4592 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4599 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4603 /******************************************************************************
4604 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4606 * hw - Struct containing variables accessed by shared code
4607 *****************************************************************************/
4609 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4611 uint32_t attempts = 100000;
4612 uint32_t i, reg = 0;
4613 int32_t done = E1000_ERR_EEPROM;
4615 for(i = 0; i < attempts; i++) {
4616 if(eerd == E1000_EEPROM_POLL_READ)
4617 reg = E1000_READ_REG(hw, EERD);
4619 reg = E1000_READ_REG(hw, EEWR);
4621 if(reg & E1000_EEPROM_RW_REG_DONE) {
4622 done = E1000_SUCCESS;
4631 /***************************************************************************
4632 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4634 * hw - Struct containing variables accessed by shared code
4635 ****************************************************************************/
4637 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4641 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4643 if(hw->mac_type == e1000_82573) {
4644 eecd = E1000_READ_REG(hw, EECD);
4646 /* Isolate bits 15 & 16 */
4647 eecd = ((eecd >> 15) & 0x03);
4649 /* If both bits are set, device is Flash type */
4657 /******************************************************************************
4658 * Verifies that the EEPROM has a valid checksum
4660 * hw - Struct containing variables accessed by shared code
4662 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4663 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4665 *****************************************************************************/
4667 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4669 uint16_t checksum = 0;
4670 uint16_t i, eeprom_data;
4672 DEBUGFUNC("e1000_validate_eeprom_checksum");
4674 if ((hw->mac_type == e1000_82573) &&
4675 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
4676 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4677 * 10h-12h. Checksum may need to be fixed. */
4678 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
4679 if ((eeprom_data & 0x10) == 0) {
4680 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4681 * has already been fixed. If the checksum is still wrong and this
4682 * bit is a 1, we need to return bad checksum. Otherwise, we need
4683 * to set this bit to a 1 and update the checksum. */
4684 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
4685 if ((eeprom_data & 0x8000) == 0) {
4686 eeprom_data |= 0x8000;
4687 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
4688 e1000_update_eeprom_checksum(hw);
4693 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4694 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4695 DEBUGOUT("EEPROM Read Error\n");
4696 return -E1000_ERR_EEPROM;
4698 checksum += eeprom_data;
4701 if(checksum == (uint16_t) EEPROM_SUM)
4702 return E1000_SUCCESS;
4704 DEBUGOUT("EEPROM Checksum Invalid\n");
4705 return -E1000_ERR_EEPROM;
4709 /******************************************************************************
4710 * Calculates the EEPROM checksum and writes it to the EEPROM
4712 * hw - Struct containing variables accessed by shared code
4714 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4715 * Writes the difference to word offset 63 of the EEPROM.
4716 *****************************************************************************/
4718 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4720 uint16_t checksum = 0;
4721 uint16_t i, eeprom_data;
4723 DEBUGFUNC("e1000_update_eeprom_checksum");
4725 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4726 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4727 DEBUGOUT("EEPROM Read Error\n");
4728 return -E1000_ERR_EEPROM;
4730 checksum += eeprom_data;
4732 checksum = (uint16_t) EEPROM_SUM - checksum;
4733 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4734 DEBUGOUT("EEPROM Write Error\n");
4735 return -E1000_ERR_EEPROM;
4736 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4737 e1000_commit_shadow_ram(hw);
4739 return E1000_SUCCESS;
4742 /******************************************************************************
4743 * Parent function for writing words to the different EEPROM types.
4745 * hw - Struct containing variables accessed by shared code
4746 * offset - offset within the EEPROM to be written to
4747 * words - number of words to write
4748 * data - 16 bit word to be written to the EEPROM
4750 * If e1000_update_eeprom_checksum is not called after this function, the
4751 * EEPROM will most likely contain an invalid checksum.
4752 *****************************************************************************/
4754 e1000_write_eeprom(struct e1000_hw *hw,
4759 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4762 DEBUGFUNC("e1000_write_eeprom");
4764 /* A check for invalid values: offset too large, too many words, and not
4767 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4769 DEBUGOUT("\"words\" parameter out of bounds\n");
4770 return -E1000_ERR_EEPROM;
4773 /* 82573 writes only through eewr */
4774 if(eeprom->use_eewr == TRUE)
4775 return e1000_write_eeprom_eewr(hw, offset, words, data);
4777 /* Prepare the EEPROM for writing */
4778 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4779 return -E1000_ERR_EEPROM;
4781 if(eeprom->type == e1000_eeprom_microwire) {
4782 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4784 status = e1000_write_eeprom_spi(hw, offset, words, data);
4788 /* Done with writing */
4789 e1000_release_eeprom(hw);
4794 /******************************************************************************
4795 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4797 * hw - Struct containing variables accessed by shared code
4798 * offset - offset within the EEPROM to be written to
4799 * words - number of words to write
4800 * data - pointer to array of 8 bit words to be written to the EEPROM
4802 *****************************************************************************/
4804 e1000_write_eeprom_spi(struct e1000_hw *hw,
4809 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4812 DEBUGFUNC("e1000_write_eeprom_spi");
4814 while (widx < words) {
4815 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
4817 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
4819 e1000_standby_eeprom(hw);
4821 /* Send the WRITE ENABLE command (8 bit opcode ) */
4822 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4823 eeprom->opcode_bits);
4825 e1000_standby_eeprom(hw);
4827 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4828 if((eeprom->address_bits == 8) && (offset >= 128))
4829 write_opcode |= EEPROM_A8_OPCODE_SPI;
4831 /* Send the Write command (8-bit opcode + addr) */
4832 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4834 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
4835 eeprom->address_bits);
4839 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4840 while (widx < words) {
4841 uint16_t word_out = data[widx];
4842 word_out = (word_out >> 8) | (word_out << 8);
4843 e1000_shift_out_ee_bits(hw, word_out, 16);
4846 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4847 * operation, while the smaller eeproms are capable of an 8-byte
4848 * PAGE WRITE operation. Break the inner loop to pass new address
4850 if((((offset + widx)*2) % eeprom->page_size) == 0) {
4851 e1000_standby_eeprom(hw);
4857 return E1000_SUCCESS;
4860 /******************************************************************************
4861 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4863 * hw - Struct containing variables accessed by shared code
4864 * offset - offset within the EEPROM to be written to
4865 * words - number of words to write
4866 * data - pointer to array of 16 bit words to be written to the EEPROM
4868 *****************************************************************************/
4870 e1000_write_eeprom_microwire(struct e1000_hw *hw,
4875 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4877 uint16_t words_written = 0;
4880 DEBUGFUNC("e1000_write_eeprom_microwire");
4882 /* Send the write enable command to the EEPROM (3-bit opcode plus
4883 * 6/8-bit dummy address beginning with 11). It's less work to include
4884 * the 11 of the dummy address as part of the opcode than it is to shift
4885 * it over the correct number of bits for the address. This puts the
4886 * EEPROM into write/erase mode.
4888 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4889 (uint16_t)(eeprom->opcode_bits + 2));
4891 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4893 /* Prepare the EEPROM */
4894 e1000_standby_eeprom(hw);
4896 while (words_written < words) {
4897 /* Send the Write command (3-bit opcode + addr) */
4898 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4899 eeprom->opcode_bits);
4901 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
4902 eeprom->address_bits);
4905 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4907 /* Toggle the CS line. This in effect tells the EEPROM to execute
4908 * the previous command.
4910 e1000_standby_eeprom(hw);
4912 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4913 * signal that the command has been completed by raising the DO signal.
4914 * If DO does not go high in 10 milliseconds, then error out.
4916 for(i = 0; i < 200; i++) {
4917 eecd = E1000_READ_REG(hw, EECD);
4918 if(eecd & E1000_EECD_DO) break;
4922 DEBUGOUT("EEPROM Write did not complete\n");
4923 return -E1000_ERR_EEPROM;
4926 /* Recover from write */
4927 e1000_standby_eeprom(hw);
4932 /* Send the write disable command to the EEPROM (3-bit opcode plus
4933 * 6/8-bit dummy address beginning with 10). It's less work to include
4934 * the 10 of the dummy address as part of the opcode than it is to shift
4935 * it over the correct number of bits for the address. This takes the
4936 * EEPROM out of write/erase mode.
4938 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4939 (uint16_t)(eeprom->opcode_bits + 2));
4941 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4943 return E1000_SUCCESS;
4946 /******************************************************************************
4947 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4948 * in the eeprom cache and the non modified values in the currently active bank
4951 * hw - Struct containing variables accessed by shared code
4952 * offset - offset of word in the EEPROM to read
4953 * data - word read from the EEPROM
4954 * words - number of words to read
4955 *****************************************************************************/
4957 e1000_commit_shadow_ram(struct e1000_hw *hw)
4959 uint32_t attempts = 100000;
4963 int32_t error = E1000_SUCCESS;
4965 /* The flop register will be used to determine if flash type is STM */
4966 flop = E1000_READ_REG(hw, FLOP);
4968 if (hw->mac_type == e1000_82573) {
4969 for (i=0; i < attempts; i++) {
4970 eecd = E1000_READ_REG(hw, EECD);
4971 if ((eecd & E1000_EECD_FLUPD) == 0) {
4977 if (i == attempts) {
4978 return -E1000_ERR_EEPROM;
4981 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4982 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4983 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4986 /* Perform the flash update */
4987 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4989 for (i=0; i < attempts; i++) {
4990 eecd = E1000_READ_REG(hw, EECD);
4991 if ((eecd & E1000_EECD_FLUPD) == 0) {
4997 if (i == attempts) {
4998 return -E1000_ERR_EEPROM;
5005 /******************************************************************************
5006 * Reads the adapter's part number from the EEPROM
5008 * hw - Struct containing variables accessed by shared code
5009 * part_num - Adapter's part number
5010 *****************************************************************************/
5012 e1000_read_part_num(struct e1000_hw *hw,
5015 uint16_t offset = EEPROM_PBA_BYTE_1;
5016 uint16_t eeprom_data;
5018 DEBUGFUNC("e1000_read_part_num");
5020 /* Get word 0 from EEPROM */
5021 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5022 DEBUGOUT("EEPROM Read Error\n");
5023 return -E1000_ERR_EEPROM;
5025 /* Save word 0 in upper half of part_num */
5026 *part_num = (uint32_t) (eeprom_data << 16);
5028 /* Get word 1 from EEPROM */
5029 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
5030 DEBUGOUT("EEPROM Read Error\n");
5031 return -E1000_ERR_EEPROM;
5033 /* Save word 1 in lower half of part_num */
5034 *part_num |= eeprom_data;
5036 return E1000_SUCCESS;
5039 /******************************************************************************
5040 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5041 * second function of dual function devices
5043 * hw - Struct containing variables accessed by shared code
5044 *****************************************************************************/
5046 e1000_read_mac_addr(struct e1000_hw * hw)
5049 uint16_t eeprom_data, i;
5051 DEBUGFUNC("e1000_read_mac_addr");
5053 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5055 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5056 DEBUGOUT("EEPROM Read Error\n");
5057 return -E1000_ERR_EEPROM;
5059 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5060 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5063 switch (hw->mac_type) {
5067 case e1000_82546_rev_3:
5069 case e1000_80003es2lan:
5070 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5071 hw->perm_mac_addr[5] ^= 0x01;
5075 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
5076 hw->mac_addr[i] = hw->perm_mac_addr[i];
5077 return E1000_SUCCESS;
5080 /******************************************************************************
5081 * Initializes receive address filters.
5083 * hw - Struct containing variables accessed by shared code
5085 * Places the MAC address in receive address register 0 and clears the rest
5086 * of the receive addresss registers. Clears the multicast table. Assumes
5087 * the receiver is in reset when the routine is called.
5088 *****************************************************************************/
5090 e1000_init_rx_addrs(struct e1000_hw *hw)
5095 DEBUGFUNC("e1000_init_rx_addrs");
5097 /* Setup the receive address. */
5098 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5100 e1000_rar_set(hw, hw->mac_addr, 0);
5102 rar_num = E1000_RAR_ENTRIES;
5104 /* Reserve a spot for the Locally Administered Address to work around
5105 * an 82571 issue in which a reset on one port will reload the MAC on
5106 * the other port. */
5107 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5109 /* Zero out the other 15 receive addresses. */
5110 DEBUGOUT("Clearing RAR[1-15]\n");
5111 for(i = 1; i < rar_num; i++) {
5112 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5113 E1000_WRITE_FLUSH(hw);
5114 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5115 E1000_WRITE_FLUSH(hw);
5120 /******************************************************************************
5121 * Updates the MAC's list of multicast addresses.
5123 * hw - Struct containing variables accessed by shared code
5124 * mc_addr_list - the list of new multicast addresses
5125 * mc_addr_count - number of addresses
5126 * pad - number of bytes between addresses in the list
5127 * rar_used_count - offset where to start adding mc addresses into the RAR's
5129 * The given list replaces any existing list. Clears the last 15 receive
5130 * address registers and the multicast table. Uses receive address registers
5131 * for the first 15 multicast addresses, and hashes the rest into the
5133 *****************************************************************************/
5135 e1000_mc_addr_list_update(struct e1000_hw *hw,
5136 uint8_t *mc_addr_list,
5137 uint32_t mc_addr_count,
5139 uint32_t rar_used_count)
5141 uint32_t hash_value;
5143 uint32_t num_rar_entry;
5144 uint32_t num_mta_entry;
5146 DEBUGFUNC("e1000_mc_addr_list_update");
5148 /* Set the new number of MC addresses that we are being requested to use. */
5149 hw->num_mc_addrs = mc_addr_count;
5151 /* Clear RAR[1-15] */
5152 DEBUGOUT(" Clearing RAR[1-15]\n");
5153 num_rar_entry = E1000_RAR_ENTRIES;
5154 /* Reserve a spot for the Locally Administered Address to work around
5155 * an 82571 issue in which a reset on one port will reload the MAC on
5156 * the other port. */
5157 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5160 for(i = rar_used_count; i < num_rar_entry; i++) {
5161 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5162 E1000_WRITE_FLUSH(hw);
5163 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5164 E1000_WRITE_FLUSH(hw);
5168 DEBUGOUT(" Clearing MTA\n");
5169 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5170 for(i = 0; i < num_mta_entry; i++) {
5171 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5172 E1000_WRITE_FLUSH(hw);
5175 /* Add the new addresses */
5176 for(i = 0; i < mc_addr_count; i++) {
5177 DEBUGOUT(" Adding the multicast addresses:\n");
5178 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5179 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5180 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5181 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5182 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5183 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5184 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5186 hash_value = e1000_hash_mc_addr(hw,
5188 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5190 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5192 /* Place this multicast address in the RAR if there is room, *
5193 * else put it in the MTA
5195 if (rar_used_count < num_rar_entry) {
5197 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5201 e1000_mta_set(hw, hash_value);
5204 DEBUGOUT("MC Update Complete\n");
5208 /******************************************************************************
5209 * Hashes an address to determine its location in the multicast table
5211 * hw - Struct containing variables accessed by shared code
5212 * mc_addr - the multicast address to hash
5213 *****************************************************************************/
5215 e1000_hash_mc_addr(struct e1000_hw *hw,
5218 uint32_t hash_value = 0;
5220 /* The portion of the address that is used for the hash table is
5221 * determined by the mc_filter_type setting.
5223 switch (hw->mc_filter_type) {
5224 /* [0] [1] [2] [3] [4] [5]
5229 /* [47:36] i.e. 0x563 for above example address */
5230 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5233 /* [46:35] i.e. 0xAC6 for above example address */
5234 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5237 /* [45:34] i.e. 0x5D8 for above example address */
5238 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5241 /* [43:32] i.e. 0x634 for above example address */
5242 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5246 hash_value &= 0xFFF;
5251 /******************************************************************************
5252 * Sets the bit in the multicast table corresponding to the hash value.
5254 * hw - Struct containing variables accessed by shared code
5255 * hash_value - Multicast address hash value
5256 *****************************************************************************/
5258 e1000_mta_set(struct e1000_hw *hw,
5259 uint32_t hash_value)
5261 uint32_t hash_bit, hash_reg;
5265 /* The MTA is a register array of 128 32-bit registers.
5266 * It is treated like an array of 4096 bits. We want to set
5267 * bit BitArray[hash_value]. So we figure out what register
5268 * the bit is in, read it, OR in the new bit, then write
5269 * back the new value. The register is determined by the
5270 * upper 7 bits of the hash value and the bit within that
5271 * register are determined by the lower 5 bits of the value.
5273 hash_reg = (hash_value >> 5) & 0x7F;
5274 hash_bit = hash_value & 0x1F;
5276 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5278 mta |= (1 << hash_bit);
5280 /* If we are on an 82544 and we are trying to write an odd offset
5281 * in the MTA, save off the previous entry before writing and
5282 * restore the old value after writing.
5284 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5285 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5286 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5287 E1000_WRITE_FLUSH(hw);
5288 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5289 E1000_WRITE_FLUSH(hw);
5291 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5292 E1000_WRITE_FLUSH(hw);
5296 /******************************************************************************
5297 * Puts an ethernet address into a receive address register.
5299 * hw - Struct containing variables accessed by shared code
5300 * addr - Address to put into receive address register
5301 * index - Receive address register to write
5302 *****************************************************************************/
5304 e1000_rar_set(struct e1000_hw *hw,
5308 uint32_t rar_low, rar_high;
5310 /* HW expects these in little endian so we reverse the byte order
5311 * from network order (big endian) to little endian
5313 rar_low = ((uint32_t) addr[0] |
5314 ((uint32_t) addr[1] << 8) |
5315 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5316 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5318 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5322 * If there are any Rx frames queued up or otherwise present in the HW
5323 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5324 * hang. To work around this issue, we have to disable receives and
5325 * flush out all Rx frames before we enable RSS. To do so, we modify we
5326 * redirect all Rx traffic to manageability and then reset the HW.
5327 * This flushes away Rx frames, and (since the redirections to
5328 * manageability persists across resets) keeps new ones from coming in
5329 * while we work. Then, we clear the Address Valid AV bit for all MAC
5330 * addresses and undo the re-direction to manageability.
5331 * Now, frames are coming in again, but the MAC won't accept them, so
5332 * far so good. We now proceed to initialize RSS (if necessary) and
5333 * configure the Rx unit. Last, we re-enable the AV bits and continue
5336 switch (hw->mac_type) {
5339 case e1000_80003es2lan:
5340 if (hw->leave_av_bit_off == TRUE)
5343 /* Indicate to hardware the Address is Valid. */
5344 rar_high |= E1000_RAH_AV;
5348 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5349 E1000_WRITE_FLUSH(hw);
5350 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5351 E1000_WRITE_FLUSH(hw);
5354 /******************************************************************************
5355 * Writes a value to the specified offset in the VLAN filter table.
5357 * hw - Struct containing variables accessed by shared code
5358 * offset - Offset in VLAN filer table to write
5359 * value - Value to write into VLAN filter table
5360 *****************************************************************************/
5362 e1000_write_vfta(struct e1000_hw *hw,
5368 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5369 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5370 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5371 E1000_WRITE_FLUSH(hw);
5372 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5373 E1000_WRITE_FLUSH(hw);
5375 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5376 E1000_WRITE_FLUSH(hw);
5380 /******************************************************************************
5381 * Clears the VLAN filer table
5383 * hw - Struct containing variables accessed by shared code
5384 *****************************************************************************/
5386 e1000_clear_vfta(struct e1000_hw *hw)
5389 uint32_t vfta_value = 0;
5390 uint32_t vfta_offset = 0;
5391 uint32_t vfta_bit_in_reg = 0;
5393 if (hw->mac_type == e1000_82573) {
5394 if (hw->mng_cookie.vlan_id != 0) {
5395 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5396 * ID. The following operations determine which 32b entry
5397 * (i.e. offset) into the array we want to set the VLAN ID
5398 * (i.e. bit) of the manageability unit. */
5399 vfta_offset = (hw->mng_cookie.vlan_id >>
5400 E1000_VFTA_ENTRY_SHIFT) &
5401 E1000_VFTA_ENTRY_MASK;
5402 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5403 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5406 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5407 /* If the offset we want to clear is the same offset of the
5408 * manageability VLAN ID, then clear all bits except that of the
5409 * manageability unit */
5410 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5411 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5412 E1000_WRITE_FLUSH(hw);
5417 e1000_id_led_init(struct e1000_hw * hw)
5420 const uint32_t ledctl_mask = 0x000000FF;
5421 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5422 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5423 uint16_t eeprom_data, i, temp;
5424 const uint16_t led_mask = 0x0F;
5426 DEBUGFUNC("e1000_id_led_init");
5428 if(hw->mac_type < e1000_82540) {
5430 return E1000_SUCCESS;
5433 ledctl = E1000_READ_REG(hw, LEDCTL);
5434 hw->ledctl_default = ledctl;
5435 hw->ledctl_mode1 = hw->ledctl_default;
5436 hw->ledctl_mode2 = hw->ledctl_default;
5438 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5439 DEBUGOUT("EEPROM Read Error\n");
5440 return -E1000_ERR_EEPROM;
5442 if((eeprom_data== ID_LED_RESERVED_0000) ||
5443 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
5444 for(i = 0; i < 4; i++) {
5445 temp = (eeprom_data >> (i << 2)) & led_mask;
5447 case ID_LED_ON1_DEF2:
5448 case ID_LED_ON1_ON2:
5449 case ID_LED_ON1_OFF2:
5450 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5451 hw->ledctl_mode1 |= ledctl_on << (i << 3);
5453 case ID_LED_OFF1_DEF2:
5454 case ID_LED_OFF1_ON2:
5455 case ID_LED_OFF1_OFF2:
5456 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5457 hw->ledctl_mode1 |= ledctl_off << (i << 3);
5464 case ID_LED_DEF1_ON2:
5465 case ID_LED_ON1_ON2:
5466 case ID_LED_OFF1_ON2:
5467 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5468 hw->ledctl_mode2 |= ledctl_on << (i << 3);
5470 case ID_LED_DEF1_OFF2:
5471 case ID_LED_ON1_OFF2:
5472 case ID_LED_OFF1_OFF2:
5473 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5474 hw->ledctl_mode2 |= ledctl_off << (i << 3);
5481 return E1000_SUCCESS;
5484 /******************************************************************************
5485 * Prepares SW controlable LED for use and saves the current state of the LED.
5487 * hw - Struct containing variables accessed by shared code
5488 *****************************************************************************/
5490 e1000_setup_led(struct e1000_hw *hw)
5493 int32_t ret_val = E1000_SUCCESS;
5495 DEBUGFUNC("e1000_setup_led");
5497 switch(hw->mac_type) {
5498 case e1000_82542_rev2_0:
5499 case e1000_82542_rev2_1:
5502 /* No setup necessary */
5506 case e1000_82541_rev_2:
5507 case e1000_82547_rev_2:
5508 /* Turn off PHY Smart Power Down (if enabled) */
5509 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
5510 &hw->phy_spd_default);
5513 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5514 (uint16_t)(hw->phy_spd_default &
5515 ~IGP01E1000_GMII_SPD));
5520 if(hw->media_type == e1000_media_type_fiber) {
5521 ledctl = E1000_READ_REG(hw, LEDCTL);
5522 /* Save current LEDCTL settings */
5523 hw->ledctl_default = ledctl;
5525 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
5526 E1000_LEDCTL_LED0_BLINK |
5527 E1000_LEDCTL_LED0_MODE_MASK);
5528 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
5529 E1000_LEDCTL_LED0_MODE_SHIFT);
5530 E1000_WRITE_REG(hw, LEDCTL, ledctl);
5531 } else if(hw->media_type == e1000_media_type_copper)
5532 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5536 return E1000_SUCCESS;
5539 /******************************************************************************
5540 * Restores the saved state of the SW controlable LED.
5542 * hw - Struct containing variables accessed by shared code
5543 *****************************************************************************/
5545 e1000_cleanup_led(struct e1000_hw *hw)
5547 int32_t ret_val = E1000_SUCCESS;
5549 DEBUGFUNC("e1000_cleanup_led");
5551 switch(hw->mac_type) {
5552 case e1000_82542_rev2_0:
5553 case e1000_82542_rev2_1:
5556 /* No cleanup necessary */
5560 case e1000_82541_rev_2:
5561 case e1000_82547_rev_2:
5562 /* Turn on PHY Smart Power Down (if previously enabled) */
5563 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5564 hw->phy_spd_default);
5569 /* Restore LEDCTL settings */
5570 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5574 return E1000_SUCCESS;
5577 /******************************************************************************
5578 * Turns on the software controllable LED
5580 * hw - Struct containing variables accessed by shared code
5581 *****************************************************************************/
5583 e1000_led_on(struct e1000_hw *hw)
5585 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
5587 DEBUGFUNC("e1000_led_on");
5589 switch(hw->mac_type) {
5590 case e1000_82542_rev2_0:
5591 case e1000_82542_rev2_1:
5593 /* Set SW Defineable Pin 0 to turn on the LED */
5594 ctrl |= E1000_CTRL_SWDPIN0;
5595 ctrl |= E1000_CTRL_SWDPIO0;
5598 if(hw->media_type == e1000_media_type_fiber) {
5599 /* Set SW Defineable Pin 0 to turn on the LED */
5600 ctrl |= E1000_CTRL_SWDPIN0;
5601 ctrl |= E1000_CTRL_SWDPIO0;
5603 /* Clear SW Defineable Pin 0 to turn on the LED */
5604 ctrl &= ~E1000_CTRL_SWDPIN0;
5605 ctrl |= E1000_CTRL_SWDPIO0;
5609 if(hw->media_type == e1000_media_type_fiber) {
5610 /* Clear SW Defineable Pin 0 to turn on the LED */
5611 ctrl &= ~E1000_CTRL_SWDPIN0;
5612 ctrl |= E1000_CTRL_SWDPIO0;
5613 } else if(hw->media_type == e1000_media_type_copper) {
5614 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5615 return E1000_SUCCESS;
5620 E1000_WRITE_REG(hw, CTRL, ctrl);
5622 return E1000_SUCCESS;
5625 /******************************************************************************
5626 * Turns off the software controllable LED
5628 * hw - Struct containing variables accessed by shared code
5629 *****************************************************************************/
5631 e1000_led_off(struct e1000_hw *hw)
5633 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
5635 DEBUGFUNC("e1000_led_off");
5637 switch(hw->mac_type) {
5638 case e1000_82542_rev2_0:
5639 case e1000_82542_rev2_1:
5641 /* Clear SW Defineable Pin 0 to turn off the LED */
5642 ctrl &= ~E1000_CTRL_SWDPIN0;
5643 ctrl |= E1000_CTRL_SWDPIO0;
5646 if(hw->media_type == e1000_media_type_fiber) {
5647 /* Clear SW Defineable Pin 0 to turn off the LED */
5648 ctrl &= ~E1000_CTRL_SWDPIN0;
5649 ctrl |= E1000_CTRL_SWDPIO0;
5651 /* Set SW Defineable Pin 0 to turn off the LED */
5652 ctrl |= E1000_CTRL_SWDPIN0;
5653 ctrl |= E1000_CTRL_SWDPIO0;
5657 if(hw->media_type == e1000_media_type_fiber) {
5658 /* Set SW Defineable Pin 0 to turn off the LED */
5659 ctrl |= E1000_CTRL_SWDPIN0;
5660 ctrl |= E1000_CTRL_SWDPIO0;
5661 } else if(hw->media_type == e1000_media_type_copper) {
5662 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5663 return E1000_SUCCESS;
5668 E1000_WRITE_REG(hw, CTRL, ctrl);
5670 return E1000_SUCCESS;
5673 /******************************************************************************
5674 * Clears all hardware statistics counters.
5676 * hw - Struct containing variables accessed by shared code
5677 *****************************************************************************/
5679 e1000_clear_hw_cntrs(struct e1000_hw *hw)
5681 volatile uint32_t temp;
5683 temp = E1000_READ_REG(hw, CRCERRS);
5684 temp = E1000_READ_REG(hw, SYMERRS);
5685 temp = E1000_READ_REG(hw, MPC);
5686 temp = E1000_READ_REG(hw, SCC);
5687 temp = E1000_READ_REG(hw, ECOL);
5688 temp = E1000_READ_REG(hw, MCC);
5689 temp = E1000_READ_REG(hw, LATECOL);
5690 temp = E1000_READ_REG(hw, COLC);
5691 temp = E1000_READ_REG(hw, DC);
5692 temp = E1000_READ_REG(hw, SEC);
5693 temp = E1000_READ_REG(hw, RLEC);
5694 temp = E1000_READ_REG(hw, XONRXC);
5695 temp = E1000_READ_REG(hw, XONTXC);
5696 temp = E1000_READ_REG(hw, XOFFRXC);
5697 temp = E1000_READ_REG(hw, XOFFTXC);
5698 temp = E1000_READ_REG(hw, FCRUC);
5699 temp = E1000_READ_REG(hw, PRC64);
5700 temp = E1000_READ_REG(hw, PRC127);
5701 temp = E1000_READ_REG(hw, PRC255);
5702 temp = E1000_READ_REG(hw, PRC511);
5703 temp = E1000_READ_REG(hw, PRC1023);
5704 temp = E1000_READ_REG(hw, PRC1522);
5705 temp = E1000_READ_REG(hw, GPRC);
5706 temp = E1000_READ_REG(hw, BPRC);
5707 temp = E1000_READ_REG(hw, MPRC);
5708 temp = E1000_READ_REG(hw, GPTC);
5709 temp = E1000_READ_REG(hw, GORCL);
5710 temp = E1000_READ_REG(hw, GORCH);
5711 temp = E1000_READ_REG(hw, GOTCL);
5712 temp = E1000_READ_REG(hw, GOTCH);
5713 temp = E1000_READ_REG(hw, RNBC);
5714 temp = E1000_READ_REG(hw, RUC);
5715 temp = E1000_READ_REG(hw, RFC);
5716 temp = E1000_READ_REG(hw, ROC);
5717 temp = E1000_READ_REG(hw, RJC);
5718 temp = E1000_READ_REG(hw, TORL);
5719 temp = E1000_READ_REG(hw, TORH);
5720 temp = E1000_READ_REG(hw, TOTL);
5721 temp = E1000_READ_REG(hw, TOTH);
5722 temp = E1000_READ_REG(hw, TPR);
5723 temp = E1000_READ_REG(hw, TPT);
5724 temp = E1000_READ_REG(hw, PTC64);
5725 temp = E1000_READ_REG(hw, PTC127);
5726 temp = E1000_READ_REG(hw, PTC255);
5727 temp = E1000_READ_REG(hw, PTC511);
5728 temp = E1000_READ_REG(hw, PTC1023);
5729 temp = E1000_READ_REG(hw, PTC1522);
5730 temp = E1000_READ_REG(hw, MPTC);
5731 temp = E1000_READ_REG(hw, BPTC);
5733 if(hw->mac_type < e1000_82543) return;
5735 temp = E1000_READ_REG(hw, ALGNERRC);
5736 temp = E1000_READ_REG(hw, RXERRC);
5737 temp = E1000_READ_REG(hw, TNCRS);
5738 temp = E1000_READ_REG(hw, CEXTERR);
5739 temp = E1000_READ_REG(hw, TSCTC);
5740 temp = E1000_READ_REG(hw, TSCTFC);
5742 if(hw->mac_type <= e1000_82544) return;
5744 temp = E1000_READ_REG(hw, MGTPRC);
5745 temp = E1000_READ_REG(hw, MGTPDC);
5746 temp = E1000_READ_REG(hw, MGTPTC);
5748 if(hw->mac_type <= e1000_82547_rev_2) return;
5750 temp = E1000_READ_REG(hw, IAC);
5751 temp = E1000_READ_REG(hw, ICRXOC);
5752 temp = E1000_READ_REG(hw, ICRXPTC);
5753 temp = E1000_READ_REG(hw, ICRXATC);
5754 temp = E1000_READ_REG(hw, ICTXPTC);
5755 temp = E1000_READ_REG(hw, ICTXATC);
5756 temp = E1000_READ_REG(hw, ICTXQEC);
5757 temp = E1000_READ_REG(hw, ICTXQMTC);
5758 temp = E1000_READ_REG(hw, ICRXDMTC);
5761 /******************************************************************************
5762 * Resets Adaptive IFS to its default state.
5764 * hw - Struct containing variables accessed by shared code
5766 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5767 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5768 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5769 * before calling this function.
5770 *****************************************************************************/
5772 e1000_reset_adaptive(struct e1000_hw *hw)
5774 DEBUGFUNC("e1000_reset_adaptive");
5776 if(hw->adaptive_ifs) {
5777 if(!hw->ifs_params_forced) {
5778 hw->current_ifs_val = 0;
5779 hw->ifs_min_val = IFS_MIN;
5780 hw->ifs_max_val = IFS_MAX;
5781 hw->ifs_step_size = IFS_STEP;
5782 hw->ifs_ratio = IFS_RATIO;
5784 hw->in_ifs_mode = FALSE;
5785 E1000_WRITE_REG(hw, AIT, 0);
5787 DEBUGOUT("Not in Adaptive IFS mode!\n");
5791 /******************************************************************************
5792 * Called during the callback/watchdog routine to update IFS value based on
5793 * the ratio of transmits to collisions.
5795 * hw - Struct containing variables accessed by shared code
5796 * tx_packets - Number of transmits since last callback
5797 * total_collisions - Number of collisions since last callback
5798 *****************************************************************************/
5800 e1000_update_adaptive(struct e1000_hw *hw)
5802 DEBUGFUNC("e1000_update_adaptive");
5804 if(hw->adaptive_ifs) {
5805 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
5806 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
5807 hw->in_ifs_mode = TRUE;
5808 if(hw->current_ifs_val < hw->ifs_max_val) {
5809 if(hw->current_ifs_val == 0)
5810 hw->current_ifs_val = hw->ifs_min_val;
5812 hw->current_ifs_val += hw->ifs_step_size;
5813 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
5817 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
5818 hw->current_ifs_val = 0;
5819 hw->in_ifs_mode = FALSE;
5820 E1000_WRITE_REG(hw, AIT, 0);
5824 DEBUGOUT("Not in Adaptive IFS mode!\n");
5828 /******************************************************************************
5829 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5831 * hw - Struct containing variables accessed by shared code
5832 * frame_len - The length of the frame in question
5833 * mac_addr - The Ethernet destination address of the frame in question
5834 *****************************************************************************/
5836 e1000_tbi_adjust_stats(struct e1000_hw *hw,
5837 struct e1000_hw_stats *stats,
5843 /* First adjust the frame length. */
5845 /* We need to adjust the statistics counters, since the hardware
5846 * counters overcount this packet as a CRC error and undercount
5847 * the packet as a good packet
5849 /* This packet should not be counted as a CRC error. */
5851 /* This packet does count as a Good Packet Received. */
5854 /* Adjust the Good Octets received counters */
5855 carry_bit = 0x80000000 & stats->gorcl;
5856 stats->gorcl += frame_len;
5857 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5858 * Received Count) was one before the addition,
5859 * AND it is zero after, then we lost the carry out,
5860 * need to add one to Gorch (Good Octets Received Count High).
5861 * This could be simplified if all environments supported
5864 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
5866 /* Is this a broadcast or multicast? Check broadcast first,
5867 * since the test for a multicast frame will test positive on
5868 * a broadcast frame.
5870 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
5871 /* Broadcast packet */
5873 else if(*mac_addr & 0x01)
5874 /* Multicast packet */
5877 if(frame_len == hw->max_frame_size) {
5878 /* In this case, the hardware has overcounted the number of
5885 /* Adjust the bin counters when the extra byte put the frame in the
5886 * wrong bin. Remember that the frame_len was adjusted above.
5888 if(frame_len == 64) {
5891 } else if(frame_len == 127) {
5894 } else if(frame_len == 255) {
5897 } else if(frame_len == 511) {
5900 } else if(frame_len == 1023) {
5903 } else if(frame_len == 1522) {
5908 /******************************************************************************
5909 * Gets the current PCI bus type, speed, and width of the hardware
5911 * hw - Struct containing variables accessed by shared code
5912 *****************************************************************************/
5914 e1000_get_bus_info(struct e1000_hw *hw)
5918 switch (hw->mac_type) {
5919 case e1000_82542_rev2_0:
5920 case e1000_82542_rev2_1:
5921 hw->bus_type = e1000_bus_type_unknown;
5922 hw->bus_speed = e1000_bus_speed_unknown;
5923 hw->bus_width = e1000_bus_width_unknown;
5927 hw->bus_type = e1000_bus_type_pci_express;
5928 hw->bus_speed = e1000_bus_speed_2500;
5929 hw->bus_width = e1000_bus_width_pciex_1;
5932 case e1000_80003es2lan:
5933 hw->bus_type = e1000_bus_type_pci_express;
5934 hw->bus_speed = e1000_bus_speed_2500;
5935 hw->bus_width = e1000_bus_width_pciex_4;
5938 status = E1000_READ_REG(hw, STATUS);
5939 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5940 e1000_bus_type_pcix : e1000_bus_type_pci;
5942 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
5943 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
5944 e1000_bus_speed_66 : e1000_bus_speed_120;
5945 } else if(hw->bus_type == e1000_bus_type_pci) {
5946 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
5947 e1000_bus_speed_66 : e1000_bus_speed_33;
5949 switch (status & E1000_STATUS_PCIX_SPEED) {
5950 case E1000_STATUS_PCIX_SPEED_66:
5951 hw->bus_speed = e1000_bus_speed_66;
5953 case E1000_STATUS_PCIX_SPEED_100:
5954 hw->bus_speed = e1000_bus_speed_100;
5956 case E1000_STATUS_PCIX_SPEED_133:
5957 hw->bus_speed = e1000_bus_speed_133;
5960 hw->bus_speed = e1000_bus_speed_reserved;
5964 hw->bus_width = (status & E1000_STATUS_BUS64) ?
5965 e1000_bus_width_64 : e1000_bus_width_32;
5971 /******************************************************************************
5972 * Reads a value from one of the devices registers using port I/O (as opposed
5973 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5975 * hw - Struct containing variables accessed by shared code
5976 * offset - offset to read from
5977 *****************************************************************************/
5979 e1000_read_reg_io(struct e1000_hw *hw,
5982 unsigned long io_addr = hw->io_base;
5983 unsigned long io_data = hw->io_base + 4;
5985 e1000_io_write(hw, io_addr, offset);
5986 return e1000_io_read(hw, io_data);
5990 /******************************************************************************
5991 * Writes a value to one of the devices registers using port I/O (as opposed to
5992 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5994 * hw - Struct containing variables accessed by shared code
5995 * offset - offset to write to
5996 * value - value to write
5997 *****************************************************************************/
5999 e1000_write_reg_io(struct e1000_hw *hw,
6003 unsigned long io_addr = hw->io_base;
6004 unsigned long io_data = hw->io_base + 4;
6006 e1000_io_write(hw, io_addr, offset);
6007 e1000_io_write(hw, io_data, value);
6011 /******************************************************************************
6012 * Estimates the cable length.
6014 * hw - Struct containing variables accessed by shared code
6015 * min_length - The estimated minimum length
6016 * max_length - The estimated maximum length
6018 * returns: - E1000_ERR_XXX
6021 * This function always returns a ranged length (minimum & maximum).
6022 * So for M88 phy's, this function interprets the one value returned from the
6023 * register to the minimum and maximum range.
6024 * For IGP phy's, the function calculates the range by the AGC registers.
6025 *****************************************************************************/
6027 e1000_get_cable_length(struct e1000_hw *hw,
6028 uint16_t *min_length,
6029 uint16_t *max_length)
6032 uint16_t agc_value = 0;
6033 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6034 uint16_t max_agc = 0;
6035 uint16_t i, phy_data;
6036 uint16_t cable_length;
6038 DEBUGFUNC("e1000_get_cable_length");
6040 *min_length = *max_length = 0;
6042 /* Use old method for Phy older than IGP */
6043 if(hw->phy_type == e1000_phy_m88) {
6045 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6049 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6050 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6052 /* Convert the enum value to ranged values */
6053 switch (cable_length) {
6054 case e1000_cable_length_50:
6056 *max_length = e1000_igp_cable_length_50;
6058 case e1000_cable_length_50_80:
6059 *min_length = e1000_igp_cable_length_50;
6060 *max_length = e1000_igp_cable_length_80;
6062 case e1000_cable_length_80_110:
6063 *min_length = e1000_igp_cable_length_80;
6064 *max_length = e1000_igp_cable_length_110;
6066 case e1000_cable_length_110_140:
6067 *min_length = e1000_igp_cable_length_110;
6068 *max_length = e1000_igp_cable_length_140;
6070 case e1000_cable_length_140:
6071 *min_length = e1000_igp_cable_length_140;
6072 *max_length = e1000_igp_cable_length_170;
6075 return -E1000_ERR_PHY;
6078 } else if (hw->phy_type == e1000_phy_gg82563) {
6079 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6083 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6085 switch (cable_length) {
6086 case e1000_gg_cable_length_60:
6088 *max_length = e1000_igp_cable_length_60;
6090 case e1000_gg_cable_length_60_115:
6091 *min_length = e1000_igp_cable_length_60;
6092 *max_length = e1000_igp_cable_length_115;
6094 case e1000_gg_cable_length_115_150:
6095 *min_length = e1000_igp_cable_length_115;
6096 *max_length = e1000_igp_cable_length_150;
6098 case e1000_gg_cable_length_150:
6099 *min_length = e1000_igp_cable_length_150;
6100 *max_length = e1000_igp_cable_length_180;
6103 return -E1000_ERR_PHY;
6106 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6107 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6108 {IGP01E1000_PHY_AGC_A,
6109 IGP01E1000_PHY_AGC_B,
6110 IGP01E1000_PHY_AGC_C,
6111 IGP01E1000_PHY_AGC_D};
6112 /* Read the AGC registers for all channels */
6113 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6115 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6119 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6121 /* Array bound check. */
6122 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6124 return -E1000_ERR_PHY;
6126 agc_value += cur_agc;
6128 /* Update minimal AGC value. */
6129 if(min_agc > cur_agc)
6133 /* Remove the minimal AGC result for length < 50m */
6134 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6135 agc_value -= min_agc;
6137 /* Get the average length of the remaining 3 channels */
6138 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6140 /* Get the average length of all the 4 channels. */
6141 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6144 /* Set the range of the calculated length. */
6145 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6146 IGP01E1000_AGC_RANGE) > 0) ?
6147 (e1000_igp_cable_length_table[agc_value] -
6148 IGP01E1000_AGC_RANGE) : 0;
6149 *max_length = e1000_igp_cable_length_table[agc_value] +
6150 IGP01E1000_AGC_RANGE;
6151 } else if (hw->phy_type == e1000_phy_igp_2) {
6152 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6153 {IGP02E1000_PHY_AGC_A,
6154 IGP02E1000_PHY_AGC_B,
6155 IGP02E1000_PHY_AGC_C,
6156 IGP02E1000_PHY_AGC_D};
6157 /* Read the AGC registers for all channels */
6158 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6159 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6163 /* Getting bits 15:9, which represent the combination of course and
6164 * fine gain values. The result is a number that can be put into
6165 * the lookup table to obtain the approximate cable length. */
6166 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6167 IGP02E1000_AGC_LENGTH_MASK;
6169 /* Remove min & max AGC values from calculation. */
6170 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
6172 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
6175 agc_value += e1000_igp_2_cable_length_table[cur_agc];
6178 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
6179 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6181 /* Calculate cable length with the error range of +/- 10 meters. */
6182 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6183 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6184 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6187 return E1000_SUCCESS;
6190 /******************************************************************************
6191 * Check the cable polarity
6193 * hw - Struct containing variables accessed by shared code
6194 * polarity - output parameter : 0 - Polarity is not reversed
6195 * 1 - Polarity is reversed.
6197 * returns: - E1000_ERR_XXX
6200 * For phy's older then IGP, this function simply reads the polarity bit in the
6201 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6202 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6203 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6204 * IGP01E1000_PHY_PCS_INIT_REG.
6205 *****************************************************************************/
6207 e1000_check_polarity(struct e1000_hw *hw,
6213 DEBUGFUNC("e1000_check_polarity");
6215 if ((hw->phy_type == e1000_phy_m88) ||
6216 (hw->phy_type == e1000_phy_gg82563)) {
6217 /* return the Polarity bit in the Status register. */
6218 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6222 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6223 M88E1000_PSSR_REV_POLARITY_SHIFT;
6224 } else if(hw->phy_type == e1000_phy_igp ||
6225 hw->phy_type == e1000_phy_igp_2) {
6226 /* Read the Status register to check the speed */
6227 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6232 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6233 * find the polarity status */
6234 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6235 IGP01E1000_PSSR_SPEED_1000MBPS) {
6237 /* Read the GIG initialization PCS register (0x00B4) */
6238 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6243 /* Check the polarity bits */
6244 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6246 /* For 10 Mbps, read the polarity bit in the status register. (for
6247 * 100 Mbps this bit is always 0) */
6248 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6251 return E1000_SUCCESS;
6254 /******************************************************************************
6255 * Check if Downshift occured
6257 * hw - Struct containing variables accessed by shared code
6258 * downshift - output parameter : 0 - No Downshift ocured.
6259 * 1 - Downshift ocured.
6261 * returns: - E1000_ERR_XXX
6264 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6265 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6266 * Link Health register. In IGP this bit is latched high, so the driver must
6267 * read it immediately after link is established.
6268 *****************************************************************************/
6270 e1000_check_downshift(struct e1000_hw *hw)
6275 DEBUGFUNC("e1000_check_downshift");
6277 if(hw->phy_type == e1000_phy_igp ||
6278 hw->phy_type == e1000_phy_igp_2) {
6279 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6284 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6285 } else if ((hw->phy_type == e1000_phy_m88) ||
6286 (hw->phy_type == e1000_phy_gg82563)) {
6287 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6292 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6293 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6296 return E1000_SUCCESS;
6299 /*****************************************************************************
6301 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6302 * gigabit link is achieved to improve link quality.
6304 * hw: Struct containing variables accessed by shared code
6306 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6307 * E1000_SUCCESS at any other case.
6309 ****************************************************************************/
6312 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6316 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6317 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6318 {IGP01E1000_PHY_AGC_PARAM_A,
6319 IGP01E1000_PHY_AGC_PARAM_B,
6320 IGP01E1000_PHY_AGC_PARAM_C,
6321 IGP01E1000_PHY_AGC_PARAM_D};
6322 uint16_t min_length, max_length;
6324 DEBUGFUNC("e1000_config_dsp_after_link_change");
6326 if(hw->phy_type != e1000_phy_igp)
6327 return E1000_SUCCESS;
6330 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6332 DEBUGOUT("Error getting link speed and duplex\n");
6336 if(speed == SPEED_1000) {
6338 e1000_get_cable_length(hw, &min_length, &max_length);
6340 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6341 min_length >= e1000_igp_cable_length_50) {
6343 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6344 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6349 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6351 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6356 hw->dsp_config_state = e1000_dsp_config_activated;
6359 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6360 (min_length < e1000_igp_cable_length_50)) {
6362 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6363 uint32_t idle_errs = 0;
6365 /* clear previous idle error counts */
6366 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6371 for(i = 0; i < ffe_idle_err_timeout; i++) {
6373 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6378 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6379 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6380 hw->ffe_config_state = e1000_ffe_config_active;
6382 ret_val = e1000_write_phy_reg(hw,
6383 IGP01E1000_PHY_DSP_FFE,
6384 IGP01E1000_PHY_DSP_FFE_CM_CP);
6391 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6396 if(hw->dsp_config_state == e1000_dsp_config_activated) {
6397 /* Save off the current value of register 0x2F5B to be restored at
6398 * the end of the routines. */
6399 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6404 /* Disable the PHY transmitter */
6405 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6412 ret_val = e1000_write_phy_reg(hw, 0x0000,
6413 IGP01E1000_IEEE_FORCE_GIGA);
6416 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6417 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6421 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6422 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6424 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
6429 ret_val = e1000_write_phy_reg(hw, 0x0000,
6430 IGP01E1000_IEEE_RESTART_AUTONEG);
6436 /* Now enable the transmitter */
6437 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6442 hw->dsp_config_state = e1000_dsp_config_enabled;
6445 if(hw->ffe_config_state == e1000_ffe_config_active) {
6446 /* Save off the current value of register 0x2F5B to be restored at
6447 * the end of the routines. */
6448 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6453 /* Disable the PHY transmitter */
6454 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6461 ret_val = e1000_write_phy_reg(hw, 0x0000,
6462 IGP01E1000_IEEE_FORCE_GIGA);
6465 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
6466 IGP01E1000_PHY_DSP_FFE_DEFAULT);
6470 ret_val = e1000_write_phy_reg(hw, 0x0000,
6471 IGP01E1000_IEEE_RESTART_AUTONEG);
6477 /* Now enable the transmitter */
6478 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6483 hw->ffe_config_state = e1000_ffe_config_enabled;
6486 return E1000_SUCCESS;
6489 /*****************************************************************************
6490 * Set PHY to class A mode
6491 * Assumes the following operations will follow to enable the new class mode.
6492 * 1. Do a PHY soft reset
6493 * 2. Restart auto-negotiation or force link.
6495 * hw - Struct containing variables accessed by shared code
6496 ****************************************************************************/
6498 e1000_set_phy_mode(struct e1000_hw *hw)
6501 uint16_t eeprom_data;
6503 DEBUGFUNC("e1000_set_phy_mode");
6505 if((hw->mac_type == e1000_82545_rev_3) &&
6506 (hw->media_type == e1000_media_type_copper)) {
6507 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
6512 if((eeprom_data != EEPROM_RESERVED_WORD) &&
6513 (eeprom_data & EEPROM_PHY_CLASS_A)) {
6514 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
6517 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
6521 hw->phy_reset_disable = FALSE;
6525 return E1000_SUCCESS;
6528 /*****************************************************************************
6530 * This function sets the lplu state according to the active flag. When
6531 * activating lplu this function also disables smart speed and vise versa.
6532 * lplu will not be activated unless the device autonegotiation advertisment
6533 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6534 * hw: Struct containing variables accessed by shared code
6535 * active - true to enable lplu false to disable lplu.
6537 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6538 * E1000_SUCCESS at any other case.
6540 ****************************************************************************/
6543 e1000_set_d3_lplu_state(struct e1000_hw *hw,
6548 DEBUGFUNC("e1000_set_d3_lplu_state");
6550 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
6551 return E1000_SUCCESS;
6553 /* During driver activity LPLU should not be used or it will attain link
6554 * from the lowest speeds starting from 10Mbps. The capability is used for
6555 * Dx transitions and states */
6556 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6557 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6561 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6567 if(hw->mac_type == e1000_82541_rev_2 ||
6568 hw->mac_type == e1000_82547_rev_2) {
6569 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
6570 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6574 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6575 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6581 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6582 * Dx states where the power conservation is most important. During
6583 * driver activity we should enable SmartSpeed, so performance is
6585 if (hw->smart_speed == e1000_smart_speed_on) {
6586 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6591 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6592 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6596 } else if (hw->smart_speed == e1000_smart_speed_off) {
6597 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6602 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6603 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6609 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
6610 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
6611 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6613 if(hw->mac_type == e1000_82541_rev_2 ||
6614 hw->mac_type == e1000_82547_rev_2) {
6615 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6616 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6620 phy_data |= IGP02E1000_PM_D3_LPLU;
6621 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6627 /* When LPLU is enabled we should disable SmartSpeed */
6628 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6632 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6633 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6638 return E1000_SUCCESS;
6641 /*****************************************************************************
6643 * This function sets the lplu d0 state according to the active flag. When
6644 * activating lplu this function also disables smart speed and vise versa.
6645 * lplu will not be activated unless the device autonegotiation advertisment
6646 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
6647 * hw: Struct containing variables accessed by shared code
6648 * active - true to enable lplu false to disable lplu.
6650 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6651 * E1000_SUCCESS at any other case.
6653 ****************************************************************************/
6656 e1000_set_d0_lplu_state(struct e1000_hw *hw,
6661 DEBUGFUNC("e1000_set_d0_lplu_state");
6663 if(hw->mac_type <= e1000_82547_rev_2)
6664 return E1000_SUCCESS;
6666 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6671 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6672 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6676 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6677 * Dx states where the power conservation is most important. During
6678 * driver activity we should enable SmartSpeed, so performance is
6680 if (hw->smart_speed == e1000_smart_speed_on) {
6681 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6686 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6687 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6691 } else if (hw->smart_speed == e1000_smart_speed_off) {
6692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6697 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6698 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6707 phy_data |= IGP02E1000_PM_D0_LPLU;
6708 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6712 /* When LPLU is enabled we should disable SmartSpeed */
6713 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6717 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6718 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6723 return E1000_SUCCESS;
6726 /******************************************************************************
6727 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6729 * hw - Struct containing variables accessed by shared code
6730 *****************************************************************************/
6732 e1000_set_vco_speed(struct e1000_hw *hw)
6735 uint16_t default_page = 0;
6738 DEBUGFUNC("e1000_set_vco_speed");
6740 switch(hw->mac_type) {
6741 case e1000_82545_rev_3:
6742 case e1000_82546_rev_3:
6745 return E1000_SUCCESS;
6748 /* Set PHY register 30, page 5, bit 8 to 0 */
6750 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
6754 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
6758 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6762 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
6763 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6767 /* Set PHY register 30, page 4, bit 11 to 1 */
6769 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
6773 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6777 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
6778 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6782 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
6786 return E1000_SUCCESS;
6790 /*****************************************************************************
6791 * This function reads the cookie from ARC ram.
6793 * returns: - E1000_SUCCESS .
6794 ****************************************************************************/
6796 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
6799 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
6800 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
6802 length = (length >> 2);
6803 offset = (offset >> 2);
6805 for (i = 0; i < length; i++) {
6806 *((uint32_t *) buffer + i) =
6807 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
6809 return E1000_SUCCESS;
6813 /*****************************************************************************
6814 * This function checks whether the HOST IF is enabled for command operaton
6815 * and also checks whether the previous command is completed.
6816 * It busy waits in case of previous command is not completed.
6818 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6820 * - E1000_SUCCESS for success.
6821 ****************************************************************************/
6823 e1000_mng_enable_host_if(struct e1000_hw * hw)
6828 /* Check that the host interface is enabled. */
6829 hicr = E1000_READ_REG(hw, HICR);
6830 if ((hicr & E1000_HICR_EN) == 0) {
6831 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6832 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6834 /* check the previous command is completed */
6835 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
6836 hicr = E1000_READ_REG(hw, HICR);
6837 if (!(hicr & E1000_HICR_C))
6842 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
6843 DEBUGOUT("Previous command timeout failed .\n");
6844 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6846 return E1000_SUCCESS;
6849 /*****************************************************************************
6850 * This function writes the buffer content at the offset given on the host if.
6851 * It also does alignment considerations to do the writes in most efficient way.
6852 * Also fills up the sum of the buffer in *buffer parameter.
6854 * returns - E1000_SUCCESS for success.
6855 ****************************************************************************/
6857 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6858 uint16_t length, uint16_t offset, uint8_t *sum)
6861 uint8_t *bufptr = buffer;
6863 uint16_t remaining, i, j, prev_bytes;
6865 /* sum = only sum of the data and it is not checksum */
6867 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6868 return -E1000_ERR_PARAM;
6871 tmp = (uint8_t *)&data;
6872 prev_bytes = offset & 0x3;
6877 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6878 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6879 *(tmp + j) = *bufptr++;
6882 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6883 length -= j - prev_bytes;
6887 remaining = length & 0x3;
6888 length -= remaining;
6890 /* Calculate length in DWORDs */
6893 /* The device driver writes the relevant command block into the
6895 for (i = 0; i < length; i++) {
6896 for (j = 0; j < sizeof(uint32_t); j++) {
6897 *(tmp + j) = *bufptr++;
6901 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6904 for (j = 0; j < sizeof(uint32_t); j++) {
6906 *(tmp + j) = *bufptr++;
6912 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6915 return E1000_SUCCESS;
6919 /*****************************************************************************
6920 * This function writes the command header after does the checksum calculation.
6922 * returns - E1000_SUCCESS for success.
6923 ****************************************************************************/
6925 e1000_mng_write_cmd_header(struct e1000_hw * hw,
6926 struct e1000_host_mng_command_header * hdr)
6932 /* Write the whole command header structure which includes sum of
6935 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6937 sum = hdr->checksum;
6940 buffer = (uint8_t *) hdr;
6945 hdr->checksum = 0 - sum;
6948 /* The device driver writes the relevant command block into the ram area. */
6949 for (i = 0; i < length; i++) {
6950 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6951 E1000_WRITE_FLUSH(hw);
6954 return E1000_SUCCESS;
6958 /*****************************************************************************
6959 * This function indicates to ARC that a new command is pending which completes
6960 * one write operation by the driver.
6962 * returns - E1000_SUCCESS for success.
6963 ****************************************************************************/
6965 e1000_mng_write_commit(
6966 struct e1000_hw * hw)
6970 hicr = E1000_READ_REG(hw, HICR);
6971 /* Setting this bit tells the ARC that a new command is pending. */
6972 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6974 return E1000_SUCCESS;
6978 /*****************************************************************************
6979 * This function checks the mode of the firmware.
6981 * returns - TRUE when the mode is IAMT or FALSE.
6982 ****************************************************************************/
6984 e1000_check_mng_mode(
6985 struct e1000_hw *hw)
6989 fwsm = E1000_READ_REG(hw, FWSM);
6991 if((fwsm & E1000_FWSM_MODE_MASK) ==
6992 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6999 /*****************************************************************************
7000 * This function writes the dhcp info .
7001 ****************************************************************************/
7003 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7007 struct e1000_host_mng_command_header hdr;
7009 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7010 hdr.command_length = length;
7015 ret_val = e1000_mng_enable_host_if(hw);
7016 if (ret_val == E1000_SUCCESS) {
7017 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7019 if (ret_val == E1000_SUCCESS) {
7020 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7021 if (ret_val == E1000_SUCCESS)
7022 ret_val = e1000_mng_write_commit(hw);
7029 /*****************************************************************************
7030 * This function calculates the checksum.
7032 * returns - checksum of buffer contents.
7033 ****************************************************************************/
7035 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7043 for (i=0; i < length; i++)
7046 return (uint8_t) (0 - sum);
7049 /*****************************************************************************
7050 * This function checks whether tx pkt filtering needs to be enabled or not.
7052 * returns - TRUE for packet filtering or FALSE.
7053 ****************************************************************************/
7055 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7057 /* called in init as well as watchdog timer functions */
7059 int32_t ret_val, checksum;
7060 boolean_t tx_filter = FALSE;
7061 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7062 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7064 if (e1000_check_mng_mode(hw)) {
7065 ret_val = e1000_mng_enable_host_if(hw);
7066 if (ret_val == E1000_SUCCESS) {
7067 ret_val = e1000_host_if_read_cookie(hw, buffer);
7068 if (ret_val == E1000_SUCCESS) {
7069 checksum = hdr->checksum;
7071 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7072 checksum == e1000_calculate_mng_checksum((char *)buffer,
7073 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7075 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7084 hw->tx_pkt_filtering = tx_filter;
7088 /******************************************************************************
7089 * Verifies the hardware needs to allow ARPs to be processed by the host
7091 * hw - Struct containing variables accessed by shared code
7093 * returns: - TRUE/FALSE
7095 *****************************************************************************/
7097 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7100 uint32_t fwsm, factps;
7102 if (hw->asf_firmware_present) {
7103 manc = E1000_READ_REG(hw, MANC);
7105 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7106 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7108 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7109 fwsm = E1000_READ_REG(hw, FWSM);
7110 factps = E1000_READ_REG(hw, FACTPS);
7112 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7113 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7114 (factps & E1000_FACTPS_MNGCG))
7117 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7124 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7127 uint16_t mii_status_reg;
7130 /* Polarity reversal workaround for forced 10F/10H links. */
7132 /* Disable the transmitter on the PHY */
7134 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7137 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7141 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7145 /* This loop will early-out if the NO link condition has been met. */
7146 for(i = PHY_FORCE_TIME; i > 0; i--) {
7147 /* Read the MII Status Register and wait for Link Status bit
7151 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7155 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7159 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7160 msec_delay_irq(100);
7163 /* Recommended delay time after link has been lost */
7164 msec_delay_irq(1000);
7166 /* Now we will re-enable th transmitter on the PHY */
7168 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7172 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7176 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7180 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7184 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7188 /* This loop will early-out if the link condition has been met. */
7189 for(i = PHY_FORCE_TIME; i > 0; i--) {
7190 /* Read the MII Status Register and wait for Link Status bit
7194 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7198 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7202 if(mii_status_reg & MII_SR_LINK_STATUS) break;
7203 msec_delay_irq(100);
7205 return E1000_SUCCESS;
7208 /***************************************************************************
7210 * Disables PCI-Express master access.
7212 * hw: Struct containing variables accessed by shared code
7216 ***************************************************************************/
7218 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7222 DEBUGFUNC("e1000_set_pci_express_master_disable");
7224 if (hw->bus_type != e1000_bus_type_pci_express)
7227 ctrl = E1000_READ_REG(hw, CTRL);
7228 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7229 E1000_WRITE_REG(hw, CTRL, ctrl);
7233 /***************************************************************************
7235 * Enables PCI-Express master access.
7237 * hw: Struct containing variables accessed by shared code
7241 ***************************************************************************/
7243 e1000_enable_pciex_master(struct e1000_hw *hw)
7247 DEBUGFUNC("e1000_enable_pciex_master");
7249 if (hw->bus_type != e1000_bus_type_pci_express)
7252 ctrl = E1000_READ_REG(hw, CTRL);
7253 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7254 E1000_WRITE_REG(hw, CTRL, ctrl);
7258 /*******************************************************************************
7260 * Disables PCI-Express master access and verifies there are no pending requests
7262 * hw: Struct containing variables accessed by shared code
7264 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7265 * caused the master requests to be disabled.
7266 * E1000_SUCCESS master requests disabled.
7268 ******************************************************************************/
7270 e1000_disable_pciex_master(struct e1000_hw *hw)
7272 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7274 DEBUGFUNC("e1000_disable_pciex_master");
7276 if (hw->bus_type != e1000_bus_type_pci_express)
7277 return E1000_SUCCESS;
7279 e1000_set_pci_express_master_disable(hw);
7282 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7290 DEBUGOUT("Master requests are pending.\n");
7291 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7294 return E1000_SUCCESS;
7297 /*******************************************************************************
7299 * Check for EEPROM Auto Read bit done.
7301 * hw: Struct containing variables accessed by shared code
7303 * returns: - E1000_ERR_RESET if fail to reset MAC
7304 * E1000_SUCCESS at any other case.
7306 ******************************************************************************/
7308 e1000_get_auto_rd_done(struct e1000_hw *hw)
7310 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7312 DEBUGFUNC("e1000_get_auto_rd_done");
7314 switch (hw->mac_type) {
7321 case e1000_80003es2lan:
7323 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
7329 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7330 return -E1000_ERR_RESET;
7335 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7336 * Need to wait for PHY configuration completion before accessing NVM
7338 if (hw->mac_type == e1000_82573)
7341 return E1000_SUCCESS;
7344 /***************************************************************************
7345 * Checks if the PHY configuration is done
7347 * hw: Struct containing variables accessed by shared code
7349 * returns: - E1000_ERR_RESET if fail to reset MAC
7350 * E1000_SUCCESS at any other case.
7352 ***************************************************************************/
7354 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7356 int32_t timeout = PHY_CFG_TIMEOUT;
7357 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
7359 DEBUGFUNC("e1000_get_phy_cfg_done");
7361 switch (hw->mac_type) {
7365 case e1000_80003es2lan:
7366 /* Separate *_CFG_DONE_* bit for each port */
7367 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
7368 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7373 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
7381 DEBUGOUT("MNG configuration cycle has not completed.\n");
7382 return -E1000_ERR_RESET;
7387 return E1000_SUCCESS;
7390 /***************************************************************************
7392 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
7393 * adapter or Eeprom access.
7395 * hw: Struct containing variables accessed by shared code
7397 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
7398 * E1000_SUCCESS at any other case.
7400 ***************************************************************************/
7402 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7407 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7409 if(!hw->eeprom_semaphore_present)
7410 return E1000_SUCCESS;
7412 if (hw->mac_type == e1000_80003es2lan) {
7413 /* Get the SW semaphore. */
7414 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7415 return -E1000_ERR_EEPROM;
7418 /* Get the FW semaphore. */
7419 timeout = hw->eeprom.word_size + 1;
7421 swsm = E1000_READ_REG(hw, SWSM);
7422 swsm |= E1000_SWSM_SWESMBI;
7423 E1000_WRITE_REG(hw, SWSM, swsm);
7424 /* if we managed to set the bit we got the semaphore. */
7425 swsm = E1000_READ_REG(hw, SWSM);
7426 if(swsm & E1000_SWSM_SWESMBI)
7434 /* Release semaphores */
7435 e1000_put_hw_eeprom_semaphore(hw);
7436 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7437 return -E1000_ERR_EEPROM;
7440 return E1000_SUCCESS;
7443 /***************************************************************************
7444 * This function clears HW semaphore bits.
7446 * hw: Struct containing variables accessed by shared code
7450 ***************************************************************************/
7452 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
7456 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
7458 if(!hw->eeprom_semaphore_present)
7461 swsm = E1000_READ_REG(hw, SWSM);
7462 if (hw->mac_type == e1000_80003es2lan) {
7463 /* Release both semaphores. */
7464 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
7466 swsm &= ~(E1000_SWSM_SWESMBI);
7467 E1000_WRITE_REG(hw, SWSM, swsm);
7470 /***************************************************************************
7472 * Obtaining software semaphore bit (SMBI) before resetting PHY.
7474 * hw: Struct containing variables accessed by shared code
7476 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
7477 * E1000_SUCCESS at any other case.
7479 ***************************************************************************/
7481 e1000_get_software_semaphore(struct e1000_hw *hw)
7483 int32_t timeout = hw->eeprom.word_size + 1;
7486 DEBUGFUNC("e1000_get_software_semaphore");
7488 if (hw->mac_type != e1000_80003es2lan)
7489 return E1000_SUCCESS;
7492 swsm = E1000_READ_REG(hw, SWSM);
7493 /* If SMBI bit cleared, it is now set and we hold the semaphore */
7494 if(!(swsm & E1000_SWSM_SMBI))
7501 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
7502 return -E1000_ERR_RESET;
7505 return E1000_SUCCESS;
7508 /***************************************************************************
7510 * Release semaphore bit (SMBI).
7512 * hw: Struct containing variables accessed by shared code
7514 ***************************************************************************/
7516 e1000_release_software_semaphore(struct e1000_hw *hw)
7520 DEBUGFUNC("e1000_release_software_semaphore");
7522 if (hw->mac_type != e1000_80003es2lan)
7525 swsm = E1000_READ_REG(hw, SWSM);
7526 /* Release the SW semaphores.*/
7527 swsm &= ~E1000_SWSM_SMBI;
7528 E1000_WRITE_REG(hw, SWSM, swsm);
7531 /******************************************************************************
7532 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
7533 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
7534 * the caller to figure out how to deal with it.
7536 * hw - Struct containing variables accessed by shared code
7538 * returns: - E1000_BLK_PHY_RESET
7541 *****************************************************************************/
7543 e1000_check_phy_reset_block(struct e1000_hw *hw)
7547 if (hw->mac_type > e1000_82547_rev_2)
7548 manc = E1000_READ_REG(hw, MANC);
7549 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
7550 E1000_BLK_PHY_RESET : E1000_SUCCESS;
7554 e1000_arc_subsystem_valid(struct e1000_hw *hw)
7558 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
7559 * may not be provided a DMA clock when no manageability features are
7560 * enabled. We do not want to perform any reads/writes to these registers
7561 * if this is the case. We read FWSM to determine the manageability mode.
7563 switch (hw->mac_type) {
7567 case e1000_80003es2lan:
7568 fwsm = E1000_READ_REG(hw, FWSM);
7569 if((fwsm & E1000_FWSM_MODE_MASK) != 0)