1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41 static void e1000_release_software_semaphore(struct e1000_hw *hw);
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44 static int32_t e1000_check_downshift(struct e1000_hw *hw);
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
65 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
66 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
67 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
68 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
69 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
70 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
71 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
73 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
75 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
76 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
77 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
78 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
79 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
81 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
82 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
83 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
84 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static void e1000_release_software_flag(struct e1000_hw *hw);
86 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
87 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
89 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
90 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
91 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
92 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
93 static void e1000_phy_init_script(struct e1000_hw *hw);
94 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
95 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
96 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
97 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
98 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
99 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
100 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
104 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
105 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
106 uint16_t words, uint16_t *data);
107 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
108 uint16_t offset, uint16_t words,
110 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
111 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
112 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
120 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
121 static void e1000_release_eeprom(struct e1000_hw *hw);
122 static void e1000_standby_eeprom(struct e1000_hw *hw);
123 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
124 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
125 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
126 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
127 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
128 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132 /* IGP cable length table */
134 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
135 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
136 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
137 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
138 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
139 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
140 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
141 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
142 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
145 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
146 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
147 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
148 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
149 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
150 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
151 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
152 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
153 104, 109, 114, 118, 121, 124};
155 /******************************************************************************
156 * Set the phy type member in the hw struct.
158 * hw - Struct containing variables accessed by shared code
159 *****************************************************************************/
161 e1000_set_phy_type(struct e1000_hw *hw)
163 DEBUGFUNC("e1000_set_phy_type");
165 if (hw->mac_type == e1000_undefined)
166 return -E1000_ERR_PHY_TYPE;
168 switch (hw->phy_id) {
169 case M88E1000_E_PHY_ID:
170 case M88E1000_I_PHY_ID:
171 case M88E1011_I_PHY_ID:
172 case M88E1111_I_PHY_ID:
173 hw->phy_type = e1000_phy_m88;
175 case IGP01E1000_I_PHY_ID:
176 if (hw->mac_type == e1000_82541 ||
177 hw->mac_type == e1000_82541_rev_2 ||
178 hw->mac_type == e1000_82547 ||
179 hw->mac_type == e1000_82547_rev_2) {
180 hw->phy_type = e1000_phy_igp;
183 case IGP03E1000_E_PHY_ID:
184 hw->phy_type = e1000_phy_igp_3;
187 case IFE_PLUS_E_PHY_ID:
189 hw->phy_type = e1000_phy_ife;
191 case GG82563_E_PHY_ID:
192 if (hw->mac_type == e1000_80003es2lan) {
193 hw->phy_type = e1000_phy_gg82563;
198 /* Should never have loaded on this device */
199 hw->phy_type = e1000_phy_undefined;
200 return -E1000_ERR_PHY_TYPE;
203 return E1000_SUCCESS;
206 /******************************************************************************
207 * IGP phy init script - initializes the GbE PHY
209 * hw - Struct containing variables accessed by shared code
210 *****************************************************************************/
212 e1000_phy_init_script(struct e1000_hw *hw)
215 uint16_t phy_saved_data;
217 DEBUGFUNC("e1000_phy_init_script");
219 if (hw->phy_init_script) {
222 /* Save off the current value of register 0x2F5B to be restored at
223 * the end of this routine. */
224 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226 /* Disabled the PHY transmitter */
227 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
231 e1000_write_phy_reg(hw,0x0000,0x0140);
235 switch (hw->mac_type) {
238 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254 e1000_write_phy_reg(hw, 0x2010, 0x0008);
257 case e1000_82541_rev_2:
258 case e1000_82547_rev_2:
259 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
265 e1000_write_phy_reg(hw, 0x0000, 0x3300);
269 /* Now enable the transmitter */
270 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272 if (hw->mac_type == e1000_82547) {
273 uint16_t fused, fine, coarse;
275 /* Move to analog registers page */
276 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
279 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
282 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
285 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
286 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
287 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
288 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
291 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
292 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
296 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
302 /******************************************************************************
303 * Set the mac type member in the hw struct.
305 * hw - Struct containing variables accessed by shared code
306 *****************************************************************************/
308 e1000_set_mac_type(struct e1000_hw *hw)
310 DEBUGFUNC("e1000_set_mac_type");
312 switch (hw->device_id) {
313 case E1000_DEV_ID_82542:
314 switch (hw->revision_id) {
315 case E1000_82542_2_0_REV_ID:
316 hw->mac_type = e1000_82542_rev2_0;
318 case E1000_82542_2_1_REV_ID:
319 hw->mac_type = e1000_82542_rev2_1;
322 /* Invalid 82542 revision ID */
323 return -E1000_ERR_MAC_TYPE;
326 case E1000_DEV_ID_82543GC_FIBER:
327 case E1000_DEV_ID_82543GC_COPPER:
328 hw->mac_type = e1000_82543;
330 case E1000_DEV_ID_82544EI_COPPER:
331 case E1000_DEV_ID_82544EI_FIBER:
332 case E1000_DEV_ID_82544GC_COPPER:
333 case E1000_DEV_ID_82544GC_LOM:
334 hw->mac_type = e1000_82544;
336 case E1000_DEV_ID_82540EM:
337 case E1000_DEV_ID_82540EM_LOM:
338 case E1000_DEV_ID_82540EP:
339 case E1000_DEV_ID_82540EP_LOM:
340 case E1000_DEV_ID_82540EP_LP:
341 hw->mac_type = e1000_82540;
343 case E1000_DEV_ID_82545EM_COPPER:
344 case E1000_DEV_ID_82545EM_FIBER:
345 hw->mac_type = e1000_82545;
347 case E1000_DEV_ID_82545GM_COPPER:
348 case E1000_DEV_ID_82545GM_FIBER:
349 case E1000_DEV_ID_82545GM_SERDES:
350 hw->mac_type = e1000_82545_rev_3;
352 case E1000_DEV_ID_82546EB_COPPER:
353 case E1000_DEV_ID_82546EB_FIBER:
354 case E1000_DEV_ID_82546EB_QUAD_COPPER:
355 hw->mac_type = e1000_82546;
357 case E1000_DEV_ID_82546GB_COPPER:
358 case E1000_DEV_ID_82546GB_FIBER:
359 case E1000_DEV_ID_82546GB_SERDES:
360 case E1000_DEV_ID_82546GB_PCIE:
361 case E1000_DEV_ID_82546GB_QUAD_COPPER:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
363 hw->mac_type = e1000_82546_rev_3;
365 case E1000_DEV_ID_82541EI:
366 case E1000_DEV_ID_82541EI_MOBILE:
367 case E1000_DEV_ID_82541ER_LOM:
368 hw->mac_type = e1000_82541;
370 case E1000_DEV_ID_82541ER:
371 case E1000_DEV_ID_82541GI:
372 case E1000_DEV_ID_82541GI_LF:
373 case E1000_DEV_ID_82541GI_MOBILE:
374 hw->mac_type = e1000_82541_rev_2;
376 case E1000_DEV_ID_82547EI:
377 case E1000_DEV_ID_82547EI_MOBILE:
378 hw->mac_type = e1000_82547;
380 case E1000_DEV_ID_82547GI:
381 hw->mac_type = e1000_82547_rev_2;
383 case E1000_DEV_ID_82571EB_COPPER:
384 case E1000_DEV_ID_82571EB_FIBER:
385 case E1000_DEV_ID_82571EB_SERDES:
386 case E1000_DEV_ID_82571EB_QUAD_COPPER:
387 hw->mac_type = e1000_82571;
389 case E1000_DEV_ID_82572EI_COPPER:
390 case E1000_DEV_ID_82572EI_FIBER:
391 case E1000_DEV_ID_82572EI_SERDES:
392 case E1000_DEV_ID_82572EI:
393 hw->mac_type = e1000_82572;
395 case E1000_DEV_ID_82573E:
396 case E1000_DEV_ID_82573E_IAMT:
397 case E1000_DEV_ID_82573L:
398 hw->mac_type = e1000_82573;
400 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
401 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
402 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
403 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
404 hw->mac_type = e1000_80003es2lan;
406 case E1000_DEV_ID_ICH8_IGP_M_AMT:
407 case E1000_DEV_ID_ICH8_IGP_AMT:
408 case E1000_DEV_ID_ICH8_IGP_C:
409 case E1000_DEV_ID_ICH8_IFE:
410 case E1000_DEV_ID_ICH8_IGP_M:
411 hw->mac_type = e1000_ich8lan;
414 /* Should never have loaded on this device */
415 return -E1000_ERR_MAC_TYPE;
418 switch (hw->mac_type) {
420 hw->swfwhw_semaphore_present = TRUE;
421 hw->asf_firmware_present = TRUE;
423 case e1000_80003es2lan:
424 hw->swfw_sync_present = TRUE;
429 hw->eeprom_semaphore_present = TRUE;
433 case e1000_82541_rev_2:
434 case e1000_82547_rev_2:
435 hw->asf_firmware_present = TRUE;
441 return E1000_SUCCESS;
444 /*****************************************************************************
445 * Set media type and TBI compatibility.
447 * hw - Struct containing variables accessed by shared code
448 * **************************************************************************/
450 e1000_set_media_type(struct e1000_hw *hw)
454 DEBUGFUNC("e1000_set_media_type");
456 if (hw->mac_type != e1000_82543) {
457 /* tbi_compatibility is only valid on 82543 */
458 hw->tbi_compatibility_en = FALSE;
461 switch (hw->device_id) {
462 case E1000_DEV_ID_82545GM_SERDES:
463 case E1000_DEV_ID_82546GB_SERDES:
464 case E1000_DEV_ID_82571EB_SERDES:
465 case E1000_DEV_ID_82572EI_SERDES:
466 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
467 hw->media_type = e1000_media_type_internal_serdes;
470 switch (hw->mac_type) {
471 case e1000_82542_rev2_0:
472 case e1000_82542_rev2_1:
473 hw->media_type = e1000_media_type_fiber;
477 /* The STATUS_TBIMODE bit is reserved or reused for the this
480 hw->media_type = e1000_media_type_copper;
483 status = E1000_READ_REG(hw, STATUS);
484 if (status & E1000_STATUS_TBIMODE) {
485 hw->media_type = e1000_media_type_fiber;
486 /* tbi_compatibility not valid on fiber */
487 hw->tbi_compatibility_en = FALSE;
489 hw->media_type = e1000_media_type_copper;
496 /******************************************************************************
497 * Reset the transmit and receive units; mask and clear all interrupts.
499 * hw - Struct containing variables accessed by shared code
500 *****************************************************************************/
502 e1000_reset_hw(struct e1000_hw *hw)
510 uint32_t extcnf_ctrl;
513 DEBUGFUNC("e1000_reset_hw");
515 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
516 if (hw->mac_type == e1000_82542_rev2_0) {
517 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
518 e1000_pci_clear_mwi(hw);
521 if (hw->bus_type == e1000_bus_type_pci_express) {
522 /* Prevent the PCI-E bus from sticking if there is no TLP connection
523 * on the last TLP read/write transaction when MAC is reset.
525 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
526 DEBUGOUT("PCI-E Master disable polling has failed.\n");
530 /* Clear interrupt mask to stop board from generating interrupts */
531 DEBUGOUT("Masking off all interrupts\n");
532 E1000_WRITE_REG(hw, IMC, 0xffffffff);
534 /* Disable the Transmit and Receive units. Then delay to allow
535 * any pending transactions to complete before we hit the MAC with
538 E1000_WRITE_REG(hw, RCTL, 0);
539 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
540 E1000_WRITE_FLUSH(hw);
542 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
543 hw->tbi_compatibility_on = FALSE;
545 /* Delay to allow any outstanding PCI transactions to complete before
546 * resetting the device
550 ctrl = E1000_READ_REG(hw, CTRL);
552 /* Must reset the PHY before resetting the MAC */
553 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
558 /* Must acquire the MDIO ownership before MAC reset.
559 * Ownership defaults to firmware after a reset. */
560 if (hw->mac_type == e1000_82573) {
563 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
564 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
567 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
568 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
570 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
573 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
580 /* Workaround for ICH8 bit corruption issue in FIFO memory */
581 if (hw->mac_type == e1000_ich8lan) {
582 /* Set Tx and Rx buffer allocation to 8k apiece. */
583 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
584 /* Set Packet Buffer Size to 16k. */
585 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
588 /* Issue a global reset to the MAC. This will reset the chip's
589 * transmit, receive, DMA, and link units. It will not effect
590 * the current PCI configuration. The global reset bit is self-
591 * clearing, and should clear within a microsecond.
593 DEBUGOUT("Issuing a global reset to MAC\n");
595 switch (hw->mac_type) {
601 case e1000_82541_rev_2:
602 /* These controllers can't ack the 64-bit write when issuing the
603 * reset, so use IO-mapping as a workaround to issue the reset */
604 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
606 case e1000_82545_rev_3:
607 case e1000_82546_rev_3:
608 /* Reset is performed on a shadow of the control register */
609 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
612 if (!hw->phy_reset_disable &&
613 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
614 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
615 * at the same time to make sure the interface between
616 * MAC and the external PHY is reset.
618 ctrl |= E1000_CTRL_PHY_RST;
621 e1000_get_software_flag(hw);
622 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
626 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
630 /* After MAC reset, force reload of EEPROM to restore power-on settings to
631 * device. Later controllers reload the EEPROM automatically, so just wait
632 * for reload to complete.
634 switch (hw->mac_type) {
635 case e1000_82542_rev2_0:
636 case e1000_82542_rev2_1:
639 /* Wait for reset to complete */
641 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
642 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
643 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
644 E1000_WRITE_FLUSH(hw);
645 /* Wait for EEPROM reload */
649 case e1000_82541_rev_2:
651 case e1000_82547_rev_2:
652 /* Wait for EEPROM reload */
656 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
658 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
659 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
660 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
661 E1000_WRITE_FLUSH(hw);
667 case e1000_80003es2lan:
668 ret_val = e1000_get_auto_rd_done(hw);
670 /* We don't want to continue accessing MAC registers. */
674 /* Wait for EEPROM reload (it happens automatically) */
679 /* Disable HW ARPs on ASF enabled adapters */
680 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
681 manc = E1000_READ_REG(hw, MANC);
682 manc &= ~(E1000_MANC_ARP_EN);
683 E1000_WRITE_REG(hw, MANC, manc);
686 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
687 e1000_phy_init_script(hw);
689 /* Configure activity LED after PHY reset */
690 led_ctrl = E1000_READ_REG(hw, LEDCTL);
691 led_ctrl &= IGP_ACTIVITY_LED_MASK;
692 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
693 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
696 /* Clear interrupt mask to stop board from generating interrupts */
697 DEBUGOUT("Masking off all interrupts\n");
698 E1000_WRITE_REG(hw, IMC, 0xffffffff);
700 /* Clear any pending interrupt events. */
701 icr = E1000_READ_REG(hw, ICR);
703 /* If MWI was previously enabled, reenable it. */
704 if (hw->mac_type == e1000_82542_rev2_0) {
705 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
706 e1000_pci_set_mwi(hw);
709 if (hw->mac_type == e1000_ich8lan) {
710 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
711 kab |= E1000_KABGTXD_BGSQLBIAS;
712 E1000_WRITE_REG(hw, KABGTXD, kab);
715 return E1000_SUCCESS;
718 /******************************************************************************
719 * Performs basic configuration of the adapter.
721 * hw - Struct containing variables accessed by shared code
723 * Assumes that the controller has previously been reset and is in a
724 * post-reset uninitialized state. Initializes the receive address registers,
725 * multicast table, and VLAN filter table. Calls routines to setup link
726 * configuration and flow control settings. Clears all on-chip counters. Leaves
727 * the transmit and receive units disabled and uninitialized.
728 *****************************************************************************/
730 e1000_init_hw(struct e1000_hw *hw)
735 uint16_t pcix_cmd_word;
736 uint16_t pcix_stat_hi_word;
743 DEBUGFUNC("e1000_init_hw");
745 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
746 if (hw->mac_type == e1000_ich8lan) {
747 reg_data = E1000_READ_REG(hw, TARC0);
748 reg_data |= 0x30000000;
749 E1000_WRITE_REG(hw, TARC0, reg_data);
751 reg_data = E1000_READ_REG(hw, STATUS);
752 reg_data &= ~0x80000000;
753 E1000_WRITE_REG(hw, STATUS, reg_data);
756 /* Initialize Identification LED */
757 ret_val = e1000_id_led_init(hw);
759 DEBUGOUT("Error Initializing Identification LED\n");
763 /* Set the media type and TBI compatibility */
764 e1000_set_media_type(hw);
766 /* Disabling VLAN filtering. */
767 DEBUGOUT("Initializing the IEEE VLAN\n");
768 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
769 if (hw->mac_type != e1000_ich8lan) {
770 if (hw->mac_type < e1000_82545_rev_3)
771 E1000_WRITE_REG(hw, VET, 0);
772 e1000_clear_vfta(hw);
775 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
776 if (hw->mac_type == e1000_82542_rev2_0) {
777 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
778 e1000_pci_clear_mwi(hw);
779 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
780 E1000_WRITE_FLUSH(hw);
784 /* Setup the receive address. This involves initializing all of the Receive
785 * Address Registers (RARs 0 - 15).
787 e1000_init_rx_addrs(hw);
789 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
790 if (hw->mac_type == e1000_82542_rev2_0) {
791 E1000_WRITE_REG(hw, RCTL, 0);
792 E1000_WRITE_FLUSH(hw);
794 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
795 e1000_pci_set_mwi(hw);
798 /* Zero out the Multicast HASH table */
799 DEBUGOUT("Zeroing the MTA\n");
800 mta_size = E1000_MC_TBL_SIZE;
801 if (hw->mac_type == e1000_ich8lan)
802 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
803 for (i = 0; i < mta_size; i++) {
804 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
805 /* use write flush to prevent Memory Write Block (MWB) from
806 * occuring when accessing our register space */
807 E1000_WRITE_FLUSH(hw);
810 /* Set the PCI priority bit correctly in the CTRL register. This
811 * determines if the adapter gives priority to receives, or if it
812 * gives equal priority to transmits and receives. Valid only on
813 * 82542 and 82543 silicon.
815 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
816 ctrl = E1000_READ_REG(hw, CTRL);
817 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
820 switch (hw->mac_type) {
821 case e1000_82545_rev_3:
822 case e1000_82546_rev_3:
825 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
826 if (hw->bus_type == e1000_bus_type_pcix) {
827 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
828 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
830 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
831 PCIX_COMMAND_MMRBC_SHIFT;
832 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
833 PCIX_STATUS_HI_MMRBC_SHIFT;
834 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
835 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
836 if (cmd_mmrbc > stat_mmrbc) {
837 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
838 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
839 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
846 /* More time needed for PHY to initialize */
847 if (hw->mac_type == e1000_ich8lan)
850 /* Call a subroutine to configure the link and setup flow control. */
851 ret_val = e1000_setup_link(hw);
853 /* Set the transmit descriptor write-back policy */
854 if (hw->mac_type > e1000_82544) {
855 ctrl = E1000_READ_REG(hw, TXDCTL);
856 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
857 switch (hw->mac_type) {
864 case e1000_80003es2lan:
865 ctrl |= E1000_TXDCTL_COUNT_DESC;
868 E1000_WRITE_REG(hw, TXDCTL, ctrl);
871 if (hw->mac_type == e1000_82573) {
872 e1000_enable_tx_pkt_filtering(hw);
875 switch (hw->mac_type) {
878 case e1000_80003es2lan:
879 /* Enable retransmit on late collisions */
880 reg_data = E1000_READ_REG(hw, TCTL);
881 reg_data |= E1000_TCTL_RTLC;
882 E1000_WRITE_REG(hw, TCTL, reg_data);
884 /* Configure Gigabit Carry Extend Padding */
885 reg_data = E1000_READ_REG(hw, TCTL_EXT);
886 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
887 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
888 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
890 /* Configure Transmit Inter-Packet Gap */
891 reg_data = E1000_READ_REG(hw, TIPG);
892 reg_data &= ~E1000_TIPG_IPGT_MASK;
893 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
894 E1000_WRITE_REG(hw, TIPG, reg_data);
896 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
897 reg_data &= ~0x00100000;
898 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
903 ctrl = E1000_READ_REG(hw, TXDCTL1);
904 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
905 if (hw->mac_type >= e1000_82571)
906 ctrl |= E1000_TXDCTL_COUNT_DESC;
907 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
912 if (hw->mac_type == e1000_82573) {
913 uint32_t gcr = E1000_READ_REG(hw, GCR);
914 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
915 E1000_WRITE_REG(hw, GCR, gcr);
918 /* Clear all of the statistics registers (clear on read). It is
919 * important that we do this after we have tried to establish link
920 * because the symbol error count will increment wildly if there
923 e1000_clear_hw_cntrs(hw);
925 /* ICH8 No-snoop bits are opposite polarity.
926 * Set to snoop by default after reset. */
927 if (hw->mac_type == e1000_ich8lan)
928 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
930 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
931 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
932 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
933 /* Relaxed ordering must be disabled to avoid a parity
934 * error crash in a PCI slot. */
935 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
936 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
942 /******************************************************************************
943 * Adjust SERDES output amplitude based on EEPROM setting.
945 * hw - Struct containing variables accessed by shared code.
946 *****************************************************************************/
948 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
950 uint16_t eeprom_data;
953 DEBUGFUNC("e1000_adjust_serdes_amplitude");
955 if (hw->media_type != e1000_media_type_internal_serdes)
956 return E1000_SUCCESS;
958 switch (hw->mac_type) {
959 case e1000_82545_rev_3:
960 case e1000_82546_rev_3:
963 return E1000_SUCCESS;
966 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
971 if (eeprom_data != EEPROM_RESERVED_WORD) {
972 /* Adjust SERDES output amplitude only. */
973 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
974 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
979 return E1000_SUCCESS;
982 /******************************************************************************
983 * Configures flow control and link settings.
985 * hw - Struct containing variables accessed by shared code
987 * Determines which flow control settings to use. Calls the apropriate media-
988 * specific link configuration function. Configures the flow control settings.
989 * Assuming the adapter has a valid link partner, a valid link should be
990 * established. Assumes the hardware has previously been reset and the
991 * transmitter and receiver are not enabled.
992 *****************************************************************************/
994 e1000_setup_link(struct e1000_hw *hw)
998 uint16_t eeprom_data;
1000 DEBUGFUNC("e1000_setup_link");
1002 /* In the case of the phy reset being blocked, we already have a link.
1003 * We do not have to set it up again. */
1004 if (e1000_check_phy_reset_block(hw))
1005 return E1000_SUCCESS;
1007 /* Read and store word 0x0F of the EEPROM. This word contains bits
1008 * that determine the hardware's default PAUSE (flow control) mode,
1009 * a bit that determines whether the HW defaults to enabling or
1010 * disabling auto-negotiation, and the direction of the
1011 * SW defined pins. If there is no SW over-ride of the flow
1012 * control setting, then the variable hw->fc will
1013 * be initialized based on a value in the EEPROM.
1015 if (hw->fc == E1000_FC_DEFAULT) {
1016 switch (hw->mac_type) {
1019 hw->fc = E1000_FC_FULL;
1022 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1025 DEBUGOUT("EEPROM Read Error\n");
1026 return -E1000_ERR_EEPROM;
1028 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1029 hw->fc = E1000_FC_NONE;
1030 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1031 EEPROM_WORD0F_ASM_DIR)
1032 hw->fc = E1000_FC_TX_PAUSE;
1034 hw->fc = E1000_FC_FULL;
1039 /* We want to save off the original Flow Control configuration just
1040 * in case we get disconnected and then reconnected into a different
1041 * hub or switch with different Flow Control capabilities.
1043 if (hw->mac_type == e1000_82542_rev2_0)
1044 hw->fc &= (~E1000_FC_TX_PAUSE);
1046 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1047 hw->fc &= (~E1000_FC_RX_PAUSE);
1049 hw->original_fc = hw->fc;
1051 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1053 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1054 * polarity value for the SW controlled pins, and setup the
1055 * Extended Device Control reg with that info.
1056 * This is needed because one of the SW controlled pins is used for
1057 * signal detection. So this should be done before e1000_setup_pcs_link()
1058 * or e1000_phy_setup() is called.
1060 if (hw->mac_type == e1000_82543) {
1061 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1064 DEBUGOUT("EEPROM Read Error\n");
1065 return -E1000_ERR_EEPROM;
1067 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1069 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1072 /* Call the necessary subroutine to configure the link. */
1073 ret_val = (hw->media_type == e1000_media_type_copper) ?
1074 e1000_setup_copper_link(hw) :
1075 e1000_setup_fiber_serdes_link(hw);
1077 /* Initialize the flow control address, type, and PAUSE timer
1078 * registers to their default values. This is done even if flow
1079 * control is disabled, because it does not hurt anything to
1080 * initialize these registers.
1082 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1084 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1085 if (hw->mac_type != e1000_ich8lan) {
1086 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1087 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1088 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1091 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1093 /* Set the flow control receive threshold registers. Normally,
1094 * these registers will be set to a default threshold that may be
1095 * adjusted later by the driver's runtime code. However, if the
1096 * ability to transmit pause frames in not enabled, then these
1097 * registers will be set to 0.
1099 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1100 E1000_WRITE_REG(hw, FCRTL, 0);
1101 E1000_WRITE_REG(hw, FCRTH, 0);
1103 /* We need to set up the Receive Threshold high and low water marks
1104 * as well as (optionally) enabling the transmission of XON frames.
1106 if (hw->fc_send_xon) {
1107 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1108 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1110 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1111 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1117 /******************************************************************************
1118 * Sets up link for a fiber based or serdes based adapter
1120 * hw - Struct containing variables accessed by shared code
1122 * Manipulates Physical Coding Sublayer functions in order to configure
1123 * link. Assumes the hardware has been previously reset and the transmitter
1124 * and receiver are not enabled.
1125 *****************************************************************************/
1127 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1133 uint32_t signal = 0;
1136 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1138 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1139 * until explicitly turned off or a power cycle is performed. A read to
1140 * the register does not indicate its status. Therefore, we ensure
1141 * loopback mode is disabled during initialization.
1143 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1144 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1146 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1147 * set when the optics detect a signal. On older adapters, it will be
1148 * cleared when there is a signal. This applies to fiber media only.
1149 * If we're on serdes media, adjust the output amplitude to value set in
1152 ctrl = E1000_READ_REG(hw, CTRL);
1153 if (hw->media_type == e1000_media_type_fiber)
1154 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1156 ret_val = e1000_adjust_serdes_amplitude(hw);
1160 /* Take the link out of reset */
1161 ctrl &= ~(E1000_CTRL_LRST);
1163 /* Adjust VCO speed to improve BER performance */
1164 ret_val = e1000_set_vco_speed(hw);
1168 e1000_config_collision_dist(hw);
1170 /* Check for a software override of the flow control settings, and setup
1171 * the device accordingly. If auto-negotiation is enabled, then software
1172 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1173 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1174 * auto-negotiation is disabled, then software will have to manually
1175 * configure the two flow control enable bits in the CTRL register.
1177 * The possible values of the "fc" parameter are:
1178 * 0: Flow control is completely disabled
1179 * 1: Rx flow control is enabled (we can receive pause frames, but
1180 * not send pause frames).
1181 * 2: Tx flow control is enabled (we can send pause frames but we do
1182 * not support receiving pause frames).
1183 * 3: Both Rx and TX flow control (symmetric) are enabled.
1187 /* Flow control is completely disabled by a software over-ride. */
1188 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1190 case E1000_FC_RX_PAUSE:
1191 /* RX Flow control is enabled and TX Flow control is disabled by a
1192 * software over-ride. Since there really isn't a way to advertise
1193 * that we are capable of RX Pause ONLY, we will advertise that we
1194 * support both symmetric and asymmetric RX PAUSE. Later, we will
1195 * disable the adapter's ability to send PAUSE frames.
1197 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1199 case E1000_FC_TX_PAUSE:
1200 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1201 * software over-ride.
1203 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1206 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1207 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1210 DEBUGOUT("Flow control param set incorrectly\n");
1211 return -E1000_ERR_CONFIG;
1215 /* Since auto-negotiation is enabled, take the link out of reset (the link
1216 * will be in reset, because we previously reset the chip). This will
1217 * restart auto-negotiation. If auto-neogtiation is successful then the
1218 * link-up status bit will be set and the flow control enable bits (RFCE
1219 * and TFCE) will be set according to their negotiated value.
1221 DEBUGOUT("Auto-negotiation enabled\n");
1223 E1000_WRITE_REG(hw, TXCW, txcw);
1224 E1000_WRITE_REG(hw, CTRL, ctrl);
1225 E1000_WRITE_FLUSH(hw);
1230 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1231 * indication in the Device Status Register. Time-out if a link isn't
1232 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1233 * less than 500 milliseconds even if the other end is doing it in SW).
1234 * For internal serdes, we just assume a signal is present, then poll.
1236 if (hw->media_type == e1000_media_type_internal_serdes ||
1237 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1238 DEBUGOUT("Looking for Link\n");
1239 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1241 status = E1000_READ_REG(hw, STATUS);
1242 if (status & E1000_STATUS_LU) break;
1244 if (i == (LINK_UP_TIMEOUT / 10)) {
1245 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1246 hw->autoneg_failed = 1;
1247 /* AutoNeg failed to achieve a link, so we'll call
1248 * e1000_check_for_link. This routine will force the link up if
1249 * we detect a signal. This will allow us to communicate with
1250 * non-autonegotiating link partners.
1252 ret_val = e1000_check_for_link(hw);
1254 DEBUGOUT("Error while checking for link\n");
1257 hw->autoneg_failed = 0;
1259 hw->autoneg_failed = 0;
1260 DEBUGOUT("Valid Link Found\n");
1263 DEBUGOUT("No Signal Detected\n");
1265 return E1000_SUCCESS;
1268 /******************************************************************************
1269 * Make sure we have a valid PHY and change PHY mode before link setup.
1271 * hw - Struct containing variables accessed by shared code
1272 ******************************************************************************/
1274 e1000_copper_link_preconfig(struct e1000_hw *hw)
1280 DEBUGFUNC("e1000_copper_link_preconfig");
1282 ctrl = E1000_READ_REG(hw, CTRL);
1283 /* With 82543, we need to force speed and duplex on the MAC equal to what
1284 * the PHY speed and duplex configuration is. In addition, we need to
1285 * perform a hardware reset on the PHY to take it out of reset.
1287 if (hw->mac_type > e1000_82543) {
1288 ctrl |= E1000_CTRL_SLU;
1289 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1290 E1000_WRITE_REG(hw, CTRL, ctrl);
1292 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1293 E1000_WRITE_REG(hw, CTRL, ctrl);
1294 ret_val = e1000_phy_hw_reset(hw);
1299 /* Make sure we have a valid PHY */
1300 ret_val = e1000_detect_gig_phy(hw);
1302 DEBUGOUT("Error, did not detect valid phy.\n");
1305 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1307 /* Set PHY to class A mode (if necessary) */
1308 ret_val = e1000_set_phy_mode(hw);
1312 if ((hw->mac_type == e1000_82545_rev_3) ||
1313 (hw->mac_type == e1000_82546_rev_3)) {
1314 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1315 phy_data |= 0x00000008;
1316 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1319 if (hw->mac_type <= e1000_82543 ||
1320 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1321 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1322 hw->phy_reset_disable = FALSE;
1324 return E1000_SUCCESS;
1328 /********************************************************************
1329 * Copper link setup for e1000_phy_igp series.
1331 * hw - Struct containing variables accessed by shared code
1332 *********************************************************************/
1334 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1340 DEBUGFUNC("e1000_copper_link_igp_setup");
1342 if (hw->phy_reset_disable)
1343 return E1000_SUCCESS;
1345 ret_val = e1000_phy_reset(hw);
1347 DEBUGOUT("Error Resetting the PHY\n");
1351 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1353 if (hw->mac_type != e1000_ich8lan) {
1354 /* Configure activity LED after PHY reset */
1355 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1356 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1357 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1358 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1361 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1362 if (hw->phy_type == e1000_phy_igp) {
1363 /* disable lplu d3 during driver init */
1364 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1366 DEBUGOUT("Error Disabling LPLU D3\n");
1371 /* disable lplu d0 during driver init */
1372 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1374 DEBUGOUT("Error Disabling LPLU D0\n");
1377 /* Configure mdi-mdix settings */
1378 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1382 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1383 hw->dsp_config_state = e1000_dsp_config_disabled;
1384 /* Force MDI for earlier revs of the IGP PHY */
1385 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1389 hw->dsp_config_state = e1000_dsp_config_enabled;
1390 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1394 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1397 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1401 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1405 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1409 /* set auto-master slave resolution settings */
1411 e1000_ms_type phy_ms_setting = hw->master_slave;
1413 if (hw->ffe_config_state == e1000_ffe_config_active)
1414 hw->ffe_config_state = e1000_ffe_config_enabled;
1416 if (hw->dsp_config_state == e1000_dsp_config_activated)
1417 hw->dsp_config_state = e1000_dsp_config_enabled;
1419 /* when autonegotiation advertisment is only 1000Mbps then we
1420 * should disable SmartSpeed and enable Auto MasterSlave
1421 * resolution as hardware default. */
1422 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1423 /* Disable SmartSpeed */
1424 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1428 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1429 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1433 /* Set auto Master/Slave resolution process */
1434 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1437 phy_data &= ~CR_1000T_MS_ENABLE;
1438 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1443 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1447 /* load defaults for future use */
1448 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1449 ((phy_data & CR_1000T_MS_VALUE) ?
1450 e1000_ms_force_master :
1451 e1000_ms_force_slave) :
1454 switch (phy_ms_setting) {
1455 case e1000_ms_force_master:
1456 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1458 case e1000_ms_force_slave:
1459 phy_data |= CR_1000T_MS_ENABLE;
1460 phy_data &= ~(CR_1000T_MS_VALUE);
1463 phy_data &= ~CR_1000T_MS_ENABLE;
1467 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1472 return E1000_SUCCESS;
1475 /********************************************************************
1476 * Copper link setup for e1000_phy_gg82563 series.
1478 * hw - Struct containing variables accessed by shared code
1479 *********************************************************************/
1481 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1487 DEBUGFUNC("e1000_copper_link_ggp_setup");
1489 if (!hw->phy_reset_disable) {
1491 /* Enable CRS on TX for half-duplex operation. */
1492 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1497 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1498 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1499 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1501 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1507 * MDI/MDI-X = 0 (default)
1508 * 0 - Auto for all speeds
1511 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1513 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1517 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1521 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1524 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1528 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1533 * disable_polarity_correction = 0 (default)
1534 * Automatic Correction for Reversed Cable Polarity
1538 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1539 if (hw->disable_polarity_correction == 1)
1540 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1541 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1546 /* SW Reset the PHY so all changes take effect */
1547 ret_val = e1000_phy_reset(hw);
1549 DEBUGOUT("Error Resetting the PHY\n");
1552 } /* phy_reset_disable */
1554 if (hw->mac_type == e1000_80003es2lan) {
1555 /* Bypass RX and TX FIFO's */
1556 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1557 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1558 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1562 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1566 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1567 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1572 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1573 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1574 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1576 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1581 /* Do not init these registers when the HW is in IAMT mode, since the
1582 * firmware will have already initialized them. We only initialize
1583 * them if the HW is not in IAMT mode.
1585 if (e1000_check_mng_mode(hw) == FALSE) {
1586 /* Enable Electrical Idle on the PHY */
1587 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1588 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1593 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1598 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1599 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1606 /* Workaround: Disable padding in Kumeran interface in the MAC
1607 * and in the PHY to avoid CRC errors.
1609 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1613 phy_data |= GG82563_ICR_DIS_PADDING;
1614 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1620 return E1000_SUCCESS;
1623 /********************************************************************
1624 * Copper link setup for e1000_phy_m88 series.
1626 * hw - Struct containing variables accessed by shared code
1627 *********************************************************************/
1629 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1634 DEBUGFUNC("e1000_copper_link_mgp_setup");
1636 if (hw->phy_reset_disable)
1637 return E1000_SUCCESS;
1639 /* Enable CRS on TX. This must be set for half-duplex operation. */
1640 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1644 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1647 * MDI/MDI-X = 0 (default)
1648 * 0 - Auto for all speeds
1651 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1653 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1657 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1660 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1663 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1667 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1672 * disable_polarity_correction = 0 (default)
1673 * Automatic Correction for Reversed Cable Polarity
1677 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1678 if (hw->disable_polarity_correction == 1)
1679 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1680 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1684 if (hw->phy_revision < M88E1011_I_REV_4) {
1685 /* Force TX_CLK in the Extended PHY Specific Control Register
1688 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1692 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1694 if ((hw->phy_revision == E1000_REVISION_2) &&
1695 (hw->phy_id == M88E1111_I_PHY_ID)) {
1696 /* Vidalia Phy, set the downshift counter to 5x */
1697 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1698 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1699 ret_val = e1000_write_phy_reg(hw,
1700 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1704 /* Configure Master and Slave downshift values */
1705 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1706 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1707 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1708 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1709 ret_val = e1000_write_phy_reg(hw,
1710 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1716 /* SW Reset the PHY so all changes take effect */
1717 ret_val = e1000_phy_reset(hw);
1719 DEBUGOUT("Error Resetting the PHY\n");
1723 return E1000_SUCCESS;
1726 /********************************************************************
1727 * Setup auto-negotiation and flow control advertisements,
1728 * and then perform auto-negotiation.
1730 * hw - Struct containing variables accessed by shared code
1731 *********************************************************************/
1733 e1000_copper_link_autoneg(struct e1000_hw *hw)
1738 DEBUGFUNC("e1000_copper_link_autoneg");
1740 /* Perform some bounds checking on the hw->autoneg_advertised
1741 * parameter. If this variable is zero, then set it to the default.
1743 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1745 /* If autoneg_advertised is zero, we assume it was not defaulted
1746 * by the calling code so we set to advertise full capability.
1748 if (hw->autoneg_advertised == 0)
1749 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1751 /* IFE phy only supports 10/100 */
1752 if (hw->phy_type == e1000_phy_ife)
1753 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1755 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1756 ret_val = e1000_phy_setup_autoneg(hw);
1758 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1761 DEBUGOUT("Restarting Auto-Neg\n");
1763 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1764 * the Auto Neg Restart bit in the PHY control register.
1766 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1770 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1771 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1775 /* Does the user want to wait for Auto-Neg to complete here, or
1776 * check at a later time (for example, callback routine).
1778 if (hw->wait_autoneg_complete) {
1779 ret_val = e1000_wait_autoneg(hw);
1781 DEBUGOUT("Error while waiting for autoneg to complete\n");
1786 hw->get_link_status = TRUE;
1788 return E1000_SUCCESS;
1791 /******************************************************************************
1792 * Config the MAC and the PHY after link is up.
1793 * 1) Set up the MAC to the current PHY speed/duplex
1794 * if we are on 82543. If we
1795 * are on newer silicon, we only need to configure
1796 * collision distance in the Transmit Control Register.
1797 * 2) Set up flow control on the MAC to that established with
1799 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1801 * hw - Struct containing variables accessed by shared code
1802 ******************************************************************************/
1804 e1000_copper_link_postconfig(struct e1000_hw *hw)
1807 DEBUGFUNC("e1000_copper_link_postconfig");
1809 if (hw->mac_type >= e1000_82544) {
1810 e1000_config_collision_dist(hw);
1812 ret_val = e1000_config_mac_to_phy(hw);
1814 DEBUGOUT("Error configuring MAC to PHY settings\n");
1818 ret_val = e1000_config_fc_after_link_up(hw);
1820 DEBUGOUT("Error Configuring Flow Control\n");
1824 /* Config DSP to improve Giga link quality */
1825 if (hw->phy_type == e1000_phy_igp) {
1826 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1828 DEBUGOUT("Error Configuring DSP after link up\n");
1833 return E1000_SUCCESS;
1836 /******************************************************************************
1837 * Detects which PHY is present and setup the speed and duplex
1839 * hw - Struct containing variables accessed by shared code
1840 ******************************************************************************/
1842 e1000_setup_copper_link(struct e1000_hw *hw)
1849 DEBUGFUNC("e1000_setup_copper_link");
1851 switch (hw->mac_type) {
1852 case e1000_80003es2lan:
1854 /* Set the mac to wait the maximum time between each
1855 * iteration and increase the max iterations when
1856 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1857 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1860 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1864 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1871 /* Check if it is a valid PHY and set PHY mode if necessary. */
1872 ret_val = e1000_copper_link_preconfig(hw);
1876 switch (hw->mac_type) {
1877 case e1000_80003es2lan:
1878 /* Kumeran registers are written-only */
1879 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1880 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1881 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1890 if (hw->phy_type == e1000_phy_igp ||
1891 hw->phy_type == e1000_phy_igp_3 ||
1892 hw->phy_type == e1000_phy_igp_2) {
1893 ret_val = e1000_copper_link_igp_setup(hw);
1896 } else if (hw->phy_type == e1000_phy_m88) {
1897 ret_val = e1000_copper_link_mgp_setup(hw);
1900 } else if (hw->phy_type == e1000_phy_gg82563) {
1901 ret_val = e1000_copper_link_ggp_setup(hw);
1907 /* Setup autoneg and flow control advertisement
1908 * and perform autonegotiation */
1909 ret_val = e1000_copper_link_autoneg(hw);
1913 /* PHY will be set to 10H, 10F, 100H,or 100F
1914 * depending on value from forced_speed_duplex. */
1915 DEBUGOUT("Forcing speed and duplex\n");
1916 ret_val = e1000_phy_force_speed_duplex(hw);
1918 DEBUGOUT("Error Forcing Speed and Duplex\n");
1923 /* Check link status. Wait up to 100 microseconds for link to become
1926 for (i = 0; i < 10; i++) {
1927 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1930 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1934 if (phy_data & MII_SR_LINK_STATUS) {
1935 /* Config the MAC and PHY after link is up */
1936 ret_val = e1000_copper_link_postconfig(hw);
1940 DEBUGOUT("Valid link established!!!\n");
1941 return E1000_SUCCESS;
1946 DEBUGOUT("Unable to establish link!!!\n");
1947 return E1000_SUCCESS;
1950 /******************************************************************************
1951 * Configure the MAC-to-PHY interface for 10/100Mbps
1953 * hw - Struct containing variables accessed by shared code
1954 ******************************************************************************/
1956 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1958 int32_t ret_val = E1000_SUCCESS;
1962 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1964 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1965 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1970 /* Configure Transmit Inter-Packet Gap */
1971 tipg = E1000_READ_REG(hw, TIPG);
1972 tipg &= ~E1000_TIPG_IPGT_MASK;
1973 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1974 E1000_WRITE_REG(hw, TIPG, tipg);
1976 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1981 if (duplex == HALF_DUPLEX)
1982 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1984 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1986 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1992 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1994 int32_t ret_val = E1000_SUCCESS;
1998 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2000 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2001 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2006 /* Configure Transmit Inter-Packet Gap */
2007 tipg = E1000_READ_REG(hw, TIPG);
2008 tipg &= ~E1000_TIPG_IPGT_MASK;
2009 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2010 E1000_WRITE_REG(hw, TIPG, tipg);
2012 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
2017 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2018 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2023 /******************************************************************************
2024 * Configures PHY autoneg and flow control advertisement settings
2026 * hw - Struct containing variables accessed by shared code
2027 ******************************************************************************/
2029 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2032 uint16_t mii_autoneg_adv_reg;
2033 uint16_t mii_1000t_ctrl_reg;
2035 DEBUGFUNC("e1000_phy_setup_autoneg");
2037 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2038 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2042 if (hw->phy_type != e1000_phy_ife) {
2043 /* Read the MII 1000Base-T Control Register (Address 9). */
2044 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2048 mii_1000t_ctrl_reg=0;
2050 /* Need to parse both autoneg_advertised and fc and set up
2051 * the appropriate PHY registers. First we will parse for
2052 * autoneg_advertised software override. Since we can advertise
2053 * a plethora of combinations, we need to check each bit
2057 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2058 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2059 * the 1000Base-T Control Register (Address 9).
2061 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2062 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2064 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2066 /* Do we want to advertise 10 Mb Half Duplex? */
2067 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2068 DEBUGOUT("Advertise 10mb Half duplex\n");
2069 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2072 /* Do we want to advertise 10 Mb Full Duplex? */
2073 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2074 DEBUGOUT("Advertise 10mb Full duplex\n");
2075 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2078 /* Do we want to advertise 100 Mb Half Duplex? */
2079 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2080 DEBUGOUT("Advertise 100mb Half duplex\n");
2081 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2084 /* Do we want to advertise 100 Mb Full Duplex? */
2085 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2086 DEBUGOUT("Advertise 100mb Full duplex\n");
2087 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2090 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2091 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2092 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2095 /* Do we want to advertise 1000 Mb Full Duplex? */
2096 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2097 DEBUGOUT("Advertise 1000mb Full duplex\n");
2098 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2099 if (hw->phy_type == e1000_phy_ife) {
2100 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2104 /* Check for a software override of the flow control settings, and
2105 * setup the PHY advertisement registers accordingly. If
2106 * auto-negotiation is enabled, then software will have to set the
2107 * "PAUSE" bits to the correct value in the Auto-Negotiation
2108 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2110 * The possible values of the "fc" parameter are:
2111 * 0: Flow control is completely disabled
2112 * 1: Rx flow control is enabled (we can receive pause frames
2113 * but not send pause frames).
2114 * 2: Tx flow control is enabled (we can send pause frames
2115 * but we do not support receiving pause frames).
2116 * 3: Both Rx and TX flow control (symmetric) are enabled.
2117 * other: No software override. The flow control configuration
2118 * in the EEPROM is used.
2121 case E1000_FC_NONE: /* 0 */
2122 /* Flow control (RX & TX) is completely disabled by a
2123 * software over-ride.
2125 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2127 case E1000_FC_RX_PAUSE: /* 1 */
2128 /* RX Flow control is enabled, and TX Flow control is
2129 * disabled, by a software over-ride.
2131 /* Since there really isn't a way to advertise that we are
2132 * capable of RX Pause ONLY, we will advertise that we
2133 * support both symmetric and asymmetric RX PAUSE. Later
2134 * (in e1000_config_fc_after_link_up) we will disable the
2135 *hw's ability to send PAUSE frames.
2137 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2139 case E1000_FC_TX_PAUSE: /* 2 */
2140 /* TX Flow control is enabled, and RX Flow control is
2141 * disabled, by a software over-ride.
2143 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2144 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2146 case E1000_FC_FULL: /* 3 */
2147 /* Flow control (both RX and TX) is enabled by a software
2150 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2153 DEBUGOUT("Flow control param set incorrectly\n");
2154 return -E1000_ERR_CONFIG;
2157 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2161 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2163 if (hw->phy_type != e1000_phy_ife) {
2164 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2169 return E1000_SUCCESS;
2172 /******************************************************************************
2173 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2175 * hw - Struct containing variables accessed by shared code
2176 ******************************************************************************/
2178 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2182 uint16_t mii_ctrl_reg;
2183 uint16_t mii_status_reg;
2187 DEBUGFUNC("e1000_phy_force_speed_duplex");
2189 /* Turn off Flow control if we are forcing speed and duplex. */
2190 hw->fc = E1000_FC_NONE;
2192 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2194 /* Read the Device Control Register. */
2195 ctrl = E1000_READ_REG(hw, CTRL);
2197 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2198 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2199 ctrl &= ~(DEVICE_SPEED_MASK);
2201 /* Clear the Auto Speed Detect Enable bit. */
2202 ctrl &= ~E1000_CTRL_ASDE;
2204 /* Read the MII Control Register. */
2205 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2209 /* We need to disable autoneg in order to force link and duplex. */
2211 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2213 /* Are we forcing Full or Half Duplex? */
2214 if (hw->forced_speed_duplex == e1000_100_full ||
2215 hw->forced_speed_duplex == e1000_10_full) {
2216 /* We want to force full duplex so we SET the full duplex bits in the
2217 * Device and MII Control Registers.
2219 ctrl |= E1000_CTRL_FD;
2220 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2221 DEBUGOUT("Full Duplex\n");
2223 /* We want to force half duplex so we CLEAR the full duplex bits in
2224 * the Device and MII Control Registers.
2226 ctrl &= ~E1000_CTRL_FD;
2227 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2228 DEBUGOUT("Half Duplex\n");
2231 /* Are we forcing 100Mbps??? */
2232 if (hw->forced_speed_duplex == e1000_100_full ||
2233 hw->forced_speed_duplex == e1000_100_half) {
2234 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2235 ctrl |= E1000_CTRL_SPD_100;
2236 mii_ctrl_reg |= MII_CR_SPEED_100;
2237 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2238 DEBUGOUT("Forcing 100mb ");
2240 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2241 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2242 mii_ctrl_reg |= MII_CR_SPEED_10;
2243 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2244 DEBUGOUT("Forcing 10mb ");
2247 e1000_config_collision_dist(hw);
2249 /* Write the configured values back to the Device Control Reg. */
2250 E1000_WRITE_REG(hw, CTRL, ctrl);
2252 if ((hw->phy_type == e1000_phy_m88) ||
2253 (hw->phy_type == e1000_phy_gg82563)) {
2254 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2258 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2259 * forced whenever speed are duplex are forced.
2261 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2262 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2266 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2268 /* Need to reset the PHY or these changes will be ignored */
2269 mii_ctrl_reg |= MII_CR_RESET;
2270 /* Disable MDI-X support for 10/100 */
2271 } else if (hw->phy_type == e1000_phy_ife) {
2272 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2276 phy_data &= ~IFE_PMC_AUTO_MDIX;
2277 phy_data &= ~IFE_PMC_FORCE_MDIX;
2279 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2283 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2284 * forced whenever speed or duplex are forced.
2286 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2290 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2291 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2293 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2298 /* Write back the modified PHY MII control register. */
2299 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2305 /* The wait_autoneg_complete flag may be a little misleading here.
2306 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2307 * But we do want to delay for a period while forcing only so we
2308 * don't generate false No Link messages. So we will wait here
2309 * only if the user has set wait_autoneg_complete to 1, which is
2312 if (hw->wait_autoneg_complete) {
2313 /* We will wait for autoneg to complete. */
2314 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2317 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2318 for (i = PHY_FORCE_TIME; i > 0; i--) {
2319 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2322 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2326 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2330 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2334 ((hw->phy_type == e1000_phy_m88) ||
2335 (hw->phy_type == e1000_phy_gg82563))) {
2336 /* We didn't get link. Reset the DSP and wait again for link. */
2337 ret_val = e1000_phy_reset_dsp(hw);
2339 DEBUGOUT("Error Resetting PHY DSP\n");
2343 /* This loop will early-out if the link condition has been met. */
2344 for (i = PHY_FORCE_TIME; i > 0; i--) {
2345 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2347 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2350 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2354 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2360 if (hw->phy_type == e1000_phy_m88) {
2361 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2362 * Extended PHY Specific Control Register to 25MHz clock. This value
2363 * defaults back to a 2.5MHz clock when the PHY is reset.
2365 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2369 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2370 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2374 /* In addition, because of the s/w reset above, we need to enable CRS on
2375 * TX. This must be set for both full and half duplex operation.
2377 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2381 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2382 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2386 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2387 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2388 hw->forced_speed_duplex == e1000_10_half)) {
2389 ret_val = e1000_polarity_reversal_workaround(hw);
2393 } else if (hw->phy_type == e1000_phy_gg82563) {
2394 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2395 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2396 * we're not in a forced 10/duplex configuration. */
2397 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2401 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2402 if ((hw->forced_speed_duplex == e1000_10_full) ||
2403 (hw->forced_speed_duplex == e1000_10_half))
2404 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2406 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2408 /* Also due to the reset, we need to enable CRS on Tx. */
2409 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2411 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2415 return E1000_SUCCESS;
2418 /******************************************************************************
2419 * Sets the collision distance in the Transmit Control register
2421 * hw - Struct containing variables accessed by shared code
2423 * Link should have been established previously. Reads the speed and duplex
2424 * information from the Device Status register.
2425 ******************************************************************************/
2427 e1000_config_collision_dist(struct e1000_hw *hw)
2429 uint32_t tctl, coll_dist;
2431 DEBUGFUNC("e1000_config_collision_dist");
2433 if (hw->mac_type < e1000_82543)
2434 coll_dist = E1000_COLLISION_DISTANCE_82542;
2436 coll_dist = E1000_COLLISION_DISTANCE;
2438 tctl = E1000_READ_REG(hw, TCTL);
2440 tctl &= ~E1000_TCTL_COLD;
2441 tctl |= coll_dist << E1000_COLD_SHIFT;
2443 E1000_WRITE_REG(hw, TCTL, tctl);
2444 E1000_WRITE_FLUSH(hw);
2447 /******************************************************************************
2448 * Sets MAC speed and duplex settings to reflect the those in the PHY
2450 * hw - Struct containing variables accessed by shared code
2451 * mii_reg - data to write to the MII control register
2453 * The contents of the PHY register containing the needed information need to
2455 ******************************************************************************/
2457 e1000_config_mac_to_phy(struct e1000_hw *hw)
2463 DEBUGFUNC("e1000_config_mac_to_phy");
2465 /* 82544 or newer MAC, Auto Speed Detection takes care of
2466 * MAC speed/duplex configuration.*/
2467 if (hw->mac_type >= e1000_82544)
2468 return E1000_SUCCESS;
2470 /* Read the Device Control Register and set the bits to Force Speed
2473 ctrl = E1000_READ_REG(hw, CTRL);
2474 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2475 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2477 /* Set up duplex in the Device Control and Transmit Control
2478 * registers depending on negotiated values.
2480 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2484 if (phy_data & M88E1000_PSSR_DPLX)
2485 ctrl |= E1000_CTRL_FD;
2487 ctrl &= ~E1000_CTRL_FD;
2489 e1000_config_collision_dist(hw);
2491 /* Set up speed in the Device Control register depending on
2492 * negotiated values.
2494 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2495 ctrl |= E1000_CTRL_SPD_1000;
2496 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2497 ctrl |= E1000_CTRL_SPD_100;
2499 /* Write the configured values back to the Device Control Reg. */
2500 E1000_WRITE_REG(hw, CTRL, ctrl);
2501 return E1000_SUCCESS;
2504 /******************************************************************************
2505 * Forces the MAC's flow control settings.
2507 * hw - Struct containing variables accessed by shared code
2509 * Sets the TFCE and RFCE bits in the device control register to reflect
2510 * the adapter settings. TFCE and RFCE need to be explicitly set by
2511 * software when a Copper PHY is used because autonegotiation is managed
2512 * by the PHY rather than the MAC. Software must also configure these
2513 * bits when link is forced on a fiber connection.
2514 *****************************************************************************/
2516 e1000_force_mac_fc(struct e1000_hw *hw)
2520 DEBUGFUNC("e1000_force_mac_fc");
2522 /* Get the current configuration of the Device Control Register */
2523 ctrl = E1000_READ_REG(hw, CTRL);
2525 /* Because we didn't get link via the internal auto-negotiation
2526 * mechanism (we either forced link or we got link via PHY
2527 * auto-neg), we have to manually enable/disable transmit an
2528 * receive flow control.
2530 * The "Case" statement below enables/disable flow control
2531 * according to the "hw->fc" parameter.
2533 * The possible values of the "fc" parameter are:
2534 * 0: Flow control is completely disabled
2535 * 1: Rx flow control is enabled (we can receive pause
2536 * frames but not send pause frames).
2537 * 2: Tx flow control is enabled (we can send pause frames
2538 * frames but we do not receive pause frames).
2539 * 3: Both Rx and TX flow control (symmetric) is enabled.
2540 * other: No other values should be possible at this point.
2545 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2547 case E1000_FC_RX_PAUSE:
2548 ctrl &= (~E1000_CTRL_TFCE);
2549 ctrl |= E1000_CTRL_RFCE;
2551 case E1000_FC_TX_PAUSE:
2552 ctrl &= (~E1000_CTRL_RFCE);
2553 ctrl |= E1000_CTRL_TFCE;
2556 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2559 DEBUGOUT("Flow control param set incorrectly\n");
2560 return -E1000_ERR_CONFIG;
2563 /* Disable TX Flow Control for 82542 (rev 2.0) */
2564 if (hw->mac_type == e1000_82542_rev2_0)
2565 ctrl &= (~E1000_CTRL_TFCE);
2567 E1000_WRITE_REG(hw, CTRL, ctrl);
2568 return E1000_SUCCESS;
2571 /******************************************************************************
2572 * Configures flow control settings after link is established
2574 * hw - Struct containing variables accessed by shared code
2576 * Should be called immediately after a valid link has been established.
2577 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2578 * and autonegotiation is enabled, the MAC flow control settings will be set
2579 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2580 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2581 *****************************************************************************/
2583 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2586 uint16_t mii_status_reg;
2587 uint16_t mii_nway_adv_reg;
2588 uint16_t mii_nway_lp_ability_reg;
2592 DEBUGFUNC("e1000_config_fc_after_link_up");
2594 /* Check for the case where we have fiber media and auto-neg failed
2595 * so we had to force link. In this case, we need to force the
2596 * configuration of the MAC to match the "fc" parameter.
2598 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2599 ((hw->media_type == e1000_media_type_internal_serdes) &&
2600 (hw->autoneg_failed)) ||
2601 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2602 ret_val = e1000_force_mac_fc(hw);
2604 DEBUGOUT("Error forcing flow control settings\n");
2609 /* Check for the case where we have copper media and auto-neg is
2610 * enabled. In this case, we need to check and see if Auto-Neg
2611 * has completed, and if so, how the PHY and link partner has
2612 * flow control configured.
2614 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2615 /* Read the MII Status Register and check to see if AutoNeg
2616 * has completed. We read this twice because this reg has
2617 * some "sticky" (latched) bits.
2619 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2622 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2626 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2627 /* The AutoNeg process has completed, so we now need to
2628 * read both the Auto Negotiation Advertisement Register
2629 * (Address 4) and the Auto_Negotiation Base Page Ability
2630 * Register (Address 5) to determine how flow control was
2633 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2637 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2638 &mii_nway_lp_ability_reg);
2642 /* Two bits in the Auto Negotiation Advertisement Register
2643 * (Address 4) and two bits in the Auto Negotiation Base
2644 * Page Ability Register (Address 5) determine flow control
2645 * for both the PHY and the link partner. The following
2646 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2647 * 1999, describes these PAUSE resolution bits and how flow
2648 * control is determined based upon these settings.
2649 * NOTE: DC = Don't Care
2651 * LOCAL DEVICE | LINK PARTNER
2652 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2653 *-------|---------|-------|---------|--------------------
2654 * 0 | 0 | DC | DC | E1000_FC_NONE
2655 * 0 | 1 | 0 | DC | E1000_FC_NONE
2656 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2657 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2658 * 1 | 0 | 0 | DC | E1000_FC_NONE
2659 * 1 | DC | 1 | DC | E1000_FC_FULL
2660 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2661 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2664 /* Are both PAUSE bits set to 1? If so, this implies
2665 * Symmetric Flow Control is enabled at both ends. The
2666 * ASM_DIR bits are irrelevant per the spec.
2668 * For Symmetric Flow Control:
2670 * LOCAL DEVICE | LINK PARTNER
2671 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2672 *-------|---------|-------|---------|--------------------
2673 * 1 | DC | 1 | DC | E1000_FC_FULL
2676 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2677 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2678 /* Now we need to check if the user selected RX ONLY
2679 * of pause frames. In this case, we had to advertise
2680 * FULL flow control because we could not advertise RX
2681 * ONLY. Hence, we must now check to see if we need to
2682 * turn OFF the TRANSMISSION of PAUSE frames.
2684 if (hw->original_fc == E1000_FC_FULL) {
2685 hw->fc = E1000_FC_FULL;
2686 DEBUGOUT("Flow Control = FULL.\n");
2688 hw->fc = E1000_FC_RX_PAUSE;
2689 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2692 /* For receiving PAUSE frames ONLY.
2694 * LOCAL DEVICE | LINK PARTNER
2695 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2696 *-------|---------|-------|---------|--------------------
2697 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2700 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2701 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2702 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2703 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2704 hw->fc = E1000_FC_TX_PAUSE;
2705 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2707 /* For transmitting PAUSE frames ONLY.
2709 * LOCAL DEVICE | LINK PARTNER
2710 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2711 *-------|---------|-------|---------|--------------------
2712 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2715 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2716 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2717 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2718 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2719 hw->fc = E1000_FC_RX_PAUSE;
2720 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2722 /* Per the IEEE spec, at this point flow control should be
2723 * disabled. However, we want to consider that we could
2724 * be connected to a legacy switch that doesn't advertise
2725 * desired flow control, but can be forced on the link
2726 * partner. So if we advertised no flow control, that is
2727 * what we will resolve to. If we advertised some kind of
2728 * receive capability (Rx Pause Only or Full Flow Control)
2729 * and the link partner advertised none, we will configure
2730 * ourselves to enable Rx Flow Control only. We can do
2731 * this safely for two reasons: If the link partner really
2732 * didn't want flow control enabled, and we enable Rx, no
2733 * harm done since we won't be receiving any PAUSE frames
2734 * anyway. If the intent on the link partner was to have
2735 * flow control enabled, then by us enabling RX only, we
2736 * can at least receive pause frames and process them.
2737 * This is a good idea because in most cases, since we are
2738 * predominantly a server NIC, more times than not we will
2739 * be asked to delay transmission of packets than asking
2740 * our link partner to pause transmission of frames.
2742 else if ((hw->original_fc == E1000_FC_NONE ||
2743 hw->original_fc == E1000_FC_TX_PAUSE) ||
2744 hw->fc_strict_ieee) {
2745 hw->fc = E1000_FC_NONE;
2746 DEBUGOUT("Flow Control = NONE.\n");
2748 hw->fc = E1000_FC_RX_PAUSE;
2749 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2752 /* Now we need to do one last check... If we auto-
2753 * negotiated to HALF DUPLEX, flow control should not be
2754 * enabled per IEEE 802.3 spec.
2756 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2758 DEBUGOUT("Error getting link speed and duplex\n");
2762 if (duplex == HALF_DUPLEX)
2763 hw->fc = E1000_FC_NONE;
2765 /* Now we call a subroutine to actually force the MAC
2766 * controller to use the correct flow control settings.
2768 ret_val = e1000_force_mac_fc(hw);
2770 DEBUGOUT("Error forcing flow control settings\n");
2774 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2777 return E1000_SUCCESS;
2780 /******************************************************************************
2781 * Checks to see if the link status of the hardware has changed.
2783 * hw - Struct containing variables accessed by shared code
2785 * Called by any function that needs to check the link status of the adapter.
2786 *****************************************************************************/
2788 e1000_check_for_link(struct e1000_hw *hw)
2795 uint32_t signal = 0;
2799 DEBUGFUNC("e1000_check_for_link");
2801 ctrl = E1000_READ_REG(hw, CTRL);
2802 status = E1000_READ_REG(hw, STATUS);
2804 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2805 * set when the optics detect a signal. On older adapters, it will be
2806 * cleared when there is a signal. This applies to fiber media only.
2808 if ((hw->media_type == e1000_media_type_fiber) ||
2809 (hw->media_type == e1000_media_type_internal_serdes)) {
2810 rxcw = E1000_READ_REG(hw, RXCW);
2812 if (hw->media_type == e1000_media_type_fiber) {
2813 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2814 if (status & E1000_STATUS_LU)
2815 hw->get_link_status = FALSE;
2819 /* If we have a copper PHY then we only want to go out to the PHY
2820 * registers to see if Auto-Neg has completed and/or if our link
2821 * status has changed. The get_link_status flag will be set if we
2822 * receive a Link Status Change interrupt or we have Rx Sequence
2825 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2826 /* First we want to see if the MII Status Register reports
2827 * link. If so, then we want to get the current speed/duplex
2829 * Read the register twice since the link bit is sticky.
2831 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2834 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2838 if (phy_data & MII_SR_LINK_STATUS) {
2839 hw->get_link_status = FALSE;
2840 /* Check if there was DownShift, must be checked immediately after
2842 e1000_check_downshift(hw);
2844 /* If we are on 82544 or 82543 silicon and speed/duplex
2845 * are forced to 10H or 10F, then we will implement the polarity
2846 * reversal workaround. We disable interrupts first, and upon
2847 * returning, place the devices interrupt state to its previous
2848 * value except for the link status change interrupt which will
2849 * happen due to the execution of this workaround.
2852 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2854 (hw->forced_speed_duplex == e1000_10_full ||
2855 hw->forced_speed_duplex == e1000_10_half)) {
2856 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2857 ret_val = e1000_polarity_reversal_workaround(hw);
2858 icr = E1000_READ_REG(hw, ICR);
2859 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2860 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2864 /* No link detected */
2865 e1000_config_dsp_after_link_change(hw, FALSE);
2869 /* If we are forcing speed/duplex, then we simply return since
2870 * we have already determined whether we have link or not.
2872 if (!hw->autoneg) return -E1000_ERR_CONFIG;
2874 /* optimize the dsp settings for the igp phy */
2875 e1000_config_dsp_after_link_change(hw, TRUE);
2877 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2878 * have Si on board that is 82544 or newer, Auto
2879 * Speed Detection takes care of MAC speed/duplex
2880 * configuration. So we only need to configure Collision
2881 * Distance in the MAC. Otherwise, we need to force
2882 * speed/duplex on the MAC to the current PHY speed/duplex
2885 if (hw->mac_type >= e1000_82544)
2886 e1000_config_collision_dist(hw);
2888 ret_val = e1000_config_mac_to_phy(hw);
2890 DEBUGOUT("Error configuring MAC to PHY settings\n");
2895 /* Configure Flow Control now that Auto-Neg has completed. First, we
2896 * need to restore the desired flow control settings because we may
2897 * have had to re-autoneg with a different link partner.
2899 ret_val = e1000_config_fc_after_link_up(hw);
2901 DEBUGOUT("Error configuring flow control\n");
2905 /* At this point we know that we are on copper and we have
2906 * auto-negotiated link. These are conditions for checking the link
2907 * partner capability register. We use the link speed to determine if
2908 * TBI compatibility needs to be turned on or off. If the link is not
2909 * at gigabit speed, then TBI compatibility is not needed. If we are
2910 * at gigabit speed, we turn on TBI compatibility.
2912 if (hw->tbi_compatibility_en) {
2913 uint16_t speed, duplex;
2914 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2916 DEBUGOUT("Error getting link speed and duplex\n");
2919 if (speed != SPEED_1000) {
2920 /* If link speed is not set to gigabit speed, we do not need
2921 * to enable TBI compatibility.
2923 if (hw->tbi_compatibility_on) {
2924 /* If we previously were in the mode, turn it off. */
2925 rctl = E1000_READ_REG(hw, RCTL);
2926 rctl &= ~E1000_RCTL_SBP;
2927 E1000_WRITE_REG(hw, RCTL, rctl);
2928 hw->tbi_compatibility_on = FALSE;
2931 /* If TBI compatibility is was previously off, turn it on. For
2932 * compatibility with a TBI link partner, we will store bad
2933 * packets. Some frames have an additional byte on the end and
2934 * will look like CRC errors to to the hardware.
2936 if (!hw->tbi_compatibility_on) {
2937 hw->tbi_compatibility_on = TRUE;
2938 rctl = E1000_READ_REG(hw, RCTL);
2939 rctl |= E1000_RCTL_SBP;
2940 E1000_WRITE_REG(hw, RCTL, rctl);
2945 /* If we don't have link (auto-negotiation failed or link partner cannot
2946 * auto-negotiate), the cable is plugged in (we have signal), and our
2947 * link partner is not trying to auto-negotiate with us (we are receiving
2948 * idles or data), we need to force link up. We also need to give
2949 * auto-negotiation time to complete, in case the cable was just plugged
2950 * in. The autoneg_failed flag does this.
2952 else if ((((hw->media_type == e1000_media_type_fiber) &&
2953 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2954 (hw->media_type == e1000_media_type_internal_serdes)) &&
2955 (!(status & E1000_STATUS_LU)) &&
2956 (!(rxcw & E1000_RXCW_C))) {
2957 if (hw->autoneg_failed == 0) {
2958 hw->autoneg_failed = 1;
2961 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
2963 /* Disable auto-negotiation in the TXCW register */
2964 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2966 /* Force link-up and also force full-duplex. */
2967 ctrl = E1000_READ_REG(hw, CTRL);
2968 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2969 E1000_WRITE_REG(hw, CTRL, ctrl);
2971 /* Configure Flow Control after forcing link up. */
2972 ret_val = e1000_config_fc_after_link_up(hw);
2974 DEBUGOUT("Error configuring flow control\n");
2978 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2979 * auto-negotiation in the TXCW register and disable forced link in the
2980 * Device Control register in an attempt to auto-negotiate with our link
2983 else if (((hw->media_type == e1000_media_type_fiber) ||
2984 (hw->media_type == e1000_media_type_internal_serdes)) &&
2985 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2986 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
2987 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2988 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2990 hw->serdes_link_down = FALSE;
2992 /* If we force link for non-auto-negotiation switch, check link status
2993 * based on MAC synchronization for internal serdes media type.
2995 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
2996 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2997 /* SYNCH bit and IV bit are sticky. */
2999 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3000 if (!(rxcw & E1000_RXCW_IV)) {
3001 hw->serdes_link_down = FALSE;
3002 DEBUGOUT("SERDES: Link is up.\n");
3005 hw->serdes_link_down = TRUE;
3006 DEBUGOUT("SERDES: Link is down.\n");
3009 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3010 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3011 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3013 return E1000_SUCCESS;
3016 /******************************************************************************
3017 * Detects the current speed and duplex settings of the hardware.
3019 * hw - Struct containing variables accessed by shared code
3020 * speed - Speed of the connection
3021 * duplex - Duplex setting of the connection
3022 *****************************************************************************/
3024 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3032 DEBUGFUNC("e1000_get_speed_and_duplex");
3034 if (hw->mac_type >= e1000_82543) {
3035 status = E1000_READ_REG(hw, STATUS);
3036 if (status & E1000_STATUS_SPEED_1000) {
3037 *speed = SPEED_1000;
3038 DEBUGOUT("1000 Mbs, ");
3039 } else if (status & E1000_STATUS_SPEED_100) {
3041 DEBUGOUT("100 Mbs, ");
3044 DEBUGOUT("10 Mbs, ");
3047 if (status & E1000_STATUS_FD) {
3048 *duplex = FULL_DUPLEX;
3049 DEBUGOUT("Full Duplex\n");
3051 *duplex = HALF_DUPLEX;
3052 DEBUGOUT(" Half Duplex\n");
3055 DEBUGOUT("1000 Mbs, Full Duplex\n");
3056 *speed = SPEED_1000;
3057 *duplex = FULL_DUPLEX;
3060 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3061 * if it is operating at half duplex. Here we set the duplex settings to
3062 * match the duplex in the link partner's capabilities.
3064 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3065 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3069 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3070 *duplex = HALF_DUPLEX;
3072 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3075 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3076 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3077 *duplex = HALF_DUPLEX;
3081 if ((hw->mac_type == e1000_80003es2lan) &&
3082 (hw->media_type == e1000_media_type_copper)) {
3083 if (*speed == SPEED_1000)
3084 ret_val = e1000_configure_kmrn_for_1000(hw);
3086 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3091 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3092 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3097 return E1000_SUCCESS;
3100 /******************************************************************************
3101 * Blocks until autoneg completes or times out (~4.5 seconds)
3103 * hw - Struct containing variables accessed by shared code
3104 ******************************************************************************/
3106 e1000_wait_autoneg(struct e1000_hw *hw)
3112 DEBUGFUNC("e1000_wait_autoneg");
3113 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3115 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3116 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3117 /* Read the MII Status Register and wait for Auto-Neg
3118 * Complete bit to be set.
3120 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3123 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3126 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3127 return E1000_SUCCESS;
3131 return E1000_SUCCESS;
3134 /******************************************************************************
3135 * Raises the Management Data Clock
3137 * hw - Struct containing variables accessed by shared code
3138 * ctrl - Device control register's current value
3139 ******************************************************************************/
3141 e1000_raise_mdi_clk(struct e1000_hw *hw,
3144 /* Raise the clock input to the Management Data Clock (by setting the MDC
3145 * bit), and then delay 10 microseconds.
3147 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3148 E1000_WRITE_FLUSH(hw);
3152 /******************************************************************************
3153 * Lowers the Management Data Clock
3155 * hw - Struct containing variables accessed by shared code
3156 * ctrl - Device control register's current value
3157 ******************************************************************************/
3159 e1000_lower_mdi_clk(struct e1000_hw *hw,
3162 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3163 * bit), and then delay 10 microseconds.
3165 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3166 E1000_WRITE_FLUSH(hw);
3170 /******************************************************************************
3171 * Shifts data bits out to the PHY
3173 * hw - Struct containing variables accessed by shared code
3174 * data - Data to send out to the PHY
3175 * count - Number of bits to shift out
3177 * Bits are shifted out in MSB to LSB order.
3178 ******************************************************************************/
3180 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3187 /* We need to shift "count" number of bits out to the PHY. So, the value
3188 * in the "data" parameter will be shifted out to the PHY one bit at a
3189 * time. In order to do this, "data" must be broken down into bits.
3192 mask <<= (count - 1);
3194 ctrl = E1000_READ_REG(hw, CTRL);
3196 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3197 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3200 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3201 * then raising and lowering the Management Data Clock. A "0" is
3202 * shifted out to the PHY by setting the MDIO bit to "0" and then
3203 * raising and lowering the clock.
3206 ctrl |= E1000_CTRL_MDIO;
3208 ctrl &= ~E1000_CTRL_MDIO;
3210 E1000_WRITE_REG(hw, CTRL, ctrl);
3211 E1000_WRITE_FLUSH(hw);
3215 e1000_raise_mdi_clk(hw, &ctrl);
3216 e1000_lower_mdi_clk(hw, &ctrl);
3222 /******************************************************************************
3223 * Shifts data bits in from the PHY
3225 * hw - Struct containing variables accessed by shared code
3227 * Bits are shifted in in MSB to LSB order.
3228 ******************************************************************************/
3230 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3236 /* In order to read a register from the PHY, we need to shift in a total
3237 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3238 * to avoid contention on the MDIO pin when a read operation is performed.
3239 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3240 * by raising the input to the Management Data Clock (setting the MDC bit),
3241 * and then reading the value of the MDIO bit.
3243 ctrl = E1000_READ_REG(hw, CTRL);
3245 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3246 ctrl &= ~E1000_CTRL_MDIO_DIR;
3247 ctrl &= ~E1000_CTRL_MDIO;
3249 E1000_WRITE_REG(hw, CTRL, ctrl);
3250 E1000_WRITE_FLUSH(hw);
3252 /* Raise and Lower the clock before reading in the data. This accounts for
3253 * the turnaround bits. The first clock occurred when we clocked out the
3254 * last bit of the Register Address.
3256 e1000_raise_mdi_clk(hw, &ctrl);
3257 e1000_lower_mdi_clk(hw, &ctrl);
3259 for (data = 0, i = 0; i < 16; i++) {
3261 e1000_raise_mdi_clk(hw, &ctrl);
3262 ctrl = E1000_READ_REG(hw, CTRL);
3263 /* Check to see if we shifted in a "1". */
3264 if (ctrl & E1000_CTRL_MDIO)
3266 e1000_lower_mdi_clk(hw, &ctrl);
3269 e1000_raise_mdi_clk(hw, &ctrl);
3270 e1000_lower_mdi_clk(hw, &ctrl);
3276 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3278 uint32_t swfw_sync = 0;
3279 uint32_t swmask = mask;
3280 uint32_t fwmask = mask << 16;
3281 int32_t timeout = 200;
3283 DEBUGFUNC("e1000_swfw_sync_acquire");
3285 if (hw->swfwhw_semaphore_present)
3286 return e1000_get_software_flag(hw);
3288 if (!hw->swfw_sync_present)
3289 return e1000_get_hw_eeprom_semaphore(hw);
3292 if (e1000_get_hw_eeprom_semaphore(hw))
3293 return -E1000_ERR_SWFW_SYNC;
3295 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3296 if (!(swfw_sync & (fwmask | swmask))) {
3300 /* firmware currently using resource (fwmask) */
3301 /* or other software thread currently using resource (swmask) */
3302 e1000_put_hw_eeprom_semaphore(hw);
3308 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3309 return -E1000_ERR_SWFW_SYNC;
3312 swfw_sync |= swmask;
3313 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3315 e1000_put_hw_eeprom_semaphore(hw);
3316 return E1000_SUCCESS;
3320 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3323 uint32_t swmask = mask;
3325 DEBUGFUNC("e1000_swfw_sync_release");
3327 if (hw->swfwhw_semaphore_present) {
3328 e1000_release_software_flag(hw);
3332 if (!hw->swfw_sync_present) {
3333 e1000_put_hw_eeprom_semaphore(hw);
3337 /* if (e1000_get_hw_eeprom_semaphore(hw))
3338 * return -E1000_ERR_SWFW_SYNC; */
3339 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3342 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3343 swfw_sync &= ~swmask;
3344 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3346 e1000_put_hw_eeprom_semaphore(hw);
3349 /*****************************************************************************
3350 * Reads the value from a PHY register, if the value is on a specific non zero
3351 * page, sets the page first.
3352 * hw - Struct containing variables accessed by shared code
3353 * reg_addr - address of the PHY register to read
3354 ******************************************************************************/
3356 e1000_read_phy_reg(struct e1000_hw *hw,
3363 DEBUGFUNC("e1000_read_phy_reg");
3365 if ((hw->mac_type == e1000_80003es2lan) &&
3366 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3367 swfw = E1000_SWFW_PHY1_SM;
3369 swfw = E1000_SWFW_PHY0_SM;
3371 if (e1000_swfw_sync_acquire(hw, swfw))
3372 return -E1000_ERR_SWFW_SYNC;
3374 if ((hw->phy_type == e1000_phy_igp ||
3375 hw->phy_type == e1000_phy_igp_3 ||
3376 hw->phy_type == e1000_phy_igp_2) &&
3377 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3378 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3379 (uint16_t)reg_addr);
3381 e1000_swfw_sync_release(hw, swfw);
3384 } else if (hw->phy_type == e1000_phy_gg82563) {
3385 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3386 (hw->mac_type == e1000_80003es2lan)) {
3387 /* Select Configuration Page */
3388 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3389 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3390 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3392 /* Use Alternative Page Select register to access
3393 * registers 30 and 31
3395 ret_val = e1000_write_phy_reg_ex(hw,
3396 GG82563_PHY_PAGE_SELECT_ALT,
3397 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3401 e1000_swfw_sync_release(hw, swfw);
3407 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3410 e1000_swfw_sync_release(hw, swfw);
3415 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3420 const uint32_t phy_addr = 1;
3422 DEBUGFUNC("e1000_read_phy_reg_ex");
3424 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3425 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3426 return -E1000_ERR_PARAM;
3429 if (hw->mac_type > e1000_82543) {
3430 /* Set up Op-code, Phy Address, and register address in the MDI
3431 * Control register. The MAC will take care of interfacing with the
3432 * PHY to retrieve the desired data.
3434 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3435 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3436 (E1000_MDIC_OP_READ));
3438 E1000_WRITE_REG(hw, MDIC, mdic);
3440 /* Poll the ready bit to see if the MDI read completed */
3441 for (i = 0; i < 64; i++) {
3443 mdic = E1000_READ_REG(hw, MDIC);
3444 if (mdic & E1000_MDIC_READY) break;
3446 if (!(mdic & E1000_MDIC_READY)) {
3447 DEBUGOUT("MDI Read did not complete\n");
3448 return -E1000_ERR_PHY;
3450 if (mdic & E1000_MDIC_ERROR) {
3451 DEBUGOUT("MDI Error\n");
3452 return -E1000_ERR_PHY;
3454 *phy_data = (uint16_t) mdic;
3456 /* We must first send a preamble through the MDIO pin to signal the
3457 * beginning of an MII instruction. This is done by sending 32
3458 * consecutive "1" bits.
3460 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3462 /* Now combine the next few fields that are required for a read
3463 * operation. We use this method instead of calling the
3464 * e1000_shift_out_mdi_bits routine five different times. The format of
3465 * a MII read instruction consists of a shift out of 14 bits and is
3466 * defined as follows:
3467 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3468 * followed by a shift in of 18 bits. This first two bits shifted in
3469 * are TurnAround bits used to avoid contention on the MDIO pin when a
3470 * READ operation is performed. These two bits are thrown away
3471 * followed by a shift in of 16 bits which contains the desired data.
3473 mdic = ((reg_addr) | (phy_addr << 5) |
3474 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3476 e1000_shift_out_mdi_bits(hw, mdic, 14);
3478 /* Now that we've shifted out the read command to the MII, we need to
3479 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3482 *phy_data = e1000_shift_in_mdi_bits(hw);
3484 return E1000_SUCCESS;
3487 /******************************************************************************
3488 * Writes a value to a PHY register
3490 * hw - Struct containing variables accessed by shared code
3491 * reg_addr - address of the PHY register to write
3492 * data - data to write to the PHY
3493 ******************************************************************************/
3495 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3501 DEBUGFUNC("e1000_write_phy_reg");
3503 if ((hw->mac_type == e1000_80003es2lan) &&
3504 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3505 swfw = E1000_SWFW_PHY1_SM;
3507 swfw = E1000_SWFW_PHY0_SM;
3509 if (e1000_swfw_sync_acquire(hw, swfw))
3510 return -E1000_ERR_SWFW_SYNC;
3512 if ((hw->phy_type == e1000_phy_igp ||
3513 hw->phy_type == e1000_phy_igp_3 ||
3514 hw->phy_type == e1000_phy_igp_2) &&
3515 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3516 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3517 (uint16_t)reg_addr);
3519 e1000_swfw_sync_release(hw, swfw);
3522 } else if (hw->phy_type == e1000_phy_gg82563) {
3523 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3524 (hw->mac_type == e1000_80003es2lan)) {
3525 /* Select Configuration Page */
3526 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3527 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3528 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3530 /* Use Alternative Page Select register to access
3531 * registers 30 and 31
3533 ret_val = e1000_write_phy_reg_ex(hw,
3534 GG82563_PHY_PAGE_SELECT_ALT,
3535 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3539 e1000_swfw_sync_release(hw, swfw);
3545 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3548 e1000_swfw_sync_release(hw, swfw);
3553 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3558 const uint32_t phy_addr = 1;
3560 DEBUGFUNC("e1000_write_phy_reg_ex");
3562 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3563 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3564 return -E1000_ERR_PARAM;
3567 if (hw->mac_type > e1000_82543) {
3568 /* Set up Op-code, Phy Address, register address, and data intended
3569 * for the PHY register in the MDI Control register. The MAC will take
3570 * care of interfacing with the PHY to send the desired data.
3572 mdic = (((uint32_t) phy_data) |
3573 (reg_addr << E1000_MDIC_REG_SHIFT) |
3574 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3575 (E1000_MDIC_OP_WRITE));
3577 E1000_WRITE_REG(hw, MDIC, mdic);
3579 /* Poll the ready bit to see if the MDI read completed */
3580 for (i = 0; i < 641; i++) {
3582 mdic = E1000_READ_REG(hw, MDIC);
3583 if (mdic & E1000_MDIC_READY) break;
3585 if (!(mdic & E1000_MDIC_READY)) {
3586 DEBUGOUT("MDI Write did not complete\n");
3587 return -E1000_ERR_PHY;
3590 /* We'll need to use the SW defined pins to shift the write command
3591 * out to the PHY. We first send a preamble to the PHY to signal the
3592 * beginning of the MII instruction. This is done by sending 32
3593 * consecutive "1" bits.
3595 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3597 /* Now combine the remaining required fields that will indicate a
3598 * write operation. We use this method instead of calling the
3599 * e1000_shift_out_mdi_bits routine for each field in the command. The
3600 * format of a MII write instruction is as follows:
3601 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3603 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3604 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3606 mdic |= (uint32_t) phy_data;
3608 e1000_shift_out_mdi_bits(hw, mdic, 32);
3611 return E1000_SUCCESS;
3615 e1000_read_kmrn_reg(struct e1000_hw *hw,
3621 DEBUGFUNC("e1000_read_kmrn_reg");
3623 if ((hw->mac_type == e1000_80003es2lan) &&
3624 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3625 swfw = E1000_SWFW_PHY1_SM;
3627 swfw = E1000_SWFW_PHY0_SM;
3629 if (e1000_swfw_sync_acquire(hw, swfw))
3630 return -E1000_ERR_SWFW_SYNC;
3632 /* Write register address */
3633 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3634 E1000_KUMCTRLSTA_OFFSET) |
3635 E1000_KUMCTRLSTA_REN;
3636 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3639 /* Read the data returned */
3640 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3641 *data = (uint16_t)reg_val;
3643 e1000_swfw_sync_release(hw, swfw);
3644 return E1000_SUCCESS;
3648 e1000_write_kmrn_reg(struct e1000_hw *hw,
3654 DEBUGFUNC("e1000_write_kmrn_reg");
3656 if ((hw->mac_type == e1000_80003es2lan) &&
3657 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3658 swfw = E1000_SWFW_PHY1_SM;
3660 swfw = E1000_SWFW_PHY0_SM;
3662 if (e1000_swfw_sync_acquire(hw, swfw))
3663 return -E1000_ERR_SWFW_SYNC;
3665 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3666 E1000_KUMCTRLSTA_OFFSET) | data;
3667 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3670 e1000_swfw_sync_release(hw, swfw);
3671 return E1000_SUCCESS;
3674 /******************************************************************************
3675 * Returns the PHY to the power-on reset state
3677 * hw - Struct containing variables accessed by shared code
3678 ******************************************************************************/
3680 e1000_phy_hw_reset(struct e1000_hw *hw)
3682 uint32_t ctrl, ctrl_ext;
3687 DEBUGFUNC("e1000_phy_hw_reset");
3689 /* In the case of the phy reset being blocked, it's not an error, we
3690 * simply return success without performing the reset. */
3691 ret_val = e1000_check_phy_reset_block(hw);
3693 return E1000_SUCCESS;
3695 DEBUGOUT("Resetting Phy...\n");
3697 if (hw->mac_type > e1000_82543) {
3698 if ((hw->mac_type == e1000_80003es2lan) &&
3699 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3700 swfw = E1000_SWFW_PHY1_SM;
3702 swfw = E1000_SWFW_PHY0_SM;
3704 if (e1000_swfw_sync_acquire(hw, swfw)) {
3705 e1000_release_software_semaphore(hw);
3706 return -E1000_ERR_SWFW_SYNC;
3708 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3709 * bit. Then, take it out of reset.
3710 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3711 * and deassert. For e1000_82571 hardware and later, we instead delay
3712 * for 50us between and 10ms after the deassertion.
3714 ctrl = E1000_READ_REG(hw, CTRL);
3715 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3716 E1000_WRITE_FLUSH(hw);
3718 if (hw->mac_type < e1000_82571)
3723 E1000_WRITE_REG(hw, CTRL, ctrl);
3724 E1000_WRITE_FLUSH(hw);
3726 if (hw->mac_type >= e1000_82571)
3729 e1000_swfw_sync_release(hw, swfw);
3731 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3732 * bit to put the PHY into reset. Then, take it out of reset.
3734 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3735 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3736 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3737 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3738 E1000_WRITE_FLUSH(hw);
3740 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3741 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3742 E1000_WRITE_FLUSH(hw);
3746 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3747 /* Configure activity LED after PHY reset */
3748 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3749 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3750 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3751 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3754 /* Wait for FW to finish PHY configuration. */
3755 ret_val = e1000_get_phy_cfg_done(hw);
3756 if (ret_val != E1000_SUCCESS)
3758 e1000_release_software_semaphore(hw);
3760 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3761 ret_val = e1000_init_lcd_from_nvm(hw);
3766 /******************************************************************************
3769 * hw - Struct containing variables accessed by shared code
3771 * Sets bit 15 of the MII Control regiser
3772 ******************************************************************************/
3774 e1000_phy_reset(struct e1000_hw *hw)
3779 DEBUGFUNC("e1000_phy_reset");
3781 /* In the case of the phy reset being blocked, it's not an error, we
3782 * simply return success without performing the reset. */
3783 ret_val = e1000_check_phy_reset_block(hw);
3785 return E1000_SUCCESS;
3787 switch (hw->mac_type) {
3788 case e1000_82541_rev_2:
3792 ret_val = e1000_phy_hw_reset(hw);
3797 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3801 phy_data |= MII_CR_RESET;
3802 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3810 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3811 e1000_phy_init_script(hw);
3813 return E1000_SUCCESS;
3816 /******************************************************************************
3817 * Work-around for 82566 power-down: on D3 entry-
3818 * 1) disable gigabit link
3819 * 2) write VR power-down enable
3821 * if successful continue, else issue LCD reset and repeat
3823 * hw - struct containing variables accessed by shared code
3824 ******************************************************************************/
3826 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3832 DEBUGFUNC("e1000_phy_powerdown_workaround");
3834 if (hw->phy_type != e1000_phy_igp_3)
3839 reg = E1000_READ_REG(hw, PHY_CTRL);
3840 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3841 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3843 /* Write VR power-down enable */
3844 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3845 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3846 IGP3_VR_CTRL_MODE_SHUT);
3848 /* Read it back and test */
3849 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3850 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3853 /* Issue PHY reset and repeat at most one more time */
3854 reg = E1000_READ_REG(hw, CTRL);
3855 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3863 /******************************************************************************
3864 * Work-around for 82566 Kumeran PCS lock loss:
3865 * On link status change (i.e. PCI reset, speed change) and link is up and
3867 * 0) if workaround is optionally disabled do nothing
3868 * 1) wait 1ms for Kumeran link to come up
3869 * 2) check Kumeran Diagnostic register PCS lock loss bit
3870 * 3) if not set the link is locked (all is good), otherwise...
3872 * 5) repeat up to 10 times
3873 * Note: this is only called for IGP3 copper when speed is 1gb.
3875 * hw - struct containing variables accessed by shared code
3876 ******************************************************************************/
3878 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3885 if (hw->kmrn_lock_loss_workaround_disabled)
3886 return E1000_SUCCESS;
3888 /* Make sure link is up before proceeding. If not just return.
3889 * Attempting this while link is negotiating fouled up link
3891 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3892 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3894 if (phy_data & MII_SR_LINK_STATUS) {
3895 for (cnt = 0; cnt < 10; cnt++) {
3896 /* read once to clear */
3897 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3900 /* and again to get new status */
3901 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3905 /* check for PCS lock */
3906 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3907 return E1000_SUCCESS;
3909 /* Issue PHY reset */
3910 e1000_phy_hw_reset(hw);
3913 /* Disable GigE link negotiation */
3914 reg = E1000_READ_REG(hw, PHY_CTRL);
3915 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3916 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3918 /* unable to acquire PCS lock */
3919 return E1000_ERR_PHY;
3922 return E1000_SUCCESS;
3925 /******************************************************************************
3926 * Probes the expected PHY address for known PHY IDs
3928 * hw - Struct containing variables accessed by shared code
3929 ******************************************************************************/
3931 e1000_detect_gig_phy(struct e1000_hw *hw)
3933 int32_t phy_init_status, ret_val;
3934 uint16_t phy_id_high, phy_id_low;
3935 boolean_t match = FALSE;
3937 DEBUGFUNC("e1000_detect_gig_phy");
3939 /* The 82571 firmware may still be configuring the PHY. In this
3940 * case, we cannot access the PHY until the configuration is done. So
3941 * we explicitly set the PHY values. */
3942 if (hw->mac_type == e1000_82571 ||
3943 hw->mac_type == e1000_82572) {
3944 hw->phy_id = IGP01E1000_I_PHY_ID;
3945 hw->phy_type = e1000_phy_igp_2;
3946 return E1000_SUCCESS;
3949 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3950 * around that forces PHY page 0 to be set or the reads fail. The rest of
3951 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3952 * So for ESB-2 we need to have this set so our reads won't fail. If the
3953 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3954 * this out as well. */
3955 if (hw->mac_type == e1000_80003es2lan)
3956 hw->phy_type = e1000_phy_gg82563;
3958 /* Read the PHY ID Registers to identify which PHY is onboard. */
3959 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3963 hw->phy_id = (uint32_t) (phy_id_high << 16);
3965 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3969 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3970 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3972 switch (hw->mac_type) {
3974 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3977 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3981 case e1000_82545_rev_3:
3983 case e1000_82546_rev_3:
3984 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3987 case e1000_82541_rev_2:
3989 case e1000_82547_rev_2:
3990 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3993 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3995 case e1000_80003es2lan:
3996 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3999 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4000 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4001 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4002 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4005 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4006 return -E1000_ERR_CONFIG;
4008 phy_init_status = e1000_set_phy_type(hw);
4010 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4011 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4012 return E1000_SUCCESS;
4014 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4015 return -E1000_ERR_PHY;
4018 /******************************************************************************
4019 * Resets the PHY's DSP
4021 * hw - Struct containing variables accessed by shared code
4022 ******************************************************************************/
4024 e1000_phy_reset_dsp(struct e1000_hw *hw)
4027 DEBUGFUNC("e1000_phy_reset_dsp");
4030 if (hw->phy_type != e1000_phy_gg82563) {
4031 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4034 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4036 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4038 ret_val = E1000_SUCCESS;
4044 /******************************************************************************
4045 * Get PHY information from various PHY registers for igp PHY only.
4047 * hw - Struct containing variables accessed by shared code
4048 * phy_info - PHY information structure
4049 ******************************************************************************/
4051 e1000_phy_igp_get_info(struct e1000_hw *hw,
4052 struct e1000_phy_info *phy_info)
4055 uint16_t phy_data, min_length, max_length, average;
4056 e1000_rev_polarity polarity;
4058 DEBUGFUNC("e1000_phy_igp_get_info");
4060 /* The downshift status is checked only once, after link is established,
4061 * and it stored in the hw->speed_downgraded parameter. */
4062 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4064 /* IGP01E1000 does not need to support it. */
4065 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4067 /* IGP01E1000 always correct polarity reversal */
4068 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4070 /* Check polarity status */
4071 ret_val = e1000_check_polarity(hw, &polarity);
4075 phy_info->cable_polarity = polarity;
4077 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4081 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4082 IGP01E1000_PSSR_MDIX_SHIFT);
4084 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4085 IGP01E1000_PSSR_SPEED_1000MBPS) {
4086 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4087 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4091 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4092 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4093 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4094 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4095 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4096 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4098 /* Get cable length */
4099 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4103 /* Translate to old method */
4104 average = (max_length + min_length) / 2;
4106 if (average <= e1000_igp_cable_length_50)
4107 phy_info->cable_length = e1000_cable_length_50;
4108 else if (average <= e1000_igp_cable_length_80)
4109 phy_info->cable_length = e1000_cable_length_50_80;
4110 else if (average <= e1000_igp_cable_length_110)
4111 phy_info->cable_length = e1000_cable_length_80_110;
4112 else if (average <= e1000_igp_cable_length_140)
4113 phy_info->cable_length = e1000_cable_length_110_140;
4115 phy_info->cable_length = e1000_cable_length_140;
4118 return E1000_SUCCESS;
4121 /******************************************************************************
4122 * Get PHY information from various PHY registers for ife PHY only.
4124 * hw - Struct containing variables accessed by shared code
4125 * phy_info - PHY information structure
4126 ******************************************************************************/
4128 e1000_phy_ife_get_info(struct e1000_hw *hw,
4129 struct e1000_phy_info *phy_info)
4133 e1000_rev_polarity polarity;
4135 DEBUGFUNC("e1000_phy_ife_get_info");
4137 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4138 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4140 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4143 phy_info->polarity_correction =
4144 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4145 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4146 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4148 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4149 ret_val = e1000_check_polarity(hw, &polarity);
4153 /* Polarity is forced. */
4154 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4155 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4156 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4158 phy_info->cable_polarity = polarity;
4160 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4164 phy_info->mdix_mode = (e1000_auto_x_mode)
4165 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4166 IFE_PMC_MDIX_MODE_SHIFT);
4168 return E1000_SUCCESS;
4171 /******************************************************************************
4172 * Get PHY information from various PHY registers fot m88 PHY only.
4174 * hw - Struct containing variables accessed by shared code
4175 * phy_info - PHY information structure
4176 ******************************************************************************/
4178 e1000_phy_m88_get_info(struct e1000_hw *hw,
4179 struct e1000_phy_info *phy_info)
4183 e1000_rev_polarity polarity;
4185 DEBUGFUNC("e1000_phy_m88_get_info");
4187 /* The downshift status is checked only once, after link is established,
4188 * and it stored in the hw->speed_downgraded parameter. */
4189 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4191 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4195 phy_info->extended_10bt_distance =
4196 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4197 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4198 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4200 phy_info->polarity_correction =
4201 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4202 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4203 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4205 /* Check polarity status */
4206 ret_val = e1000_check_polarity(hw, &polarity);
4209 phy_info->cable_polarity = polarity;
4211 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4215 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4216 M88E1000_PSSR_MDIX_SHIFT);
4218 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4219 /* Cable Length Estimation and Local/Remote Receiver Information
4220 * are only valid at 1000 Mbps.
4222 if (hw->phy_type != e1000_phy_gg82563) {
4223 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4224 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4226 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4231 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4234 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4238 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4239 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4240 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4241 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4242 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4243 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4247 return E1000_SUCCESS;
4250 /******************************************************************************
4251 * Get PHY information from various PHY registers
4253 * hw - Struct containing variables accessed by shared code
4254 * phy_info - PHY information structure
4255 ******************************************************************************/
4257 e1000_phy_get_info(struct e1000_hw *hw,
4258 struct e1000_phy_info *phy_info)
4263 DEBUGFUNC("e1000_phy_get_info");
4265 phy_info->cable_length = e1000_cable_length_undefined;
4266 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4267 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4268 phy_info->downshift = e1000_downshift_undefined;
4269 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4270 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4271 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4272 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4274 if (hw->media_type != e1000_media_type_copper) {
4275 DEBUGOUT("PHY info is only valid for copper media\n");
4276 return -E1000_ERR_CONFIG;
4279 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4283 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4287 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4288 DEBUGOUT("PHY info is only valid if link is up\n");
4289 return -E1000_ERR_CONFIG;
4292 if (hw->phy_type == e1000_phy_igp ||
4293 hw->phy_type == e1000_phy_igp_3 ||
4294 hw->phy_type == e1000_phy_igp_2)
4295 return e1000_phy_igp_get_info(hw, phy_info);
4296 else if (hw->phy_type == e1000_phy_ife)
4297 return e1000_phy_ife_get_info(hw, phy_info);
4299 return e1000_phy_m88_get_info(hw, phy_info);
4303 e1000_validate_mdi_setting(struct e1000_hw *hw)
4305 DEBUGFUNC("e1000_validate_mdi_settings");
4307 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4308 DEBUGOUT("Invalid MDI setting detected\n");
4310 return -E1000_ERR_CONFIG;
4312 return E1000_SUCCESS;
4316 /******************************************************************************
4317 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4318 * is configured. Additionally, if this is ICH8, the flash controller GbE
4319 * registers must be mapped, or this will crash.
4321 * hw - Struct containing variables accessed by shared code
4322 *****************************************************************************/
4324 e1000_init_eeprom_params(struct e1000_hw *hw)
4326 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4327 uint32_t eecd = E1000_READ_REG(hw, EECD);
4328 int32_t ret_val = E1000_SUCCESS;
4329 uint16_t eeprom_size;
4331 DEBUGFUNC("e1000_init_eeprom_params");
4333 switch (hw->mac_type) {
4334 case e1000_82542_rev2_0:
4335 case e1000_82542_rev2_1:
4338 eeprom->type = e1000_eeprom_microwire;
4339 eeprom->word_size = 64;
4340 eeprom->opcode_bits = 3;
4341 eeprom->address_bits = 6;
4342 eeprom->delay_usec = 50;
4343 eeprom->use_eerd = FALSE;
4344 eeprom->use_eewr = FALSE;
4348 case e1000_82545_rev_3:
4350 case e1000_82546_rev_3:
4351 eeprom->type = e1000_eeprom_microwire;
4352 eeprom->opcode_bits = 3;
4353 eeprom->delay_usec = 50;
4354 if (eecd & E1000_EECD_SIZE) {
4355 eeprom->word_size = 256;
4356 eeprom->address_bits = 8;
4358 eeprom->word_size = 64;
4359 eeprom->address_bits = 6;
4361 eeprom->use_eerd = FALSE;
4362 eeprom->use_eewr = FALSE;
4365 case e1000_82541_rev_2:
4367 case e1000_82547_rev_2:
4368 if (eecd & E1000_EECD_TYPE) {
4369 eeprom->type = e1000_eeprom_spi;
4370 eeprom->opcode_bits = 8;
4371 eeprom->delay_usec = 1;
4372 if (eecd & E1000_EECD_ADDR_BITS) {
4373 eeprom->page_size = 32;
4374 eeprom->address_bits = 16;
4376 eeprom->page_size = 8;
4377 eeprom->address_bits = 8;
4380 eeprom->type = e1000_eeprom_microwire;
4381 eeprom->opcode_bits = 3;
4382 eeprom->delay_usec = 50;
4383 if (eecd & E1000_EECD_ADDR_BITS) {
4384 eeprom->word_size = 256;
4385 eeprom->address_bits = 8;
4387 eeprom->word_size = 64;
4388 eeprom->address_bits = 6;
4391 eeprom->use_eerd = FALSE;
4392 eeprom->use_eewr = FALSE;
4396 eeprom->type = e1000_eeprom_spi;
4397 eeprom->opcode_bits = 8;
4398 eeprom->delay_usec = 1;
4399 if (eecd & E1000_EECD_ADDR_BITS) {
4400 eeprom->page_size = 32;
4401 eeprom->address_bits = 16;
4403 eeprom->page_size = 8;
4404 eeprom->address_bits = 8;
4406 eeprom->use_eerd = FALSE;
4407 eeprom->use_eewr = FALSE;
4410 eeprom->type = e1000_eeprom_spi;
4411 eeprom->opcode_bits = 8;
4412 eeprom->delay_usec = 1;
4413 if (eecd & E1000_EECD_ADDR_BITS) {
4414 eeprom->page_size = 32;
4415 eeprom->address_bits = 16;
4417 eeprom->page_size = 8;
4418 eeprom->address_bits = 8;
4420 eeprom->use_eerd = TRUE;
4421 eeprom->use_eewr = TRUE;
4422 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4423 eeprom->type = e1000_eeprom_flash;
4424 eeprom->word_size = 2048;
4426 /* Ensure that the Autonomous FLASH update bit is cleared due to
4427 * Flash update issue on parts which use a FLASH for NVM. */
4428 eecd &= ~E1000_EECD_AUPDEN;
4429 E1000_WRITE_REG(hw, EECD, eecd);
4432 case e1000_80003es2lan:
4433 eeprom->type = e1000_eeprom_spi;
4434 eeprom->opcode_bits = 8;
4435 eeprom->delay_usec = 1;
4436 if (eecd & E1000_EECD_ADDR_BITS) {
4437 eeprom->page_size = 32;
4438 eeprom->address_bits = 16;
4440 eeprom->page_size = 8;
4441 eeprom->address_bits = 8;
4443 eeprom->use_eerd = TRUE;
4444 eeprom->use_eewr = FALSE;
4449 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4451 eeprom->type = e1000_eeprom_ich8;
4452 eeprom->use_eerd = FALSE;
4453 eeprom->use_eewr = FALSE;
4454 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4456 /* Zero the shadow RAM structure. But don't load it from NVM
4457 * so as to save time for driver init */
4458 if (hw->eeprom_shadow_ram != NULL) {
4459 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4460 hw->eeprom_shadow_ram[i].modified = FALSE;
4461 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4465 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4466 ICH8_FLASH_SECTOR_SIZE;
4468 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4469 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4470 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4471 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4479 if (eeprom->type == e1000_eeprom_spi) {
4480 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4481 * 32KB (incremented by powers of 2).
4483 if (hw->mac_type <= e1000_82547_rev_2) {
4484 /* Set to default value for initial eeprom read. */
4485 eeprom->word_size = 64;
4486 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4489 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4490 /* 256B eeprom size was not supported in earlier hardware, so we
4491 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4492 * is never the result used in the shifting logic below. */
4496 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4497 E1000_EECD_SIZE_EX_SHIFT);
4500 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4505 /******************************************************************************
4506 * Raises the EEPROM's clock input.
4508 * hw - Struct containing variables accessed by shared code
4509 * eecd - EECD's current value
4510 *****************************************************************************/
4512 e1000_raise_ee_clk(struct e1000_hw *hw,
4515 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4516 * wait <delay> microseconds.
4518 *eecd = *eecd | E1000_EECD_SK;
4519 E1000_WRITE_REG(hw, EECD, *eecd);
4520 E1000_WRITE_FLUSH(hw);
4521 udelay(hw->eeprom.delay_usec);
4524 /******************************************************************************
4525 * Lowers the EEPROM's clock input.
4527 * hw - Struct containing variables accessed by shared code
4528 * eecd - EECD's current value
4529 *****************************************************************************/
4531 e1000_lower_ee_clk(struct e1000_hw *hw,
4534 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4535 * wait 50 microseconds.
4537 *eecd = *eecd & ~E1000_EECD_SK;
4538 E1000_WRITE_REG(hw, EECD, *eecd);
4539 E1000_WRITE_FLUSH(hw);
4540 udelay(hw->eeprom.delay_usec);
4543 /******************************************************************************
4544 * Shift data bits out to the EEPROM.
4546 * hw - Struct containing variables accessed by shared code
4547 * data - data to send to the EEPROM
4548 * count - number of bits to shift out
4549 *****************************************************************************/
4551 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4555 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4559 /* We need to shift "count" bits out to the EEPROM. So, value in the
4560 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4561 * In order to do this, "data" must be broken down into bits.
4563 mask = 0x01 << (count - 1);
4564 eecd = E1000_READ_REG(hw, EECD);
4565 if (eeprom->type == e1000_eeprom_microwire) {
4566 eecd &= ~E1000_EECD_DO;
4567 } else if (eeprom->type == e1000_eeprom_spi) {
4568 eecd |= E1000_EECD_DO;
4571 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4572 * and then raising and then lowering the clock (the SK bit controls
4573 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4574 * by setting "DI" to "0" and then raising and then lowering the clock.
4576 eecd &= ~E1000_EECD_DI;
4579 eecd |= E1000_EECD_DI;
4581 E1000_WRITE_REG(hw, EECD, eecd);
4582 E1000_WRITE_FLUSH(hw);
4584 udelay(eeprom->delay_usec);
4586 e1000_raise_ee_clk(hw, &eecd);
4587 e1000_lower_ee_clk(hw, &eecd);
4593 /* We leave the "DI" bit set to "0" when we leave this routine. */
4594 eecd &= ~E1000_EECD_DI;
4595 E1000_WRITE_REG(hw, EECD, eecd);
4598 /******************************************************************************
4599 * Shift data bits in from the EEPROM
4601 * hw - Struct containing variables accessed by shared code
4602 *****************************************************************************/
4604 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4611 /* In order to read a register from the EEPROM, we need to shift 'count'
4612 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4613 * input to the EEPROM (setting the SK bit), and then reading the value of
4614 * the "DO" bit. During this "shifting in" process the "DI" bit should
4618 eecd = E1000_READ_REG(hw, EECD);
4620 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4623 for (i = 0; i < count; i++) {
4625 e1000_raise_ee_clk(hw, &eecd);
4627 eecd = E1000_READ_REG(hw, EECD);
4629 eecd &= ~(E1000_EECD_DI);
4630 if (eecd & E1000_EECD_DO)
4633 e1000_lower_ee_clk(hw, &eecd);
4639 /******************************************************************************
4640 * Prepares EEPROM for access
4642 * hw - Struct containing variables accessed by shared code
4644 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4645 * function should be called before issuing a command to the EEPROM.
4646 *****************************************************************************/
4648 e1000_acquire_eeprom(struct e1000_hw *hw)
4650 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4653 DEBUGFUNC("e1000_acquire_eeprom");
4655 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4656 return -E1000_ERR_SWFW_SYNC;
4657 eecd = E1000_READ_REG(hw, EECD);
4659 if (hw->mac_type != e1000_82573) {
4660 /* Request EEPROM Access */
4661 if (hw->mac_type > e1000_82544) {
4662 eecd |= E1000_EECD_REQ;
4663 E1000_WRITE_REG(hw, EECD, eecd);
4664 eecd = E1000_READ_REG(hw, EECD);
4665 while ((!(eecd & E1000_EECD_GNT)) &&
4666 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4669 eecd = E1000_READ_REG(hw, EECD);
4671 if (!(eecd & E1000_EECD_GNT)) {
4672 eecd &= ~E1000_EECD_REQ;
4673 E1000_WRITE_REG(hw, EECD, eecd);
4674 DEBUGOUT("Could not acquire EEPROM grant\n");
4675 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4676 return -E1000_ERR_EEPROM;
4681 /* Setup EEPROM for Read/Write */
4683 if (eeprom->type == e1000_eeprom_microwire) {
4684 /* Clear SK and DI */
4685 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4686 E1000_WRITE_REG(hw, EECD, eecd);
4689 eecd |= E1000_EECD_CS;
4690 E1000_WRITE_REG(hw, EECD, eecd);
4691 } else if (eeprom->type == e1000_eeprom_spi) {
4692 /* Clear SK and CS */
4693 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4694 E1000_WRITE_REG(hw, EECD, eecd);
4698 return E1000_SUCCESS;
4701 /******************************************************************************
4702 * Returns EEPROM to a "standby" state
4704 * hw - Struct containing variables accessed by shared code
4705 *****************************************************************************/
4707 e1000_standby_eeprom(struct e1000_hw *hw)
4709 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4712 eecd = E1000_READ_REG(hw, EECD);
4714 if (eeprom->type == e1000_eeprom_microwire) {
4715 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4716 E1000_WRITE_REG(hw, EECD, eecd);
4717 E1000_WRITE_FLUSH(hw);
4718 udelay(eeprom->delay_usec);
4721 eecd |= E1000_EECD_SK;
4722 E1000_WRITE_REG(hw, EECD, eecd);
4723 E1000_WRITE_FLUSH(hw);
4724 udelay(eeprom->delay_usec);
4727 eecd |= E1000_EECD_CS;
4728 E1000_WRITE_REG(hw, EECD, eecd);
4729 E1000_WRITE_FLUSH(hw);
4730 udelay(eeprom->delay_usec);
4733 eecd &= ~E1000_EECD_SK;
4734 E1000_WRITE_REG(hw, EECD, eecd);
4735 E1000_WRITE_FLUSH(hw);
4736 udelay(eeprom->delay_usec);
4737 } else if (eeprom->type == e1000_eeprom_spi) {
4738 /* Toggle CS to flush commands */
4739 eecd |= E1000_EECD_CS;
4740 E1000_WRITE_REG(hw, EECD, eecd);
4741 E1000_WRITE_FLUSH(hw);
4742 udelay(eeprom->delay_usec);
4743 eecd &= ~E1000_EECD_CS;
4744 E1000_WRITE_REG(hw, EECD, eecd);
4745 E1000_WRITE_FLUSH(hw);
4746 udelay(eeprom->delay_usec);
4750 /******************************************************************************
4751 * Terminates a command by inverting the EEPROM's chip select pin
4753 * hw - Struct containing variables accessed by shared code
4754 *****************************************************************************/
4756 e1000_release_eeprom(struct e1000_hw *hw)
4760 DEBUGFUNC("e1000_release_eeprom");
4762 eecd = E1000_READ_REG(hw, EECD);
4764 if (hw->eeprom.type == e1000_eeprom_spi) {
4765 eecd |= E1000_EECD_CS; /* Pull CS high */
4766 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4768 E1000_WRITE_REG(hw, EECD, eecd);
4770 udelay(hw->eeprom.delay_usec);
4771 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4772 /* cleanup eeprom */
4774 /* CS on Microwire is active-high */
4775 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4777 E1000_WRITE_REG(hw, EECD, eecd);
4779 /* Rising edge of clock */
4780 eecd |= E1000_EECD_SK;
4781 E1000_WRITE_REG(hw, EECD, eecd);
4782 E1000_WRITE_FLUSH(hw);
4783 udelay(hw->eeprom.delay_usec);
4785 /* Falling edge of clock */
4786 eecd &= ~E1000_EECD_SK;
4787 E1000_WRITE_REG(hw, EECD, eecd);
4788 E1000_WRITE_FLUSH(hw);
4789 udelay(hw->eeprom.delay_usec);
4792 /* Stop requesting EEPROM access */
4793 if (hw->mac_type > e1000_82544) {
4794 eecd &= ~E1000_EECD_REQ;
4795 E1000_WRITE_REG(hw, EECD, eecd);
4798 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4801 /******************************************************************************
4802 * Reads a 16 bit word from the EEPROM.
4804 * hw - Struct containing variables accessed by shared code
4805 *****************************************************************************/
4807 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4809 uint16_t retry_count = 0;
4810 uint8_t spi_stat_reg;
4812 DEBUGFUNC("e1000_spi_eeprom_ready");
4814 /* Read "Status Register" repeatedly until the LSB is cleared. The
4815 * EEPROM will signal that the command has been completed by clearing
4816 * bit 0 of the internal status register. If it's not cleared within
4817 * 5 milliseconds, then error out.
4821 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4822 hw->eeprom.opcode_bits);
4823 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4824 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4830 e1000_standby_eeprom(hw);
4831 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4833 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4834 * only 0-5mSec on 5V devices)
4836 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4837 DEBUGOUT("SPI EEPROM Status error\n");
4838 return -E1000_ERR_EEPROM;
4841 return E1000_SUCCESS;
4844 /******************************************************************************
4845 * Reads a 16 bit word from the EEPROM.
4847 * hw - Struct containing variables accessed by shared code
4848 * offset - offset of word in the EEPROM to read
4849 * data - word read from the EEPROM
4850 * words - number of words to read
4851 *****************************************************************************/
4853 e1000_read_eeprom(struct e1000_hw *hw,
4858 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4862 DEBUGFUNC("e1000_read_eeprom");
4864 /* A check for invalid values: offset too large, too many words, and not
4867 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4869 DEBUGOUT("\"words\" parameter out of bounds\n");
4870 return -E1000_ERR_EEPROM;
4873 /* FLASH reads without acquiring the semaphore are safe */
4874 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
4875 hw->eeprom.use_eerd == FALSE) {
4876 switch (hw->mac_type) {
4877 case e1000_80003es2lan:
4880 /* Prepare the EEPROM for reading */
4881 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4882 return -E1000_ERR_EEPROM;
4887 if (eeprom->use_eerd == TRUE) {
4888 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4889 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4890 (hw->mac_type != e1000_82573))
4891 e1000_release_eeprom(hw);
4895 if (eeprom->type == e1000_eeprom_ich8)
4896 return e1000_read_eeprom_ich8(hw, offset, words, data);
4898 if (eeprom->type == e1000_eeprom_spi) {
4900 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4902 if (e1000_spi_eeprom_ready(hw)) {
4903 e1000_release_eeprom(hw);
4904 return -E1000_ERR_EEPROM;
4907 e1000_standby_eeprom(hw);
4909 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4910 if ((eeprom->address_bits == 8) && (offset >= 128))
4911 read_opcode |= EEPROM_A8_OPCODE_SPI;
4913 /* Send the READ command (opcode + addr) */
4914 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4915 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4917 /* Read the data. The address of the eeprom internally increments with
4918 * each byte (spi) being read, saving on the overhead of eeprom setup
4919 * and tear-down. The address counter will roll over if reading beyond
4920 * the size of the eeprom, thus allowing the entire memory to be read
4921 * starting from any offset. */
4922 for (i = 0; i < words; i++) {
4923 word_in = e1000_shift_in_ee_bits(hw, 16);
4924 data[i] = (word_in >> 8) | (word_in << 8);
4926 } else if (eeprom->type == e1000_eeprom_microwire) {
4927 for (i = 0; i < words; i++) {
4928 /* Send the READ command (opcode + addr) */
4929 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4930 eeprom->opcode_bits);
4931 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4932 eeprom->address_bits);
4934 /* Read the data. For microwire, each word requires the overhead
4935 * of eeprom setup and tear-down. */
4936 data[i] = e1000_shift_in_ee_bits(hw, 16);
4937 e1000_standby_eeprom(hw);
4941 /* End this read operation */
4942 e1000_release_eeprom(hw);
4944 return E1000_SUCCESS;
4947 /******************************************************************************
4948 * Reads a 16 bit word from the EEPROM using the EERD register.
4950 * hw - Struct containing variables accessed by shared code
4951 * offset - offset of word in the EEPROM to read
4952 * data - word read from the EEPROM
4953 * words - number of words to read
4954 *****************************************************************************/
4956 e1000_read_eeprom_eerd(struct e1000_hw *hw,
4961 uint32_t i, eerd = 0;
4964 for (i = 0; i < words; i++) {
4965 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4966 E1000_EEPROM_RW_REG_START;
4968 E1000_WRITE_REG(hw, EERD, eerd);
4969 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
4974 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
4981 /******************************************************************************
4982 * Writes a 16 bit word from the EEPROM using the EEWR register.
4984 * hw - Struct containing variables accessed by shared code
4985 * offset - offset of word in the EEPROM to read
4986 * data - word read from the EEPROM
4987 * words - number of words to read
4988 *****************************************************************************/
4990 e1000_write_eeprom_eewr(struct e1000_hw *hw,
4995 uint32_t register_value = 0;
4999 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5000 return -E1000_ERR_SWFW_SYNC;
5002 for (i = 0; i < words; i++) {
5003 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5004 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5005 E1000_EEPROM_RW_REG_START;
5007 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5012 E1000_WRITE_REG(hw, EEWR, register_value);
5014 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5021 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5025 /******************************************************************************
5026 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5028 * hw - Struct containing variables accessed by shared code
5029 *****************************************************************************/
5031 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5033 uint32_t attempts = 100000;
5034 uint32_t i, reg = 0;
5035 int32_t done = E1000_ERR_EEPROM;
5037 for (i = 0; i < attempts; i++) {
5038 if (eerd == E1000_EEPROM_POLL_READ)
5039 reg = E1000_READ_REG(hw, EERD);
5041 reg = E1000_READ_REG(hw, EEWR);
5043 if (reg & E1000_EEPROM_RW_REG_DONE) {
5044 done = E1000_SUCCESS;
5053 /***************************************************************************
5054 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5056 * hw - Struct containing variables accessed by shared code
5057 ****************************************************************************/
5059 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5063 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5065 if (hw->mac_type == e1000_ich8lan)
5068 if (hw->mac_type == e1000_82573) {
5069 eecd = E1000_READ_REG(hw, EECD);
5071 /* Isolate bits 15 & 16 */
5072 eecd = ((eecd >> 15) & 0x03);
5074 /* If both bits are set, device is Flash type */
5082 /******************************************************************************
5083 * Verifies that the EEPROM has a valid checksum
5085 * hw - Struct containing variables accessed by shared code
5087 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5088 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5090 *****************************************************************************/
5092 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5094 uint16_t checksum = 0;
5095 uint16_t i, eeprom_data;
5097 DEBUGFUNC("e1000_validate_eeprom_checksum");
5099 if ((hw->mac_type == e1000_82573) &&
5100 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5101 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5102 * 10h-12h. Checksum may need to be fixed. */
5103 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5104 if ((eeprom_data & 0x10) == 0) {
5105 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5106 * has already been fixed. If the checksum is still wrong and this
5107 * bit is a 1, we need to return bad checksum. Otherwise, we need
5108 * to set this bit to a 1 and update the checksum. */
5109 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5110 if ((eeprom_data & 0x8000) == 0) {
5111 eeprom_data |= 0x8000;
5112 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5113 e1000_update_eeprom_checksum(hw);
5118 if (hw->mac_type == e1000_ich8lan) {
5119 /* Drivers must allocate the shadow ram structure for the
5120 * EEPROM checksum to be updated. Otherwise, this bit as well
5121 * as the checksum must both be set correctly for this
5122 * validation to pass.
5124 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5125 if ((eeprom_data & 0x40) == 0) {
5126 eeprom_data |= 0x40;
5127 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5128 e1000_update_eeprom_checksum(hw);
5132 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5133 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5134 DEBUGOUT("EEPROM Read Error\n");
5135 return -E1000_ERR_EEPROM;
5137 checksum += eeprom_data;
5140 if (checksum == (uint16_t) EEPROM_SUM)
5141 return E1000_SUCCESS;
5143 DEBUGOUT("EEPROM Checksum Invalid\n");
5144 return -E1000_ERR_EEPROM;
5148 /******************************************************************************
5149 * Calculates the EEPROM checksum and writes it to the EEPROM
5151 * hw - Struct containing variables accessed by shared code
5153 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5154 * Writes the difference to word offset 63 of the EEPROM.
5155 *****************************************************************************/
5157 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5160 uint16_t checksum = 0;
5161 uint16_t i, eeprom_data;
5163 DEBUGFUNC("e1000_update_eeprom_checksum");
5165 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5166 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5167 DEBUGOUT("EEPROM Read Error\n");
5168 return -E1000_ERR_EEPROM;
5170 checksum += eeprom_data;
5172 checksum = (uint16_t) EEPROM_SUM - checksum;
5173 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5174 DEBUGOUT("EEPROM Write Error\n");
5175 return -E1000_ERR_EEPROM;
5176 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5177 e1000_commit_shadow_ram(hw);
5178 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5179 e1000_commit_shadow_ram(hw);
5180 /* Reload the EEPROM, or else modifications will not appear
5181 * until after next adapter reset. */
5182 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5183 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5184 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5187 return E1000_SUCCESS;
5190 /******************************************************************************
5191 * Parent function for writing words to the different EEPROM types.
5193 * hw - Struct containing variables accessed by shared code
5194 * offset - offset within the EEPROM to be written to
5195 * words - number of words to write
5196 * data - 16 bit word to be written to the EEPROM
5198 * If e1000_update_eeprom_checksum is not called after this function, the
5199 * EEPROM will most likely contain an invalid checksum.
5200 *****************************************************************************/
5202 e1000_write_eeprom(struct e1000_hw *hw,
5207 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5210 DEBUGFUNC("e1000_write_eeprom");
5212 /* A check for invalid values: offset too large, too many words, and not
5215 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5217 DEBUGOUT("\"words\" parameter out of bounds\n");
5218 return -E1000_ERR_EEPROM;
5221 /* 82573 writes only through eewr */
5222 if (eeprom->use_eewr == TRUE)
5223 return e1000_write_eeprom_eewr(hw, offset, words, data);
5225 if (eeprom->type == e1000_eeprom_ich8)
5226 return e1000_write_eeprom_ich8(hw, offset, words, data);
5228 /* Prepare the EEPROM for writing */
5229 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5230 return -E1000_ERR_EEPROM;
5232 if (eeprom->type == e1000_eeprom_microwire) {
5233 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5235 status = e1000_write_eeprom_spi(hw, offset, words, data);
5239 /* Done with writing */
5240 e1000_release_eeprom(hw);
5245 /******************************************************************************
5246 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5248 * hw - Struct containing variables accessed by shared code
5249 * offset - offset within the EEPROM to be written to
5250 * words - number of words to write
5251 * data - pointer to array of 8 bit words to be written to the EEPROM
5253 *****************************************************************************/
5255 e1000_write_eeprom_spi(struct e1000_hw *hw,
5260 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5263 DEBUGFUNC("e1000_write_eeprom_spi");
5265 while (widx < words) {
5266 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5268 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5270 e1000_standby_eeprom(hw);
5272 /* Send the WRITE ENABLE command (8 bit opcode ) */
5273 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5274 eeprom->opcode_bits);
5276 e1000_standby_eeprom(hw);
5278 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5279 if ((eeprom->address_bits == 8) && (offset >= 128))
5280 write_opcode |= EEPROM_A8_OPCODE_SPI;
5282 /* Send the Write command (8-bit opcode + addr) */
5283 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5285 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5286 eeprom->address_bits);
5290 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5291 while (widx < words) {
5292 uint16_t word_out = data[widx];
5293 word_out = (word_out >> 8) | (word_out << 8);
5294 e1000_shift_out_ee_bits(hw, word_out, 16);
5297 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5298 * operation, while the smaller eeproms are capable of an 8-byte
5299 * PAGE WRITE operation. Break the inner loop to pass new address
5301 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5302 e1000_standby_eeprom(hw);
5308 return E1000_SUCCESS;
5311 /******************************************************************************
5312 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5314 * hw - Struct containing variables accessed by shared code
5315 * offset - offset within the EEPROM to be written to
5316 * words - number of words to write
5317 * data - pointer to array of 16 bit words to be written to the EEPROM
5319 *****************************************************************************/
5321 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5326 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5328 uint16_t words_written = 0;
5331 DEBUGFUNC("e1000_write_eeprom_microwire");
5333 /* Send the write enable command to the EEPROM (3-bit opcode plus
5334 * 6/8-bit dummy address beginning with 11). It's less work to include
5335 * the 11 of the dummy address as part of the opcode than it is to shift
5336 * it over the correct number of bits for the address. This puts the
5337 * EEPROM into write/erase mode.
5339 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5340 (uint16_t)(eeprom->opcode_bits + 2));
5342 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5344 /* Prepare the EEPROM */
5345 e1000_standby_eeprom(hw);
5347 while (words_written < words) {
5348 /* Send the Write command (3-bit opcode + addr) */
5349 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5350 eeprom->opcode_bits);
5352 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5353 eeprom->address_bits);
5356 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5358 /* Toggle the CS line. This in effect tells the EEPROM to execute
5359 * the previous command.
5361 e1000_standby_eeprom(hw);
5363 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5364 * signal that the command has been completed by raising the DO signal.
5365 * If DO does not go high in 10 milliseconds, then error out.
5367 for (i = 0; i < 200; i++) {
5368 eecd = E1000_READ_REG(hw, EECD);
5369 if (eecd & E1000_EECD_DO) break;
5373 DEBUGOUT("EEPROM Write did not complete\n");
5374 return -E1000_ERR_EEPROM;
5377 /* Recover from write */
5378 e1000_standby_eeprom(hw);
5383 /* Send the write disable command to the EEPROM (3-bit opcode plus
5384 * 6/8-bit dummy address beginning with 10). It's less work to include
5385 * the 10 of the dummy address as part of the opcode than it is to shift
5386 * it over the correct number of bits for the address. This takes the
5387 * EEPROM out of write/erase mode.
5389 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5390 (uint16_t)(eeprom->opcode_bits + 2));
5392 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5394 return E1000_SUCCESS;
5397 /******************************************************************************
5398 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5399 * in the eeprom cache and the non modified values in the currently active bank
5402 * hw - Struct containing variables accessed by shared code
5403 * offset - offset of word in the EEPROM to read
5404 * data - word read from the EEPROM
5405 * words - number of words to read
5406 *****************************************************************************/
5408 e1000_commit_shadow_ram(struct e1000_hw *hw)
5410 uint32_t attempts = 100000;
5414 int32_t error = E1000_SUCCESS;
5415 uint32_t old_bank_offset = 0;
5416 uint32_t new_bank_offset = 0;
5417 uint32_t sector_retries = 0;
5418 uint8_t low_byte = 0;
5419 uint8_t high_byte = 0;
5420 uint8_t temp_byte = 0;
5421 boolean_t sector_write_failed = FALSE;
5423 if (hw->mac_type == e1000_82573) {
5424 /* The flop register will be used to determine if flash type is STM */
5425 flop = E1000_READ_REG(hw, FLOP);
5426 for (i=0; i < attempts; i++) {
5427 eecd = E1000_READ_REG(hw, EECD);
5428 if ((eecd & E1000_EECD_FLUPD) == 0) {
5434 if (i == attempts) {
5435 return -E1000_ERR_EEPROM;
5438 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5439 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5440 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5443 /* Perform the flash update */
5444 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5446 for (i=0; i < attempts; i++) {
5447 eecd = E1000_READ_REG(hw, EECD);
5448 if ((eecd & E1000_EECD_FLUPD) == 0) {
5454 if (i == attempts) {
5455 return -E1000_ERR_EEPROM;
5459 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5460 /* We're writing to the opposite bank so if we're on bank 1,
5461 * write to bank 0 etc. We also need to erase the segment that
5462 * is going to be written */
5463 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5464 new_bank_offset = hw->flash_bank_size * 2;
5465 old_bank_offset = 0;
5466 e1000_erase_ich8_4k_segment(hw, 1);
5468 old_bank_offset = hw->flash_bank_size * 2;
5469 new_bank_offset = 0;
5470 e1000_erase_ich8_4k_segment(hw, 0);
5474 sector_write_failed = FALSE;
5475 /* Loop for every byte in the shadow RAM,
5476 * which is in units of words. */
5477 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5478 /* Determine whether to write the value stored
5479 * in the other NVM bank or a modified value stored
5480 * in the shadow RAM */
5481 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5482 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5483 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5486 error = e1000_verify_write_ich8_byte(hw,
5487 (i << 1) + new_bank_offset,
5489 if (error != E1000_SUCCESS)
5490 sector_write_failed = TRUE;
5492 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5493 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5497 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5500 error = e1000_verify_write_ich8_byte(hw,
5501 (i << 1) + new_bank_offset, low_byte);
5502 if (error != E1000_SUCCESS)
5503 sector_write_failed = TRUE;
5504 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5508 /* If the word is 0x13, then make sure the signature bits
5509 * (15:14) are 11b until the commit has completed.
5510 * This will allow us to write 10b which indicates the
5511 * signature is valid. We want to do this after the write
5512 * has completed so that we don't mark the segment valid
5513 * while the write is still in progress */
5514 if (i == E1000_ICH8_NVM_SIG_WORD)
5515 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5517 error = e1000_verify_write_ich8_byte(hw,
5518 (i << 1) + new_bank_offset + 1, high_byte);
5519 if (error != E1000_SUCCESS)
5520 sector_write_failed = TRUE;
5522 if (sector_write_failed == FALSE) {
5523 /* Clear the now not used entry in the cache */
5524 hw->eeprom_shadow_ram[i].modified = FALSE;
5525 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5529 /* Don't bother writing the segment valid bits if sector
5530 * programming failed. */
5531 if (sector_write_failed == FALSE) {
5532 /* Finally validate the new segment by setting bit 15:14
5533 * to 10b in word 0x13 , this can be done without an
5534 * erase as well since these bits are 11 to start with
5535 * and we need to change bit 14 to 0b */
5536 e1000_read_ich8_byte(hw,
5537 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5540 error = e1000_verify_write_ich8_byte(hw,
5541 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5543 if (error != E1000_SUCCESS)
5544 sector_write_failed = TRUE;
5546 /* And invalidate the previously valid segment by setting
5547 * its signature word (0x13) high_byte to 0b. This can be
5548 * done without an erase because flash erase sets all bits
5549 * to 1's. We can write 1's to 0's without an erase */
5550 error = e1000_verify_write_ich8_byte(hw,
5551 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5553 if (error != E1000_SUCCESS)
5554 sector_write_failed = TRUE;
5556 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5562 /******************************************************************************
5563 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5564 * second function of dual function devices
5566 * hw - Struct containing variables accessed by shared code
5567 *****************************************************************************/
5569 e1000_read_mac_addr(struct e1000_hw * hw)
5572 uint16_t eeprom_data, i;
5574 DEBUGFUNC("e1000_read_mac_addr");
5576 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5578 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5579 DEBUGOUT("EEPROM Read Error\n");
5580 return -E1000_ERR_EEPROM;
5582 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5583 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5586 switch (hw->mac_type) {
5590 case e1000_82546_rev_3:
5592 case e1000_80003es2lan:
5593 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5594 hw->perm_mac_addr[5] ^= 0x01;
5598 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5599 hw->mac_addr[i] = hw->perm_mac_addr[i];
5600 return E1000_SUCCESS;
5603 /******************************************************************************
5604 * Initializes receive address filters.
5606 * hw - Struct containing variables accessed by shared code
5608 * Places the MAC address in receive address register 0 and clears the rest
5609 * of the receive addresss registers. Clears the multicast table. Assumes
5610 * the receiver is in reset when the routine is called.
5611 *****************************************************************************/
5613 e1000_init_rx_addrs(struct e1000_hw *hw)
5618 DEBUGFUNC("e1000_init_rx_addrs");
5620 /* Setup the receive address. */
5621 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5623 e1000_rar_set(hw, hw->mac_addr, 0);
5625 rar_num = E1000_RAR_ENTRIES;
5627 /* Reserve a spot for the Locally Administered Address to work around
5628 * an 82571 issue in which a reset on one port will reload the MAC on
5629 * the other port. */
5630 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5632 if (hw->mac_type == e1000_ich8lan)
5633 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5635 /* Zero out the other 15 receive addresses. */
5636 DEBUGOUT("Clearing RAR[1-15]\n");
5637 for (i = 1; i < rar_num; i++) {
5638 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5639 E1000_WRITE_FLUSH(hw);
5640 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5641 E1000_WRITE_FLUSH(hw);
5645 /******************************************************************************
5646 * Hashes an address to determine its location in the multicast table
5648 * hw - Struct containing variables accessed by shared code
5649 * mc_addr - the multicast address to hash
5650 *****************************************************************************/
5652 e1000_hash_mc_addr(struct e1000_hw *hw,
5655 uint32_t hash_value = 0;
5657 /* The portion of the address that is used for the hash table is
5658 * determined by the mc_filter_type setting.
5660 switch (hw->mc_filter_type) {
5661 /* [0] [1] [2] [3] [4] [5]
5666 if (hw->mac_type == e1000_ich8lan) {
5667 /* [47:38] i.e. 0x158 for above example address */
5668 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5670 /* [47:36] i.e. 0x563 for above example address */
5671 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5675 if (hw->mac_type == e1000_ich8lan) {
5676 /* [46:37] i.e. 0x2B1 for above example address */
5677 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5679 /* [46:35] i.e. 0xAC6 for above example address */
5680 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5684 if (hw->mac_type == e1000_ich8lan) {
5685 /*[45:36] i.e. 0x163 for above example address */
5686 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5688 /* [45:34] i.e. 0x5D8 for above example address */
5689 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5693 if (hw->mac_type == e1000_ich8lan) {
5694 /* [43:34] i.e. 0x18D for above example address */
5695 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5697 /* [43:32] i.e. 0x634 for above example address */
5698 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5703 hash_value &= 0xFFF;
5704 if (hw->mac_type == e1000_ich8lan)
5705 hash_value &= 0x3FF;
5710 /******************************************************************************
5711 * Sets the bit in the multicast table corresponding to the hash value.
5713 * hw - Struct containing variables accessed by shared code
5714 * hash_value - Multicast address hash value
5715 *****************************************************************************/
5717 e1000_mta_set(struct e1000_hw *hw,
5718 uint32_t hash_value)
5720 uint32_t hash_bit, hash_reg;
5724 /* The MTA is a register array of 128 32-bit registers.
5725 * It is treated like an array of 4096 bits. We want to set
5726 * bit BitArray[hash_value]. So we figure out what register
5727 * the bit is in, read it, OR in the new bit, then write
5728 * back the new value. The register is determined by the
5729 * upper 7 bits of the hash value and the bit within that
5730 * register are determined by the lower 5 bits of the value.
5732 hash_reg = (hash_value >> 5) & 0x7F;
5733 if (hw->mac_type == e1000_ich8lan)
5735 hash_bit = hash_value & 0x1F;
5737 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5739 mta |= (1 << hash_bit);
5741 /* If we are on an 82544 and we are trying to write an odd offset
5742 * in the MTA, save off the previous entry before writing and
5743 * restore the old value after writing.
5745 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5746 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5747 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5748 E1000_WRITE_FLUSH(hw);
5749 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5750 E1000_WRITE_FLUSH(hw);
5752 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5753 E1000_WRITE_FLUSH(hw);
5757 /******************************************************************************
5758 * Puts an ethernet address into a receive address register.
5760 * hw - Struct containing variables accessed by shared code
5761 * addr - Address to put into receive address register
5762 * index - Receive address register to write
5763 *****************************************************************************/
5765 e1000_rar_set(struct e1000_hw *hw,
5769 uint32_t rar_low, rar_high;
5771 /* HW expects these in little endian so we reverse the byte order
5772 * from network order (big endian) to little endian
5774 rar_low = ((uint32_t) addr[0] |
5775 ((uint32_t) addr[1] << 8) |
5776 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5777 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5779 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5783 * If there are any Rx frames queued up or otherwise present in the HW
5784 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5785 * hang. To work around this issue, we have to disable receives and
5786 * flush out all Rx frames before we enable RSS. To do so, we modify we
5787 * redirect all Rx traffic to manageability and then reset the HW.
5788 * This flushes away Rx frames, and (since the redirections to
5789 * manageability persists across resets) keeps new ones from coming in
5790 * while we work. Then, we clear the Address Valid AV bit for all MAC
5791 * addresses and undo the re-direction to manageability.
5792 * Now, frames are coming in again, but the MAC won't accept them, so
5793 * far so good. We now proceed to initialize RSS (if necessary) and
5794 * configure the Rx unit. Last, we re-enable the AV bits and continue
5797 switch (hw->mac_type) {
5800 case e1000_80003es2lan:
5801 if (hw->leave_av_bit_off == TRUE)
5804 /* Indicate to hardware the Address is Valid. */
5805 rar_high |= E1000_RAH_AV;
5809 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5810 E1000_WRITE_FLUSH(hw);
5811 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5812 E1000_WRITE_FLUSH(hw);
5815 /******************************************************************************
5816 * Writes a value to the specified offset in the VLAN filter table.
5818 * hw - Struct containing variables accessed by shared code
5819 * offset - Offset in VLAN filer table to write
5820 * value - Value to write into VLAN filter table
5821 *****************************************************************************/
5823 e1000_write_vfta(struct e1000_hw *hw,
5829 if (hw->mac_type == e1000_ich8lan)
5832 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5833 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5834 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5835 E1000_WRITE_FLUSH(hw);
5836 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5837 E1000_WRITE_FLUSH(hw);
5839 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5840 E1000_WRITE_FLUSH(hw);
5844 /******************************************************************************
5845 * Clears the VLAN filer table
5847 * hw - Struct containing variables accessed by shared code
5848 *****************************************************************************/
5850 e1000_clear_vfta(struct e1000_hw *hw)
5853 uint32_t vfta_value = 0;
5854 uint32_t vfta_offset = 0;
5855 uint32_t vfta_bit_in_reg = 0;
5857 if (hw->mac_type == e1000_ich8lan)
5860 if (hw->mac_type == e1000_82573) {
5861 if (hw->mng_cookie.vlan_id != 0) {
5862 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5863 * ID. The following operations determine which 32b entry
5864 * (i.e. offset) into the array we want to set the VLAN ID
5865 * (i.e. bit) of the manageability unit. */
5866 vfta_offset = (hw->mng_cookie.vlan_id >>
5867 E1000_VFTA_ENTRY_SHIFT) &
5868 E1000_VFTA_ENTRY_MASK;
5869 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5870 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5873 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5874 /* If the offset we want to clear is the same offset of the
5875 * manageability VLAN ID, then clear all bits except that of the
5876 * manageability unit */
5877 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5878 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
5879 E1000_WRITE_FLUSH(hw);
5884 e1000_id_led_init(struct e1000_hw * hw)
5887 const uint32_t ledctl_mask = 0x000000FF;
5888 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5889 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5890 uint16_t eeprom_data, i, temp;
5891 const uint16_t led_mask = 0x0F;
5893 DEBUGFUNC("e1000_id_led_init");
5895 if (hw->mac_type < e1000_82540) {
5897 return E1000_SUCCESS;
5900 ledctl = E1000_READ_REG(hw, LEDCTL);
5901 hw->ledctl_default = ledctl;
5902 hw->ledctl_mode1 = hw->ledctl_default;
5903 hw->ledctl_mode2 = hw->ledctl_default;
5905 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
5906 DEBUGOUT("EEPROM Read Error\n");
5907 return -E1000_ERR_EEPROM;
5910 if ((hw->mac_type == e1000_82573) &&
5911 (eeprom_data == ID_LED_RESERVED_82573))
5912 eeprom_data = ID_LED_DEFAULT_82573;
5913 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5914 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5915 if (hw->mac_type == e1000_ich8lan)
5916 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5918 eeprom_data = ID_LED_DEFAULT;
5920 for (i = 0; i < 4; i++) {
5921 temp = (eeprom_data >> (i << 2)) & led_mask;
5923 case ID_LED_ON1_DEF2:
5924 case ID_LED_ON1_ON2:
5925 case ID_LED_ON1_OFF2:
5926 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5927 hw->ledctl_mode1 |= ledctl_on << (i << 3);
5929 case ID_LED_OFF1_DEF2:
5930 case ID_LED_OFF1_ON2:
5931 case ID_LED_OFF1_OFF2:
5932 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
5933 hw->ledctl_mode1 |= ledctl_off << (i << 3);
5940 case ID_LED_DEF1_ON2:
5941 case ID_LED_ON1_ON2:
5942 case ID_LED_OFF1_ON2:
5943 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5944 hw->ledctl_mode2 |= ledctl_on << (i << 3);
5946 case ID_LED_DEF1_OFF2:
5947 case ID_LED_ON1_OFF2:
5948 case ID_LED_OFF1_OFF2:
5949 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
5950 hw->ledctl_mode2 |= ledctl_off << (i << 3);
5957 return E1000_SUCCESS;
5960 /******************************************************************************
5961 * Prepares SW controlable LED for use and saves the current state of the LED.
5963 * hw - Struct containing variables accessed by shared code
5964 *****************************************************************************/
5966 e1000_setup_led(struct e1000_hw *hw)
5969 int32_t ret_val = E1000_SUCCESS;
5971 DEBUGFUNC("e1000_setup_led");
5973 switch (hw->mac_type) {
5974 case e1000_82542_rev2_0:
5975 case e1000_82542_rev2_1:
5978 /* No setup necessary */
5982 case e1000_82541_rev_2:
5983 case e1000_82547_rev_2:
5984 /* Turn off PHY Smart Power Down (if enabled) */
5985 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
5986 &hw->phy_spd_default);
5989 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5990 (uint16_t)(hw->phy_spd_default &
5991 ~IGP01E1000_GMII_SPD));
5996 if (hw->media_type == e1000_media_type_fiber) {
5997 ledctl = E1000_READ_REG(hw, LEDCTL);
5998 /* Save current LEDCTL settings */
5999 hw->ledctl_default = ledctl;
6001 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6002 E1000_LEDCTL_LED0_BLINK |
6003 E1000_LEDCTL_LED0_MODE_MASK);
6004 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6005 E1000_LEDCTL_LED0_MODE_SHIFT);
6006 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6007 } else if (hw->media_type == e1000_media_type_copper)
6008 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6012 return E1000_SUCCESS;
6016 /******************************************************************************
6017 * Used on 82571 and later Si that has LED blink bits.
6018 * Callers must use their own timer and should have already called
6019 * e1000_id_led_init()
6020 * Call e1000_cleanup led() to stop blinking
6022 * hw - Struct containing variables accessed by shared code
6023 *****************************************************************************/
6025 e1000_blink_led_start(struct e1000_hw *hw)
6028 uint32_t ledctl_blink = 0;
6030 DEBUGFUNC("e1000_id_led_blink_on");
6032 if (hw->mac_type < e1000_82571) {
6034 return E1000_SUCCESS;
6036 if (hw->media_type == e1000_media_type_fiber) {
6037 /* always blink LED0 for PCI-E fiber */
6038 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6039 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6041 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6042 ledctl_blink = hw->ledctl_mode2;
6043 for (i=0; i < 4; i++)
6044 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6045 E1000_LEDCTL_MODE_LED_ON)
6046 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6049 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6051 return E1000_SUCCESS;
6054 /******************************************************************************
6055 * Restores the saved state of the SW controlable LED.
6057 * hw - Struct containing variables accessed by shared code
6058 *****************************************************************************/
6060 e1000_cleanup_led(struct e1000_hw *hw)
6062 int32_t ret_val = E1000_SUCCESS;
6064 DEBUGFUNC("e1000_cleanup_led");
6066 switch (hw->mac_type) {
6067 case e1000_82542_rev2_0:
6068 case e1000_82542_rev2_1:
6071 /* No cleanup necessary */
6075 case e1000_82541_rev_2:
6076 case e1000_82547_rev_2:
6077 /* Turn on PHY Smart Power Down (if previously enabled) */
6078 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6079 hw->phy_spd_default);
6084 if (hw->phy_type == e1000_phy_ife) {
6085 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6088 /* Restore LEDCTL settings */
6089 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6093 return E1000_SUCCESS;
6096 /******************************************************************************
6097 * Turns on the software controllable LED
6099 * hw - Struct containing variables accessed by shared code
6100 *****************************************************************************/
6102 e1000_led_on(struct e1000_hw *hw)
6104 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6106 DEBUGFUNC("e1000_led_on");
6108 switch (hw->mac_type) {
6109 case e1000_82542_rev2_0:
6110 case e1000_82542_rev2_1:
6112 /* Set SW Defineable Pin 0 to turn on the LED */
6113 ctrl |= E1000_CTRL_SWDPIN0;
6114 ctrl |= E1000_CTRL_SWDPIO0;
6117 if (hw->media_type == e1000_media_type_fiber) {
6118 /* Set SW Defineable Pin 0 to turn on the LED */
6119 ctrl |= E1000_CTRL_SWDPIN0;
6120 ctrl |= E1000_CTRL_SWDPIO0;
6122 /* Clear SW Defineable Pin 0 to turn on the LED */
6123 ctrl &= ~E1000_CTRL_SWDPIN0;
6124 ctrl |= E1000_CTRL_SWDPIO0;
6128 if (hw->media_type == e1000_media_type_fiber) {
6129 /* Clear SW Defineable Pin 0 to turn on the LED */
6130 ctrl &= ~E1000_CTRL_SWDPIN0;
6131 ctrl |= E1000_CTRL_SWDPIO0;
6132 } else if (hw->phy_type == e1000_phy_ife) {
6133 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6134 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6135 } else if (hw->media_type == e1000_media_type_copper) {
6136 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6137 return E1000_SUCCESS;
6142 E1000_WRITE_REG(hw, CTRL, ctrl);
6144 return E1000_SUCCESS;
6147 /******************************************************************************
6148 * Turns off the software controllable LED
6150 * hw - Struct containing variables accessed by shared code
6151 *****************************************************************************/
6153 e1000_led_off(struct e1000_hw *hw)
6155 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6157 DEBUGFUNC("e1000_led_off");
6159 switch (hw->mac_type) {
6160 case e1000_82542_rev2_0:
6161 case e1000_82542_rev2_1:
6163 /* Clear SW Defineable Pin 0 to turn off the LED */
6164 ctrl &= ~E1000_CTRL_SWDPIN0;
6165 ctrl |= E1000_CTRL_SWDPIO0;
6168 if (hw->media_type == e1000_media_type_fiber) {
6169 /* Clear SW Defineable Pin 0 to turn off the LED */
6170 ctrl &= ~E1000_CTRL_SWDPIN0;
6171 ctrl |= E1000_CTRL_SWDPIO0;
6173 /* Set SW Defineable Pin 0 to turn off the LED */
6174 ctrl |= E1000_CTRL_SWDPIN0;
6175 ctrl |= E1000_CTRL_SWDPIO0;
6179 if (hw->media_type == e1000_media_type_fiber) {
6180 /* Set SW Defineable Pin 0 to turn off the LED */
6181 ctrl |= E1000_CTRL_SWDPIN0;
6182 ctrl |= E1000_CTRL_SWDPIO0;
6183 } else if (hw->phy_type == e1000_phy_ife) {
6184 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6185 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6186 } else if (hw->media_type == e1000_media_type_copper) {
6187 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6188 return E1000_SUCCESS;
6193 E1000_WRITE_REG(hw, CTRL, ctrl);
6195 return E1000_SUCCESS;
6198 /******************************************************************************
6199 * Clears all hardware statistics counters.
6201 * hw - Struct containing variables accessed by shared code
6202 *****************************************************************************/
6204 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6206 volatile uint32_t temp;
6208 temp = E1000_READ_REG(hw, CRCERRS);
6209 temp = E1000_READ_REG(hw, SYMERRS);
6210 temp = E1000_READ_REG(hw, MPC);
6211 temp = E1000_READ_REG(hw, SCC);
6212 temp = E1000_READ_REG(hw, ECOL);
6213 temp = E1000_READ_REG(hw, MCC);
6214 temp = E1000_READ_REG(hw, LATECOL);
6215 temp = E1000_READ_REG(hw, COLC);
6216 temp = E1000_READ_REG(hw, DC);
6217 temp = E1000_READ_REG(hw, SEC);
6218 temp = E1000_READ_REG(hw, RLEC);
6219 temp = E1000_READ_REG(hw, XONRXC);
6220 temp = E1000_READ_REG(hw, XONTXC);
6221 temp = E1000_READ_REG(hw, XOFFRXC);
6222 temp = E1000_READ_REG(hw, XOFFTXC);
6223 temp = E1000_READ_REG(hw, FCRUC);
6225 if (hw->mac_type != e1000_ich8lan) {
6226 temp = E1000_READ_REG(hw, PRC64);
6227 temp = E1000_READ_REG(hw, PRC127);
6228 temp = E1000_READ_REG(hw, PRC255);
6229 temp = E1000_READ_REG(hw, PRC511);
6230 temp = E1000_READ_REG(hw, PRC1023);
6231 temp = E1000_READ_REG(hw, PRC1522);
6234 temp = E1000_READ_REG(hw, GPRC);
6235 temp = E1000_READ_REG(hw, BPRC);
6236 temp = E1000_READ_REG(hw, MPRC);
6237 temp = E1000_READ_REG(hw, GPTC);
6238 temp = E1000_READ_REG(hw, GORCL);
6239 temp = E1000_READ_REG(hw, GORCH);
6240 temp = E1000_READ_REG(hw, GOTCL);
6241 temp = E1000_READ_REG(hw, GOTCH);
6242 temp = E1000_READ_REG(hw, RNBC);
6243 temp = E1000_READ_REG(hw, RUC);
6244 temp = E1000_READ_REG(hw, RFC);
6245 temp = E1000_READ_REG(hw, ROC);
6246 temp = E1000_READ_REG(hw, RJC);
6247 temp = E1000_READ_REG(hw, TORL);
6248 temp = E1000_READ_REG(hw, TORH);
6249 temp = E1000_READ_REG(hw, TOTL);
6250 temp = E1000_READ_REG(hw, TOTH);
6251 temp = E1000_READ_REG(hw, TPR);
6252 temp = E1000_READ_REG(hw, TPT);
6254 if (hw->mac_type != e1000_ich8lan) {
6255 temp = E1000_READ_REG(hw, PTC64);
6256 temp = E1000_READ_REG(hw, PTC127);
6257 temp = E1000_READ_REG(hw, PTC255);
6258 temp = E1000_READ_REG(hw, PTC511);
6259 temp = E1000_READ_REG(hw, PTC1023);
6260 temp = E1000_READ_REG(hw, PTC1522);
6263 temp = E1000_READ_REG(hw, MPTC);
6264 temp = E1000_READ_REG(hw, BPTC);
6266 if (hw->mac_type < e1000_82543) return;
6268 temp = E1000_READ_REG(hw, ALGNERRC);
6269 temp = E1000_READ_REG(hw, RXERRC);
6270 temp = E1000_READ_REG(hw, TNCRS);
6271 temp = E1000_READ_REG(hw, CEXTERR);
6272 temp = E1000_READ_REG(hw, TSCTC);
6273 temp = E1000_READ_REG(hw, TSCTFC);
6275 if (hw->mac_type <= e1000_82544) return;
6277 temp = E1000_READ_REG(hw, MGTPRC);
6278 temp = E1000_READ_REG(hw, MGTPDC);
6279 temp = E1000_READ_REG(hw, MGTPTC);
6281 if (hw->mac_type <= e1000_82547_rev_2) return;
6283 temp = E1000_READ_REG(hw, IAC);
6284 temp = E1000_READ_REG(hw, ICRXOC);
6286 if (hw->mac_type == e1000_ich8lan) return;
6288 temp = E1000_READ_REG(hw, ICRXPTC);
6289 temp = E1000_READ_REG(hw, ICRXATC);
6290 temp = E1000_READ_REG(hw, ICTXPTC);
6291 temp = E1000_READ_REG(hw, ICTXATC);
6292 temp = E1000_READ_REG(hw, ICTXQEC);
6293 temp = E1000_READ_REG(hw, ICTXQMTC);
6294 temp = E1000_READ_REG(hw, ICRXDMTC);
6297 /******************************************************************************
6298 * Resets Adaptive IFS to its default state.
6300 * hw - Struct containing variables accessed by shared code
6302 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6303 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6304 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6305 * before calling this function.
6306 *****************************************************************************/
6308 e1000_reset_adaptive(struct e1000_hw *hw)
6310 DEBUGFUNC("e1000_reset_adaptive");
6312 if (hw->adaptive_ifs) {
6313 if (!hw->ifs_params_forced) {
6314 hw->current_ifs_val = 0;
6315 hw->ifs_min_val = IFS_MIN;
6316 hw->ifs_max_val = IFS_MAX;
6317 hw->ifs_step_size = IFS_STEP;
6318 hw->ifs_ratio = IFS_RATIO;
6320 hw->in_ifs_mode = FALSE;
6321 E1000_WRITE_REG(hw, AIT, 0);
6323 DEBUGOUT("Not in Adaptive IFS mode!\n");
6327 /******************************************************************************
6328 * Called during the callback/watchdog routine to update IFS value based on
6329 * the ratio of transmits to collisions.
6331 * hw - Struct containing variables accessed by shared code
6332 * tx_packets - Number of transmits since last callback
6333 * total_collisions - Number of collisions since last callback
6334 *****************************************************************************/
6336 e1000_update_adaptive(struct e1000_hw *hw)
6338 DEBUGFUNC("e1000_update_adaptive");
6340 if (hw->adaptive_ifs) {
6341 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6342 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6343 hw->in_ifs_mode = TRUE;
6344 if (hw->current_ifs_val < hw->ifs_max_val) {
6345 if (hw->current_ifs_val == 0)
6346 hw->current_ifs_val = hw->ifs_min_val;
6348 hw->current_ifs_val += hw->ifs_step_size;
6349 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6353 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6354 hw->current_ifs_val = 0;
6355 hw->in_ifs_mode = FALSE;
6356 E1000_WRITE_REG(hw, AIT, 0);
6360 DEBUGOUT("Not in Adaptive IFS mode!\n");
6364 /******************************************************************************
6365 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6367 * hw - Struct containing variables accessed by shared code
6368 * frame_len - The length of the frame in question
6369 * mac_addr - The Ethernet destination address of the frame in question
6370 *****************************************************************************/
6372 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6373 struct e1000_hw_stats *stats,
6379 /* First adjust the frame length. */
6381 /* We need to adjust the statistics counters, since the hardware
6382 * counters overcount this packet as a CRC error and undercount
6383 * the packet as a good packet
6385 /* This packet should not be counted as a CRC error. */
6387 /* This packet does count as a Good Packet Received. */
6390 /* Adjust the Good Octets received counters */
6391 carry_bit = 0x80000000 & stats->gorcl;
6392 stats->gorcl += frame_len;
6393 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6394 * Received Count) was one before the addition,
6395 * AND it is zero after, then we lost the carry out,
6396 * need to add one to Gorch (Good Octets Received Count High).
6397 * This could be simplified if all environments supported
6400 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6402 /* Is this a broadcast or multicast? Check broadcast first,
6403 * since the test for a multicast frame will test positive on
6404 * a broadcast frame.
6406 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6407 /* Broadcast packet */
6409 else if (*mac_addr & 0x01)
6410 /* Multicast packet */
6413 if (frame_len == hw->max_frame_size) {
6414 /* In this case, the hardware has overcounted the number of
6421 /* Adjust the bin counters when the extra byte put the frame in the
6422 * wrong bin. Remember that the frame_len was adjusted above.
6424 if (frame_len == 64) {
6427 } else if (frame_len == 127) {
6430 } else if (frame_len == 255) {
6433 } else if (frame_len == 511) {
6436 } else if (frame_len == 1023) {
6439 } else if (frame_len == 1522) {
6444 /******************************************************************************
6445 * Gets the current PCI bus type, speed, and width of the hardware
6447 * hw - Struct containing variables accessed by shared code
6448 *****************************************************************************/
6450 e1000_get_bus_info(struct e1000_hw *hw)
6454 switch (hw->mac_type) {
6455 case e1000_82542_rev2_0:
6456 case e1000_82542_rev2_1:
6457 hw->bus_type = e1000_bus_type_unknown;
6458 hw->bus_speed = e1000_bus_speed_unknown;
6459 hw->bus_width = e1000_bus_width_unknown;
6463 hw->bus_type = e1000_bus_type_pci_express;
6464 hw->bus_speed = e1000_bus_speed_2500;
6465 hw->bus_width = e1000_bus_width_pciex_1;
6469 case e1000_80003es2lan:
6470 hw->bus_type = e1000_bus_type_pci_express;
6471 hw->bus_speed = e1000_bus_speed_2500;
6472 hw->bus_width = e1000_bus_width_pciex_4;
6475 status = E1000_READ_REG(hw, STATUS);
6476 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6477 e1000_bus_type_pcix : e1000_bus_type_pci;
6479 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6480 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6481 e1000_bus_speed_66 : e1000_bus_speed_120;
6482 } else if (hw->bus_type == e1000_bus_type_pci) {
6483 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6484 e1000_bus_speed_66 : e1000_bus_speed_33;
6486 switch (status & E1000_STATUS_PCIX_SPEED) {
6487 case E1000_STATUS_PCIX_SPEED_66:
6488 hw->bus_speed = e1000_bus_speed_66;
6490 case E1000_STATUS_PCIX_SPEED_100:
6491 hw->bus_speed = e1000_bus_speed_100;
6493 case E1000_STATUS_PCIX_SPEED_133:
6494 hw->bus_speed = e1000_bus_speed_133;
6497 hw->bus_speed = e1000_bus_speed_reserved;
6501 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6502 e1000_bus_width_64 : e1000_bus_width_32;
6507 /******************************************************************************
6508 * Writes a value to one of the devices registers using port I/O (as opposed to
6509 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6511 * hw - Struct containing variables accessed by shared code
6512 * offset - offset to write to
6513 * value - value to write
6514 *****************************************************************************/
6516 e1000_write_reg_io(struct e1000_hw *hw,
6520 unsigned long io_addr = hw->io_base;
6521 unsigned long io_data = hw->io_base + 4;
6523 e1000_io_write(hw, io_addr, offset);
6524 e1000_io_write(hw, io_data, value);
6527 /******************************************************************************
6528 * Estimates the cable length.
6530 * hw - Struct containing variables accessed by shared code
6531 * min_length - The estimated minimum length
6532 * max_length - The estimated maximum length
6534 * returns: - E1000_ERR_XXX
6537 * This function always returns a ranged length (minimum & maximum).
6538 * So for M88 phy's, this function interprets the one value returned from the
6539 * register to the minimum and maximum range.
6540 * For IGP phy's, the function calculates the range by the AGC registers.
6541 *****************************************************************************/
6543 e1000_get_cable_length(struct e1000_hw *hw,
6544 uint16_t *min_length,
6545 uint16_t *max_length)
6548 uint16_t agc_value = 0;
6549 uint16_t i, phy_data;
6550 uint16_t cable_length;
6552 DEBUGFUNC("e1000_get_cable_length");
6554 *min_length = *max_length = 0;
6556 /* Use old method for Phy older than IGP */
6557 if (hw->phy_type == e1000_phy_m88) {
6559 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6563 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6564 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6566 /* Convert the enum value to ranged values */
6567 switch (cable_length) {
6568 case e1000_cable_length_50:
6570 *max_length = e1000_igp_cable_length_50;
6572 case e1000_cable_length_50_80:
6573 *min_length = e1000_igp_cable_length_50;
6574 *max_length = e1000_igp_cable_length_80;
6576 case e1000_cable_length_80_110:
6577 *min_length = e1000_igp_cable_length_80;
6578 *max_length = e1000_igp_cable_length_110;
6580 case e1000_cable_length_110_140:
6581 *min_length = e1000_igp_cable_length_110;
6582 *max_length = e1000_igp_cable_length_140;
6584 case e1000_cable_length_140:
6585 *min_length = e1000_igp_cable_length_140;
6586 *max_length = e1000_igp_cable_length_170;
6589 return -E1000_ERR_PHY;
6592 } else if (hw->phy_type == e1000_phy_gg82563) {
6593 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6597 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6599 switch (cable_length) {
6600 case e1000_gg_cable_length_60:
6602 *max_length = e1000_igp_cable_length_60;
6604 case e1000_gg_cable_length_60_115:
6605 *min_length = e1000_igp_cable_length_60;
6606 *max_length = e1000_igp_cable_length_115;
6608 case e1000_gg_cable_length_115_150:
6609 *min_length = e1000_igp_cable_length_115;
6610 *max_length = e1000_igp_cable_length_150;
6612 case e1000_gg_cable_length_150:
6613 *min_length = e1000_igp_cable_length_150;
6614 *max_length = e1000_igp_cable_length_180;
6617 return -E1000_ERR_PHY;
6620 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6621 uint16_t cur_agc_value;
6622 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6623 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6624 {IGP01E1000_PHY_AGC_A,
6625 IGP01E1000_PHY_AGC_B,
6626 IGP01E1000_PHY_AGC_C,
6627 IGP01E1000_PHY_AGC_D};
6628 /* Read the AGC registers for all channels */
6629 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6631 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6635 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6637 /* Value bound check. */
6638 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6639 (cur_agc_value == 0))
6640 return -E1000_ERR_PHY;
6642 agc_value += cur_agc_value;
6644 /* Update minimal AGC value. */
6645 if (min_agc_value > cur_agc_value)
6646 min_agc_value = cur_agc_value;
6649 /* Remove the minimal AGC result for length < 50m */
6650 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6651 agc_value -= min_agc_value;
6653 /* Get the average length of the remaining 3 channels */
6654 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6656 /* Get the average length of all the 4 channels. */
6657 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6660 /* Set the range of the calculated length. */
6661 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6662 IGP01E1000_AGC_RANGE) > 0) ?
6663 (e1000_igp_cable_length_table[agc_value] -
6664 IGP01E1000_AGC_RANGE) : 0;
6665 *max_length = e1000_igp_cable_length_table[agc_value] +
6666 IGP01E1000_AGC_RANGE;
6667 } else if (hw->phy_type == e1000_phy_igp_2 ||
6668 hw->phy_type == e1000_phy_igp_3) {
6669 uint16_t cur_agc_index, max_agc_index = 0;
6670 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6671 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6672 {IGP02E1000_PHY_AGC_A,
6673 IGP02E1000_PHY_AGC_B,
6674 IGP02E1000_PHY_AGC_C,
6675 IGP02E1000_PHY_AGC_D};
6676 /* Read the AGC registers for all channels */
6677 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6678 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6682 /* Getting bits 15:9, which represent the combination of course and
6683 * fine gain values. The result is a number that can be put into
6684 * the lookup table to obtain the approximate cable length. */
6685 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6686 IGP02E1000_AGC_LENGTH_MASK;
6688 /* Array index bound check. */
6689 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6690 (cur_agc_index == 0))
6691 return -E1000_ERR_PHY;
6693 /* Remove min & max AGC values from calculation. */
6694 if (e1000_igp_2_cable_length_table[min_agc_index] >
6695 e1000_igp_2_cable_length_table[cur_agc_index])
6696 min_agc_index = cur_agc_index;
6697 if (e1000_igp_2_cable_length_table[max_agc_index] <
6698 e1000_igp_2_cable_length_table[cur_agc_index])
6699 max_agc_index = cur_agc_index;
6701 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6704 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6705 e1000_igp_2_cable_length_table[max_agc_index]);
6706 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6708 /* Calculate cable length with the error range of +/- 10 meters. */
6709 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6710 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6711 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6714 return E1000_SUCCESS;
6717 /******************************************************************************
6718 * Check the cable polarity
6720 * hw - Struct containing variables accessed by shared code
6721 * polarity - output parameter : 0 - Polarity is not reversed
6722 * 1 - Polarity is reversed.
6724 * returns: - E1000_ERR_XXX
6727 * For phy's older then IGP, this function simply reads the polarity bit in the
6728 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6729 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6730 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6731 * IGP01E1000_PHY_PCS_INIT_REG.
6732 *****************************************************************************/
6734 e1000_check_polarity(struct e1000_hw *hw,
6735 e1000_rev_polarity *polarity)
6740 DEBUGFUNC("e1000_check_polarity");
6742 if ((hw->phy_type == e1000_phy_m88) ||
6743 (hw->phy_type == e1000_phy_gg82563)) {
6744 /* return the Polarity bit in the Status register. */
6745 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6749 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6750 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6751 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6753 } else if (hw->phy_type == e1000_phy_igp ||
6754 hw->phy_type == e1000_phy_igp_3 ||
6755 hw->phy_type == e1000_phy_igp_2) {
6756 /* Read the Status register to check the speed */
6757 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6762 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6763 * find the polarity status */
6764 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6765 IGP01E1000_PSSR_SPEED_1000MBPS) {
6767 /* Read the GIG initialization PCS register (0x00B4) */
6768 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6773 /* Check the polarity bits */
6774 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6775 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6777 /* For 10 Mbps, read the polarity bit in the status register. (for
6778 * 100 Mbps this bit is always 0) */
6779 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6780 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6782 } else if (hw->phy_type == e1000_phy_ife) {
6783 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6787 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6788 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6789 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6791 return E1000_SUCCESS;
6794 /******************************************************************************
6795 * Check if Downshift occured
6797 * hw - Struct containing variables accessed by shared code
6798 * downshift - output parameter : 0 - No Downshift ocured.
6799 * 1 - Downshift ocured.
6801 * returns: - E1000_ERR_XXX
6804 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6805 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6806 * Link Health register. In IGP this bit is latched high, so the driver must
6807 * read it immediately after link is established.
6808 *****************************************************************************/
6810 e1000_check_downshift(struct e1000_hw *hw)
6815 DEBUGFUNC("e1000_check_downshift");
6817 if (hw->phy_type == e1000_phy_igp ||
6818 hw->phy_type == e1000_phy_igp_3 ||
6819 hw->phy_type == e1000_phy_igp_2) {
6820 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6825 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6826 } else if ((hw->phy_type == e1000_phy_m88) ||
6827 (hw->phy_type == e1000_phy_gg82563)) {
6828 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6833 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6834 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6835 } else if (hw->phy_type == e1000_phy_ife) {
6836 /* e1000_phy_ife supports 10/100 speed only */
6837 hw->speed_downgraded = FALSE;
6840 return E1000_SUCCESS;
6843 /*****************************************************************************
6845 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6846 * gigabit link is achieved to improve link quality.
6848 * hw: Struct containing variables accessed by shared code
6850 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6851 * E1000_SUCCESS at any other case.
6853 ****************************************************************************/
6856 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6860 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6861 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6862 {IGP01E1000_PHY_AGC_PARAM_A,
6863 IGP01E1000_PHY_AGC_PARAM_B,
6864 IGP01E1000_PHY_AGC_PARAM_C,
6865 IGP01E1000_PHY_AGC_PARAM_D};
6866 uint16_t min_length, max_length;
6868 DEBUGFUNC("e1000_config_dsp_after_link_change");
6870 if (hw->phy_type != e1000_phy_igp)
6871 return E1000_SUCCESS;
6874 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
6876 DEBUGOUT("Error getting link speed and duplex\n");
6880 if (speed == SPEED_1000) {
6882 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6886 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6887 min_length >= e1000_igp_cable_length_50) {
6889 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6890 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6895 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6897 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
6902 hw->dsp_config_state = e1000_dsp_config_activated;
6905 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
6906 (min_length < e1000_igp_cable_length_50)) {
6908 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
6909 uint32_t idle_errs = 0;
6911 /* clear previous idle error counts */
6912 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6917 for (i = 0; i < ffe_idle_err_timeout; i++) {
6919 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
6924 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
6925 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
6926 hw->ffe_config_state = e1000_ffe_config_active;
6928 ret_val = e1000_write_phy_reg(hw,
6929 IGP01E1000_PHY_DSP_FFE,
6930 IGP01E1000_PHY_DSP_FFE_CM_CP);
6937 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
6942 if (hw->dsp_config_state == e1000_dsp_config_activated) {
6943 /* Save off the current value of register 0x2F5B to be restored at
6944 * the end of the routines. */
6945 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6950 /* Disable the PHY transmitter */
6951 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
6958 ret_val = e1000_write_phy_reg(hw, 0x0000,
6959 IGP01E1000_IEEE_FORCE_GIGA);
6962 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6963 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
6967 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
6968 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
6970 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
6975 ret_val = e1000_write_phy_reg(hw, 0x0000,
6976 IGP01E1000_IEEE_RESTART_AUTONEG);
6982 /* Now enable the transmitter */
6983 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
6988 hw->dsp_config_state = e1000_dsp_config_enabled;
6991 if (hw->ffe_config_state == e1000_ffe_config_active) {
6992 /* Save off the current value of register 0x2F5B to be restored at
6993 * the end of the routines. */
6994 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
6999 /* Disable the PHY transmitter */
7000 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7007 ret_val = e1000_write_phy_reg(hw, 0x0000,
7008 IGP01E1000_IEEE_FORCE_GIGA);
7011 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7012 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7016 ret_val = e1000_write_phy_reg(hw, 0x0000,
7017 IGP01E1000_IEEE_RESTART_AUTONEG);
7023 /* Now enable the transmitter */
7024 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7029 hw->ffe_config_state = e1000_ffe_config_enabled;
7032 return E1000_SUCCESS;
7035 /*****************************************************************************
7036 * Set PHY to class A mode
7037 * Assumes the following operations will follow to enable the new class mode.
7038 * 1. Do a PHY soft reset
7039 * 2. Restart auto-negotiation or force link.
7041 * hw - Struct containing variables accessed by shared code
7042 ****************************************************************************/
7044 e1000_set_phy_mode(struct e1000_hw *hw)
7047 uint16_t eeprom_data;
7049 DEBUGFUNC("e1000_set_phy_mode");
7051 if ((hw->mac_type == e1000_82545_rev_3) &&
7052 (hw->media_type == e1000_media_type_copper)) {
7053 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7058 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7059 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7060 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7063 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7067 hw->phy_reset_disable = FALSE;
7071 return E1000_SUCCESS;
7074 /*****************************************************************************
7076 * This function sets the lplu state according to the active flag. When
7077 * activating lplu this function also disables smart speed and vise versa.
7078 * lplu will not be activated unless the device autonegotiation advertisment
7079 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7080 * hw: Struct containing variables accessed by shared code
7081 * active - true to enable lplu false to disable lplu.
7083 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7084 * E1000_SUCCESS at any other case.
7086 ****************************************************************************/
7089 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7092 uint32_t phy_ctrl = 0;
7095 DEBUGFUNC("e1000_set_d3_lplu_state");
7097 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7098 && hw->phy_type != e1000_phy_igp_3)
7099 return E1000_SUCCESS;
7101 /* During driver activity LPLU should not be used or it will attain link
7102 * from the lowest speeds starting from 10Mbps. The capability is used for
7103 * Dx transitions and states */
7104 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7105 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7108 } else if (hw->mac_type == e1000_ich8lan) {
7109 /* MAC writes into PHY register based on the state transition
7110 * and start auto-negotiation. SW driver can overwrite the settings
7111 * in CSR PHY power control E1000_PHY_CTRL register. */
7112 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7114 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7120 if (hw->mac_type == e1000_82541_rev_2 ||
7121 hw->mac_type == e1000_82547_rev_2) {
7122 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7123 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7127 if (hw->mac_type == e1000_ich8lan) {
7128 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7129 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7131 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7132 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7139 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7140 * Dx states where the power conservation is most important. During
7141 * driver activity we should enable SmartSpeed, so performance is
7143 if (hw->smart_speed == e1000_smart_speed_on) {
7144 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7149 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7150 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7154 } else if (hw->smart_speed == e1000_smart_speed_off) {
7155 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7160 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7161 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7167 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7168 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7169 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7171 if (hw->mac_type == e1000_82541_rev_2 ||
7172 hw->mac_type == e1000_82547_rev_2) {
7173 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7174 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7178 if (hw->mac_type == e1000_ich8lan) {
7179 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7180 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7182 phy_data |= IGP02E1000_PM_D3_LPLU;
7183 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7190 /* When LPLU is enabled we should disable SmartSpeed */
7191 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7195 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7196 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7201 return E1000_SUCCESS;
7204 /*****************************************************************************
7206 * This function sets the lplu d0 state according to the active flag. When
7207 * activating lplu this function also disables smart speed and vise versa.
7208 * lplu will not be activated unless the device autonegotiation advertisment
7209 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7210 * hw: Struct containing variables accessed by shared code
7211 * active - true to enable lplu false to disable lplu.
7213 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7214 * E1000_SUCCESS at any other case.
7216 ****************************************************************************/
7219 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7222 uint32_t phy_ctrl = 0;
7225 DEBUGFUNC("e1000_set_d0_lplu_state");
7227 if (hw->mac_type <= e1000_82547_rev_2)
7228 return E1000_SUCCESS;
7230 if (hw->mac_type == e1000_ich8lan) {
7231 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7233 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7239 if (hw->mac_type == e1000_ich8lan) {
7240 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7241 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7243 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7244 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7249 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7250 * Dx states where the power conservation is most important. During
7251 * driver activity we should enable SmartSpeed, so performance is
7253 if (hw->smart_speed == e1000_smart_speed_on) {
7254 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7259 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7260 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7264 } else if (hw->smart_speed == e1000_smart_speed_off) {
7265 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7270 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7271 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7280 if (hw->mac_type == e1000_ich8lan) {
7281 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7282 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7284 phy_data |= IGP02E1000_PM_D0_LPLU;
7285 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7290 /* When LPLU is enabled we should disable SmartSpeed */
7291 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7295 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7296 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7301 return E1000_SUCCESS;
7304 /******************************************************************************
7305 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7307 * hw - Struct containing variables accessed by shared code
7308 *****************************************************************************/
7310 e1000_set_vco_speed(struct e1000_hw *hw)
7313 uint16_t default_page = 0;
7316 DEBUGFUNC("e1000_set_vco_speed");
7318 switch (hw->mac_type) {
7319 case e1000_82545_rev_3:
7320 case e1000_82546_rev_3:
7323 return E1000_SUCCESS;
7326 /* Set PHY register 30, page 5, bit 8 to 0 */
7328 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7332 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7336 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7340 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7341 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7345 /* Set PHY register 30, page 4, bit 11 to 1 */
7347 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7351 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7355 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7356 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7360 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7364 return E1000_SUCCESS;
7368 /*****************************************************************************
7369 * This function reads the cookie from ARC ram.
7371 * returns: - E1000_SUCCESS .
7372 ****************************************************************************/
7374 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7377 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7378 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7380 length = (length >> 2);
7381 offset = (offset >> 2);
7383 for (i = 0; i < length; i++) {
7384 *((uint32_t *) buffer + i) =
7385 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7387 return E1000_SUCCESS;
7391 /*****************************************************************************
7392 * This function checks whether the HOST IF is enabled for command operaton
7393 * and also checks whether the previous command is completed.
7394 * It busy waits in case of previous command is not completed.
7396 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7398 * - E1000_SUCCESS for success.
7399 ****************************************************************************/
7401 e1000_mng_enable_host_if(struct e1000_hw * hw)
7406 /* Check that the host interface is enabled. */
7407 hicr = E1000_READ_REG(hw, HICR);
7408 if ((hicr & E1000_HICR_EN) == 0) {
7409 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7410 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7412 /* check the previous command is completed */
7413 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7414 hicr = E1000_READ_REG(hw, HICR);
7415 if (!(hicr & E1000_HICR_C))
7420 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7421 DEBUGOUT("Previous command timeout failed .\n");
7422 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7424 return E1000_SUCCESS;
7427 /*****************************************************************************
7428 * This function writes the buffer content at the offset given on the host if.
7429 * It also does alignment considerations to do the writes in most efficient way.
7430 * Also fills up the sum of the buffer in *buffer parameter.
7432 * returns - E1000_SUCCESS for success.
7433 ****************************************************************************/
7435 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7436 uint16_t length, uint16_t offset, uint8_t *sum)
7439 uint8_t *bufptr = buffer;
7441 uint16_t remaining, i, j, prev_bytes;
7443 /* sum = only sum of the data and it is not checksum */
7445 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7446 return -E1000_ERR_PARAM;
7449 tmp = (uint8_t *)&data;
7450 prev_bytes = offset & 0x3;
7455 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7456 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7457 *(tmp + j) = *bufptr++;
7460 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7461 length -= j - prev_bytes;
7465 remaining = length & 0x3;
7466 length -= remaining;
7468 /* Calculate length in DWORDs */
7471 /* The device driver writes the relevant command block into the
7473 for (i = 0; i < length; i++) {
7474 for (j = 0; j < sizeof(uint32_t); j++) {
7475 *(tmp + j) = *bufptr++;
7479 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7482 for (j = 0; j < sizeof(uint32_t); j++) {
7484 *(tmp + j) = *bufptr++;
7490 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7493 return E1000_SUCCESS;
7497 /*****************************************************************************
7498 * This function writes the command header after does the checksum calculation.
7500 * returns - E1000_SUCCESS for success.
7501 ****************************************************************************/
7503 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7504 struct e1000_host_mng_command_header * hdr)
7510 /* Write the whole command header structure which includes sum of
7513 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7515 sum = hdr->checksum;
7518 buffer = (uint8_t *) hdr;
7523 hdr->checksum = 0 - sum;
7526 /* The device driver writes the relevant command block into the ram area. */
7527 for (i = 0; i < length; i++) {
7528 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7529 E1000_WRITE_FLUSH(hw);
7532 return E1000_SUCCESS;
7536 /*****************************************************************************
7537 * This function indicates to ARC that a new command is pending which completes
7538 * one write operation by the driver.
7540 * returns - E1000_SUCCESS for success.
7541 ****************************************************************************/
7543 e1000_mng_write_commit(struct e1000_hw * hw)
7547 hicr = E1000_READ_REG(hw, HICR);
7548 /* Setting this bit tells the ARC that a new command is pending. */
7549 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7551 return E1000_SUCCESS;
7555 /*****************************************************************************
7556 * This function checks the mode of the firmware.
7558 * returns - TRUE when the mode is IAMT or FALSE.
7559 ****************************************************************************/
7561 e1000_check_mng_mode(struct e1000_hw *hw)
7565 fwsm = E1000_READ_REG(hw, FWSM);
7567 if (hw->mac_type == e1000_ich8lan) {
7568 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7569 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7571 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7572 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7579 /*****************************************************************************
7580 * This function writes the dhcp info .
7581 ****************************************************************************/
7583 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7587 struct e1000_host_mng_command_header hdr;
7589 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7590 hdr.command_length = length;
7595 ret_val = e1000_mng_enable_host_if(hw);
7596 if (ret_val == E1000_SUCCESS) {
7597 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7599 if (ret_val == E1000_SUCCESS) {
7600 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7601 if (ret_val == E1000_SUCCESS)
7602 ret_val = e1000_mng_write_commit(hw);
7609 /*****************************************************************************
7610 * This function calculates the checksum.
7612 * returns - checksum of buffer contents.
7613 ****************************************************************************/
7615 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7623 for (i=0; i < length; i++)
7626 return (uint8_t) (0 - sum);
7629 /*****************************************************************************
7630 * This function checks whether tx pkt filtering needs to be enabled or not.
7632 * returns - TRUE for packet filtering or FALSE.
7633 ****************************************************************************/
7635 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7637 /* called in init as well as watchdog timer functions */
7639 int32_t ret_val, checksum;
7640 boolean_t tx_filter = FALSE;
7641 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7642 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7644 if (e1000_check_mng_mode(hw)) {
7645 ret_val = e1000_mng_enable_host_if(hw);
7646 if (ret_val == E1000_SUCCESS) {
7647 ret_val = e1000_host_if_read_cookie(hw, buffer);
7648 if (ret_val == E1000_SUCCESS) {
7649 checksum = hdr->checksum;
7651 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7652 checksum == e1000_calculate_mng_checksum((char *)buffer,
7653 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7655 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7664 hw->tx_pkt_filtering = tx_filter;
7668 /******************************************************************************
7669 * Verifies the hardware needs to allow ARPs to be processed by the host
7671 * hw - Struct containing variables accessed by shared code
7673 * returns: - TRUE/FALSE
7675 *****************************************************************************/
7677 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7680 uint32_t fwsm, factps;
7682 if (hw->asf_firmware_present) {
7683 manc = E1000_READ_REG(hw, MANC);
7685 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7686 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7688 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7689 fwsm = E1000_READ_REG(hw, FWSM);
7690 factps = E1000_READ_REG(hw, FACTPS);
7692 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7693 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7694 (factps & E1000_FACTPS_MNGCG))
7697 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7704 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7707 uint16_t mii_status_reg;
7710 /* Polarity reversal workaround for forced 10F/10H links. */
7712 /* Disable the transmitter on the PHY */
7714 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7717 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7721 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7725 /* This loop will early-out if the NO link condition has been met. */
7726 for (i = PHY_FORCE_TIME; i > 0; i--) {
7727 /* Read the MII Status Register and wait for Link Status bit
7731 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7735 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7739 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7743 /* Recommended delay time after link has been lost */
7746 /* Now we will re-enable th transmitter on the PHY */
7748 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7752 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7756 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7760 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7764 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7768 /* This loop will early-out if the link condition has been met. */
7769 for (i = PHY_FORCE_TIME; i > 0; i--) {
7770 /* Read the MII Status Register and wait for Link Status bit
7774 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7778 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7782 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7785 return E1000_SUCCESS;
7788 /***************************************************************************
7790 * Disables PCI-Express master access.
7792 * hw: Struct containing variables accessed by shared code
7796 ***************************************************************************/
7798 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7802 DEBUGFUNC("e1000_set_pci_express_master_disable");
7804 if (hw->bus_type != e1000_bus_type_pci_express)
7807 ctrl = E1000_READ_REG(hw, CTRL);
7808 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7809 E1000_WRITE_REG(hw, CTRL, ctrl);
7812 /*******************************************************************************
7814 * Disables PCI-Express master access and verifies there are no pending requests
7816 * hw: Struct containing variables accessed by shared code
7818 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7819 * caused the master requests to be disabled.
7820 * E1000_SUCCESS master requests disabled.
7822 ******************************************************************************/
7824 e1000_disable_pciex_master(struct e1000_hw *hw)
7826 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7828 DEBUGFUNC("e1000_disable_pciex_master");
7830 if (hw->bus_type != e1000_bus_type_pci_express)
7831 return E1000_SUCCESS;
7833 e1000_set_pci_express_master_disable(hw);
7836 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7844 DEBUGOUT("Master requests are pending.\n");
7845 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7848 return E1000_SUCCESS;
7851 /*******************************************************************************
7853 * Check for EEPROM Auto Read bit done.
7855 * hw: Struct containing variables accessed by shared code
7857 * returns: - E1000_ERR_RESET if fail to reset MAC
7858 * E1000_SUCCESS at any other case.
7860 ******************************************************************************/
7862 e1000_get_auto_rd_done(struct e1000_hw *hw)
7864 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7866 DEBUGFUNC("e1000_get_auto_rd_done");
7868 switch (hw->mac_type) {
7875 case e1000_80003es2lan:
7878 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7885 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
7886 return -E1000_ERR_RESET;
7891 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
7892 * Need to wait for PHY configuration completion before accessing NVM
7894 if (hw->mac_type == e1000_82573)
7897 return E1000_SUCCESS;
7900 /***************************************************************************
7901 * Checks if the PHY configuration is done
7903 * hw: Struct containing variables accessed by shared code
7905 * returns: - E1000_ERR_RESET if fail to reset MAC
7906 * E1000_SUCCESS at any other case.
7908 ***************************************************************************/
7910 e1000_get_phy_cfg_done(struct e1000_hw *hw)
7912 int32_t timeout = PHY_CFG_TIMEOUT;
7913 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
7915 DEBUGFUNC("e1000_get_phy_cfg_done");
7917 switch (hw->mac_type) {
7921 case e1000_80003es2lan:
7922 /* Separate *_CFG_DONE_* bit for each port */
7923 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
7924 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
7929 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
7936 DEBUGOUT("MNG configuration cycle has not completed.\n");
7937 return -E1000_ERR_RESET;
7942 return E1000_SUCCESS;
7945 /***************************************************************************
7947 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
7948 * adapter or Eeprom access.
7950 * hw: Struct containing variables accessed by shared code
7952 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
7953 * E1000_SUCCESS at any other case.
7955 ***************************************************************************/
7957 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
7962 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
7964 if (!hw->eeprom_semaphore_present)
7965 return E1000_SUCCESS;
7967 if (hw->mac_type == e1000_80003es2lan) {
7968 /* Get the SW semaphore. */
7969 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
7970 return -E1000_ERR_EEPROM;
7973 /* Get the FW semaphore. */
7974 timeout = hw->eeprom.word_size + 1;
7976 swsm = E1000_READ_REG(hw, SWSM);
7977 swsm |= E1000_SWSM_SWESMBI;
7978 E1000_WRITE_REG(hw, SWSM, swsm);
7979 /* if we managed to set the bit we got the semaphore. */
7980 swsm = E1000_READ_REG(hw, SWSM);
7981 if (swsm & E1000_SWSM_SWESMBI)
7989 /* Release semaphores */
7990 e1000_put_hw_eeprom_semaphore(hw);
7991 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
7992 return -E1000_ERR_EEPROM;
7995 return E1000_SUCCESS;
7998 /***************************************************************************
7999 * This function clears HW semaphore bits.
8001 * hw: Struct containing variables accessed by shared code
8005 ***************************************************************************/
8007 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8011 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8013 if (!hw->eeprom_semaphore_present)
8016 swsm = E1000_READ_REG(hw, SWSM);
8017 if (hw->mac_type == e1000_80003es2lan) {
8018 /* Release both semaphores. */
8019 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8021 swsm &= ~(E1000_SWSM_SWESMBI);
8022 E1000_WRITE_REG(hw, SWSM, swsm);
8025 /***************************************************************************
8027 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8029 * hw: Struct containing variables accessed by shared code
8031 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8032 * E1000_SUCCESS at any other case.
8034 ***************************************************************************/
8036 e1000_get_software_semaphore(struct e1000_hw *hw)
8038 int32_t timeout = hw->eeprom.word_size + 1;
8041 DEBUGFUNC("e1000_get_software_semaphore");
8043 if (hw->mac_type != e1000_80003es2lan) {
8044 return E1000_SUCCESS;
8048 swsm = E1000_READ_REG(hw, SWSM);
8049 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8050 if (!(swsm & E1000_SWSM_SMBI))
8057 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8058 return -E1000_ERR_RESET;
8061 return E1000_SUCCESS;
8064 /***************************************************************************
8066 * Release semaphore bit (SMBI).
8068 * hw: Struct containing variables accessed by shared code
8070 ***************************************************************************/
8072 e1000_release_software_semaphore(struct e1000_hw *hw)
8076 DEBUGFUNC("e1000_release_software_semaphore");
8078 if (hw->mac_type != e1000_80003es2lan) {
8082 swsm = E1000_READ_REG(hw, SWSM);
8083 /* Release the SW semaphores.*/
8084 swsm &= ~E1000_SWSM_SMBI;
8085 E1000_WRITE_REG(hw, SWSM, swsm);
8088 /******************************************************************************
8089 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8090 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8091 * the caller to figure out how to deal with it.
8093 * hw - Struct containing variables accessed by shared code
8095 * returns: - E1000_BLK_PHY_RESET
8098 *****************************************************************************/
8100 e1000_check_phy_reset_block(struct e1000_hw *hw)
8105 if (hw->mac_type == e1000_ich8lan) {
8106 fwsm = E1000_READ_REG(hw, FWSM);
8107 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8108 : E1000_BLK_PHY_RESET;
8111 if (hw->mac_type > e1000_82547_rev_2)
8112 manc = E1000_READ_REG(hw, MANC);
8113 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8114 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8118 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8122 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8123 * may not be provided a DMA clock when no manageability features are
8124 * enabled. We do not want to perform any reads/writes to these registers
8125 * if this is the case. We read FWSM to determine the manageability mode.
8127 switch (hw->mac_type) {
8131 case e1000_80003es2lan:
8132 fwsm = E1000_READ_REG(hw, FWSM);
8133 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8145 /******************************************************************************
8146 * Configure PCI-Ex no-snoop
8148 * hw - Struct containing variables accessed by shared code.
8149 * no_snoop - Bitmap of no-snoop events.
8151 * returns: E1000_SUCCESS
8153 *****************************************************************************/
8155 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8157 uint32_t gcr_reg = 0;
8159 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8161 if (hw->bus_type == e1000_bus_type_unknown)
8162 e1000_get_bus_info(hw);
8164 if (hw->bus_type != e1000_bus_type_pci_express)
8165 return E1000_SUCCESS;
8168 gcr_reg = E1000_READ_REG(hw, GCR);
8169 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8170 gcr_reg |= no_snoop;
8171 E1000_WRITE_REG(hw, GCR, gcr_reg);
8173 if (hw->mac_type == e1000_ich8lan) {
8176 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8178 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8179 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8180 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8183 return E1000_SUCCESS;
8186 /***************************************************************************
8188 * Get software semaphore FLAG bit (SWFLAG).
8189 * SWFLAG is used to synchronize the access to all shared resource between
8192 * hw: Struct containing variables accessed by shared code
8194 ***************************************************************************/
8196 e1000_get_software_flag(struct e1000_hw *hw)
8198 int32_t timeout = PHY_CFG_TIMEOUT;
8199 uint32_t extcnf_ctrl;
8201 DEBUGFUNC("e1000_get_software_flag");
8203 if (hw->mac_type == e1000_ich8lan) {
8205 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8206 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8207 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8209 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8210 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8217 DEBUGOUT("FW or HW locks the resource too long.\n");
8218 return -E1000_ERR_CONFIG;
8222 return E1000_SUCCESS;
8225 /***************************************************************************
8227 * Release software semaphore FLAG bit (SWFLAG).
8228 * SWFLAG is used to synchronize the access to all shared resource between
8231 * hw: Struct containing variables accessed by shared code
8233 ***************************************************************************/
8235 e1000_release_software_flag(struct e1000_hw *hw)
8237 uint32_t extcnf_ctrl;
8239 DEBUGFUNC("e1000_release_software_flag");
8241 if (hw->mac_type == e1000_ich8lan) {
8242 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8243 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8244 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8250 /******************************************************************************
8251 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8254 * hw - Struct containing variables accessed by shared code
8255 * offset - offset of word in the EEPROM to read
8256 * data - word read from the EEPROM
8257 * words - number of words to read
8258 *****************************************************************************/
8260 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8263 int32_t error = E1000_SUCCESS;
8264 uint32_t flash_bank = 0;
8265 uint32_t act_offset = 0;
8266 uint32_t bank_offset = 0;
8270 /* We need to know which is the valid flash bank. In the event
8271 * that we didn't allocate eeprom_shadow_ram, we may not be
8272 * managing flash_bank. So it cannot be trusted and needs
8273 * to be updated with each read.
8275 /* Value of bit 22 corresponds to the flash bank we're on. */
8276 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8278 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8279 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8281 error = e1000_get_software_flag(hw);
8282 if (error != E1000_SUCCESS)
8285 for (i = 0; i < words; i++) {
8286 if (hw->eeprom_shadow_ram != NULL &&
8287 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8288 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8290 /* The NVM part needs a byte offset, hence * 2 */
8291 act_offset = bank_offset + ((offset + i) * 2);
8292 error = e1000_read_ich8_word(hw, act_offset, &word);
8293 if (error != E1000_SUCCESS)
8299 e1000_release_software_flag(hw);
8304 /******************************************************************************
8305 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8306 * register. Actually, writes are written to the shadow ram cache in the hw
8307 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8308 * the NVM, which occurs when the NVM checksum is updated.
8310 * hw - Struct containing variables accessed by shared code
8311 * offset - offset of word in the EEPROM to write
8312 * words - number of words to write
8313 * data - words to write to the EEPROM
8314 *****************************************************************************/
8316 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8320 int32_t error = E1000_SUCCESS;
8322 error = e1000_get_software_flag(hw);
8323 if (error != E1000_SUCCESS)
8326 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8327 * allocated. Subsequent reads to the modified words are read from
8328 * this cached structure as well. Writes will only go into this
8329 * cached structure unless it's followed by a call to
8330 * e1000_update_eeprom_checksum() where it will commit the changes
8331 * and clear the "modified" field.
8333 if (hw->eeprom_shadow_ram != NULL) {
8334 for (i = 0; i < words; i++) {
8335 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8336 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8337 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8339 error = -E1000_ERR_EEPROM;
8344 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8345 * as they don't perform any NVM writes. An attempt in doing so
8346 * will result in this error.
8348 error = -E1000_ERR_EEPROM;
8351 e1000_release_software_flag(hw);
8356 /******************************************************************************
8357 * This function does initial flash setup so that a new read/write/erase cycle
8360 * hw - The pointer to the hw structure
8361 ****************************************************************************/
8363 e1000_ich8_cycle_init(struct e1000_hw *hw)
8365 union ich8_hws_flash_status hsfsts;
8366 int32_t error = E1000_ERR_EEPROM;
8369 DEBUGFUNC("e1000_ich8_cycle_init");
8371 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8373 /* May be check the Flash Des Valid bit in Hw status */
8374 if (hsfsts.hsf_status.fldesvalid == 0) {
8375 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8379 /* Clear FCERR in Hw status by writing 1 */
8380 /* Clear DAEL in Hw status by writing a 1 */
8381 hsfsts.hsf_status.flcerr = 1;
8382 hsfsts.hsf_status.dael = 1;
8384 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8386 /* Either we should have a hardware SPI cycle in progress bit to check
8387 * against, in order to start a new cycle or FDONE bit should be changed
8388 * in the hardware so that it is 1 after harware reset, which can then be
8389 * used as an indication whether a cycle is in progress or has been
8390 * completed .. we should also have some software semaphore mechanism to
8391 * guard FDONE or the cycle in progress bit so that two threads access to
8392 * those bits can be sequentiallized or a way so that 2 threads dont
8393 * start the cycle at the same time */
8395 if (hsfsts.hsf_status.flcinprog == 0) {
8396 /* There is no cycle running at present, so we can start a cycle */
8397 /* Begin by setting Flash Cycle Done. */
8398 hsfsts.hsf_status.flcdone = 1;
8399 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8400 error = E1000_SUCCESS;
8402 /* otherwise poll for sometime so the current cycle has a chance
8403 * to end before giving up. */
8404 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8405 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8406 if (hsfsts.hsf_status.flcinprog == 0) {
8407 error = E1000_SUCCESS;
8412 if (error == E1000_SUCCESS) {
8413 /* Successful in waiting for previous cycle to timeout,
8414 * now set the Flash Cycle Done. */
8415 hsfsts.hsf_status.flcdone = 1;
8416 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8418 DEBUGOUT("Flash controller busy, cannot get access");
8424 /******************************************************************************
8425 * This function starts a flash cycle and waits for its completion
8427 * hw - The pointer to the hw structure
8428 ****************************************************************************/
8430 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8432 union ich8_hws_flash_ctrl hsflctl;
8433 union ich8_hws_flash_status hsfsts;
8434 int32_t error = E1000_ERR_EEPROM;
8437 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8438 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8439 hsflctl.hsf_ctrl.flcgo = 1;
8440 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8442 /* wait till FDONE bit is set to 1 */
8444 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8445 if (hsfsts.hsf_status.flcdone == 1)
8449 } while (i < timeout);
8450 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8451 error = E1000_SUCCESS;
8456 /******************************************************************************
8457 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8459 * hw - The pointer to the hw structure
8460 * index - The index of the byte or word to read.
8461 * size - Size of data to read, 1=byte 2=word
8462 * data - Pointer to the word to store the value read.
8463 *****************************************************************************/
8465 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8466 uint32_t size, uint16_t* data)
8468 union ich8_hws_flash_status hsfsts;
8469 union ich8_hws_flash_ctrl hsflctl;
8470 uint32_t flash_linear_address;
8471 uint32_t flash_data = 0;
8472 int32_t error = -E1000_ERR_EEPROM;
8475 DEBUGFUNC("e1000_read_ich8_data");
8477 if (size < 1 || size > 2 || data == 0x0 ||
8478 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8481 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8482 hw->flash_base_addr;
8487 error = e1000_ich8_cycle_init(hw);
8488 if (error != E1000_SUCCESS)
8491 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8492 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8493 hsflctl.hsf_ctrl.fldbcount = size - 1;
8494 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8495 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8497 /* Write the last 24 bits of index into Flash Linear address field in
8499 /* TODO: TBD maybe check the index against the size of flash */
8501 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8503 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8505 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8506 * sequence a few more times, else read in (shift in) the Flash Data0,
8507 * the order is least significant byte first msb to lsb */
8508 if (error == E1000_SUCCESS) {
8509 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8511 *data = (uint8_t)(flash_data & 0x000000FF);
8512 } else if (size == 2) {
8513 *data = (uint16_t)(flash_data & 0x0000FFFF);
8517 /* If we've gotten here, then things are probably completely hosed,
8518 * but if the error condition is detected, it won't hurt to give
8519 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8521 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8522 if (hsfsts.hsf_status.flcerr == 1) {
8523 /* Repeat for some time before giving up. */
8525 } else if (hsfsts.hsf_status.flcdone == 0) {
8526 DEBUGOUT("Timeout error - flash cycle did not complete.");
8530 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8535 /******************************************************************************
8536 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8538 * hw - The pointer to the hw structure
8539 * index - The index of the byte/word to read.
8540 * size - Size of data to read, 1=byte 2=word
8541 * data - The byte(s) to write to the NVM.
8542 *****************************************************************************/
8544 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8547 union ich8_hws_flash_status hsfsts;
8548 union ich8_hws_flash_ctrl hsflctl;
8549 uint32_t flash_linear_address;
8550 uint32_t flash_data = 0;
8551 int32_t error = -E1000_ERR_EEPROM;
8554 DEBUGFUNC("e1000_write_ich8_data");
8556 if (size < 1 || size > 2 || data > size * 0xff ||
8557 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8560 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8561 hw->flash_base_addr;
8566 error = e1000_ich8_cycle_init(hw);
8567 if (error != E1000_SUCCESS)
8570 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8571 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8572 hsflctl.hsf_ctrl.fldbcount = size -1;
8573 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8574 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8576 /* Write the last 24 bits of index into Flash Linear address field in
8578 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8581 flash_data = (uint32_t)data & 0x00FF;
8583 flash_data = (uint32_t)data;
8585 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8587 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8588 * sequence a few more times else done */
8589 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8590 if (error == E1000_SUCCESS) {
8593 /* If we're here, then things are most likely completely hosed,
8594 * but if the error condition is detected, it won't hurt to give
8595 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8597 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8598 if (hsfsts.hsf_status.flcerr == 1) {
8599 /* Repeat for some time before giving up. */
8601 } else if (hsfsts.hsf_status.flcdone == 0) {
8602 DEBUGOUT("Timeout error - flash cycle did not complete.");
8606 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8611 /******************************************************************************
8612 * Reads a single byte from the NVM using the ICH8 flash access registers.
8614 * hw - pointer to e1000_hw structure
8615 * index - The index of the byte to read.
8616 * data - Pointer to a byte to store the value read.
8617 *****************************************************************************/
8619 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8621 int32_t status = E1000_SUCCESS;
8624 status = e1000_read_ich8_data(hw, index, 1, &word);
8625 if (status == E1000_SUCCESS) {
8626 *data = (uint8_t)word;
8632 /******************************************************************************
8633 * Writes a single byte to the NVM using the ICH8 flash access registers.
8634 * Performs verification by reading back the value and then going through
8635 * a retry algorithm before giving up.
8637 * hw - pointer to e1000_hw structure
8638 * index - The index of the byte to write.
8639 * byte - The byte to write to the NVM.
8640 *****************************************************************************/
8642 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8644 int32_t error = E1000_SUCCESS;
8645 int32_t program_retries;
8648 e1000_write_ich8_byte(hw, index, byte);
8651 for (program_retries = 0; program_retries < 100; program_retries++) {
8652 e1000_read_ich8_byte(hw, index, &temp_byte);
8653 if (temp_byte == byte)
8656 e1000_write_ich8_byte(hw, index, byte);
8659 if (program_retries == 100)
8660 error = E1000_ERR_EEPROM;
8665 /******************************************************************************
8666 * Writes a single byte to the NVM using the ICH8 flash access registers.
8668 * hw - pointer to e1000_hw structure
8669 * index - The index of the byte to read.
8670 * data - The byte to write to the NVM.
8671 *****************************************************************************/
8673 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8675 int32_t status = E1000_SUCCESS;
8676 uint16_t word = (uint16_t)data;
8678 status = e1000_write_ich8_data(hw, index, 1, word);
8683 /******************************************************************************
8684 * Reads a word from the NVM using the ICH8 flash access registers.
8686 * hw - pointer to e1000_hw structure
8687 * index - The starting byte index of the word to read.
8688 * data - Pointer to a word to store the value read.
8689 *****************************************************************************/
8691 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8693 int32_t status = E1000_SUCCESS;
8694 status = e1000_read_ich8_data(hw, index, 2, data);
8698 /******************************************************************************
8699 * Writes a word to the NVM using the ICH8 flash access registers.
8701 * hw - pointer to e1000_hw structure
8702 * index - The starting byte index of the word to read.
8703 * data - The word to write to the NVM.
8704 *****************************************************************************/
8707 e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8709 int32_t status = E1000_SUCCESS;
8710 status = e1000_write_ich8_data(hw, index, 2, data);
8715 /******************************************************************************
8716 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8717 * segment N is 4096 * N + flash_reg_addr.
8719 * hw - pointer to e1000_hw structure
8720 * segment - 0 for first segment, 1 for second segment, etc.
8721 *****************************************************************************/
8723 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8725 union ich8_hws_flash_status hsfsts;
8726 union ich8_hws_flash_ctrl hsflctl;
8727 uint32_t flash_linear_address;
8729 int32_t error = E1000_ERR_EEPROM;
8730 int32_t iteration, seg_size;
8731 int32_t sector_size;
8733 int32_t error_flag = 0;
8735 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8737 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8738 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8739 * consecutive sectors. The start index for the nth Hw sector can be
8740 * calculated as = segment * 4096 + n * 256
8741 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8742 * The start index for the nth Hw sector can be calculated
8743 * as = segment * 4096
8744 * 10: Error condition
8745 * 11: The Hw sector size is much bigger than the size asked to
8746 * erase...error condition */
8747 if (hsfsts.hsf_status.berasesz == 0x0) {
8748 /* Hw sector size 256 */
8749 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8750 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8751 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8752 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8754 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8755 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8761 for (j = 0; j < iteration ; j++) {
8765 error = e1000_ich8_cycle_init(hw);
8766 if (error != E1000_SUCCESS) {
8771 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8773 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8774 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8775 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8777 /* Write the last 24 bits of an index within the block into Flash
8778 * Linear address field in Flash Address. This probably needs to
8779 * be calculated here based off the on-chip segment size and the
8780 * software segment size assumed (4K) */
8782 flash_linear_address = segment * sector_size + j * seg_size;
8783 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8784 flash_linear_address += hw->flash_base_addr;
8786 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8788 error = e1000_ich8_flash_cycle(hw, 1000000);
8789 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8790 * sequence a few more times else Done */
8791 if (error == E1000_SUCCESS) {
8794 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8795 if (hsfsts.hsf_status.flcerr == 1) {
8796 /* repeat for some time before giving up */
8798 } else if (hsfsts.hsf_status.flcdone == 0) {
8803 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8804 if (error_flag == 1)
8807 if (error_flag != 1)
8808 error = E1000_SUCCESS;
8813 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8814 uint32_t cnf_base_addr, uint32_t cnf_size)
8816 uint32_t ret_val = E1000_SUCCESS;
8817 uint16_t word_addr, reg_data, reg_addr;
8820 /* cnf_base_addr is in DWORD */
8821 word_addr = (uint16_t)(cnf_base_addr << 1);
8823 /* cnf_size is returned in size of dwords */
8824 for (i = 0; i < cnf_size; i++) {
8825 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data);
8829 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr);
8833 ret_val = e1000_get_software_flag(hw);
8834 if (ret_val != E1000_SUCCESS)
8837 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8839 e1000_release_software_flag(hw);
8847 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8849 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8851 if (hw->phy_type != e1000_phy_igp_3)
8852 return E1000_SUCCESS;
8854 /* Check if SW needs configure the PHY */
8855 reg_data = E1000_READ_REG(hw, FEXTNVM);
8856 if (!(reg_data & FEXTNVM_SW_CONFIG))
8857 return E1000_SUCCESS;
8859 /* Wait for basic configuration completes before proceeding*/
8862 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8865 } while ((!reg_data) && (loop < 50));
8867 /* Clear the Init Done bit for the next init event */
8868 reg_data = E1000_READ_REG(hw, STATUS);
8869 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
8870 E1000_WRITE_REG(hw, STATUS, reg_data);
8872 /* Make sure HW does not configure LCD from PHY extended configuration
8873 before SW configuration */
8874 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8875 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
8876 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
8877 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
8880 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
8881 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
8882 /* cnf_base_addr is in DWORD */
8883 cnf_base_addr >>= 16;
8885 /* Configure LCD from extended configuration region. */
8886 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
8893 return E1000_SUCCESS;