2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/if_bridge.h>
17 #include <linux/phy.h>
18 #include <linux/phylink.h>
23 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
26 int addr = chip->info->port_base_addr + port;
28 return mv88e6xxx_read(chip, addr, reg, val);
31 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
34 int addr = chip->info->port_base_addr + port;
36 return mv88e6xxx_write(chip, addr, reg, val);
39 /* Offset 0x01: MAC (or PCS or Physical) Control Register
41 * Link, Duplex and Flow Control have one force bit, one value bit.
43 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
44 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
45 * Newer chips need a ForcedSpd bit 13 set to consider the value.
48 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
54 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
58 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
59 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
62 case PHY_INTERFACE_MODE_RGMII_RXID:
63 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
65 case PHY_INTERFACE_MODE_RGMII_TXID:
66 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
68 case PHY_INTERFACE_MODE_RGMII_ID:
69 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
70 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
72 case PHY_INTERFACE_MODE_RGMII:
78 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
82 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
83 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
84 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
89 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
95 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
98 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
104 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
107 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
112 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
116 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
117 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
120 case LINK_FORCED_DOWN:
121 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
124 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
125 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
128 /* normal link detection */
134 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
138 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
139 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
140 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
145 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
150 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
154 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
155 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
159 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
162 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
163 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
165 case DUPLEX_UNFORCED:
166 /* normal duplex detection */
172 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
176 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
177 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
178 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
183 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
184 int speed, bool alt_bit, bool force_bit)
191 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
194 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
198 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
199 MV88E6390_PORT_MAC_CTL_ALTSPEED;
201 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
204 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
207 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
208 MV88E6390_PORT_MAC_CTL_ALTSPEED;
211 /* all bits set, fall through... */
213 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
219 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
223 reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
225 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
227 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
228 if (speed != SPEED_UNFORCED)
229 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
233 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
238 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
240 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
245 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
246 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
248 if (speed == SPEED_MAX)
254 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
255 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
258 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
259 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
261 if (speed == SPEED_MAX)
264 if (speed == 200 || speed > 1000)
267 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
270 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
271 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
273 if (speed == SPEED_MAX)
279 if (speed == 200 && port < 5)
282 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
285 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
286 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
288 if (speed == SPEED_MAX)
289 speed = port < 9 ? 1000 : 2500;
294 if (speed == 200 && port != 0)
297 if (speed == 2500 && port < 9)
300 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
303 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
304 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
306 if (speed == SPEED_MAX)
307 speed = port < 9 ? 1000 : 10000;
309 if (speed == 200 && port != 0)
312 if (speed >= 2500 && port < 9)
315 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
318 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
319 phy_interface_t mode)
325 if (mode == PHY_INTERFACE_MODE_NA)
328 if (port != 9 && port != 10)
332 case PHY_INTERFACE_MODE_1000BASEX:
333 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
335 case PHY_INTERFACE_MODE_SGMII:
336 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
338 case PHY_INTERFACE_MODE_2500BASEX:
339 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
341 case PHY_INTERFACE_MODE_XGMII:
342 case PHY_INTERFACE_MODE_XAUI:
343 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
345 case PHY_INTERFACE_MODE_RXAUI:
346 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
353 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
357 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
360 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
368 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
373 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
377 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
382 int mv88e6xxx_port_link_state(struct mv88e6xxx_chip *chip, int port,
383 struct phylink_link_state *state)
388 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
392 switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {
393 case MV88E6XXX_PORT_STS_SPEED_10:
394 state->speed = SPEED_10;
396 case MV88E6XXX_PORT_STS_SPEED_100:
397 state->speed = SPEED_100;
399 case MV88E6XXX_PORT_STS_SPEED_1000:
400 state->speed = SPEED_1000;
402 case MV88E6XXX_PORT_STS_SPEED_10000:
403 if ((reg &MV88E6XXX_PORT_STS_CMODE_MASK) ==
404 MV88E6XXX_PORT_STS_CMODE_2500BASEX)
405 state->speed = SPEED_2500;
407 state->speed = SPEED_10000;
411 state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?
412 DUPLEX_FULL : DUPLEX_HALF;
413 state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);
414 state->an_enabled = 1;
415 state->an_complete = state->link;
420 /* Offset 0x02: Jamming Control
422 * Do not limit the period of time that this port can be paused for by
423 * the remote end or the period of time that this port can pause the
426 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
429 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
433 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
438 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
439 MV88E6390_PORT_FLOW_CTL_UPDATE |
440 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
444 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
445 MV88E6390_PORT_FLOW_CTL_UPDATE |
446 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
449 /* Offset 0x04: Port Control Register */
451 static const char * const mv88e6xxx_port_state_names[] = {
452 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
453 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
454 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
455 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
458 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
463 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
467 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
470 case BR_STATE_DISABLED:
471 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
473 case BR_STATE_BLOCKING:
474 case BR_STATE_LISTENING:
475 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
477 case BR_STATE_LEARNING:
478 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
480 case BR_STATE_FORWARDING:
481 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
489 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
493 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
494 mv88e6xxx_port_state_names[state]);
499 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
500 enum mv88e6xxx_egress_mode mode)
505 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
509 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
512 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
513 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
515 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
516 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
518 case MV88E6XXX_EGRESS_MODE_TAGGED:
519 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
521 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
522 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
528 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
531 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
532 enum mv88e6xxx_frame_mode mode)
537 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
541 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
544 case MV88E6XXX_FRAME_MODE_NORMAL:
545 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
547 case MV88E6XXX_FRAME_MODE_DSA:
548 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
554 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
557 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
558 enum mv88e6xxx_frame_mode mode)
563 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
567 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
570 case MV88E6XXX_FRAME_MODE_NORMAL:
571 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
573 case MV88E6XXX_FRAME_MODE_DSA:
574 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
576 case MV88E6XXX_FRAME_MODE_PROVIDER:
577 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
579 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
580 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
586 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
589 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
590 int port, bool unicast)
595 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
600 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
602 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
604 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
607 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
608 bool unicast, bool multicast)
613 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
617 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
619 if (unicast && multicast)
620 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
622 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
624 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
626 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
628 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
631 /* Offset 0x05: Port Control 1 */
633 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
639 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
644 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
646 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
648 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
651 /* Offset 0x06: Port Based VLAN Map */
653 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
655 const u16 mask = mv88e6xxx_port_mask(chip);
659 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
666 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
670 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
675 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
677 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
681 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
682 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
686 *fid = (reg & 0xf000) >> 12;
688 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
690 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
695 *fid |= (reg & upper_mask) << 4;
701 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
703 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
707 if (fid >= mv88e6xxx_num_databases(chip))
710 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
711 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
716 reg |= (fid & 0x000f) << 12;
718 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
722 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
724 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
730 reg |= (fid >> 4) & upper_mask;
732 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
738 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
743 /* Offset 0x07: Default Port VLAN ID & Priority */
745 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
750 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
755 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
760 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
765 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
770 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
771 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
773 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
778 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
783 /* Offset 0x08: Port Control 2 Register */
785 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
786 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
787 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
788 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
789 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
792 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
793 int port, bool multicast)
798 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
803 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
805 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
807 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
810 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
811 bool unicast, bool multicast)
815 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
819 return mv88e6185_port_set_default_forward(chip, port, multicast);
822 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
828 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
832 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
833 reg |= upstream_port;
835 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
838 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
844 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
848 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
849 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
851 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
855 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
856 mv88e6xxx_port_8021q_mode_names[mode]);
861 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
866 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
870 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
872 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
875 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
881 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
885 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
888 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
889 else if (size <= 2048)
890 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
891 else if (size <= 10240)
892 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
896 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
899 /* Offset 0x09: Port Rate Control */
901 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
903 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
907 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
909 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
913 /* Offset 0x0C: Port ATU Control */
915 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
917 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
920 /* Offset 0x0D: (Priority) Override Register */
922 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
924 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
927 /* Offset 0x0f: Port Ether type */
929 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
932 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
935 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
936 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
939 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
943 /* Use a direct priority mapping for all IEEE tagged frames */
944 err = mv88e6xxx_port_write(chip, port,
945 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
950 return mv88e6xxx_port_write(chip, port,
951 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
955 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
956 int port, u16 table, u8 ptr, u16 data)
960 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
961 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
962 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
964 return mv88e6xxx_port_write(chip, port,
965 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
968 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
973 for (i = 0; i <= 7; i++) {
974 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
975 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
980 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
981 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
985 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
986 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
990 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
991 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);