2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/if_bridge.h>
17 #include <linux/phy.h>
22 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
25 int addr = chip->info->port_base_addr + port;
27 return mv88e6xxx_read(chip, addr, reg, val);
30 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
33 int addr = chip->info->port_base_addr + port;
35 return mv88e6xxx_write(chip, addr, reg, val);
38 /* Offset 0x01: MAC (or PCS or Physical) Control Register
40 * Link, Duplex and Flow Control have one force bit, one value bit.
42 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
43 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
44 * Newer chips need a ForcedSpd bit 13 set to consider the value.
47 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
53 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
57 reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
58 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
61 case PHY_INTERFACE_MODE_RGMII_RXID:
62 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
64 case PHY_INTERFACE_MODE_RGMII_TXID:
65 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
67 case PHY_INTERFACE_MODE_RGMII_ID:
68 reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
69 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
71 case PHY_INTERFACE_MODE_RGMII:
77 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
81 dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
82 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
83 reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
88 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
94 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
97 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
103 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
106 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
111 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
115 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
116 MV88E6XXX_PORT_MAC_CTL_LINK_UP);
119 case LINK_FORCED_DOWN:
120 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
123 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
124 MV88E6XXX_PORT_MAC_CTL_LINK_UP;
127 /* normal link detection */
133 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
137 dev_dbg(chip->dev, "p%d: %s link %s\n", port,
138 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
139 reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
144 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
149 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
153 reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
154 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
158 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
161 reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
162 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
164 case DUPLEX_UNFORCED:
165 /* normal duplex detection */
171 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
175 dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
176 reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
177 reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
182 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
183 int speed, bool alt_bit, bool force_bit)
190 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
193 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
197 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
198 MV88E6390_PORT_MAC_CTL_ALTSPEED;
200 ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
203 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
206 ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
207 MV88E6390_PORT_MAC_CTL_ALTSPEED;
210 /* all bits set, fall through... */
212 ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
218 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
222 reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
224 reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
226 reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
227 if (speed != SPEED_UNFORCED)
228 ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
232 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
237 dev_dbg(chip->dev, "p%d: Speed set to %d Mbps\n", port, speed);
239 dev_dbg(chip->dev, "p%d: Speed unforced\n", port);
244 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
245 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
247 if (speed == SPEED_MAX)
253 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
254 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
257 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
258 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
260 if (speed == SPEED_MAX)
263 if (speed == 200 || speed > 1000)
266 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
269 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
270 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
272 if (speed == SPEED_MAX)
278 if (speed == 200 && port < 5)
281 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
284 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
285 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
287 if (speed == SPEED_MAX)
288 speed = port < 9 ? 1000 : 2500;
293 if (speed == 200 && port != 0)
296 if (speed == 2500 && port < 9)
299 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
302 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
303 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
305 if (speed == SPEED_MAX)
306 speed = port < 9 ? 1000 : 10000;
308 if (speed == 200 && port != 0)
311 if (speed >= 2500 && port < 9)
314 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
317 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
318 phy_interface_t mode)
324 if (mode == PHY_INTERFACE_MODE_NA)
327 if (port != 9 && port != 10)
331 case PHY_INTERFACE_MODE_1000BASEX:
332 cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
334 case PHY_INTERFACE_MODE_SGMII:
335 cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
337 case PHY_INTERFACE_MODE_2500BASEX:
338 cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
340 case PHY_INTERFACE_MODE_XGMII:
341 case PHY_INTERFACE_MODE_XAUI:
342 cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
344 case PHY_INTERFACE_MODE_RXAUI:
345 cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
352 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
356 reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
359 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
367 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
372 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
376 *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
381 /* Offset 0x02: Jamming Control
383 * Do not limit the period of time that this port can be paused for by
384 * the remote end or the period of time that this port can pause the
387 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
390 return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
394 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
399 err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
400 MV88E6390_PORT_FLOW_CTL_UPDATE |
401 MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
405 return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
406 MV88E6390_PORT_FLOW_CTL_UPDATE |
407 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
410 /* Offset 0x04: Port Control Register */
412 static const char * const mv88e6xxx_port_state_names[] = {
413 [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
414 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
415 [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
416 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
419 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
424 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
428 reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
431 case BR_STATE_DISABLED:
432 state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
434 case BR_STATE_BLOCKING:
435 case BR_STATE_LISTENING:
436 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
438 case BR_STATE_LEARNING:
439 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
441 case BR_STATE_FORWARDING:
442 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
450 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
454 dev_dbg(chip->dev, "p%d: PortState set to %s\n", port,
455 mv88e6xxx_port_state_names[state]);
460 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
461 enum mv88e6xxx_egress_mode mode)
466 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
470 reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
473 case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
474 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
476 case MV88E6XXX_EGRESS_MODE_UNTAGGED:
477 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
479 case MV88E6XXX_EGRESS_MODE_TAGGED:
480 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
482 case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
483 reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
489 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
492 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
493 enum mv88e6xxx_frame_mode mode)
498 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
502 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
505 case MV88E6XXX_FRAME_MODE_NORMAL:
506 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
508 case MV88E6XXX_FRAME_MODE_DSA:
509 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
515 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
518 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
519 enum mv88e6xxx_frame_mode mode)
524 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
528 reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
531 case MV88E6XXX_FRAME_MODE_NORMAL:
532 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
534 case MV88E6XXX_FRAME_MODE_DSA:
535 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
537 case MV88E6XXX_FRAME_MODE_PROVIDER:
538 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
540 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
541 reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
547 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
550 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
551 int port, bool unicast)
556 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
561 reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
563 reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
565 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
568 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
569 bool unicast, bool multicast)
574 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
578 reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
580 if (unicast && multicast)
581 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
583 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
585 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
587 reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
589 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
592 /* Offset 0x05: Port Control 1 */
594 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
600 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
605 val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
607 val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
609 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
612 /* Offset 0x06: Port Based VLAN Map */
614 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
616 const u16 mask = mv88e6xxx_port_mask(chip);
620 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
627 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
631 dev_dbg(chip->dev, "p%d: VLANTable set to %.3x\n", port, map);
636 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
638 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
642 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
643 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
647 *fid = (reg & 0xf000) >> 12;
649 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
651 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
656 *fid |= (reg & upper_mask) << 4;
662 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
664 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
668 if (fid >= mv88e6xxx_num_databases(chip))
671 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
672 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
677 reg |= (fid & 0x000f) << 12;
679 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
683 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
685 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
691 reg |= (fid >> 4) & upper_mask;
693 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
699 dev_dbg(chip->dev, "p%d: FID set to %u\n", port, fid);
704 /* Offset 0x07: Default Port VLAN ID & Priority */
706 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
711 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
716 *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
721 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
726 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
731 reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
732 reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
734 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
739 dev_dbg(chip->dev, "p%d: DefaultVID set to %u\n", port, pvid);
744 /* Offset 0x08: Port Control 2 Register */
746 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
747 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
748 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
749 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
750 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
753 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
754 int port, bool multicast)
759 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
764 reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
766 reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
768 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
771 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
772 bool unicast, bool multicast)
776 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
780 return mv88e6185_port_set_default_forward(chip, port, multicast);
783 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
789 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
793 reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
794 reg |= upstream_port;
796 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
799 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
805 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
809 reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
810 reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
816 dev_dbg(chip->dev, "p%d: 802.1QMode set to %s\n", port,
817 mv88e6xxx_port_8021q_mode_names[mode]);
822 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
827 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
831 reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
833 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
836 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
842 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
846 reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
849 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
850 else if (size <= 2048)
851 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
852 else if (size <= 10240)
853 reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
857 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
860 /* Offset 0x09: Port Rate Control */
862 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
864 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
868 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
870 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
874 /* Offset 0x0C: Port ATU Control */
876 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
878 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
881 /* Offset 0x0D: (Priority) Override Register */
883 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
885 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
888 /* Offset 0x0f: Port Ether type */
890 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
893 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
896 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
897 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
900 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
904 /* Use a direct priority mapping for all IEEE tagged frames */
905 err = mv88e6xxx_port_write(chip, port,
906 MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
911 return mv88e6xxx_port_write(chip, port,
912 MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
916 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
917 int port, u16 table, u8 ptr, u16 data)
921 reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE | table |
922 (ptr << __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK)) |
923 (data & MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK);
925 return mv88e6xxx_port_write(chip, port,
926 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
929 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
934 for (i = 0; i <= 7; i++) {
935 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
936 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
941 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
942 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
946 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
947 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
951 table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
952 err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);