2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/phy.h>
16 #include "mv88e6xxx.h"
19 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
22 int addr = chip->info->port_base_addr + port;
24 return mv88e6xxx_read(chip, addr, reg, val);
27 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
30 int addr = chip->info->port_base_addr + port;
32 return mv88e6xxx_write(chip, addr, reg, val);
35 /* Offset 0x01: MAC (or PCS or Physical) Control Register
37 * Link, Duplex and Flow Control have one force bit, one value bit.
39 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
40 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
41 * Newer chips need a ForcedSpd bit 13 set to consider the value.
44 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
50 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
54 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
55 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
58 case PHY_INTERFACE_MODE_RGMII_RXID:
59 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
61 case PHY_INTERFACE_MODE_RGMII_TXID:
62 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
64 case PHY_INTERFACE_MODE_RGMII_ID:
65 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
66 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
68 case PHY_INTERFACE_MODE_RGMII:
74 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
78 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
79 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
80 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
85 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
91 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
94 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
100 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
103 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
108 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
112 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
115 case LINK_FORCED_DOWN:
116 reg |= PORT_PCS_CTRL_FORCE_LINK;
119 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
122 /* normal link detection */
128 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
132 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
133 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
134 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
139 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
144 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
148 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
152 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
155 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
157 case DUPLEX_UNFORCED:
158 /* normal duplex detection */
164 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
168 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
169 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
170 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
175 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
176 int speed, bool alt_bit, bool force_bit)
183 ctrl = PORT_PCS_CTRL_SPEED_10;
186 ctrl = PORT_PCS_CTRL_SPEED_100;
190 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
192 ctrl = PORT_PCS_CTRL_SPEED_200;
195 ctrl = PORT_PCS_CTRL_SPEED_1000;
198 ctrl = PORT_PCS_CTRL_SPEED_10000 | PORT_PCS_CTRL_ALTSPEED;
201 /* all bits set, fall through... */
203 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
209 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
213 reg &= ~PORT_PCS_CTRL_SPEED_MASK;
215 reg &= ~PORT_PCS_CTRL_ALTSPEED;
217 reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
218 if (speed != SPEED_UNFORCED)
219 ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
223 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
228 netdev_dbg(chip->ds->ports[port].netdev,
229 "Speed set to %d Mbps\n", speed);
231 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
236 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
237 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
239 if (speed == SPEED_MAX)
245 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
246 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
249 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
250 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
252 if (speed == SPEED_MAX)
255 if (speed == 200 || speed > 1000)
258 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
261 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
262 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
264 if (speed == SPEED_MAX)
270 if (speed == 200 && port < 5)
273 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
276 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
277 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
279 if (speed == SPEED_MAX)
280 speed = port < 9 ? 1000 : 2500;
285 if (speed == 200 && port != 0)
288 if (speed == 2500 && port < 9)
291 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
294 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
295 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
297 if (speed == SPEED_MAX)
298 speed = port < 9 ? 1000 : 10000;
300 if (speed == 200 && port != 0)
303 if (speed >= 2500 && port < 9)
306 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
309 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
310 phy_interface_t mode)
316 if (mode == PHY_INTERFACE_MODE_NA)
319 if (port != 9 && port != 10)
323 case PHY_INTERFACE_MODE_1000BASEX:
324 cmode = PORT_STATUS_CMODE_1000BASE_X;
326 case PHY_INTERFACE_MODE_SGMII:
327 cmode = PORT_STATUS_CMODE_SGMII;
329 case PHY_INTERFACE_MODE_2500BASEX:
330 cmode = PORT_STATUS_CMODE_2500BASEX;
332 case PHY_INTERFACE_MODE_XGMII:
333 cmode = PORT_STATUS_CMODE_XAUI;
335 case PHY_INTERFACE_MODE_RXAUI:
336 cmode = PORT_STATUS_CMODE_RXAUI;
343 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
347 reg &= ~PORT_STATUS_CMODE_MASK;
350 err = mv88e6xxx_port_write(chip, port, PORT_STATUS, reg);
358 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
363 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
367 *cmode = reg & PORT_STATUS_CMODE_MASK;
372 /* Offset 0x02: Pause Control
374 * Do not limit the period of time that this port can be paused for by
375 * the remote end or the period of time that this port can pause the
378 int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port)
380 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
383 int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port)
387 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
388 PORT_FLOW_CTRL_LIMIT_IN | 0);
392 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
393 PORT_FLOW_CTRL_LIMIT_OUT | 0);
396 /* Offset 0x04: Port Control Register */
398 static const char * const mv88e6xxx_port_state_names[] = {
399 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
400 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
401 [PORT_CONTROL_STATE_LEARNING] = "Learning",
402 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
405 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
410 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
414 reg &= ~PORT_CONTROL_STATE_MASK;
417 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
421 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
422 mv88e6xxx_port_state_names[state]);
427 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
433 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
437 reg &= ~PORT_CONTROL_EGRESS_MASK;
440 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
443 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
444 enum mv88e6xxx_frame_mode mode)
449 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
453 reg &= ~PORT_CONTROL_FRAME_MODE_DSA;
456 case MV88E6XXX_FRAME_MODE_NORMAL:
457 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
459 case MV88E6XXX_FRAME_MODE_DSA:
460 reg |= PORT_CONTROL_FRAME_MODE_DSA;
466 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
469 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
470 enum mv88e6xxx_frame_mode mode)
475 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
479 reg &= ~PORT_CONTROL_FRAME_MASK;
482 case MV88E6XXX_FRAME_MODE_NORMAL:
483 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
485 case MV88E6XXX_FRAME_MODE_DSA:
486 reg |= PORT_CONTROL_FRAME_MODE_DSA;
488 case MV88E6XXX_FRAME_MODE_PROVIDER:
489 reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
491 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
492 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
498 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
501 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
502 int port, bool unicast)
507 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
512 reg |= PORT_CONTROL_FORWARD_UNKNOWN;
514 reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
516 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
519 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
520 bool unicast, bool multicast)
525 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
529 reg &= ~PORT_CONTROL_EGRESS_FLOODS_MASK;
531 if (unicast && multicast)
532 reg |= PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA;
534 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
536 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
538 reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA;
540 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
543 /* Offset 0x05: Port Control 1 */
545 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
551 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &val);
556 val |= PORT_CONTROL_1_MESSAGE_PORT;
558 val &= ~PORT_CONTROL_1_MESSAGE_PORT;
560 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, val);
563 /* Offset 0x06: Port Based VLAN Map */
565 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
567 const u16 mask = mv88e6xxx_port_mask(chip);
571 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
578 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
582 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
588 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
590 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
594 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
595 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
599 *fid = (reg & 0xf000) >> 12;
601 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
603 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
607 *fid |= (reg & upper_mask) << 4;
613 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
615 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
619 if (fid >= mv88e6xxx_num_databases(chip))
622 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
623 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
628 reg |= (fid & 0x000f) << 12;
630 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
634 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
636 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
641 reg |= (fid >> 4) & upper_mask;
643 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
648 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
653 /* Offset 0x07: Default Port VLAN ID & Priority */
655 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
660 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
664 *pvid = reg & PORT_DEFAULT_VLAN_MASK;
669 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
674 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
678 reg &= ~PORT_DEFAULT_VLAN_MASK;
679 reg |= pvid & PORT_DEFAULT_VLAN_MASK;
681 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
685 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
691 /* Offset 0x08: Port Control 2 Register */
693 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
694 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
695 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
696 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
697 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
700 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
701 int port, bool multicast)
706 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
711 reg |= PORT_CONTROL_2_DEFAULT_FORWARD;
713 reg &= ~PORT_CONTROL_2_DEFAULT_FORWARD;
715 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
718 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
719 bool unicast, bool multicast)
723 err = mv88e6185_port_set_forward_unknown(chip, port, unicast);
727 return mv88e6185_port_set_default_forward(chip, port, multicast);
730 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
736 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
740 reg &= ~PORT_CONTROL_2_UPSTREAM_MASK;
741 reg |= upstream_port;
743 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
746 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
752 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
756 reg &= ~PORT_CONTROL_2_8021Q_MASK;
757 reg |= mode & PORT_CONTROL_2_8021Q_MASK;
759 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
763 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
764 mv88e6xxx_port_8021q_mode_names[mode]);
769 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
774 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
778 reg |= PORT_CONTROL_2_MAP_DA;
780 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
783 int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
788 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
792 reg |= PORT_CONTROL_2_JUMBO_10240;
794 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
797 /* Offset 0x09: Port Rate Control */
799 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
801 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);
804 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
806 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);
809 /* Offset 0x0C: Port ATU Control */
811 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
813 return mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 0);
816 /* Offset 0x0D: (Priority) Override Register */
818 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
820 return mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 0);
823 /* Offset 0x0f: Port Ether type */
825 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
828 return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
831 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
832 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
835 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
839 /* Use a direct priority mapping for all IEEE tagged frames */
840 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
844 return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
847 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
849 u8 pointer, u16 data)
853 reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
855 (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
858 return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
861 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
865 for (i = 0; i <= 7; i++) {
866 err = mv88e6xxx_port_ieeepmt_write(
867 chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
872 err = mv88e6xxx_port_ieeepmt_write(
873 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
878 err = mv88e6xxx_port_ieeepmt_write(
879 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
884 err = mv88e6xxx_port_ieeepmt_write(
885 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,