2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/phy.h>
15 #include "mv88e6xxx.h"
18 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
21 int addr = chip->info->port_base_addr + port;
23 return mv88e6xxx_read(chip, addr, reg, val);
26 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
29 int addr = chip->info->port_base_addr + port;
31 return mv88e6xxx_write(chip, addr, reg, val);
34 /* Offset 0x01: MAC (or PCS or Physical) Control Register
36 * Link, Duplex and Flow Control have one force bit, one value bit.
38 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
39 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
40 * Newer chips need a ForcedSpd bit 13 set to consider the value.
43 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
49 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
53 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
54 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
57 case PHY_INTERFACE_MODE_RGMII_RXID:
58 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
60 case PHY_INTERFACE_MODE_RGMII_TXID:
61 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
63 case PHY_INTERFACE_MODE_RGMII_ID:
64 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
65 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
67 case PHY_INTERFACE_MODE_RGMII:
73 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
77 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
78 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
79 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
84 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
90 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
93 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
99 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
102 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
107 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
111 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
114 case LINK_FORCED_DOWN:
115 reg |= PORT_PCS_CTRL_FORCE_LINK;
118 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
121 /* normal link detection */
127 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
131 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
132 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
133 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
138 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
143 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
147 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
151 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
154 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
156 case DUPLEX_UNFORCED:
157 /* normal duplex detection */
163 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
167 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
168 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
169 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
174 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
175 int speed, bool alt_bit, bool force_bit)
182 ctrl = PORT_PCS_CTRL_SPEED_10;
185 ctrl = PORT_PCS_CTRL_SPEED_100;
189 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
191 ctrl = PORT_PCS_CTRL_SPEED_200;
194 ctrl = PORT_PCS_CTRL_SPEED_1000;
197 ctrl = PORT_PCS_CTRL_SPEED_10000 | PORT_PCS_CTRL_ALTSPEED;
200 /* all bits set, fall through... */
202 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
208 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
212 reg &= ~PORT_PCS_CTRL_SPEED_MASK;
214 reg &= ~PORT_PCS_CTRL_ALTSPEED;
216 reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
217 if (speed != SPEED_UNFORCED)
218 ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
222 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
227 netdev_dbg(chip->ds->ports[port].netdev,
228 "Speed set to %d Mbps\n", speed);
230 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
235 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
236 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
238 if (speed == SPEED_MAX)
244 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
245 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
248 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
249 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
251 if (speed == SPEED_MAX)
254 if (speed == 200 || speed > 1000)
257 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
260 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
261 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
263 if (speed == SPEED_MAX)
269 if (speed == 200 && port < 5)
272 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
275 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
276 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
278 if (speed == SPEED_MAX)
279 speed = port < 9 ? 1000 : 2500;
284 if (speed == 200 && port != 0)
287 if (speed == 2500 && port < 9)
290 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
293 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
294 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
296 if (speed == SPEED_MAX)
297 speed = port < 9 ? 1000 : 10000;
299 if (speed == 200 && port != 0)
302 if (speed >= 2500 && port < 9)
305 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
308 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
309 phy_interface_t mode)
315 if (mode == PHY_INTERFACE_MODE_NA)
318 if (port != 9 && port != 10)
322 case PHY_INTERFACE_MODE_1000BASEX:
323 cmode = PORT_STATUS_CMODE_1000BASE_X;
325 case PHY_INTERFACE_MODE_SGMII:
326 cmode = PORT_STATUS_CMODE_SGMII;
328 case PHY_INTERFACE_MODE_2500BASEX:
329 cmode = PORT_STATUS_CMODE_2500BASEX;
331 case PHY_INTERFACE_MODE_XGMII:
332 cmode = PORT_STATUS_CMODE_XAUI;
334 case PHY_INTERFACE_MODE_RXAUI:
335 cmode = PORT_STATUS_CMODE_RXAUI;
342 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
346 reg &= ~PORT_STATUS_CMODE_MASK;
349 err = mv88e6xxx_port_write(chip, port, PORT_STATUS, reg);
357 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
362 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
366 *cmode = reg & PORT_STATUS_CMODE_MASK;
371 /* Offset 0x02: Pause Control
373 * Do not limit the period of time that this port can be paused for by
374 * the remote end or the period of time that this port can pause the
377 int mv88e6097_port_pause_config(struct mv88e6xxx_chip *chip, int port)
379 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
382 int mv88e6390_port_pause_config(struct mv88e6xxx_chip *chip, int port)
386 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
387 PORT_FLOW_CTRL_LIMIT_IN | 0);
391 return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
392 PORT_FLOW_CTRL_LIMIT_OUT | 0);
395 /* Offset 0x04: Port Control Register */
397 static const char * const mv88e6xxx_port_state_names[] = {
398 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
399 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
400 [PORT_CONTROL_STATE_LEARNING] = "Learning",
401 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
404 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
409 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
413 reg &= ~PORT_CONTROL_STATE_MASK;
416 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
420 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
421 mv88e6xxx_port_state_names[state]);
426 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
432 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
436 reg &= ~PORT_CONTROL_EGRESS_MASK;
439 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
442 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
443 enum mv88e6xxx_frame_mode mode)
448 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
452 reg &= ~PORT_CONTROL_FRAME_MODE_DSA;
455 case MV88E6XXX_FRAME_MODE_NORMAL:
456 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
458 case MV88E6XXX_FRAME_MODE_DSA:
459 reg |= PORT_CONTROL_FRAME_MODE_DSA;
465 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
468 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
469 enum mv88e6xxx_frame_mode mode)
474 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
478 reg &= ~PORT_CONTROL_FRAME_MASK;
481 case MV88E6XXX_FRAME_MODE_NORMAL:
482 reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
484 case MV88E6XXX_FRAME_MODE_DSA:
485 reg |= PORT_CONTROL_FRAME_MODE_DSA;
487 case MV88E6XXX_FRAME_MODE_PROVIDER:
488 reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
490 case MV88E6XXX_FRAME_MODE_ETHERTYPE:
491 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
497 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
500 int mv88e6085_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
506 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
511 reg |= PORT_CONTROL_FORWARD_UNKNOWN;
513 reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
515 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
518 int mv88e6351_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
524 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
529 reg |= PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
531 reg &= ~PORT_CONTROL_EGRESS_ALL_UNKNOWN_DA;
533 return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
536 /* Offset 0x05: Port Control 1 */
538 /* Offset 0x06: Port Based VLAN Map */
540 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
542 const u16 mask = GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
546 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
553 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
557 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
563 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
565 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
569 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
570 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
574 *fid = (reg & 0xf000) >> 12;
576 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
578 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
582 *fid |= (reg & upper_mask) << 4;
588 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
590 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
594 if (fid >= mv88e6xxx_num_databases(chip))
597 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
598 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
603 reg |= (fid & 0x000f) << 12;
605 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
609 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
611 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
616 reg |= (fid >> 4) & upper_mask;
618 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
623 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
628 /* Offset 0x07: Default Port VLAN ID & Priority */
630 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
635 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
639 *pvid = reg & PORT_DEFAULT_VLAN_MASK;
644 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
649 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
653 reg &= ~PORT_DEFAULT_VLAN_MASK;
654 reg |= pvid & PORT_DEFAULT_VLAN_MASK;
656 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
660 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
666 /* Offset 0x08: Port Control 2 Register */
668 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
669 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
670 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
671 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
672 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
675 int mv88e6095_port_set_egress_unknowns(struct mv88e6xxx_chip *chip, int port,
681 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
686 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
688 reg &= ~PORT_CONTROL_2_FORWARD_UNKNOWN;
690 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
693 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
699 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
703 reg &= ~PORT_CONTROL_2_UPSTREAM_MASK;
704 reg |= upstream_port;
706 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
709 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
715 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
719 reg &= ~PORT_CONTROL_2_8021Q_MASK;
720 reg |= mode & PORT_CONTROL_2_8021Q_MASK;
722 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
726 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
727 mv88e6xxx_port_8021q_mode_names[mode]);
732 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
737 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
741 reg |= PORT_CONTROL_2_MAP_DA;
743 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
746 int mv88e6165_port_jumbo_config(struct mv88e6xxx_chip *chip, int port)
751 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
755 reg |= PORT_CONTROL_2_JUMBO_10240;
757 return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
760 /* Offset 0x09: Port Rate Control */
762 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
764 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);
767 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
769 return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);
772 /* Offset 0x0f: Port Ether type */
774 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
777 return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
780 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
781 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
784 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
788 /* Use a direct priority mapping for all IEEE tagged frames */
789 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
793 return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
796 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
798 u8 pointer, u16 data)
802 reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
804 (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
807 return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
810 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
814 for (i = 0; i <= 7; i++) {
815 err = mv88e6xxx_port_ieeepmt_write(
816 chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
821 err = mv88e6xxx_port_ieeepmt_write(
822 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
827 err = mv88e6xxx_port_ieeepmt_write(
828 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
833 err = mv88e6xxx_port_ieeepmt_write(
834 chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,