2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include "mv88e6xxx.h"
17 int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
20 int addr = chip->info->port_base_addr + port;
22 return mv88e6xxx_read(chip, addr, reg, val);
25 int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
28 int addr = chip->info->port_base_addr + port;
30 return mv88e6xxx_write(chip, addr, reg, val);
33 /* Offset 0x01: MAC (or PCS or Physical) Control Register
35 * Link, Duplex and Flow Control have one force bit, one value bit.
37 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
38 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
39 * Newer chips need a ForcedSpd bit 13 set to consider the value.
42 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
48 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
52 reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
53 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
56 case PHY_INTERFACE_MODE_RGMII_RXID:
57 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
59 case PHY_INTERFACE_MODE_RGMII_TXID:
60 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
62 case PHY_INTERFACE_MODE_RGMII_ID:
63 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
64 PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
66 case PHY_INTERFACE_MODE_RGMII:
72 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
76 netdev_dbg(chip->ds->ports[port].netdev, "delay RXCLK %s, TXCLK %s\n",
77 reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
78 reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
83 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
89 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
92 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
98 return mv88e6xxx_port_set_rgmii_delay(chip, port, mode);
101 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
106 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
110 reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
113 case LINK_FORCED_DOWN:
114 reg |= PORT_PCS_CTRL_FORCE_LINK;
117 reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
120 /* normal link detection */
126 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
130 netdev_dbg(chip->ds->ports[port].netdev, "%s link %s\n",
131 reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
132 reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
137 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
142 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
146 reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
150 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
153 reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
155 case DUPLEX_UNFORCED:
156 /* normal duplex detection */
162 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
166 netdev_dbg(chip->ds->ports[port].netdev, "%s %s duplex\n",
167 reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
168 reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
173 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
174 int speed, bool alt_bit, bool force_bit)
181 ctrl = PORT_PCS_CTRL_SPEED_10;
184 ctrl = PORT_PCS_CTRL_SPEED_100;
188 ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
190 ctrl = PORT_PCS_CTRL_SPEED_200;
193 ctrl = PORT_PCS_CTRL_SPEED_1000;
196 ctrl = PORT_PCS_CTRL_SPEED_1000 | PORT_PCS_CTRL_ALTSPEED;
199 /* all bits set, fall through... */
201 ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
207 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
211 reg &= ~PORT_PCS_CTRL_SPEED_MASK;
213 reg &= ~PORT_PCS_CTRL_ALTSPEED;
215 reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
217 ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
221 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
226 netdev_dbg(chip->ds->ports[port].netdev,
227 "Speed set to %d Mbps\n", speed);
229 netdev_dbg(chip->ds->ports[port].netdev, "Speed unforced\n");
234 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
235 int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
237 if (speed == SPEED_MAX)
243 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
244 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
247 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
248 int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
250 if (speed == SPEED_MAX)
253 if (speed == 200 || speed > 1000)
256 return mv88e6xxx_port_set_speed(chip, port, speed, false, false);
259 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
260 int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
262 if (speed == SPEED_MAX)
268 if (speed == 200 && port < 5)
271 return mv88e6xxx_port_set_speed(chip, port, speed, true, false);
274 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
275 int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
277 if (speed == SPEED_MAX)
278 speed = port < 9 ? 1000 : 2500;
283 if (speed == 200 && port != 0)
286 if (speed == 2500 && port < 9)
289 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
292 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
293 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed)
295 if (speed == SPEED_MAX)
296 speed = port < 9 ? 1000 : 10000;
298 if (speed == 200 && port != 0)
301 if (speed >= 2500 && port < 9)
304 return mv88e6xxx_port_set_speed(chip, port, speed, true, true);
307 /* Offset 0x04: Port Control Register */
309 static const char * const mv88e6xxx_port_state_names[] = {
310 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
311 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
312 [PORT_CONTROL_STATE_LEARNING] = "Learning",
313 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
316 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
321 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
325 reg &= ~PORT_CONTROL_STATE_MASK;
328 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
332 netdev_dbg(chip->ds->ports[port].netdev, "PortState set to %s\n",
333 mv88e6xxx_port_state_names[state]);
338 /* Offset 0x05: Port Control 1 */
340 /* Offset 0x06: Port Based VLAN Map */
342 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
344 const u16 mask = GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
348 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
355 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
359 netdev_dbg(chip->ds->ports[port].netdev, "VLANTable set to %.3x\n",
365 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
367 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
371 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
372 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
376 *fid = (reg & 0xf000) >> 12;
378 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
380 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
384 *fid |= (reg & upper_mask) << 4;
390 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
392 const u16 upper_mask = (mv88e6xxx_num_databases(chip) - 1) >> 4;
396 if (fid >= mv88e6xxx_num_databases(chip))
399 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
400 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
405 reg |= (fid & 0x000f) << 12;
407 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
411 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
413 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
418 reg |= (fid >> 4) & upper_mask;
420 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
425 netdev_dbg(chip->ds->ports[port].netdev, "FID set to %u\n", fid);
430 /* Offset 0x07: Default Port VLAN ID & Priority */
432 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
437 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
441 *pvid = reg & PORT_DEFAULT_VLAN_MASK;
446 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
451 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
455 reg &= ~PORT_DEFAULT_VLAN_MASK;
456 reg |= pvid & PORT_DEFAULT_VLAN_MASK;
458 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
462 netdev_dbg(chip->ds->ports[port].netdev, "DefaultVID set to %u\n",
468 /* Offset 0x08: Port Control 2 Register */
470 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
471 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
472 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
473 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
474 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
477 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
483 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
487 reg &= ~PORT_CONTROL_2_8021Q_MASK;
488 reg |= mode & PORT_CONTROL_2_8021Q_MASK;
490 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
494 netdev_dbg(chip->ds->ports[port].netdev, "802.1QMode set to %s\n",
495 mv88e6xxx_port_8021q_mode_names[mode]);