2 * Marvell 88E6xxx Switch Global 2 Registers support (device address
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
16 #include <linux/irqdomain.h>
17 #include "mv88e6xxx.h"
20 #define ADDR_GLOBAL2 0x1c
22 static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
24 return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
27 static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
29 return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
32 static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
34 return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
37 static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
39 return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
42 /* Offset 0x02: Management Enable 2x */
43 /* Offset 0x03: Management Enable 0x */
45 int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
49 /* Consider the frames with reserved multicast destination
50 * addresses matching 01:80:c2:00:00:2x as MGMT.
52 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
53 err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
58 /* Consider the frames with reserved multicast destination
59 * addresses matching 01:80:c2:00:00:0x as MGMT.
61 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))
62 return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
67 /* Offset 0x06: Device Mapping Table register */
69 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
72 u16 val = (target << 8) | (port & 0xf);
74 return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val);
77 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
82 /* Initialize the routing port to the 32 possible target devices */
83 for (target = 0; target < 32; ++target) {
86 if (target < DSA_MAX_SWITCHES) {
87 port = chip->ds->rtable[target];
88 if (port == DSA_RTABLE_NONE)
92 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
100 /* Offset 0x07: Trunk Mask Table register */
102 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
105 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
106 u16 val = (num << 12) | (mask & port_mask);
109 val |= GLOBAL2_TRUNK_MASK_HASK;
111 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val);
114 /* Offset 0x08: Trunk Mapping Table register */
116 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
119 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
120 u16 val = (id << 11) | (map & port_mask);
122 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val);
125 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
127 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
130 /* Clear all eight possible Trunk Mask vectors */
131 for (i = 0; i < 8; ++i) {
132 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
137 /* Clear all sixteen possible Trunk ID routing vectors */
138 for (i = 0; i < 16; ++i) {
139 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
147 /* Offset 0x09: Ingress Rate Command register
148 * Offset 0x0A: Ingress Rate Data register
151 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
155 /* Init all Ingress Rate Limit resources of all ports */
156 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
157 /* XXX newer chips (like 88E6390) have different 2-bit ops */
158 err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD,
159 GLOBAL2_IRL_CMD_OP_INIT_ALL |
164 /* Wait for the operation to complete */
165 err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD,
166 GLOBAL2_IRL_CMD_BUSY);
174 /* Offset 0x0D: Switch MAC/WoL/WoF register */
176 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
177 unsigned int pointer, u8 data)
179 u16 val = (pointer << 8) | data;
181 return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val);
184 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
188 for (i = 0; i < 6; i++) {
189 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
197 /* Offset 0x0F: Priority Override Table */
199 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
202 u16 val = (pointer << 8) | (data & 0x7);
204 return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
207 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
211 /* Clear all sixteen possible Priority Override entries */
212 for (i = 0; i < 16; i++) {
213 err = mv88e6xxx_g2_pot_write(chip, i, 0);
221 /* Offset 0x14: EEPROM Command
222 * Offset 0x15: EEPROM Data (for 16-bit data access)
223 * Offset 0x15: EEPROM Addr (for 8-bit data access)
226 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
228 return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD,
229 GLOBAL2_EEPROM_CMD_BUSY |
230 GLOBAL2_EEPROM_CMD_RUNNING);
233 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
237 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd);
241 return mv88e6xxx_g2_eeprom_wait(chip);
244 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
247 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ;
250 err = mv88e6xxx_g2_eeprom_wait(chip);
254 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
258 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
262 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &cmd);
271 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
274 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | GLOBAL2_EEPROM_CMD_WRITE_EN;
277 err = mv88e6xxx_g2_eeprom_wait(chip);
281 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
285 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
288 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
291 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
294 err = mv88e6xxx_g2_eeprom_wait(chip);
298 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
302 return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data);
305 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
308 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
311 err = mv88e6xxx_g2_eeprom_wait(chip);
315 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data);
319 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
322 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
323 struct ethtool_eeprom *eeprom, u8 *data)
325 unsigned int offset = eeprom->offset;
326 unsigned int len = eeprom->len;
332 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
345 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
346 struct ethtool_eeprom *eeprom, u8 *data)
348 unsigned int offset = eeprom->offset;
349 unsigned int len = eeprom->len;
355 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
368 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
369 struct ethtool_eeprom *eeprom, u8 *data)
371 unsigned int offset = eeprom->offset;
372 unsigned int len = eeprom->len;
379 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
383 *data++ = (val >> 8) & 0xff;
391 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
395 *data++ = val & 0xff;
396 *data++ = (val >> 8) & 0xff;
404 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
408 *data++ = val & 0xff;
418 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
419 struct ethtool_eeprom *eeprom, u8 *data)
421 unsigned int offset = eeprom->offset;
422 unsigned int len = eeprom->len;
426 /* Ensure the RO WriteEn bit is set */
427 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val);
431 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
437 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
441 val = (*data++ << 8) | (val & 0xff);
443 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
456 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
466 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
470 val = (val & 0xff00) | *data++;
472 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
484 /* Offset 0x18: SMI PHY Command Register
485 * Offset 0x19: SMI PHY Data Register
488 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
490 return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD,
491 GLOBAL2_SMI_PHY_CMD_BUSY);
494 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
498 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd);
502 return mv88e6xxx_g2_smi_phy_wait(chip);
505 static int mv88e6xxx_g2_smi_phy_write_addr(struct mv88e6xxx_chip *chip,
506 int addr, int device, int reg,
509 int cmd = SMI_CMD_OP_45_WRITE_ADDR | (addr << 5) | device;
513 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
515 err = mv88e6xxx_g2_smi_phy_wait(chip);
519 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, reg);
523 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
526 int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, int addr,
527 int reg_c45, u16 *val, bool external)
529 int device = (reg_c45 >> 16) & 0x1f;
530 int reg = reg_c45 & 0xffff;
534 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
539 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA | (addr << 5) | device;
542 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
544 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
548 err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
557 int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, int addr,
558 int reg, u16 *val, bool external)
560 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
564 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
566 err = mv88e6xxx_g2_smi_phy_wait(chip);
570 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
574 return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
577 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
579 int addr, int reg, u16 *val)
581 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
582 bool external = mdio_bus->external;
584 if (reg & MII_ADDR_C45)
585 return mv88e6xxx_g2_smi_phy_read_c45(chip, addr, reg, val,
587 return mv88e6xxx_g2_smi_phy_read_c22(chip, addr, reg, val, external);
590 int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, int addr,
591 int reg_c45, u16 val, bool external)
593 int device = (reg_c45 >> 16) & 0x1f;
594 int reg = reg_c45 & 0xffff;
598 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
603 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA | (addr << 5) | device;
606 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
608 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
612 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
619 int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, int addr,
620 int reg, u16 val, bool external)
622 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
626 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
628 err = mv88e6xxx_g2_smi_phy_wait(chip);
632 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
636 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
639 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
641 int addr, int reg, u16 val)
643 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
644 bool external = mdio_bus->external;
646 if (reg & MII_ADDR_C45)
647 return mv88e6xxx_g2_smi_phy_write_c45(chip, addr, reg, val,
650 return mv88e6xxx_g2_smi_phy_write_c22(chip, addr, reg, val, external);
653 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
657 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
659 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
664 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
668 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
670 reg &= ~(GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
671 GLOBAL2_WDOG_CONTROL_QC_ENABLE);
673 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, reg);
676 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
678 return mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL,
679 GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
680 GLOBAL2_WDOG_CONTROL_QC_ENABLE |
681 GLOBAL2_WDOG_CONTROL_SWRESET);
684 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
685 .irq_action = mv88e6097_watchdog_action,
686 .irq_setup = mv88e6097_watchdog_setup,
687 .irq_free = mv88e6097_watchdog_free,
690 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
692 return mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
693 GLOBAL2_WDOG_INT_ENABLE |
694 GLOBAL2_WDOG_CUT_THROUGH |
695 GLOBAL2_WDOG_QUEUE_CONTROLLER |
696 GLOBAL2_WDOG_EGRESS |
697 GLOBAL2_WDOG_FORCE_IRQ);
700 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
705 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_EVENT);
706 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
708 dev_info(chip->dev, "Watchdog event: 0x%04x",
709 reg & GLOBAL2_WDOG_DATA_MASK);
711 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_HISTORY);
712 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
714 dev_info(chip->dev, "Watchdog history: 0x%04x",
715 reg & GLOBAL2_WDOG_DATA_MASK);
717 /* Trigger a software reset to try to recover the switch */
718 if (chip->info->ops->reset)
719 chip->info->ops->reset(chip);
721 mv88e6390_watchdog_setup(chip);
726 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
728 mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
729 GLOBAL2_WDOG_INT_ENABLE);
732 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
733 .irq_action = mv88e6390_watchdog_action,
734 .irq_setup = mv88e6390_watchdog_setup,
735 .irq_free = mv88e6390_watchdog_free,
738 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
740 struct mv88e6xxx_chip *chip = dev_id;
741 irqreturn_t ret = IRQ_NONE;
743 mutex_lock(&chip->reg_lock);
744 if (chip->info->ops->watchdog_ops->irq_action)
745 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
746 mutex_unlock(&chip->reg_lock);
751 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
753 mutex_lock(&chip->reg_lock);
754 if (chip->info->ops->watchdog_ops->irq_free)
755 chip->info->ops->watchdog_ops->irq_free(chip);
756 mutex_unlock(&chip->reg_lock);
758 free_irq(chip->watchdog_irq, chip);
759 irq_dispose_mapping(chip->watchdog_irq);
762 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
766 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
767 GLOBAL2_INT_SOURCE_WATCHDOG);
768 if (chip->watchdog_irq < 0)
769 return chip->watchdog_irq;
771 err = request_threaded_irq(chip->watchdog_irq, NULL,
772 mv88e6xxx_g2_watchdog_thread_fn,
773 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
774 "mv88e6xxx-watchdog", chip);
778 mutex_lock(&chip->reg_lock);
779 if (chip->info->ops->watchdog_ops->irq_setup)
780 err = chip->info->ops->watchdog_ops->irq_setup(chip);
781 mutex_unlock(&chip->reg_lock);
786 static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
788 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
789 unsigned int n = d->hwirq;
791 chip->g2_irq.masked |= (1 << n);
794 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
796 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
797 unsigned int n = d->hwirq;
799 chip->g2_irq.masked &= ~(1 << n);
802 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
804 struct mv88e6xxx_chip *chip = dev_id;
805 unsigned int nhandled = 0;
806 unsigned int sub_irq;
811 mutex_lock(&chip->reg_lock);
812 err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®);
813 mutex_unlock(&chip->reg_lock);
817 for (n = 0; n < 16; ++n) {
818 if (reg & (1 << n)) {
819 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
820 handle_nested_irq(sub_irq);
825 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
828 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
830 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
832 mutex_lock(&chip->reg_lock);
835 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
837 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
839 mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
841 mutex_unlock(&chip->reg_lock);
844 static struct irq_chip mv88e6xxx_g2_irq_chip = {
845 .name = "mv88e6xxx-g2",
846 .irq_mask = mv88e6xxx_g2_irq_mask,
847 .irq_unmask = mv88e6xxx_g2_irq_unmask,
848 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
849 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
852 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
854 irq_hw_number_t hwirq)
856 struct mv88e6xxx_chip *chip = d->host_data;
858 irq_set_chip_data(irq, d->host_data);
859 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
860 irq_set_noprobe(irq);
865 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
866 .map = mv88e6xxx_g2_irq_domain_map,
867 .xlate = irq_domain_xlate_twocell,
870 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
874 mv88e6xxx_g2_watchdog_free(chip);
876 free_irq(chip->device_irq, chip);
877 irq_dispose_mapping(chip->device_irq);
879 for (irq = 0; irq < 16; irq++) {
880 virq = irq_find_mapping(chip->g2_irq.domain, irq);
881 irq_dispose_mapping(virq);
884 irq_domain_remove(chip->g2_irq.domain);
887 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
891 if (!chip->dev->of_node)
894 chip->g2_irq.domain = irq_domain_add_simple(
895 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
896 if (!chip->g2_irq.domain)
899 for (irq = 0; irq < 16; irq++)
900 irq_create_mapping(chip->g2_irq.domain, irq);
902 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
903 chip->g2_irq.masked = ~0;
905 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
906 GLOBAL_STATUS_IRQ_DEVICE);
907 if (chip->device_irq < 0) {
908 err = chip->device_irq;
912 err = request_threaded_irq(chip->device_irq, NULL,
913 mv88e6xxx_g2_irq_thread_fn,
914 IRQF_ONESHOT, "mv88e6xxx-g1", chip);
918 return mv88e6xxx_g2_watchdog_setup(chip);
921 for (irq = 0; irq < 16; irq++) {
922 virq = irq_find_mapping(chip->g2_irq.domain, irq);
923 irq_dispose_mapping(virq);
926 irq_domain_remove(chip->g2_irq.domain);
931 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
936 /* Ignore removed tag data on doubly tagged packets, disable
937 * flow control messages, force flow control priority to the
938 * highest, and send all special multicast frames to the CPU
939 * port at the highest priority.
941 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
942 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
943 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
944 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
945 err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
949 /* Program the DSA routing table. */
950 err = mv88e6xxx_g2_set_device_mapping(chip);
954 /* Clear all trunk masks and mapping. */
955 err = mv88e6xxx_g2_clear_trunk(chip);
959 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
960 /* Disable ingress rate limiting by resetting all per port
961 * ingress rate limit resources to their initial state.
963 err = mv88e6xxx_g2_clear_irl(chip);
968 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
969 /* Initialize Cross-chip Port VLAN Table to reset defaults */
970 err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR,
971 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
976 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
977 /* Clear the priority override table. */
978 err = mv88e6xxx_g2_clear_pot(chip);