2 * Marvell 88E6xxx Switch Global 2 Registers support (device address
5 * Copyright (c) 2008 Marvell Semiconductor
7 * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/irqdomain.h>
16 #include "mv88e6xxx.h"
19 #define ADDR_GLOBAL2 0x1c
21 static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
23 return mv88e6xxx_read(chip, ADDR_GLOBAL2, reg, val);
26 static int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
28 return mv88e6xxx_write(chip, ADDR_GLOBAL2, reg, val);
31 static int mv88e6xxx_g2_update(struct mv88e6xxx_chip *chip, int reg, u16 update)
33 return mv88e6xxx_update(chip, ADDR_GLOBAL2, reg, update);
36 static int mv88e6xxx_g2_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
38 return mv88e6xxx_wait(chip, ADDR_GLOBAL2, reg, mask);
41 /* Offset 0x02: Management Enable 2x */
42 /* Offset 0x03: Management Enable 0x */
44 int mv88e6095_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
48 /* Consider the frames with reserved multicast destination
49 * addresses matching 01:80:c2:00:00:2x as MGMT.
51 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
52 err = mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_2X, 0xffff);
57 /* Consider the frames with reserved multicast destination
58 * addresses matching 01:80:c2:00:00:0x as MGMT.
60 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X))
61 return mv88e6xxx_g2_write(chip, GLOBAL2_MGMT_EN_0X, 0xffff);
66 /* Offset 0x06: Device Mapping Table register */
68 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
71 u16 val = (target << 8) | (port & 0xf);
73 return mv88e6xxx_g2_update(chip, GLOBAL2_DEVICE_MAPPING, val);
76 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
81 /* Initialize the routing port to the 32 possible target devices */
82 for (target = 0; target < 32; ++target) {
85 if (target < DSA_MAX_SWITCHES) {
86 port = chip->ds->rtable[target];
87 if (port == DSA_RTABLE_NONE)
91 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
99 /* Offset 0x07: Trunk Mask Table register */
101 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
104 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
105 u16 val = (num << 12) | (mask & port_mask);
108 val |= GLOBAL2_TRUNK_MASK_HASK;
110 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MASK, val);
113 /* Offset 0x08: Trunk Mapping Table register */
115 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
118 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
119 u16 val = (id << 11) | (map & port_mask);
121 return mv88e6xxx_g2_update(chip, GLOBAL2_TRUNK_MAPPING, val);
124 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
126 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
129 /* Clear all eight possible Trunk Mask vectors */
130 for (i = 0; i < 8; ++i) {
131 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
136 /* Clear all sixteen possible Trunk ID routing vectors */
137 for (i = 0; i < 16; ++i) {
138 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
146 /* Offset 0x09: Ingress Rate Command register
147 * Offset 0x0A: Ingress Rate Data register
150 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
154 /* Init all Ingress Rate Limit resources of all ports */
155 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
156 /* XXX newer chips (like 88E6390) have different 2-bit ops */
157 err = mv88e6xxx_g2_write(chip, GLOBAL2_IRL_CMD,
158 GLOBAL2_IRL_CMD_OP_INIT_ALL |
163 /* Wait for the operation to complete */
164 err = mv88e6xxx_g2_wait(chip, GLOBAL2_IRL_CMD,
165 GLOBAL2_IRL_CMD_BUSY);
173 /* Offset 0x0D: Switch MAC/WoL/WoF register */
175 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
176 unsigned int pointer, u8 data)
178 u16 val = (pointer << 8) | data;
180 return mv88e6xxx_g2_update(chip, GLOBAL2_SWITCH_MAC, val);
183 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
187 for (i = 0; i < 6; i++) {
188 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
196 /* Offset 0x0F: Priority Override Table */
198 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
201 u16 val = (pointer << 8) | (data & 0x7);
203 return mv88e6xxx_g2_update(chip, GLOBAL2_PRIO_OVERRIDE, val);
206 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
210 /* Clear all sixteen possible Priority Override entries */
211 for (i = 0; i < 16; i++) {
212 err = mv88e6xxx_g2_pot_write(chip, i, 0);
220 /* Offset 0x14: EEPROM Command
221 * Offset 0x15: EEPROM Data (for 16-bit data access)
222 * Offset 0x15: EEPROM Addr (for 8-bit data access)
225 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
227 return mv88e6xxx_g2_wait(chip, GLOBAL2_EEPROM_CMD,
228 GLOBAL2_EEPROM_CMD_BUSY |
229 GLOBAL2_EEPROM_CMD_RUNNING);
232 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
236 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_CMD, cmd);
240 return mv88e6xxx_g2_eeprom_wait(chip);
243 static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
246 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ;
249 err = mv88e6xxx_g2_eeprom_wait(chip);
253 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
257 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
261 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &cmd);
270 static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
273 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | GLOBAL2_EEPROM_CMD_WRITE_EN;
276 err = mv88e6xxx_g2_eeprom_wait(chip);
280 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_ADDR, addr);
284 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
287 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
290 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
293 err = mv88e6xxx_g2_eeprom_wait(chip);
297 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
301 return mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_DATA, data);
304 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
307 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
310 err = mv88e6xxx_g2_eeprom_wait(chip);
314 err = mv88e6xxx_g2_write(chip, GLOBAL2_EEPROM_DATA, data);
318 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
321 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
322 struct ethtool_eeprom *eeprom, u8 *data)
324 unsigned int offset = eeprom->offset;
325 unsigned int len = eeprom->len;
331 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
344 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
345 struct ethtool_eeprom *eeprom, u8 *data)
347 unsigned int offset = eeprom->offset;
348 unsigned int len = eeprom->len;
354 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
367 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
368 struct ethtool_eeprom *eeprom, u8 *data)
370 unsigned int offset = eeprom->offset;
371 unsigned int len = eeprom->len;
378 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
382 *data++ = (val >> 8) & 0xff;
390 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
394 *data++ = val & 0xff;
395 *data++ = (val >> 8) & 0xff;
403 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
407 *data++ = val & 0xff;
417 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
418 struct ethtool_eeprom *eeprom, u8 *data)
420 unsigned int offset = eeprom->offset;
421 unsigned int len = eeprom->len;
425 /* Ensure the RO WriteEn bit is set */
426 err = mv88e6xxx_g2_read(chip, GLOBAL2_EEPROM_CMD, &val);
430 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
436 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
440 val = (*data++ << 8) | (val & 0xff);
442 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
455 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
465 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
469 val = (val & 0xff00) | *data++;
471 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
483 /* Offset 0x18: SMI PHY Command Register
484 * Offset 0x19: SMI PHY Data Register
487 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
489 return mv88e6xxx_g2_wait(chip, GLOBAL2_SMI_PHY_CMD,
490 GLOBAL2_SMI_PHY_CMD_BUSY);
493 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
497 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_CMD, cmd);
501 return mv88e6xxx_g2_smi_phy_wait(chip);
504 static int mv88e6xxx_g2_smi_phy_write_addr(struct mv88e6xxx_chip *chip,
505 int addr, int device, int reg,
508 int cmd = SMI_CMD_OP_45_WRITE_ADDR | (addr << 5) | device;
512 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
514 err = mv88e6xxx_g2_smi_phy_wait(chip);
518 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, reg);
522 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
525 int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, int addr,
526 int reg_c45, u16 *val, bool external)
528 int device = (reg_c45 >> 16) & 0x1f;
529 int reg = reg_c45 & 0xffff;
533 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
538 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_READ_DATA | (addr << 5) | device;
541 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
543 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
547 err = mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
556 int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, int addr,
557 int reg, u16 *val, bool external)
559 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
563 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
565 err = mv88e6xxx_g2_smi_phy_wait(chip);
569 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
573 return mv88e6xxx_g2_read(chip, GLOBAL2_SMI_PHY_DATA, val);
576 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
578 int addr, int reg, u16 *val)
580 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
581 bool external = mdio_bus->external;
583 if (reg & MII_ADDR_C45)
584 return mv88e6xxx_g2_smi_phy_read_c45(chip, addr, reg, val,
586 return mv88e6xxx_g2_smi_phy_read_c22(chip, addr, reg, val, external);
589 int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, int addr,
590 int reg_c45, u16 val, bool external)
592 int device = (reg_c45 >> 16) & 0x1f;
593 int reg = reg_c45 & 0xffff;
597 err = mv88e6xxx_g2_smi_phy_write_addr(chip, addr, device, reg,
602 cmd = GLOBAL2_SMI_PHY_CMD_OP_45_WRITE_DATA | (addr << 5) | device;
605 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
607 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
611 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
618 int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, int addr,
619 int reg, u16 val, bool external)
621 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
625 cmd |= GLOBAL2_SMI_PHY_CMD_EXTERNAL;
627 err = mv88e6xxx_g2_smi_phy_wait(chip);
631 err = mv88e6xxx_g2_write(chip, GLOBAL2_SMI_PHY_DATA, val);
635 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
638 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
640 int addr, int reg, u16 val)
642 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
643 bool external = mdio_bus->external;
645 if (reg & MII_ADDR_C45)
646 return mv88e6xxx_g2_smi_phy_write_c45(chip, addr, reg, val,
649 return mv88e6xxx_g2_smi_phy_write_c22(chip, addr, reg, val, external);
652 static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
656 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
658 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
663 static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
667 mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
669 reg &= ~(GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
670 GLOBAL2_WDOG_CONTROL_QC_ENABLE);
672 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, reg);
675 static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
677 return mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL,
678 GLOBAL2_WDOG_CONTROL_EGRESS_ENABLE |
679 GLOBAL2_WDOG_CONTROL_QC_ENABLE |
680 GLOBAL2_WDOG_CONTROL_SWRESET);
683 const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
684 .irq_action = mv88e6097_watchdog_action,
685 .irq_setup = mv88e6097_watchdog_setup,
686 .irq_free = mv88e6097_watchdog_free,
689 static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
691 return mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
692 GLOBAL2_WDOG_INT_ENABLE |
693 GLOBAL2_WDOG_CUT_THROUGH |
694 GLOBAL2_WDOG_QUEUE_CONTROLLER |
695 GLOBAL2_WDOG_EGRESS |
696 GLOBAL2_WDOG_FORCE_IRQ);
699 static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
704 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_EVENT);
705 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
707 dev_info(chip->dev, "Watchdog event: 0x%04x",
708 reg & GLOBAL2_WDOG_DATA_MASK);
710 mv88e6xxx_g2_write(chip, GLOBAL2_WDOG_CONTROL, GLOBAL2_WDOG_HISTORY);
711 err = mv88e6xxx_g2_read(chip, GLOBAL2_WDOG_CONTROL, ®);
713 dev_info(chip->dev, "Watchdog history: 0x%04x",
714 reg & GLOBAL2_WDOG_DATA_MASK);
716 /* Trigger a software reset to try to recover the switch */
717 if (chip->info->ops->reset)
718 chip->info->ops->reset(chip);
720 mv88e6390_watchdog_setup(chip);
725 static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
727 mv88e6xxx_g2_update(chip, GLOBAL2_WDOG_CONTROL,
728 GLOBAL2_WDOG_INT_ENABLE);
731 const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
732 .irq_action = mv88e6390_watchdog_action,
733 .irq_setup = mv88e6390_watchdog_setup,
734 .irq_free = mv88e6390_watchdog_free,
737 static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
739 struct mv88e6xxx_chip *chip = dev_id;
740 irqreturn_t ret = IRQ_NONE;
742 mutex_lock(&chip->reg_lock);
743 if (chip->info->ops->watchdog_ops->irq_action)
744 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
745 mutex_unlock(&chip->reg_lock);
750 static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
752 mutex_lock(&chip->reg_lock);
753 if (chip->info->ops->watchdog_ops->irq_free)
754 chip->info->ops->watchdog_ops->irq_free(chip);
755 mutex_unlock(&chip->reg_lock);
757 free_irq(chip->watchdog_irq, chip);
758 irq_dispose_mapping(chip->watchdog_irq);
761 static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
765 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
766 GLOBAL2_INT_SOURCE_WATCHDOG);
767 if (chip->watchdog_irq < 0)
768 return chip->watchdog_irq;
770 err = request_threaded_irq(chip->watchdog_irq, NULL,
771 mv88e6xxx_g2_watchdog_thread_fn,
772 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
773 "mv88e6xxx-watchdog", chip);
777 mutex_lock(&chip->reg_lock);
778 if (chip->info->ops->watchdog_ops->irq_setup)
779 err = chip->info->ops->watchdog_ops->irq_setup(chip);
780 mutex_unlock(&chip->reg_lock);
785 static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
787 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
788 unsigned int n = d->hwirq;
790 chip->g2_irq.masked |= (1 << n);
793 static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
795 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
796 unsigned int n = d->hwirq;
798 chip->g2_irq.masked &= ~(1 << n);
801 static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
803 struct mv88e6xxx_chip *chip = dev_id;
804 unsigned int nhandled = 0;
805 unsigned int sub_irq;
810 mutex_lock(&chip->reg_lock);
811 err = mv88e6xxx_g2_read(chip, GLOBAL2_INT_SOURCE, ®);
812 mutex_unlock(&chip->reg_lock);
816 for (n = 0; n < 16; ++n) {
817 if (reg & (1 << n)) {
818 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
819 handle_nested_irq(sub_irq);
824 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
827 static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
829 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
831 mutex_lock(&chip->reg_lock);
834 static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
836 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
838 mv88e6xxx_g2_write(chip, GLOBAL2_INT_MASK, ~chip->g2_irq.masked);
840 mutex_unlock(&chip->reg_lock);
843 static struct irq_chip mv88e6xxx_g2_irq_chip = {
844 .name = "mv88e6xxx-g2",
845 .irq_mask = mv88e6xxx_g2_irq_mask,
846 .irq_unmask = mv88e6xxx_g2_irq_unmask,
847 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
848 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
851 static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
853 irq_hw_number_t hwirq)
855 struct mv88e6xxx_chip *chip = d->host_data;
857 irq_set_chip_data(irq, d->host_data);
858 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
859 irq_set_noprobe(irq);
864 static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
865 .map = mv88e6xxx_g2_irq_domain_map,
866 .xlate = irq_domain_xlate_twocell,
869 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
873 mv88e6xxx_g2_watchdog_free(chip);
875 free_irq(chip->device_irq, chip);
876 irq_dispose_mapping(chip->device_irq);
878 for (irq = 0; irq < 16; irq++) {
879 virq = irq_find_mapping(chip->g2_irq.domain, irq);
880 irq_dispose_mapping(virq);
883 irq_domain_remove(chip->g2_irq.domain);
886 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
890 if (!chip->dev->of_node)
893 chip->g2_irq.domain = irq_domain_add_simple(
894 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
895 if (!chip->g2_irq.domain)
898 for (irq = 0; irq < 16; irq++)
899 irq_create_mapping(chip->g2_irq.domain, irq);
901 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
902 chip->g2_irq.masked = ~0;
904 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
905 GLOBAL_STATUS_IRQ_DEVICE);
906 if (chip->device_irq < 0) {
907 err = chip->device_irq;
911 err = request_threaded_irq(chip->device_irq, NULL,
912 mv88e6xxx_g2_irq_thread_fn,
913 IRQF_ONESHOT, "mv88e6xxx-g1", chip);
917 return mv88e6xxx_g2_watchdog_setup(chip);
920 for (irq = 0; irq < 16; irq++) {
921 virq = irq_find_mapping(chip->g2_irq.domain, irq);
922 irq_dispose_mapping(virq);
925 irq_domain_remove(chip->g2_irq.domain);
930 int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
935 /* Ignore removed tag data on doubly tagged packets, disable
936 * flow control messages, force flow control priority to the
937 * highest, and send all special multicast frames to the CPU
938 * port at the highest priority.
940 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
941 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
942 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
943 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
944 err = mv88e6xxx_g2_write(chip, GLOBAL2_SWITCH_MGMT, reg);
948 /* Program the DSA routing table. */
949 err = mv88e6xxx_g2_set_device_mapping(chip);
953 /* Clear all trunk masks and mapping. */
954 err = mv88e6xxx_g2_clear_trunk(chip);
958 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
959 /* Disable ingress rate limiting by resetting all per port
960 * ingress rate limit resources to their initial state.
962 err = mv88e6xxx_g2_clear_irl(chip);
967 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
968 /* Initialize Cross-chip Port VLAN Table to reset defaults */
969 err = mv88e6xxx_g2_write(chip, GLOBAL2_PVT_ADDR,
970 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
975 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
976 /* Clear the priority override table. */
977 err = mv88e6xxx_g2_clear_pot(chip);