2 * Marvell 88E6xxx Switch Global (1) Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
20 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
22 int addr = chip->info->global1_addr;
24 return mv88e6xxx_read(chip, addr, reg, val);
27 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
29 int addr = chip->info->global1_addr;
31 return mv88e6xxx_write(chip, addr, reg, val);
34 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
36 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
39 /* Offset 0x00: Switch Global Status Register */
41 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
46 for (i = 0; i < 16; i++) {
47 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
51 /* Check the value of the PPUState bits 15:14 */
52 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
53 if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
56 usleep_range(1000, 2000);
62 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
67 for (i = 0; i < 16; ++i) {
68 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
72 /* Check the value of the PPUState bits 15:14 */
73 state &= MV88E6185_G1_STS_PPU_STATE_MASK;
74 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
77 usleep_range(1000, 2000);
83 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
88 for (i = 0; i < 16; ++i) {
89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
93 /* Check the value of the PPUState (or InitState) bit 15 */
94 if (state & MV88E6352_G1_STS_PPU_STATE)
97 usleep_range(1000, 2000);
103 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
105 const unsigned long timeout = jiffies + 1 * HZ;
109 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11
110 * is set to a one when all units inside the device (ATU, VTU, etc.)
111 * have finished their initialization and are ready to accept frames.
113 while (time_before(jiffies, timeout)) {
114 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
118 if (val & MV88E6XXX_G1_STS_INIT_READY)
121 usleep_range(1000, 2000);
124 if (time_after(jiffies, timeout))
130 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
131 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
132 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
134 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
139 reg = (addr[0] << 8) | addr[1];
140 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
144 reg = (addr[2] << 8) | addr[3];
145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
149 reg = (addr[4] << 8) | addr[5];
150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
157 /* Offset 0x04: Switch Global Control Register */
159 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
164 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
165 * the PPU, including re-doing PHY detection and initialization
167 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
171 val |= MV88E6XXX_G1_CTL1_SW_RESET;
172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
178 err = mv88e6xxx_g1_wait_init_ready(chip);
182 return mv88e6185_g1_wait_ppu_polling(chip);
185 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
190 /* Set the SWReset bit 15 */
191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
195 val |= MV88E6XXX_G1_CTL1_SW_RESET;
197 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
201 err = mv88e6xxx_g1_wait_init_ready(chip);
205 return mv88e6352_g1_wait_ppu_polling(chip);
208 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
213 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
217 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
219 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
223 return mv88e6185_g1_wait_ppu_polling(chip);
226 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
231 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
235 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
237 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
241 return mv88e6185_g1_wait_ppu_disabled(chip);
244 /* Offset 0x10: IP-PRI Mapping Register 0
245 * Offset 0x11: IP-PRI Mapping Register 1
246 * Offset 0x12: IP-PRI Mapping Register 2
247 * Offset 0x13: IP-PRI Mapping Register 3
248 * Offset 0x14: IP-PRI Mapping Register 4
249 * Offset 0x15: IP-PRI Mapping Register 5
250 * Offset 0x16: IP-PRI Mapping Register 6
251 * Offset 0x17: IP-PRI Mapping Register 7
254 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
258 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
259 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
263 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
267 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
271 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
275 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
279 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
283 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
287 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
294 /* Offset 0x18: IEEE-PRI Register */
296 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
298 /* Reset the IEEE Tag priorities to defaults */
299 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
302 /* Offset 0x1a: Monitor Control */
303 /* Offset 0x1a: Monitor & MGMT Control on some devices */
305 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
310 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
314 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
315 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
317 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
318 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
320 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
323 /* Older generations also call this the ARP destination. It has been
324 * generalized in more modern devices such that more than ARP can
327 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
332 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
336 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
337 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
339 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
342 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
343 u16 pointer, u8 data)
347 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
349 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
352 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
357 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
358 err = mv88e6390_g1_monitor_write(chip, ptr, port);
362 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
363 err = mv88e6390_g1_monitor_write(chip, ptr, port);
370 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
372 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
374 return mv88e6390_g1_monitor_write(chip, ptr, port);
377 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
382 /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
383 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
384 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
388 /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
389 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
390 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
394 /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
395 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
396 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
400 /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
401 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
402 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
409 /* Offset 0x1c: Global Control 2 */
411 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
417 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®);
424 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
427 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
429 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
431 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
434 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
436 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
437 MV88E6085_G1_CTL2_RM_ENABLE, 0);
440 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
442 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
443 MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
446 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
448 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
449 MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
452 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
454 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
455 MV88E6390_G1_CTL2_HIST_MODE_RX |
456 MV88E6390_G1_CTL2_HIST_MODE_TX);
459 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
461 return mv88e6xxx_g1_ctl2_mask(chip,
462 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
466 /* Offset 0x1d: Statistics Operation 2 */
468 int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
470 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
471 MV88E6XXX_G1_STATS_OP_BUSY);
474 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
479 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
483 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
485 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
490 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
494 /* Snapshot the hardware statistics counters for this port. */
495 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
496 MV88E6XXX_G1_STATS_OP_BUSY |
497 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
498 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
502 /* Wait for the snapshotting to complete. */
503 return mv88e6xxx_g1_stats_wait(chip);
506 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
508 port = (port + 1) << 5;
510 return mv88e6xxx_g1_stats_snapshot(chip, port);
513 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
517 port = (port + 1) << 5;
519 /* Snapshot the hardware statistics counters for this port. */
520 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
521 MV88E6XXX_G1_STATS_OP_BUSY |
522 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
526 /* Wait for the snapshotting to complete. */
527 return mv88e6xxx_g1_stats_wait(chip);
530 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
538 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
539 MV88E6XXX_G1_STATS_OP_BUSY |
540 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
544 err = mv88e6xxx_g1_stats_wait(chip);
548 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
554 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
561 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
566 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
570 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
572 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
576 /* Wait for the flush to complete. */
577 return mv88e6xxx_g1_stats_wait(chip);