2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
12 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
20 #include <linux/delay.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/if_bridge.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/irqdomain.h>
27 #include <linux/jiffies.h>
28 #include <linux/list.h>
29 #include <linux/mdio.h>
30 #include <linux/module.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_mdio.h>
34 #include <linux/netdevice.h>
35 #include <linux/gpio/consumer.h>
36 #include <linux/phy.h>
38 #include <net/switchdev.h>
40 #include "mv88e6xxx.h"
45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
66 int addr, int reg, u16 *val)
71 return chip->smi_ops->read(chip, addr, reg, val);
74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
75 int addr, int reg, u16 val)
80 return chip->smi_ops->write(chip, addr, reg, val);
83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
84 int addr, int reg, u16 *val)
88 ret = mdiobus_read_nested(chip->bus, addr, reg);
97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
98 int addr, int reg, u16 val)
102 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
110 .read = mv88e6xxx_smi_single_chip_read,
111 .write = mv88e6xxx_smi_single_chip_write,
114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
119 for (i = 0; i < 16; i++) {
120 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
124 if ((ret & SMI_CMD_BUSY) == 0)
131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
132 int addr, int reg, u16 *val)
136 /* Wait for the bus to become free. */
137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
141 /* Transmit the read command. */
142 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
143 SMI_CMD_OP_22_READ | (addr << 5) | reg);
147 /* Wait for the read command to complete. */
148 ret = mv88e6xxx_smi_multi_chip_wait(chip);
153 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
163 int addr, int reg, u16 val)
167 /* Wait for the bus to become free. */
168 ret = mv88e6xxx_smi_multi_chip_wait(chip);
172 /* Transmit the data to write. */
173 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
177 /* Transmit the write command. */
178 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
179 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
183 /* Wait for the write command to complete. */
184 ret = mv88e6xxx_smi_multi_chip_wait(chip);
191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
192 .read = mv88e6xxx_smi_multi_chip_read,
193 .write = mv88e6xxx_smi_multi_chip_write,
196 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
200 assert_reg_lock(chip);
202 err = mv88e6xxx_smi_read(chip, addr, reg, val);
206 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
212 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
216 assert_reg_lock(chip);
218 err = mv88e6xxx_smi_write(chip, addr, reg, val);
222 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
228 static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip,
230 int addr, int reg, u16 *val)
232 return mv88e6xxx_read(chip, addr, reg, val);
235 static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip,
237 int addr, int reg, u16 val)
239 return mv88e6xxx_write(chip, addr, reg, val);
242 static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
244 struct mv88e6xxx_mdio_bus *mdio_bus;
246 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
251 return mdio_bus->bus;
254 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
257 int addr = phy; /* PHY devices addresses start at 0x0 */
260 bus = mv88e6xxx_default_mdio_bus(chip);
264 if (!chip->info->ops->phy_read)
267 return chip->info->ops->phy_read(chip, bus, addr, reg, val);
270 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
273 int addr = phy; /* PHY devices addresses start at 0x0 */
276 bus = mv88e6xxx_default_mdio_bus(chip);
280 if (!chip->info->ops->phy_write)
283 return chip->info->ops->phy_write(chip, bus, addr, reg, val);
286 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
288 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
291 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
294 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
298 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
299 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
301 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
306 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
307 u8 page, int reg, u16 *val)
311 /* There is no paging for registers 22 */
315 err = mv88e6xxx_phy_page_get(chip, phy, page);
317 err = mv88e6xxx_phy_read(chip, phy, reg, val);
318 mv88e6xxx_phy_page_put(chip, phy);
324 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
325 u8 page, int reg, u16 val)
329 /* There is no paging for registers 22 */
333 err = mv88e6xxx_phy_page_get(chip, phy, page);
335 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
336 mv88e6xxx_phy_page_put(chip, phy);
342 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
344 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
348 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
350 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
354 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
356 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
357 unsigned int n = d->hwirq;
359 chip->g1_irq.masked |= (1 << n);
362 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
364 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
365 unsigned int n = d->hwirq;
367 chip->g1_irq.masked &= ~(1 << n);
370 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
372 struct mv88e6xxx_chip *chip = dev_id;
373 unsigned int nhandled = 0;
374 unsigned int sub_irq;
379 mutex_lock(&chip->reg_lock);
380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
381 mutex_unlock(&chip->reg_lock);
386 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
387 if (reg & (1 << n)) {
388 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
389 handle_nested_irq(sub_irq);
394 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
397 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
399 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
401 mutex_lock(&chip->reg_lock);
404 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
406 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
407 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
411 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
416 reg |= (~chip->g1_irq.masked & mask);
418 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
423 mutex_unlock(&chip->reg_lock);
426 static struct irq_chip mv88e6xxx_g1_irq_chip = {
427 .name = "mv88e6xxx-g1",
428 .irq_mask = mv88e6xxx_g1_irq_mask,
429 .irq_unmask = mv88e6xxx_g1_irq_unmask,
430 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
431 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
434 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
436 irq_hw_number_t hwirq)
438 struct mv88e6xxx_chip *chip = d->host_data;
440 irq_set_chip_data(irq, d->host_data);
441 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
442 irq_set_noprobe(irq);
447 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
448 .map = mv88e6xxx_g1_irq_domain_map,
449 .xlate = irq_domain_xlate_twocell,
452 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
457 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
458 mask |= GENMASK(chip->g1_irq.nirqs, 0);
459 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
461 free_irq(chip->irq, chip);
463 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
464 virq = irq_find_mapping(chip->g1_irq.domain, irq);
465 irq_dispose_mapping(virq);
468 irq_domain_remove(chip->g1_irq.domain);
471 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
476 chip->g1_irq.nirqs = chip->info->g1_irqs;
477 chip->g1_irq.domain = irq_domain_add_simple(
478 NULL, chip->g1_irq.nirqs, 0,
479 &mv88e6xxx_g1_irq_domain_ops, chip);
480 if (!chip->g1_irq.domain)
483 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
484 irq_create_mapping(chip->g1_irq.domain, irq);
486 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
487 chip->g1_irq.masked = ~0;
489 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
493 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
495 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
499 /* Reading the interrupt status clears (most of) them */
500 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
504 err = request_threaded_irq(chip->irq, NULL,
505 mv88e6xxx_g1_irq_thread_fn,
506 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
507 dev_name(chip->dev), chip);
514 mask |= GENMASK(chip->g1_irq.nirqs, 0);
515 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
518 for (irq = 0; irq < 16; irq++) {
519 virq = irq_find_mapping(chip->g1_irq.domain, irq);
520 irq_dispose_mapping(virq);
523 irq_domain_remove(chip->g1_irq.domain);
528 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
532 for (i = 0; i < 16; i++) {
536 err = mv88e6xxx_read(chip, addr, reg, &val);
543 usleep_range(1000, 2000);
546 dev_err(chip->dev, "Timeout while waiting for switch\n");
550 /* Indirect write to single pointer-data register with an Update bit */
551 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
556 /* Wait until the previous operation is completed */
557 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
561 /* Set the Update bit to trigger a write operation */
562 val = BIT(15) | update;
564 return mv88e6xxx_write(chip, addr, reg, val);
567 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
569 if (!chip->info->ops->ppu_disable)
572 return chip->info->ops->ppu_disable(chip);
575 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
577 if (!chip->info->ops->ppu_enable)
580 return chip->info->ops->ppu_enable(chip);
583 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
585 struct mv88e6xxx_chip *chip;
587 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
589 mutex_lock(&chip->reg_lock);
591 if (mutex_trylock(&chip->ppu_mutex)) {
592 if (mv88e6xxx_ppu_enable(chip) == 0)
593 chip->ppu_disabled = 0;
594 mutex_unlock(&chip->ppu_mutex);
597 mutex_unlock(&chip->reg_lock);
600 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
602 struct mv88e6xxx_chip *chip = (void *)_ps;
604 schedule_work(&chip->ppu_work);
607 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
611 mutex_lock(&chip->ppu_mutex);
613 /* If the PHY polling unit is enabled, disable it so that
614 * we can access the PHY registers. If it was already
615 * disabled, cancel the timer that is going to re-enable
618 if (!chip->ppu_disabled) {
619 ret = mv88e6xxx_ppu_disable(chip);
621 mutex_unlock(&chip->ppu_mutex);
624 chip->ppu_disabled = 1;
626 del_timer(&chip->ppu_timer);
633 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
635 /* Schedule a timer to re-enable the PHY polling unit. */
636 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
637 mutex_unlock(&chip->ppu_mutex);
640 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
642 mutex_init(&chip->ppu_mutex);
643 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
644 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
645 (unsigned long)chip);
648 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
650 del_timer_sync(&chip->ppu_timer);
653 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip,
655 int addr, int reg, u16 *val)
659 err = mv88e6xxx_ppu_access_get(chip);
661 err = mv88e6xxx_read(chip, addr, reg, val);
662 mv88e6xxx_ppu_access_put(chip);
668 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip,
670 int addr, int reg, u16 val)
674 err = mv88e6xxx_ppu_access_get(chip);
676 err = mv88e6xxx_write(chip, addr, reg, val);
677 mv88e6xxx_ppu_access_put(chip);
683 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
685 return chip->info->family == MV88E6XXX_FAMILY_6097;
688 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
690 return chip->info->family == MV88E6XXX_FAMILY_6165;
693 static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip)
695 return chip->info->family == MV88E6XXX_FAMILY_6341;
698 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
700 return chip->info->family == MV88E6XXX_FAMILY_6351;
703 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
705 return chip->info->family == MV88E6XXX_FAMILY_6352;
708 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
709 int link, int speed, int duplex,
710 phy_interface_t mode)
714 if (!chip->info->ops->port_set_link)
717 /* Port's MAC control must not be changed unless the link is down */
718 err = chip->info->ops->port_set_link(chip, port, 0);
722 if (chip->info->ops->port_set_speed) {
723 err = chip->info->ops->port_set_speed(chip, port, speed);
724 if (err && err != -EOPNOTSUPP)
728 if (chip->info->ops->port_set_duplex) {
729 err = chip->info->ops->port_set_duplex(chip, port, duplex);
730 if (err && err != -EOPNOTSUPP)
734 if (chip->info->ops->port_set_rgmii_delay) {
735 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
736 if (err && err != -EOPNOTSUPP)
740 if (chip->info->ops->port_set_cmode) {
741 err = chip->info->ops->port_set_cmode(chip, port, mode);
742 if (err && err != -EOPNOTSUPP)
748 if (chip->info->ops->port_set_link(chip, port, link))
749 netdev_err(chip->ds->ports[port].netdev,
750 "failed to restore MAC's link\n");
755 /* We expect the switch to perform auto negotiation if there is a real
756 * phy. However, in the case of a fixed link phy, we force the port
757 * settings from the fixed link settings.
759 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
760 struct phy_device *phydev)
762 struct mv88e6xxx_chip *chip = ds->priv;
765 if (!phy_is_pseudo_fixed_link(phydev))
768 mutex_lock(&chip->reg_lock);
769 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
770 phydev->duplex, phydev->interface);
771 mutex_unlock(&chip->reg_lock);
773 if (err && err != -EOPNOTSUPP)
774 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
777 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
779 if (!chip->info->ops->stats_snapshot)
782 return chip->info->ops->stats_snapshot(chip, port);
785 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
786 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
787 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
788 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
789 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
790 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
791 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
792 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
793 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
794 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
795 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
796 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
797 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
798 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
799 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
800 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
801 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
802 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
803 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
804 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
805 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
806 { "single", 4, 0x14, STATS_TYPE_BANK0, },
807 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
808 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
809 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
810 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
811 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
812 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
813 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
814 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
815 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
816 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
817 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
818 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
819 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
820 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
821 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
822 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
823 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
824 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
825 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
826 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
827 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
828 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
829 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
830 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
831 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
832 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
833 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
834 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
835 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
836 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
837 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
838 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
839 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
840 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
841 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
842 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
843 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
844 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
847 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
848 struct mv88e6xxx_hw_stat *s,
849 int port, u16 bank1_select,
859 case STATS_TYPE_PORT:
860 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
865 if (s->sizeof_stat == 4) {
866 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
872 case STATS_TYPE_BANK1:
875 case STATS_TYPE_BANK0:
876 reg |= s->reg | histogram;
877 mv88e6xxx_g1_stats_read(chip, reg, &low);
878 if (s->sizeof_stat == 8)
879 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
881 value = (((u64)high) << 16) | low;
885 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
886 uint8_t *data, int types)
888 struct mv88e6xxx_hw_stat *stat;
891 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
892 stat = &mv88e6xxx_hw_stats[i];
893 if (stat->type & types) {
894 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
901 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
904 mv88e6xxx_stats_get_strings(chip, data,
905 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
908 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
911 mv88e6xxx_stats_get_strings(chip, data,
912 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
915 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
918 struct mv88e6xxx_chip *chip = ds->priv;
920 if (chip->info->ops->stats_get_strings)
921 chip->info->ops->stats_get_strings(chip, data);
924 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
927 struct mv88e6xxx_hw_stat *stat;
930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
931 stat = &mv88e6xxx_hw_stats[i];
932 if (stat->type & types)
938 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
940 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
944 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
946 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
950 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
952 struct mv88e6xxx_chip *chip = ds->priv;
954 if (chip->info->ops->stats_get_sset_count)
955 return chip->info->ops->stats_get_sset_count(chip);
960 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
961 uint64_t *data, int types,
962 u16 bank1_select, u16 histogram)
964 struct mv88e6xxx_hw_stat *stat;
967 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
968 stat = &mv88e6xxx_hw_stats[i];
969 if (stat->type & types) {
970 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
978 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
981 return mv88e6xxx_stats_get_stats(chip, port, data,
982 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
983 0, GLOBAL_STATS_OP_HIST_RX_TX);
986 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
989 return mv88e6xxx_stats_get_stats(chip, port, data,
990 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
991 GLOBAL_STATS_OP_BANK_1_BIT_9,
992 GLOBAL_STATS_OP_HIST_RX_TX);
995 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
998 return mv88e6xxx_stats_get_stats(chip, port, data,
999 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1000 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
1003 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1006 if (chip->info->ops->stats_get_stats)
1007 chip->info->ops->stats_get_stats(chip, port, data);
1010 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1013 struct mv88e6xxx_chip *chip = ds->priv;
1016 mutex_lock(&chip->reg_lock);
1018 ret = mv88e6xxx_stats_snapshot(chip, port);
1020 mutex_unlock(&chip->reg_lock);
1024 mv88e6xxx_get_stats(chip, port, data);
1026 mutex_unlock(&chip->reg_lock);
1029 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
1031 if (chip->info->ops->stats_set_histogram)
1032 return chip->info->ops->stats_set_histogram(chip);
1037 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1039 return 32 * sizeof(u16);
1042 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1043 struct ethtool_regs *regs, void *_p)
1045 struct mv88e6xxx_chip *chip = ds->priv;
1053 memset(p, 0xff, 32 * sizeof(u16));
1055 mutex_lock(&chip->reg_lock);
1057 for (i = 0; i < 32; i++) {
1059 err = mv88e6xxx_port_read(chip, port, i, ®);
1064 mutex_unlock(&chip->reg_lock);
1067 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1068 struct ethtool_eee *e)
1070 struct mv88e6xxx_chip *chip = ds->priv;
1074 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1077 mutex_lock(&chip->reg_lock);
1079 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1083 e->eee_enabled = !!(reg & 0x0200);
1084 e->tx_lpi_enabled = !!(reg & 0x0100);
1086 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
1090 e->eee_active = !!(reg & PORT_STATUS_EEE);
1092 mutex_unlock(&chip->reg_lock);
1097 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1098 struct phy_device *phydev, struct ethtool_eee *e)
1100 struct mv88e6xxx_chip *chip = ds->priv;
1104 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1107 mutex_lock(&chip->reg_lock);
1109 err = mv88e6xxx_phy_read(chip, port, 16, ®);
1116 if (e->tx_lpi_enabled)
1119 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1121 mutex_unlock(&chip->reg_lock);
1126 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1128 struct dsa_switch *ds = NULL;
1129 struct net_device *br;
1133 if (dev < DSA_MAX_SWITCHES)
1134 ds = chip->ds->dst->ds[dev];
1136 /* Prevent frames from unknown switch or port */
1137 if (!ds || port >= ds->num_ports)
1140 /* Frames from DSA links and CPU ports can egress any local port */
1141 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1142 return mv88e6xxx_port_mask(chip);
1144 br = ds->ports[port].bridge_dev;
1147 /* Frames from user ports can egress any local DSA links and CPU ports,
1148 * as well as any local member of their bridge group.
1150 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1151 if (dsa_is_cpu_port(chip->ds, i) ||
1152 dsa_is_dsa_port(chip->ds, i) ||
1153 (br && chip->ds->ports[i].bridge_dev == br))
1159 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1161 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1163 /* prevent frames from going back out of the port they came in on */
1164 output_ports &= ~BIT(port);
1166 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1169 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1172 struct mv88e6xxx_chip *chip = ds->priv;
1177 case BR_STATE_DISABLED:
1178 stp_state = PORT_CONTROL_STATE_DISABLED;
1180 case BR_STATE_BLOCKING:
1181 case BR_STATE_LISTENING:
1182 stp_state = PORT_CONTROL_STATE_BLOCKING;
1184 case BR_STATE_LEARNING:
1185 stp_state = PORT_CONTROL_STATE_LEARNING;
1187 case BR_STATE_FORWARDING:
1189 stp_state = PORT_CONTROL_STATE_FORWARDING;
1193 mutex_lock(&chip->reg_lock);
1194 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1195 mutex_unlock(&chip->reg_lock);
1198 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1201 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1205 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1209 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1213 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1216 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1220 if (!mv88e6xxx_has_pvt(chip))
1223 /* Skip the local source device, which uses in-chip port VLAN */
1224 if (dev != chip->ds->index)
1225 pvlan = mv88e6xxx_port_mask(chip);
1227 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1230 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1235 if (!mv88e6xxx_has_pvt(chip))
1238 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1239 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1241 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1245 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1246 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1247 err = mv88e6xxx_pvt_map(chip, dev, port);
1256 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1258 struct mv88e6xxx_chip *chip = ds->priv;
1261 mutex_lock(&chip->reg_lock);
1262 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1263 mutex_unlock(&chip->reg_lock);
1266 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1269 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1271 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1274 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1278 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1282 return _mv88e6xxx_vtu_wait(chip);
1285 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1289 ret = _mv88e6xxx_vtu_wait(chip);
1293 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1296 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1297 struct mv88e6xxx_vtu_entry *entry,
1298 unsigned int nibble_offset)
1303 for (i = 0; i < 3; ++i) {
1304 u16 *reg = ®s[i];
1306 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1311 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1312 unsigned int shift = (i % 4) * 4 + nibble_offset;
1313 u16 reg = regs[i / 4];
1315 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1321 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1322 struct mv88e6xxx_vtu_entry *entry)
1324 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1327 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1328 struct mv88e6xxx_vtu_entry *entry)
1330 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1333 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1334 struct mv88e6xxx_vtu_entry *entry,
1335 unsigned int nibble_offset)
1337 u16 regs[3] = { 0 };
1340 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1341 unsigned int shift = (i % 4) * 4 + nibble_offset;
1342 u8 data = entry->data[i];
1344 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1347 for (i = 0; i < 3; ++i) {
1350 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1358 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1359 struct mv88e6xxx_vtu_entry *entry)
1361 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1364 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1365 struct mv88e6xxx_vtu_entry *entry)
1367 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1370 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1372 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1373 vid & GLOBAL_VTU_VID_MASK);
1376 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1377 struct mv88e6xxx_vtu_entry *entry)
1379 struct mv88e6xxx_vtu_entry next = { 0 };
1383 err = _mv88e6xxx_vtu_wait(chip);
1387 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1391 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1395 next.vid = val & GLOBAL_VTU_VID_MASK;
1396 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1399 err = mv88e6xxx_vtu_data_read(chip, &next);
1403 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1404 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1408 next.fid = val & GLOBAL_VTU_FID_MASK;
1409 } else if (mv88e6xxx_num_databases(chip) == 256) {
1410 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1411 * VTU DBNum[3:0] are located in VTU Operation 3:0
1413 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1417 next.fid = (val & 0xf00) >> 4;
1418 next.fid |= val & 0xf;
1421 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1422 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1426 next.sid = val & GLOBAL_VTU_SID_MASK;
1434 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1435 struct switchdev_obj_port_vlan *vlan,
1436 int (*cb)(struct switchdev_obj *obj))
1438 struct mv88e6xxx_chip *chip = ds->priv;
1439 struct mv88e6xxx_vtu_entry next;
1443 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1446 mutex_lock(&chip->reg_lock);
1448 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1452 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1457 err = _mv88e6xxx_vtu_getnext(chip, &next);
1464 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1467 /* reinit and dump this VLAN obj */
1468 vlan->vid_begin = next.vid;
1469 vlan->vid_end = next.vid;
1472 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1473 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1475 if (next.vid == pvid)
1476 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1478 err = cb(&vlan->obj);
1481 } while (next.vid < GLOBAL_VTU_VID_MASK);
1484 mutex_unlock(&chip->reg_lock);
1489 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1490 struct mv88e6xxx_vtu_entry *entry)
1492 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1496 err = _mv88e6xxx_vtu_wait(chip);
1503 /* Write port member tags */
1504 err = mv88e6xxx_vtu_data_write(chip, entry);
1508 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1509 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1510 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1515 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1516 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1517 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1520 } else if (mv88e6xxx_num_databases(chip) == 256) {
1521 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1522 * VTU DBNum[3:0] are located in VTU Operation 3:0
1524 op |= (entry->fid & 0xf0) << 8;
1525 op |= entry->fid & 0xf;
1528 reg = GLOBAL_VTU_VID_VALID;
1530 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1531 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1535 return _mv88e6xxx_vtu_cmd(chip, op);
1538 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1539 struct mv88e6xxx_vtu_entry *entry)
1541 struct mv88e6xxx_vtu_entry next = { 0 };
1545 err = _mv88e6xxx_vtu_wait(chip);
1549 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1550 sid & GLOBAL_VTU_SID_MASK);
1554 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1558 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1562 next.sid = val & GLOBAL_VTU_SID_MASK;
1564 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1568 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1571 err = mv88e6xxx_stu_data_read(chip, &next);
1580 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1581 struct mv88e6xxx_vtu_entry *entry)
1586 err = _mv88e6xxx_vtu_wait(chip);
1593 /* Write port states */
1594 err = mv88e6xxx_stu_data_write(chip, entry);
1598 reg = GLOBAL_VTU_VID_VALID;
1600 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1604 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1605 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1609 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1612 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1614 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1615 struct mv88e6xxx_vtu_entry vlan;
1618 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1620 /* Set every FID bit used by the (un)bridged ports */
1621 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1622 err = mv88e6xxx_port_get_fid(chip, i, fid);
1626 set_bit(*fid, fid_bitmap);
1629 /* Set every FID bit used by the VLAN entries */
1630 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1635 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1642 set_bit(vlan.fid, fid_bitmap);
1643 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1645 /* The reset value 0x000 is used to indicate that multiple address
1646 * databases are not needed. Return the next positive available.
1648 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1649 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1652 /* Clear the database */
1653 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1656 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1657 struct mv88e6xxx_vtu_entry *entry)
1659 struct dsa_switch *ds = chip->ds;
1660 struct mv88e6xxx_vtu_entry vlan = {
1666 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1670 /* exclude all ports except the CPU and DSA ports */
1671 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1672 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1673 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1674 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1676 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1677 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) ||
1678 mv88e6xxx_6341_family(chip)) {
1679 struct mv88e6xxx_vtu_entry vstp;
1681 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1682 * implemented, only one STU entry is needed to cover all VTU
1683 * entries. Thus, validate the SID 0.
1686 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1690 if (vstp.sid != vlan.sid || !vstp.valid) {
1691 memset(&vstp, 0, sizeof(vstp));
1693 vstp.sid = vlan.sid;
1695 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1705 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1706 struct mv88e6xxx_vtu_entry *entry, bool creat)
1713 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1717 err = _mv88e6xxx_vtu_getnext(chip, entry);
1721 if (entry->vid != vid || !entry->valid) {
1724 /* -ENOENT would've been more appropriate, but switchdev expects
1725 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1728 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1734 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1735 u16 vid_begin, u16 vid_end)
1737 struct mv88e6xxx_chip *chip = ds->priv;
1738 struct mv88e6xxx_vtu_entry vlan;
1744 mutex_lock(&chip->reg_lock);
1746 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1751 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1758 if (vlan.vid > vid_end)
1761 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1762 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1765 if (!ds->ports[port].netdev)
1769 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1772 if (ds->ports[i].bridge_dev ==
1773 ds->ports[port].bridge_dev)
1774 break; /* same bridge, check next VLAN */
1776 if (!ds->ports[i].bridge_dev)
1779 netdev_warn(ds->ports[port].netdev,
1780 "hardware VLAN %d already used by %s\n",
1782 netdev_name(ds->ports[i].bridge_dev));
1786 } while (vlan.vid < vid_end);
1789 mutex_unlock(&chip->reg_lock);
1794 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1795 bool vlan_filtering)
1797 struct mv88e6xxx_chip *chip = ds->priv;
1798 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1799 PORT_CONTROL_2_8021Q_DISABLED;
1802 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1805 mutex_lock(&chip->reg_lock);
1806 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1807 mutex_unlock(&chip->reg_lock);
1813 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1814 const struct switchdev_obj_port_vlan *vlan,
1815 struct switchdev_trans *trans)
1817 struct mv88e6xxx_chip *chip = ds->priv;
1820 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1823 /* If the requested port doesn't belong to the same bridge as the VLAN
1824 * members, do not support it (yet) and fallback to software VLAN.
1826 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1831 /* We don't need any dynamic resource from the kernel (yet),
1832 * so skip the prepare phase.
1837 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1838 u16 vid, bool untagged)
1840 struct mv88e6xxx_vtu_entry vlan;
1843 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1847 vlan.data[port] = untagged ?
1848 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1849 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1851 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1854 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1855 const struct switchdev_obj_port_vlan *vlan,
1856 struct switchdev_trans *trans)
1858 struct mv88e6xxx_chip *chip = ds->priv;
1859 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1860 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1863 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1866 mutex_lock(&chip->reg_lock);
1868 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1869 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1870 netdev_err(ds->ports[port].netdev,
1871 "failed to add VLAN %d%c\n",
1872 vid, untagged ? 'u' : 't');
1874 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1875 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1878 mutex_unlock(&chip->reg_lock);
1881 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1884 struct dsa_switch *ds = chip->ds;
1885 struct mv88e6xxx_vtu_entry vlan;
1888 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1892 /* Tell switchdev if this VLAN is handled in software */
1893 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1896 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1898 /* keep the VLAN unless all ports are excluded */
1900 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1901 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1904 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1910 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1914 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1917 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1918 const struct switchdev_obj_port_vlan *vlan)
1920 struct mv88e6xxx_chip *chip = ds->priv;
1924 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1927 mutex_lock(&chip->reg_lock);
1929 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1933 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1934 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1939 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1946 mutex_unlock(&chip->reg_lock);
1951 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1952 const unsigned char *addr, u16 vid,
1955 struct mv88e6xxx_vtu_entry vlan;
1956 struct mv88e6xxx_atu_entry entry;
1959 /* Null VLAN ID corresponds to the port private database */
1961 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1963 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1967 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1968 ether_addr_copy(entry.mac, addr);
1969 eth_addr_dec(entry.mac);
1971 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1975 /* Initialize a fresh ATU entry if it isn't found */
1976 if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
1977 !ether_addr_equal(entry.mac, addr)) {
1978 memset(&entry, 0, sizeof(entry));
1979 ether_addr_copy(entry.mac, addr);
1982 /* Purge the ATU entry only if no port is using it anymore */
1983 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
1984 entry.portvec &= ~BIT(port);
1986 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
1988 entry.portvec |= BIT(port);
1989 entry.state = state;
1992 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1995 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1996 const struct switchdev_obj_port_fdb *fdb,
1997 struct switchdev_trans *trans)
1999 /* We don't need any dynamic resource from the kernel (yet),
2000 * so skip the prepare phase.
2005 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2006 const struct switchdev_obj_port_fdb *fdb,
2007 struct switchdev_trans *trans)
2009 struct mv88e6xxx_chip *chip = ds->priv;
2011 mutex_lock(&chip->reg_lock);
2012 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2013 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2014 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2015 mutex_unlock(&chip->reg_lock);
2018 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2019 const struct switchdev_obj_port_fdb *fdb)
2021 struct mv88e6xxx_chip *chip = ds->priv;
2024 mutex_lock(&chip->reg_lock);
2025 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2026 GLOBAL_ATU_DATA_STATE_UNUSED);
2027 mutex_unlock(&chip->reg_lock);
2032 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2033 u16 fid, u16 vid, int port,
2034 struct switchdev_obj *obj,
2035 int (*cb)(struct switchdev_obj *obj))
2037 struct mv88e6xxx_atu_entry addr;
2040 addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2041 eth_broadcast_addr(addr.mac);
2044 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2048 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2051 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2054 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2055 struct switchdev_obj_port_fdb *fdb;
2057 if (!is_unicast_ether_addr(addr.mac))
2060 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2062 ether_addr_copy(fdb->addr, addr.mac);
2063 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2064 fdb->ndm_state = NUD_NOARP;
2066 fdb->ndm_state = NUD_REACHABLE;
2067 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2068 struct switchdev_obj_port_mdb *mdb;
2070 if (!is_multicast_ether_addr(addr.mac))
2073 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2075 ether_addr_copy(mdb->addr, addr.mac);
2083 } while (!is_broadcast_ether_addr(addr.mac));
2088 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2089 struct switchdev_obj *obj,
2090 int (*cb)(struct switchdev_obj *obj))
2092 struct mv88e6xxx_vtu_entry vlan = {
2093 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2098 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2099 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2103 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2107 /* Dump VLANs' Filtering Information Databases */
2108 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2113 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2120 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2124 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2129 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2130 struct switchdev_obj_port_fdb *fdb,
2131 int (*cb)(struct switchdev_obj *obj))
2133 struct mv88e6xxx_chip *chip = ds->priv;
2136 mutex_lock(&chip->reg_lock);
2137 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2138 mutex_unlock(&chip->reg_lock);
2143 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2144 struct net_device *br)
2146 struct dsa_switch *ds;
2151 /* Remap the Port VLAN of each local bridge group member */
2152 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
2153 if (chip->ds->ports[port].bridge_dev == br) {
2154 err = mv88e6xxx_port_vlan_map(chip, port);
2160 if (!mv88e6xxx_has_pvt(chip))
2163 /* Remap the Port VLAN of each cross-chip bridge group member */
2164 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
2165 ds = chip->ds->dst->ds[dev];
2169 for (port = 0; port < ds->num_ports; ++port) {
2170 if (ds->ports[port].bridge_dev == br) {
2171 err = mv88e6xxx_pvt_map(chip, dev, port);
2181 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2182 struct net_device *br)
2184 struct mv88e6xxx_chip *chip = ds->priv;
2187 mutex_lock(&chip->reg_lock);
2188 err = mv88e6xxx_bridge_map(chip, br);
2189 mutex_unlock(&chip->reg_lock);
2194 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2195 struct net_device *br)
2197 struct mv88e6xxx_chip *chip = ds->priv;
2199 mutex_lock(&chip->reg_lock);
2200 if (mv88e6xxx_bridge_map(chip, br) ||
2201 mv88e6xxx_port_vlan_map(chip, port))
2202 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2203 mutex_unlock(&chip->reg_lock);
2206 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2208 if (chip->info->ops->reset)
2209 return chip->info->ops->reset(chip);
2214 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2216 struct gpio_desc *gpiod = chip->reset;
2218 /* If there is a GPIO connected to the reset pin, toggle it */
2220 gpiod_set_value_cansleep(gpiod, 1);
2221 usleep_range(10000, 20000);
2222 gpiod_set_value_cansleep(gpiod, 0);
2223 usleep_range(10000, 20000);
2227 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2231 /* Set all ports to the Disabled state */
2232 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2233 err = mv88e6xxx_port_set_state(chip, i,
2234 PORT_CONTROL_STATE_DISABLED);
2239 /* Wait for transmit queues to drain,
2240 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2242 usleep_range(2000, 4000);
2247 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2251 err = mv88e6xxx_disable_ports(chip);
2255 mv88e6xxx_hardware_reset(chip);
2257 return mv88e6xxx_software_reset(chip);
2260 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2265 /* Clear Power Down bit */
2266 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2270 if (val & BMCR_PDOWN) {
2272 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2278 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2279 enum mv88e6xxx_frame_mode frame, u16 egress,
2284 if (!chip->info->ops->port_set_frame_mode)
2287 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2291 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2295 if (chip->info->ops->port_set_ether_type)
2296 return chip->info->ops->port_set_ether_type(chip, port, etype);
2301 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2303 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2304 PORT_CONTROL_EGRESS_UNMODIFIED,
2305 PORT_ETH_TYPE_DEFAULT);
2308 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2310 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2311 PORT_CONTROL_EGRESS_UNMODIFIED,
2312 PORT_ETH_TYPE_DEFAULT);
2315 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2317 return mv88e6xxx_set_port_mode(chip, port,
2318 MV88E6XXX_FRAME_MODE_ETHERTYPE,
2319 PORT_CONTROL_EGRESS_ADD_TAG, ETH_P_EDSA);
2322 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2324 if (dsa_is_dsa_port(chip->ds, port))
2325 return mv88e6xxx_set_port_mode_dsa(chip, port);
2327 if (dsa_is_normal_port(chip->ds, port))
2328 return mv88e6xxx_set_port_mode_normal(chip, port);
2330 /* Setup CPU port mode depending on its supported tag format */
2331 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2332 return mv88e6xxx_set_port_mode_dsa(chip, port);
2334 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2335 return mv88e6xxx_set_port_mode_edsa(chip, port);
2340 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2342 bool message = dsa_is_dsa_port(chip->ds, port);
2344 return mv88e6xxx_port_set_message_port(chip, port, message);
2347 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2349 bool flood = port == dsa_upstream_port(chip->ds);
2351 /* Upstream ports flood frames with unknown unicast or multicast DA */
2352 if (chip->info->ops->port_set_egress_floods)
2353 return chip->info->ops->port_set_egress_floods(chip, port,
2359 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2361 struct dsa_switch *ds = chip->ds;
2365 /* MAC Forcing register: don't force link, speed, duplex or flow control
2366 * state to any particular values on physical ports, but force the CPU
2367 * port and all DSA ports to their maximum bandwidth and full duplex.
2369 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2370 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2371 SPEED_MAX, DUPLEX_FULL,
2372 PHY_INTERFACE_MODE_NA);
2374 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2375 SPEED_UNFORCED, DUPLEX_UNFORCED,
2376 PHY_INTERFACE_MODE_NA);
2380 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2381 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2382 * tunneling, determine priority by looking at 802.1p and IP
2383 * priority fields (IP prio has precedence), and set STP state
2386 * If this is the CPU link, use DSA or EDSA tagging depending
2387 * on which tagging mode was configured.
2389 * If this is a link to another switch, use DSA tagging mode.
2391 * If this is the upstream port for this switch, enable
2392 * forwarding of unknown unicasts and multicasts.
2394 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2395 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2396 PORT_CONTROL_STATE_FORWARDING;
2397 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2401 err = mv88e6xxx_setup_port_mode(chip, port);
2405 err = mv88e6xxx_setup_egress_floods(chip, port);
2409 /* If this port is connected to a SerDes, make sure the SerDes is not
2412 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2413 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
2416 reg &= PORT_STATUS_CMODE_MASK;
2417 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2418 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2419 (reg == PORT_STATUS_CMODE_SGMII)) {
2420 err = mv88e6xxx_serdes_power_on(chip);
2426 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2427 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2428 * untagged frames on this port, do a destination address lookup on all
2429 * received packets as usual, disable ARP mirroring and don't send a
2430 * copy of all transmitted/received frames on this port to the CPU.
2432 err = mv88e6xxx_port_set_map_da(chip, port);
2437 if (chip->info->ops->port_set_upstream_port) {
2438 err = chip->info->ops->port_set_upstream_port(
2439 chip, port, dsa_upstream_port(ds));
2444 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2445 PORT_CONTROL_2_8021Q_DISABLED);
2449 if (chip->info->ops->port_jumbo_config) {
2450 err = chip->info->ops->port_jumbo_config(chip, port);
2455 /* Port Association Vector: when learning source addresses
2456 * of packets, add the address to the address database using
2457 * a port bitmap that has only the bit for this port set and
2458 * the other bits clear.
2461 /* Disable learning for CPU port */
2462 if (dsa_is_cpu_port(ds, port))
2465 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2469 /* Egress rate control 2: disable egress rate control. */
2470 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2474 if (chip->info->ops->port_pause_config) {
2475 err = chip->info->ops->port_pause_config(chip, port);
2480 if (chip->info->ops->port_disable_learn_limit) {
2481 err = chip->info->ops->port_disable_learn_limit(chip, port);
2486 if (chip->info->ops->port_disable_pri_override) {
2487 err = chip->info->ops->port_disable_pri_override(chip, port);
2492 if (chip->info->ops->port_tag_remap) {
2493 err = chip->info->ops->port_tag_remap(chip, port);
2498 if (chip->info->ops->port_egress_rate_limiting) {
2499 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2504 err = mv88e6xxx_setup_message_port(chip, port);
2508 /* Port based VLAN map: give each port the same default address
2509 * database, and allow bidirectional communication between the
2510 * CPU and DSA port(s), and the other ports.
2512 err = mv88e6xxx_port_set_fid(chip, port, 0);
2516 err = mv88e6xxx_port_vlan_map(chip, port);
2520 /* Default VLAN ID and priority: don't set a default VLAN
2521 * ID, and set the default packet priority to zero.
2523 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2526 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2530 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2534 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2538 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2545 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2546 unsigned int ageing_time)
2548 struct mv88e6xxx_chip *chip = ds->priv;
2551 mutex_lock(&chip->reg_lock);
2552 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2553 mutex_unlock(&chip->reg_lock);
2558 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2560 struct dsa_switch *ds = chip->ds;
2561 u32 upstream_port = dsa_upstream_port(ds);
2564 /* Enable the PHY Polling Unit if present, don't discard any packets,
2565 * and mask all interrupt sources.
2567 err = mv88e6xxx_ppu_enable(chip);
2571 if (chip->info->ops->g1_set_cpu_port) {
2572 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2577 if (chip->info->ops->g1_set_egress_port) {
2578 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2583 /* Disable remote management, and set the switch's DSA device number. */
2584 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2585 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2586 (ds->index & 0x1f));
2590 /* Clear all the VTU and STU entries */
2591 err = _mv88e6xxx_vtu_stu_flush(chip);
2595 /* Configure the IP ToS mapping registers. */
2596 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2599 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2602 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2605 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2608 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2611 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2614 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2617 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2621 /* Configure the IEEE 802.1p priority mapping register. */
2622 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2626 /* Initialize the statistics unit */
2627 err = mv88e6xxx_stats_set_histogram(chip);
2631 /* Clear the statistics counters for all ports */
2632 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2633 GLOBAL_STATS_OP_FLUSH_ALL);
2637 /* Wait for the flush to complete. */
2638 err = mv88e6xxx_g1_stats_wait(chip);
2645 static int mv88e6xxx_setup(struct dsa_switch *ds)
2647 struct mv88e6xxx_chip *chip = ds->priv;
2652 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2654 mutex_lock(&chip->reg_lock);
2656 /* Setup Switch Port Registers */
2657 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2658 err = mv88e6xxx_setup_port(chip, i);
2663 /* Setup Switch Global 1 Registers */
2664 err = mv88e6xxx_g1_setup(chip);
2668 /* Setup Switch Global 2 Registers */
2669 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2670 err = mv88e6xxx_g2_setup(chip);
2675 err = mv88e6xxx_pvt_setup(chip);
2679 err = mv88e6xxx_atu_setup(chip);
2683 /* Some generations have the configuration of sending reserved
2684 * management frames to the CPU in global2, others in
2685 * global1. Hence it does not fit the two setup functions
2688 if (chip->info->ops->mgmt_rsvd2cpu) {
2689 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2695 mutex_unlock(&chip->reg_lock);
2700 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2702 struct mv88e6xxx_chip *chip = ds->priv;
2705 if (!chip->info->ops->set_switch_mac)
2708 mutex_lock(&chip->reg_lock);
2709 err = chip->info->ops->set_switch_mac(chip, addr);
2710 mutex_unlock(&chip->reg_lock);
2715 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2717 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2718 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2722 if (!chip->info->ops->phy_read)
2725 mutex_lock(&chip->reg_lock);
2726 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2727 mutex_unlock(&chip->reg_lock);
2729 if (reg == MII_PHYSID2) {
2730 /* Some internal PHYS don't have a model number. Use
2731 * the mv88e6390 family model number instead.
2734 val |= PORT_SWITCH_ID_PROD_NUM_6390;
2737 return err ? err : val;
2740 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2742 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2743 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2746 if (!chip->info->ops->phy_write)
2749 mutex_lock(&chip->reg_lock);
2750 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2751 mutex_unlock(&chip->reg_lock);
2756 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2757 struct device_node *np,
2761 struct mv88e6xxx_mdio_bus *mdio_bus;
2762 struct mii_bus *bus;
2765 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2769 mdio_bus = bus->priv;
2770 mdio_bus->bus = bus;
2771 mdio_bus->chip = chip;
2772 INIT_LIST_HEAD(&mdio_bus->list);
2773 mdio_bus->external = external;
2776 bus->name = np->full_name;
2777 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2779 bus->name = "mv88e6xxx SMI";
2780 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2783 bus->read = mv88e6xxx_mdio_read;
2784 bus->write = mv88e6xxx_mdio_write;
2785 bus->parent = chip->dev;
2788 err = of_mdiobus_register(bus, np);
2790 err = mdiobus_register(bus);
2792 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2797 list_add_tail(&mdio_bus->list, &chip->mdios);
2799 list_add(&mdio_bus->list, &chip->mdios);
2804 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2805 { .compatible = "marvell,mv88e6xxx-mdio-external",
2806 .data = (void *)true },
2810 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2811 struct device_node *np)
2813 const struct of_device_id *match;
2814 struct device_node *child;
2817 /* Always register one mdio bus for the internal/default mdio
2818 * bus. This maybe represented in the device tree, but is
2821 child = of_get_child_by_name(np, "mdio");
2822 err = mv88e6xxx_mdio_register(chip, child, false);
2826 /* Walk the device tree, and see if there are any other nodes
2827 * which say they are compatible with the external mdio
2830 for_each_available_child_of_node(np, child) {
2831 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2833 err = mv88e6xxx_mdio_register(chip, child, true);
2842 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2845 struct mv88e6xxx_mdio_bus *mdio_bus;
2846 struct mii_bus *bus;
2848 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2849 bus = mdio_bus->bus;
2851 mdiobus_unregister(bus);
2855 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2857 struct mv88e6xxx_chip *chip = ds->priv;
2859 return chip->eeprom_len;
2862 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2863 struct ethtool_eeprom *eeprom, u8 *data)
2865 struct mv88e6xxx_chip *chip = ds->priv;
2868 if (!chip->info->ops->get_eeprom)
2871 mutex_lock(&chip->reg_lock);
2872 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2873 mutex_unlock(&chip->reg_lock);
2878 eeprom->magic = 0xc3ec4951;
2883 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2884 struct ethtool_eeprom *eeprom, u8 *data)
2886 struct mv88e6xxx_chip *chip = ds->priv;
2889 if (!chip->info->ops->set_eeprom)
2892 if (eeprom->magic != 0xc3ec4951)
2895 mutex_lock(&chip->reg_lock);
2896 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2897 mutex_unlock(&chip->reg_lock);
2902 static const struct mv88e6xxx_ops mv88e6085_ops = {
2903 /* MV88E6XXX_FAMILY_6097 */
2904 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2905 .phy_read = mv88e6xxx_phy_ppu_read,
2906 .phy_write = mv88e6xxx_phy_ppu_write,
2907 .port_set_link = mv88e6xxx_port_set_link,
2908 .port_set_duplex = mv88e6xxx_port_set_duplex,
2909 .port_set_speed = mv88e6185_port_set_speed,
2910 .port_tag_remap = mv88e6095_port_tag_remap,
2911 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2912 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2913 .port_set_ether_type = mv88e6351_port_set_ether_type,
2914 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2915 .port_pause_config = mv88e6097_port_pause_config,
2916 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2917 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2918 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2919 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2920 .stats_get_strings = mv88e6095_stats_get_strings,
2921 .stats_get_stats = mv88e6095_stats_get_stats,
2922 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2923 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2924 .watchdog_ops = &mv88e6097_watchdog_ops,
2925 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2926 .ppu_enable = mv88e6185_g1_ppu_enable,
2927 .ppu_disable = mv88e6185_g1_ppu_disable,
2928 .reset = mv88e6185_g1_reset,
2931 static const struct mv88e6xxx_ops mv88e6095_ops = {
2932 /* MV88E6XXX_FAMILY_6095 */
2933 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2934 .phy_read = mv88e6xxx_phy_ppu_read,
2935 .phy_write = mv88e6xxx_phy_ppu_write,
2936 .port_set_link = mv88e6xxx_port_set_link,
2937 .port_set_duplex = mv88e6xxx_port_set_duplex,
2938 .port_set_speed = mv88e6185_port_set_speed,
2939 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2940 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2941 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2942 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2943 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2944 .stats_get_strings = mv88e6095_stats_get_strings,
2945 .stats_get_stats = mv88e6095_stats_get_stats,
2946 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2947 .ppu_enable = mv88e6185_g1_ppu_enable,
2948 .ppu_disable = mv88e6185_g1_ppu_disable,
2949 .reset = mv88e6185_g1_reset,
2952 static const struct mv88e6xxx_ops mv88e6097_ops = {
2953 /* MV88E6XXX_FAMILY_6097 */
2954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2955 .phy_read = mv88e6xxx_g2_smi_phy_read,
2956 .phy_write = mv88e6xxx_g2_smi_phy_write,
2957 .port_set_link = mv88e6xxx_port_set_link,
2958 .port_set_duplex = mv88e6xxx_port_set_duplex,
2959 .port_set_speed = mv88e6185_port_set_speed,
2960 .port_tag_remap = mv88e6095_port_tag_remap,
2961 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2962 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2963 .port_set_ether_type = mv88e6351_port_set_ether_type,
2964 .port_jumbo_config = mv88e6165_port_jumbo_config,
2965 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2966 .port_pause_config = mv88e6097_port_pause_config,
2967 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2968 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2969 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2970 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2971 .stats_get_strings = mv88e6095_stats_get_strings,
2972 .stats_get_stats = mv88e6095_stats_get_stats,
2973 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2974 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2975 .watchdog_ops = &mv88e6097_watchdog_ops,
2976 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
2977 .reset = mv88e6352_g1_reset,
2980 static const struct mv88e6xxx_ops mv88e6123_ops = {
2981 /* MV88E6XXX_FAMILY_6165 */
2982 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2983 .phy_read = mv88e6165_phy_read,
2984 .phy_write = mv88e6165_phy_write,
2985 .port_set_link = mv88e6xxx_port_set_link,
2986 .port_set_duplex = mv88e6xxx_port_set_duplex,
2987 .port_set_speed = mv88e6185_port_set_speed,
2988 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2989 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2990 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2991 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2992 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2993 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2994 .stats_get_strings = mv88e6095_stats_get_strings,
2995 .stats_get_stats = mv88e6095_stats_get_stats,
2996 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
2997 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
2998 .watchdog_ops = &mv88e6097_watchdog_ops,
2999 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3000 .reset = mv88e6352_g1_reset,
3003 static const struct mv88e6xxx_ops mv88e6131_ops = {
3004 /* MV88E6XXX_FAMILY_6185 */
3005 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3006 .phy_read = mv88e6xxx_phy_ppu_read,
3007 .phy_write = mv88e6xxx_phy_ppu_write,
3008 .port_set_link = mv88e6xxx_port_set_link,
3009 .port_set_duplex = mv88e6xxx_port_set_duplex,
3010 .port_set_speed = mv88e6185_port_set_speed,
3011 .port_tag_remap = mv88e6095_port_tag_remap,
3012 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3013 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3014 .port_set_ether_type = mv88e6351_port_set_ether_type,
3015 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3016 .port_jumbo_config = mv88e6165_port_jumbo_config,
3017 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3018 .port_pause_config = mv88e6097_port_pause_config,
3019 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3020 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3021 .stats_get_strings = mv88e6095_stats_get_strings,
3022 .stats_get_stats = mv88e6095_stats_get_stats,
3023 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3024 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3025 .watchdog_ops = &mv88e6097_watchdog_ops,
3026 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3027 .ppu_enable = mv88e6185_g1_ppu_enable,
3028 .ppu_disable = mv88e6185_g1_ppu_disable,
3029 .reset = mv88e6185_g1_reset,
3032 static const struct mv88e6xxx_ops mv88e6141_ops = {
3033 /* MV88E6XXX_FAMILY_6341 */
3034 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3035 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3037 .phy_read = mv88e6xxx_g2_smi_phy_read,
3038 .phy_write = mv88e6xxx_g2_smi_phy_write,
3039 .port_set_link = mv88e6xxx_port_set_link,
3040 .port_set_duplex = mv88e6xxx_port_set_duplex,
3041 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3042 .port_set_speed = mv88e6390_port_set_speed,
3043 .port_tag_remap = mv88e6095_port_tag_remap,
3044 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3045 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3046 .port_set_ether_type = mv88e6351_port_set_ether_type,
3047 .port_jumbo_config = mv88e6165_port_jumbo_config,
3048 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3049 .port_pause_config = mv88e6097_port_pause_config,
3050 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3051 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3052 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3053 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3054 .stats_get_strings = mv88e6320_stats_get_strings,
3055 .stats_get_stats = mv88e6390_stats_get_stats,
3056 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3057 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3058 .watchdog_ops = &mv88e6390_watchdog_ops,
3059 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3060 .reset = mv88e6352_g1_reset,
3063 static const struct mv88e6xxx_ops mv88e6161_ops = {
3064 /* MV88E6XXX_FAMILY_6165 */
3065 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3066 .phy_read = mv88e6165_phy_read,
3067 .phy_write = mv88e6165_phy_write,
3068 .port_set_link = mv88e6xxx_port_set_link,
3069 .port_set_duplex = mv88e6xxx_port_set_duplex,
3070 .port_set_speed = mv88e6185_port_set_speed,
3071 .port_tag_remap = mv88e6095_port_tag_remap,
3072 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3073 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3074 .port_set_ether_type = mv88e6351_port_set_ether_type,
3075 .port_jumbo_config = mv88e6165_port_jumbo_config,
3076 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3077 .port_pause_config = mv88e6097_port_pause_config,
3078 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3079 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3080 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3081 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3082 .stats_get_strings = mv88e6095_stats_get_strings,
3083 .stats_get_stats = mv88e6095_stats_get_stats,
3084 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3085 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3086 .watchdog_ops = &mv88e6097_watchdog_ops,
3087 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3088 .reset = mv88e6352_g1_reset,
3091 static const struct mv88e6xxx_ops mv88e6165_ops = {
3092 /* MV88E6XXX_FAMILY_6165 */
3093 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3094 .phy_read = mv88e6165_phy_read,
3095 .phy_write = mv88e6165_phy_write,
3096 .port_set_link = mv88e6xxx_port_set_link,
3097 .port_set_duplex = mv88e6xxx_port_set_duplex,
3098 .port_set_speed = mv88e6185_port_set_speed,
3099 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3100 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3101 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3102 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3103 .stats_get_strings = mv88e6095_stats_get_strings,
3104 .stats_get_stats = mv88e6095_stats_get_stats,
3105 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3106 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3107 .watchdog_ops = &mv88e6097_watchdog_ops,
3108 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3109 .reset = mv88e6352_g1_reset,
3112 static const struct mv88e6xxx_ops mv88e6171_ops = {
3113 /* MV88E6XXX_FAMILY_6351 */
3114 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3115 .phy_read = mv88e6xxx_g2_smi_phy_read,
3116 .phy_write = mv88e6xxx_g2_smi_phy_write,
3117 .port_set_link = mv88e6xxx_port_set_link,
3118 .port_set_duplex = mv88e6xxx_port_set_duplex,
3119 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3120 .port_set_speed = mv88e6185_port_set_speed,
3121 .port_tag_remap = mv88e6095_port_tag_remap,
3122 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3123 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3124 .port_set_ether_type = mv88e6351_port_set_ether_type,
3125 .port_jumbo_config = mv88e6165_port_jumbo_config,
3126 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3127 .port_pause_config = mv88e6097_port_pause_config,
3128 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3129 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3130 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3131 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3132 .stats_get_strings = mv88e6095_stats_get_strings,
3133 .stats_get_stats = mv88e6095_stats_get_stats,
3134 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3135 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3136 .watchdog_ops = &mv88e6097_watchdog_ops,
3137 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3138 .reset = mv88e6352_g1_reset,
3141 static const struct mv88e6xxx_ops mv88e6172_ops = {
3142 /* MV88E6XXX_FAMILY_6352 */
3143 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3144 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3145 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3146 .phy_read = mv88e6xxx_g2_smi_phy_read,
3147 .phy_write = mv88e6xxx_g2_smi_phy_write,
3148 .port_set_link = mv88e6xxx_port_set_link,
3149 .port_set_duplex = mv88e6xxx_port_set_duplex,
3150 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3151 .port_set_speed = mv88e6352_port_set_speed,
3152 .port_tag_remap = mv88e6095_port_tag_remap,
3153 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3154 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3155 .port_set_ether_type = mv88e6351_port_set_ether_type,
3156 .port_jumbo_config = mv88e6165_port_jumbo_config,
3157 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3158 .port_pause_config = mv88e6097_port_pause_config,
3159 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3160 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3161 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3162 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3163 .stats_get_strings = mv88e6095_stats_get_strings,
3164 .stats_get_stats = mv88e6095_stats_get_stats,
3165 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3166 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3167 .watchdog_ops = &mv88e6097_watchdog_ops,
3168 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3169 .reset = mv88e6352_g1_reset,
3172 static const struct mv88e6xxx_ops mv88e6175_ops = {
3173 /* MV88E6XXX_FAMILY_6351 */
3174 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3175 .phy_read = mv88e6xxx_g2_smi_phy_read,
3176 .phy_write = mv88e6xxx_g2_smi_phy_write,
3177 .port_set_link = mv88e6xxx_port_set_link,
3178 .port_set_duplex = mv88e6xxx_port_set_duplex,
3179 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3180 .port_set_speed = mv88e6185_port_set_speed,
3181 .port_tag_remap = mv88e6095_port_tag_remap,
3182 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3183 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3184 .port_set_ether_type = mv88e6351_port_set_ether_type,
3185 .port_jumbo_config = mv88e6165_port_jumbo_config,
3186 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3187 .port_pause_config = mv88e6097_port_pause_config,
3188 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3189 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3190 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3191 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3192 .stats_get_strings = mv88e6095_stats_get_strings,
3193 .stats_get_stats = mv88e6095_stats_get_stats,
3194 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3195 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3196 .watchdog_ops = &mv88e6097_watchdog_ops,
3197 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3198 .reset = mv88e6352_g1_reset,
3201 static const struct mv88e6xxx_ops mv88e6176_ops = {
3202 /* MV88E6XXX_FAMILY_6352 */
3203 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3204 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3205 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3206 .phy_read = mv88e6xxx_g2_smi_phy_read,
3207 .phy_write = mv88e6xxx_g2_smi_phy_write,
3208 .port_set_link = mv88e6xxx_port_set_link,
3209 .port_set_duplex = mv88e6xxx_port_set_duplex,
3210 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3211 .port_set_speed = mv88e6352_port_set_speed,
3212 .port_tag_remap = mv88e6095_port_tag_remap,
3213 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3214 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3215 .port_set_ether_type = mv88e6351_port_set_ether_type,
3216 .port_jumbo_config = mv88e6165_port_jumbo_config,
3217 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3218 .port_pause_config = mv88e6097_port_pause_config,
3219 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3220 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3221 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3222 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3223 .stats_get_strings = mv88e6095_stats_get_strings,
3224 .stats_get_stats = mv88e6095_stats_get_stats,
3225 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3226 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3227 .watchdog_ops = &mv88e6097_watchdog_ops,
3228 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3229 .reset = mv88e6352_g1_reset,
3232 static const struct mv88e6xxx_ops mv88e6185_ops = {
3233 /* MV88E6XXX_FAMILY_6185 */
3234 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3235 .phy_read = mv88e6xxx_phy_ppu_read,
3236 .phy_write = mv88e6xxx_phy_ppu_write,
3237 .port_set_link = mv88e6xxx_port_set_link,
3238 .port_set_duplex = mv88e6xxx_port_set_duplex,
3239 .port_set_speed = mv88e6185_port_set_speed,
3240 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3241 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3242 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3243 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3244 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3245 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3246 .stats_get_strings = mv88e6095_stats_get_strings,
3247 .stats_get_stats = mv88e6095_stats_get_stats,
3248 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3249 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3250 .watchdog_ops = &mv88e6097_watchdog_ops,
3251 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3252 .ppu_enable = mv88e6185_g1_ppu_enable,
3253 .ppu_disable = mv88e6185_g1_ppu_disable,
3254 .reset = mv88e6185_g1_reset,
3257 static const struct mv88e6xxx_ops mv88e6190_ops = {
3258 /* MV88E6XXX_FAMILY_6390 */
3259 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3260 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3261 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3262 .phy_read = mv88e6xxx_g2_smi_phy_read,
3263 .phy_write = mv88e6xxx_g2_smi_phy_write,
3264 .port_set_link = mv88e6xxx_port_set_link,
3265 .port_set_duplex = mv88e6xxx_port_set_duplex,
3266 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3267 .port_set_speed = mv88e6390_port_set_speed,
3268 .port_tag_remap = mv88e6390_port_tag_remap,
3269 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3270 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3271 .port_set_ether_type = mv88e6351_port_set_ether_type,
3272 .port_pause_config = mv88e6390_port_pause_config,
3273 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3274 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3275 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3276 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3277 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3278 .stats_get_strings = mv88e6320_stats_get_strings,
3279 .stats_get_stats = mv88e6390_stats_get_stats,
3280 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3281 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3282 .watchdog_ops = &mv88e6390_watchdog_ops,
3283 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3284 .reset = mv88e6352_g1_reset,
3287 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3288 /* MV88E6XXX_FAMILY_6390 */
3289 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3290 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3291 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3292 .phy_read = mv88e6xxx_g2_smi_phy_read,
3293 .phy_write = mv88e6xxx_g2_smi_phy_write,
3294 .port_set_link = mv88e6xxx_port_set_link,
3295 .port_set_duplex = mv88e6xxx_port_set_duplex,
3296 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3297 .port_set_speed = mv88e6390x_port_set_speed,
3298 .port_tag_remap = mv88e6390_port_tag_remap,
3299 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3300 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3301 .port_set_ether_type = mv88e6351_port_set_ether_type,
3302 .port_pause_config = mv88e6390_port_pause_config,
3303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3305 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3306 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3307 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3308 .stats_get_strings = mv88e6320_stats_get_strings,
3309 .stats_get_stats = mv88e6390_stats_get_stats,
3310 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3311 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3312 .watchdog_ops = &mv88e6390_watchdog_ops,
3313 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3314 .reset = mv88e6352_g1_reset,
3317 static const struct mv88e6xxx_ops mv88e6191_ops = {
3318 /* MV88E6XXX_FAMILY_6390 */
3319 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3320 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3322 .phy_read = mv88e6xxx_g2_smi_phy_read,
3323 .phy_write = mv88e6xxx_g2_smi_phy_write,
3324 .port_set_link = mv88e6xxx_port_set_link,
3325 .port_set_duplex = mv88e6xxx_port_set_duplex,
3326 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3327 .port_set_speed = mv88e6390_port_set_speed,
3328 .port_tag_remap = mv88e6390_port_tag_remap,
3329 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3330 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3331 .port_set_ether_type = mv88e6351_port_set_ether_type,
3332 .port_pause_config = mv88e6390_port_pause_config,
3333 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3334 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3335 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3336 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3337 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3338 .stats_get_strings = mv88e6320_stats_get_strings,
3339 .stats_get_stats = mv88e6390_stats_get_stats,
3340 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3341 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3342 .watchdog_ops = &mv88e6390_watchdog_ops,
3343 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3344 .reset = mv88e6352_g1_reset,
3347 static const struct mv88e6xxx_ops mv88e6240_ops = {
3348 /* MV88E6XXX_FAMILY_6352 */
3349 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3350 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3352 .phy_read = mv88e6xxx_g2_smi_phy_read,
3353 .phy_write = mv88e6xxx_g2_smi_phy_write,
3354 .port_set_link = mv88e6xxx_port_set_link,
3355 .port_set_duplex = mv88e6xxx_port_set_duplex,
3356 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3357 .port_set_speed = mv88e6352_port_set_speed,
3358 .port_tag_remap = mv88e6095_port_tag_remap,
3359 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3360 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3361 .port_set_ether_type = mv88e6351_port_set_ether_type,
3362 .port_jumbo_config = mv88e6165_port_jumbo_config,
3363 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3364 .port_pause_config = mv88e6097_port_pause_config,
3365 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3366 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3367 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3368 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3369 .stats_get_strings = mv88e6095_stats_get_strings,
3370 .stats_get_stats = mv88e6095_stats_get_stats,
3371 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3372 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3373 .watchdog_ops = &mv88e6097_watchdog_ops,
3374 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3375 .reset = mv88e6352_g1_reset,
3378 static const struct mv88e6xxx_ops mv88e6290_ops = {
3379 /* MV88E6XXX_FAMILY_6390 */
3380 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3381 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3382 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3383 .phy_read = mv88e6xxx_g2_smi_phy_read,
3384 .phy_write = mv88e6xxx_g2_smi_phy_write,
3385 .port_set_link = mv88e6xxx_port_set_link,
3386 .port_set_duplex = mv88e6xxx_port_set_duplex,
3387 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3388 .port_set_speed = mv88e6390_port_set_speed,
3389 .port_tag_remap = mv88e6390_port_tag_remap,
3390 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3391 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3392 .port_set_ether_type = mv88e6351_port_set_ether_type,
3393 .port_pause_config = mv88e6390_port_pause_config,
3394 .port_set_cmode = mv88e6390x_port_set_cmode,
3395 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3396 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3397 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3398 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3399 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3400 .stats_get_strings = mv88e6320_stats_get_strings,
3401 .stats_get_stats = mv88e6390_stats_get_stats,
3402 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3403 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3404 .watchdog_ops = &mv88e6390_watchdog_ops,
3405 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3406 .reset = mv88e6352_g1_reset,
3409 static const struct mv88e6xxx_ops mv88e6320_ops = {
3410 /* MV88E6XXX_FAMILY_6320 */
3411 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3412 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3414 .phy_read = mv88e6xxx_g2_smi_phy_read,
3415 .phy_write = mv88e6xxx_g2_smi_phy_write,
3416 .port_set_link = mv88e6xxx_port_set_link,
3417 .port_set_duplex = mv88e6xxx_port_set_duplex,
3418 .port_set_speed = mv88e6185_port_set_speed,
3419 .port_tag_remap = mv88e6095_port_tag_remap,
3420 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3421 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3422 .port_set_ether_type = mv88e6351_port_set_ether_type,
3423 .port_jumbo_config = mv88e6165_port_jumbo_config,
3424 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3425 .port_pause_config = mv88e6097_port_pause_config,
3426 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3427 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3428 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3429 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3430 .stats_get_strings = mv88e6320_stats_get_strings,
3431 .stats_get_stats = mv88e6320_stats_get_stats,
3432 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3433 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3434 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3435 .reset = mv88e6352_g1_reset,
3438 static const struct mv88e6xxx_ops mv88e6321_ops = {
3439 /* MV88E6XXX_FAMILY_6321 */
3440 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3441 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3442 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3443 .phy_read = mv88e6xxx_g2_smi_phy_read,
3444 .phy_write = mv88e6xxx_g2_smi_phy_write,
3445 .port_set_link = mv88e6xxx_port_set_link,
3446 .port_set_duplex = mv88e6xxx_port_set_duplex,
3447 .port_set_speed = mv88e6185_port_set_speed,
3448 .port_tag_remap = mv88e6095_port_tag_remap,
3449 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3450 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3451 .port_set_ether_type = mv88e6351_port_set_ether_type,
3452 .port_jumbo_config = mv88e6165_port_jumbo_config,
3453 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3454 .port_pause_config = mv88e6097_port_pause_config,
3455 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3456 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3457 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3458 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3459 .stats_get_strings = mv88e6320_stats_get_strings,
3460 .stats_get_stats = mv88e6320_stats_get_stats,
3461 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3462 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3463 .reset = mv88e6352_g1_reset,
3466 static const struct mv88e6xxx_ops mv88e6341_ops = {
3467 /* MV88E6XXX_FAMILY_6341 */
3468 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3469 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3471 .phy_read = mv88e6xxx_g2_smi_phy_read,
3472 .phy_write = mv88e6xxx_g2_smi_phy_write,
3473 .port_set_link = mv88e6xxx_port_set_link,
3474 .port_set_duplex = mv88e6xxx_port_set_duplex,
3475 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3476 .port_set_speed = mv88e6390_port_set_speed,
3477 .port_tag_remap = mv88e6095_port_tag_remap,
3478 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3479 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3480 .port_set_ether_type = mv88e6351_port_set_ether_type,
3481 .port_jumbo_config = mv88e6165_port_jumbo_config,
3482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3483 .port_pause_config = mv88e6097_port_pause_config,
3484 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3485 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3486 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3487 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3488 .stats_get_strings = mv88e6320_stats_get_strings,
3489 .stats_get_stats = mv88e6390_stats_get_stats,
3490 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3491 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3492 .watchdog_ops = &mv88e6390_watchdog_ops,
3493 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3494 .reset = mv88e6352_g1_reset,
3497 static const struct mv88e6xxx_ops mv88e6350_ops = {
3498 /* MV88E6XXX_FAMILY_6351 */
3499 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3500 .phy_read = mv88e6xxx_g2_smi_phy_read,
3501 .phy_write = mv88e6xxx_g2_smi_phy_write,
3502 .port_set_link = mv88e6xxx_port_set_link,
3503 .port_set_duplex = mv88e6xxx_port_set_duplex,
3504 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3505 .port_set_speed = mv88e6185_port_set_speed,
3506 .port_tag_remap = mv88e6095_port_tag_remap,
3507 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3508 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3509 .port_set_ether_type = mv88e6351_port_set_ether_type,
3510 .port_jumbo_config = mv88e6165_port_jumbo_config,
3511 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3512 .port_pause_config = mv88e6097_port_pause_config,
3513 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3514 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3515 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3516 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3517 .stats_get_strings = mv88e6095_stats_get_strings,
3518 .stats_get_stats = mv88e6095_stats_get_stats,
3519 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3520 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3521 .watchdog_ops = &mv88e6097_watchdog_ops,
3522 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3523 .reset = mv88e6352_g1_reset,
3526 static const struct mv88e6xxx_ops mv88e6351_ops = {
3527 /* MV88E6XXX_FAMILY_6351 */
3528 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3529 .phy_read = mv88e6xxx_g2_smi_phy_read,
3530 .phy_write = mv88e6xxx_g2_smi_phy_write,
3531 .port_set_link = mv88e6xxx_port_set_link,
3532 .port_set_duplex = mv88e6xxx_port_set_duplex,
3533 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3534 .port_set_speed = mv88e6185_port_set_speed,
3535 .port_tag_remap = mv88e6095_port_tag_remap,
3536 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3537 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3538 .port_set_ether_type = mv88e6351_port_set_ether_type,
3539 .port_jumbo_config = mv88e6165_port_jumbo_config,
3540 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3541 .port_pause_config = mv88e6097_port_pause_config,
3542 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3543 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3544 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3545 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3546 .stats_get_strings = mv88e6095_stats_get_strings,
3547 .stats_get_stats = mv88e6095_stats_get_stats,
3548 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3549 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3550 .watchdog_ops = &mv88e6097_watchdog_ops,
3551 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3552 .reset = mv88e6352_g1_reset,
3555 static const struct mv88e6xxx_ops mv88e6352_ops = {
3556 /* MV88E6XXX_FAMILY_6352 */
3557 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3558 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3560 .phy_read = mv88e6xxx_g2_smi_phy_read,
3561 .phy_write = mv88e6xxx_g2_smi_phy_write,
3562 .port_set_link = mv88e6xxx_port_set_link,
3563 .port_set_duplex = mv88e6xxx_port_set_duplex,
3564 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3565 .port_set_speed = mv88e6352_port_set_speed,
3566 .port_tag_remap = mv88e6095_port_tag_remap,
3567 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3568 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3569 .port_set_ether_type = mv88e6351_port_set_ether_type,
3570 .port_jumbo_config = mv88e6165_port_jumbo_config,
3571 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3572 .port_pause_config = mv88e6097_port_pause_config,
3573 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3574 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3575 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3576 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3577 .stats_get_strings = mv88e6095_stats_get_strings,
3578 .stats_get_stats = mv88e6095_stats_get_stats,
3579 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3580 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3581 .watchdog_ops = &mv88e6097_watchdog_ops,
3582 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3583 .reset = mv88e6352_g1_reset,
3586 static const struct mv88e6xxx_ops mv88e6390_ops = {
3587 /* MV88E6XXX_FAMILY_6390 */
3588 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3589 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3590 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3591 .phy_read = mv88e6xxx_g2_smi_phy_read,
3592 .phy_write = mv88e6xxx_g2_smi_phy_write,
3593 .port_set_link = mv88e6xxx_port_set_link,
3594 .port_set_duplex = mv88e6xxx_port_set_duplex,
3595 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3596 .port_set_speed = mv88e6390_port_set_speed,
3597 .port_tag_remap = mv88e6390_port_tag_remap,
3598 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3599 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3600 .port_set_ether_type = mv88e6351_port_set_ether_type,
3601 .port_jumbo_config = mv88e6165_port_jumbo_config,
3602 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3603 .port_pause_config = mv88e6390_port_pause_config,
3604 .port_set_cmode = mv88e6390x_port_set_cmode,
3605 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3606 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3607 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3608 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3609 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3610 .stats_get_strings = mv88e6320_stats_get_strings,
3611 .stats_get_stats = mv88e6390_stats_get_stats,
3612 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3613 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3614 .watchdog_ops = &mv88e6390_watchdog_ops,
3615 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3616 .reset = mv88e6352_g1_reset,
3619 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3620 /* MV88E6XXX_FAMILY_6390 */
3621 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3622 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3624 .phy_read = mv88e6xxx_g2_smi_phy_read,
3625 .phy_write = mv88e6xxx_g2_smi_phy_write,
3626 .port_set_link = mv88e6xxx_port_set_link,
3627 .port_set_duplex = mv88e6xxx_port_set_duplex,
3628 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3629 .port_set_speed = mv88e6390x_port_set_speed,
3630 .port_tag_remap = mv88e6390_port_tag_remap,
3631 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3632 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3633 .port_set_ether_type = mv88e6351_port_set_ether_type,
3634 .port_jumbo_config = mv88e6165_port_jumbo_config,
3635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3636 .port_pause_config = mv88e6390_port_pause_config,
3637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3639 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3640 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3641 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3642 .stats_get_strings = mv88e6320_stats_get_strings,
3643 .stats_get_stats = mv88e6390_stats_get_stats,
3644 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3645 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3646 .watchdog_ops = &mv88e6390_watchdog_ops,
3647 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3648 .reset = mv88e6352_g1_reset,
3651 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3653 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3654 .family = MV88E6XXX_FAMILY_6097,
3655 .name = "Marvell 88E6085",
3656 .num_databases = 4096,
3658 .port_base_addr = 0x10,
3659 .global1_addr = 0x1b,
3660 .age_time_coeff = 15000,
3662 .atu_move_port_mask = 0xf,
3664 .tag_protocol = DSA_TAG_PROTO_DSA,
3665 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3666 .ops = &mv88e6085_ops,
3670 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3671 .family = MV88E6XXX_FAMILY_6095,
3672 .name = "Marvell 88E6095/88E6095F",
3673 .num_databases = 256,
3675 .port_base_addr = 0x10,
3676 .global1_addr = 0x1b,
3677 .age_time_coeff = 15000,
3679 .atu_move_port_mask = 0xf,
3680 .tag_protocol = DSA_TAG_PROTO_DSA,
3681 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3682 .ops = &mv88e6095_ops,
3686 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3687 .family = MV88E6XXX_FAMILY_6097,
3688 .name = "Marvell 88E6097/88E6097F",
3689 .num_databases = 4096,
3691 .port_base_addr = 0x10,
3692 .global1_addr = 0x1b,
3693 .age_time_coeff = 15000,
3695 .atu_move_port_mask = 0xf,
3697 .tag_protocol = DSA_TAG_PROTO_EDSA,
3698 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3699 .ops = &mv88e6097_ops,
3703 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3704 .family = MV88E6XXX_FAMILY_6165,
3705 .name = "Marvell 88E6123",
3706 .num_databases = 4096,
3708 .port_base_addr = 0x10,
3709 .global1_addr = 0x1b,
3710 .age_time_coeff = 15000,
3712 .atu_move_port_mask = 0xf,
3714 .tag_protocol = DSA_TAG_PROTO_DSA,
3715 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3716 .ops = &mv88e6123_ops,
3720 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3721 .family = MV88E6XXX_FAMILY_6185,
3722 .name = "Marvell 88E6131",
3723 .num_databases = 256,
3725 .port_base_addr = 0x10,
3726 .global1_addr = 0x1b,
3727 .age_time_coeff = 15000,
3729 .atu_move_port_mask = 0xf,
3730 .tag_protocol = DSA_TAG_PROTO_DSA,
3731 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3732 .ops = &mv88e6131_ops,
3736 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
3737 .family = MV88E6XXX_FAMILY_6341,
3738 .name = "Marvell 88E6341",
3739 .num_databases = 4096,
3741 .port_base_addr = 0x10,
3742 .global1_addr = 0x1b,
3743 .age_time_coeff = 3750,
3744 .atu_move_port_mask = 0x1f,
3746 .tag_protocol = DSA_TAG_PROTO_EDSA,
3747 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
3748 .ops = &mv88e6141_ops,
3752 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3753 .family = MV88E6XXX_FAMILY_6165,
3754 .name = "Marvell 88E6161",
3755 .num_databases = 4096,
3757 .port_base_addr = 0x10,
3758 .global1_addr = 0x1b,
3759 .age_time_coeff = 15000,
3761 .atu_move_port_mask = 0xf,
3763 .tag_protocol = DSA_TAG_PROTO_DSA,
3764 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3765 .ops = &mv88e6161_ops,
3769 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3770 .family = MV88E6XXX_FAMILY_6165,
3771 .name = "Marvell 88E6165",
3772 .num_databases = 4096,
3774 .port_base_addr = 0x10,
3775 .global1_addr = 0x1b,
3776 .age_time_coeff = 15000,
3778 .atu_move_port_mask = 0xf,
3780 .tag_protocol = DSA_TAG_PROTO_DSA,
3781 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3782 .ops = &mv88e6165_ops,
3786 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3787 .family = MV88E6XXX_FAMILY_6351,
3788 .name = "Marvell 88E6171",
3789 .num_databases = 4096,
3791 .port_base_addr = 0x10,
3792 .global1_addr = 0x1b,
3793 .age_time_coeff = 15000,
3795 .atu_move_port_mask = 0xf,
3797 .tag_protocol = DSA_TAG_PROTO_EDSA,
3798 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3799 .ops = &mv88e6171_ops,
3803 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3804 .family = MV88E6XXX_FAMILY_6352,
3805 .name = "Marvell 88E6172",
3806 .num_databases = 4096,
3808 .port_base_addr = 0x10,
3809 .global1_addr = 0x1b,
3810 .age_time_coeff = 15000,
3812 .atu_move_port_mask = 0xf,
3814 .tag_protocol = DSA_TAG_PROTO_EDSA,
3815 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3816 .ops = &mv88e6172_ops,
3820 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3821 .family = MV88E6XXX_FAMILY_6351,
3822 .name = "Marvell 88E6175",
3823 .num_databases = 4096,
3825 .port_base_addr = 0x10,
3826 .global1_addr = 0x1b,
3827 .age_time_coeff = 15000,
3829 .atu_move_port_mask = 0xf,
3831 .tag_protocol = DSA_TAG_PROTO_EDSA,
3832 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3833 .ops = &mv88e6175_ops,
3837 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3838 .family = MV88E6XXX_FAMILY_6352,
3839 .name = "Marvell 88E6176",
3840 .num_databases = 4096,
3842 .port_base_addr = 0x10,
3843 .global1_addr = 0x1b,
3844 .age_time_coeff = 15000,
3846 .atu_move_port_mask = 0xf,
3848 .tag_protocol = DSA_TAG_PROTO_EDSA,
3849 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3850 .ops = &mv88e6176_ops,
3854 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3855 .family = MV88E6XXX_FAMILY_6185,
3856 .name = "Marvell 88E6185",
3857 .num_databases = 256,
3859 .port_base_addr = 0x10,
3860 .global1_addr = 0x1b,
3861 .age_time_coeff = 15000,
3863 .atu_move_port_mask = 0xf,
3864 .tag_protocol = DSA_TAG_PROTO_EDSA,
3865 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3866 .ops = &mv88e6185_ops,
3870 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
3871 .family = MV88E6XXX_FAMILY_6390,
3872 .name = "Marvell 88E6190",
3873 .num_databases = 4096,
3874 .num_ports = 11, /* 10 + Z80 */
3875 .port_base_addr = 0x0,
3876 .global1_addr = 0x1b,
3877 .tag_protocol = DSA_TAG_PROTO_DSA,
3878 .age_time_coeff = 3750,
3881 .atu_move_port_mask = 0x1f,
3882 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3883 .ops = &mv88e6190_ops,
3887 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
3888 .family = MV88E6XXX_FAMILY_6390,
3889 .name = "Marvell 88E6190X",
3890 .num_databases = 4096,
3891 .num_ports = 11, /* 10 + Z80 */
3892 .port_base_addr = 0x0,
3893 .global1_addr = 0x1b,
3894 .age_time_coeff = 3750,
3896 .atu_move_port_mask = 0x1f,
3898 .tag_protocol = DSA_TAG_PROTO_DSA,
3899 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3900 .ops = &mv88e6190x_ops,
3904 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
3905 .family = MV88E6XXX_FAMILY_6390,
3906 .name = "Marvell 88E6191",
3907 .num_databases = 4096,
3908 .num_ports = 11, /* 10 + Z80 */
3909 .port_base_addr = 0x0,
3910 .global1_addr = 0x1b,
3911 .age_time_coeff = 3750,
3913 .atu_move_port_mask = 0x1f,
3915 .tag_protocol = DSA_TAG_PROTO_DSA,
3916 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3917 .ops = &mv88e6191_ops,
3921 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3922 .family = MV88E6XXX_FAMILY_6352,
3923 .name = "Marvell 88E6240",
3924 .num_databases = 4096,
3926 .port_base_addr = 0x10,
3927 .global1_addr = 0x1b,
3928 .age_time_coeff = 15000,
3930 .atu_move_port_mask = 0xf,
3932 .tag_protocol = DSA_TAG_PROTO_EDSA,
3933 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3934 .ops = &mv88e6240_ops,
3938 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
3939 .family = MV88E6XXX_FAMILY_6390,
3940 .name = "Marvell 88E6290",
3941 .num_databases = 4096,
3942 .num_ports = 11, /* 10 + Z80 */
3943 .port_base_addr = 0x0,
3944 .global1_addr = 0x1b,
3945 .age_time_coeff = 3750,
3947 .atu_move_port_mask = 0x1f,
3949 .tag_protocol = DSA_TAG_PROTO_DSA,
3950 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
3951 .ops = &mv88e6290_ops,
3955 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3956 .family = MV88E6XXX_FAMILY_6320,
3957 .name = "Marvell 88E6320",
3958 .num_databases = 4096,
3960 .port_base_addr = 0x10,
3961 .global1_addr = 0x1b,
3962 .age_time_coeff = 15000,
3964 .atu_move_port_mask = 0xf,
3966 .tag_protocol = DSA_TAG_PROTO_EDSA,
3967 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3968 .ops = &mv88e6320_ops,
3972 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3973 .family = MV88E6XXX_FAMILY_6320,
3974 .name = "Marvell 88E6321",
3975 .num_databases = 4096,
3977 .port_base_addr = 0x10,
3978 .global1_addr = 0x1b,
3979 .age_time_coeff = 15000,
3981 .atu_move_port_mask = 0xf,
3982 .tag_protocol = DSA_TAG_PROTO_EDSA,
3983 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3984 .ops = &mv88e6321_ops,
3988 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
3989 .family = MV88E6XXX_FAMILY_6341,
3990 .name = "Marvell 88E6341",
3991 .num_databases = 4096,
3993 .port_base_addr = 0x10,
3994 .global1_addr = 0x1b,
3995 .age_time_coeff = 3750,
3996 .atu_move_port_mask = 0x1f,
3998 .tag_protocol = DSA_TAG_PROTO_EDSA,
3999 .flags = MV88E6XXX_FLAGS_FAMILY_6341,
4000 .ops = &mv88e6341_ops,
4004 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4005 .family = MV88E6XXX_FAMILY_6351,
4006 .name = "Marvell 88E6350",
4007 .num_databases = 4096,
4009 .port_base_addr = 0x10,
4010 .global1_addr = 0x1b,
4011 .age_time_coeff = 15000,
4013 .atu_move_port_mask = 0xf,
4015 .tag_protocol = DSA_TAG_PROTO_EDSA,
4016 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4017 .ops = &mv88e6350_ops,
4021 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4022 .family = MV88E6XXX_FAMILY_6351,
4023 .name = "Marvell 88E6351",
4024 .num_databases = 4096,
4026 .port_base_addr = 0x10,
4027 .global1_addr = 0x1b,
4028 .age_time_coeff = 15000,
4030 .atu_move_port_mask = 0xf,
4032 .tag_protocol = DSA_TAG_PROTO_EDSA,
4033 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4034 .ops = &mv88e6351_ops,
4038 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4039 .family = MV88E6XXX_FAMILY_6352,
4040 .name = "Marvell 88E6352",
4041 .num_databases = 4096,
4043 .port_base_addr = 0x10,
4044 .global1_addr = 0x1b,
4045 .age_time_coeff = 15000,
4047 .atu_move_port_mask = 0xf,
4049 .tag_protocol = DSA_TAG_PROTO_EDSA,
4050 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4051 .ops = &mv88e6352_ops,
4054 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4055 .family = MV88E6XXX_FAMILY_6390,
4056 .name = "Marvell 88E6390",
4057 .num_databases = 4096,
4058 .num_ports = 11, /* 10 + Z80 */
4059 .port_base_addr = 0x0,
4060 .global1_addr = 0x1b,
4061 .age_time_coeff = 3750,
4063 .atu_move_port_mask = 0x1f,
4065 .tag_protocol = DSA_TAG_PROTO_DSA,
4066 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4067 .ops = &mv88e6390_ops,
4070 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4071 .family = MV88E6XXX_FAMILY_6390,
4072 .name = "Marvell 88E6390X",
4073 .num_databases = 4096,
4074 .num_ports = 11, /* 10 + Z80 */
4075 .port_base_addr = 0x0,
4076 .global1_addr = 0x1b,
4077 .age_time_coeff = 3750,
4079 .atu_move_port_mask = 0x1f,
4081 .tag_protocol = DSA_TAG_PROTO_DSA,
4082 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4083 .ops = &mv88e6390x_ops,
4087 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4091 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4092 if (mv88e6xxx_table[i].prod_num == prod_num)
4093 return &mv88e6xxx_table[i];
4098 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4100 const struct mv88e6xxx_info *info;
4101 unsigned int prod_num, rev;
4105 mutex_lock(&chip->reg_lock);
4106 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4107 mutex_unlock(&chip->reg_lock);
4111 prod_num = (id & 0xfff0) >> 4;
4114 info = mv88e6xxx_lookup_info(prod_num);
4118 /* Update the compatible info with the probed one */
4121 err = mv88e6xxx_g2_require(chip);
4125 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4126 chip->info->prod_num, chip->info->name, rev);
4131 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4133 struct mv88e6xxx_chip *chip;
4135 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4141 mutex_init(&chip->reg_lock);
4142 INIT_LIST_HEAD(&chip->mdios);
4147 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4149 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4150 mv88e6xxx_ppu_state_init(chip);
4153 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4155 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4156 mv88e6xxx_ppu_state_destroy(chip);
4159 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4160 struct mii_bus *bus, int sw_addr)
4163 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4164 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
4165 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4170 chip->sw_addr = sw_addr;
4175 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4177 struct mv88e6xxx_chip *chip = ds->priv;
4179 return chip->info->tag_protocol;
4182 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4183 struct device *host_dev, int sw_addr,
4186 struct mv88e6xxx_chip *chip;
4187 struct mii_bus *bus;
4190 bus = dsa_host_dev_to_mii_bus(host_dev);
4194 chip = mv88e6xxx_alloc_chip(dsa_dev);
4198 /* Legacy SMI probing will only support chips similar to 88E6085 */
4199 chip->info = &mv88e6xxx_table[MV88E6085];
4201 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4205 err = mv88e6xxx_detect(chip);
4209 mutex_lock(&chip->reg_lock);
4210 err = mv88e6xxx_switch_reset(chip);
4211 mutex_unlock(&chip->reg_lock);
4215 mv88e6xxx_phy_init(chip);
4217 err = mv88e6xxx_mdios_register(chip, NULL);
4223 return chip->info->name;
4225 devm_kfree(dsa_dev, chip);
4230 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4231 const struct switchdev_obj_port_mdb *mdb,
4232 struct switchdev_trans *trans)
4234 /* We don't need any dynamic resource from the kernel (yet),
4235 * so skip the prepare phase.
4241 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4242 const struct switchdev_obj_port_mdb *mdb,
4243 struct switchdev_trans *trans)
4245 struct mv88e6xxx_chip *chip = ds->priv;
4247 mutex_lock(&chip->reg_lock);
4248 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4249 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4250 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4251 mutex_unlock(&chip->reg_lock);
4254 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4255 const struct switchdev_obj_port_mdb *mdb)
4257 struct mv88e6xxx_chip *chip = ds->priv;
4260 mutex_lock(&chip->reg_lock);
4261 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4262 GLOBAL_ATU_DATA_STATE_UNUSED);
4263 mutex_unlock(&chip->reg_lock);
4268 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4269 struct switchdev_obj_port_mdb *mdb,
4270 int (*cb)(struct switchdev_obj *obj))
4272 struct mv88e6xxx_chip *chip = ds->priv;
4275 mutex_lock(&chip->reg_lock);
4276 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4277 mutex_unlock(&chip->reg_lock);
4282 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4283 .probe = mv88e6xxx_drv_probe,
4284 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4285 .setup = mv88e6xxx_setup,
4286 .set_addr = mv88e6xxx_set_addr,
4287 .adjust_link = mv88e6xxx_adjust_link,
4288 .get_strings = mv88e6xxx_get_strings,
4289 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4290 .get_sset_count = mv88e6xxx_get_sset_count,
4291 .set_eee = mv88e6xxx_set_eee,
4292 .get_eee = mv88e6xxx_get_eee,
4293 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4294 .get_eeprom = mv88e6xxx_get_eeprom,
4295 .set_eeprom = mv88e6xxx_set_eeprom,
4296 .get_regs_len = mv88e6xxx_get_regs_len,
4297 .get_regs = mv88e6xxx_get_regs,
4298 .set_ageing_time = mv88e6xxx_set_ageing_time,
4299 .port_bridge_join = mv88e6xxx_port_bridge_join,
4300 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4301 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4302 .port_fast_age = mv88e6xxx_port_fast_age,
4303 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4304 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4305 .port_vlan_add = mv88e6xxx_port_vlan_add,
4306 .port_vlan_del = mv88e6xxx_port_vlan_del,
4307 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4308 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4309 .port_fdb_add = mv88e6xxx_port_fdb_add,
4310 .port_fdb_del = mv88e6xxx_port_fdb_del,
4311 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4312 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4313 .port_mdb_add = mv88e6xxx_port_mdb_add,
4314 .port_mdb_del = mv88e6xxx_port_mdb_del,
4315 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4318 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4319 .ops = &mv88e6xxx_switch_ops,
4322 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4324 struct device *dev = chip->dev;
4325 struct dsa_switch *ds;
4327 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4332 ds->ops = &mv88e6xxx_switch_ops;
4333 ds->ageing_time_min = chip->info->age_time_coeff;
4334 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4336 dev_set_drvdata(dev, ds);
4338 return dsa_register_switch(ds, dev);
4341 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4343 dsa_unregister_switch(chip->ds);
4346 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4348 struct device *dev = &mdiodev->dev;
4349 struct device_node *np = dev->of_node;
4350 const struct mv88e6xxx_info *compat_info;
4351 struct mv88e6xxx_chip *chip;
4355 compat_info = of_device_get_match_data(dev);
4359 chip = mv88e6xxx_alloc_chip(dev);
4363 chip->info = compat_info;
4365 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4369 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4370 if (IS_ERR(chip->reset))
4371 return PTR_ERR(chip->reset);
4373 err = mv88e6xxx_detect(chip);
4377 mv88e6xxx_phy_init(chip);
4379 if (chip->info->ops->get_eeprom &&
4380 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4381 chip->eeprom_len = eeprom_len;
4383 mutex_lock(&chip->reg_lock);
4384 err = mv88e6xxx_switch_reset(chip);
4385 mutex_unlock(&chip->reg_lock);
4389 chip->irq = of_irq_get(np, 0);
4390 if (chip->irq == -EPROBE_DEFER) {
4395 if (chip->irq > 0) {
4396 /* Has to be performed before the MDIO bus is created,
4397 * because the PHYs will link there interrupts to these
4398 * interrupt controllers
4400 mutex_lock(&chip->reg_lock);
4401 err = mv88e6xxx_g1_irq_setup(chip);
4402 mutex_unlock(&chip->reg_lock);
4407 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4408 err = mv88e6xxx_g2_irq_setup(chip);
4414 err = mv88e6xxx_mdios_register(chip, np);
4418 err = mv88e6xxx_register_switch(chip);
4425 mv88e6xxx_mdios_unregister(chip);
4427 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4428 mv88e6xxx_g2_irq_free(chip);
4430 if (chip->irq > 0) {
4431 mutex_lock(&chip->reg_lock);
4432 mv88e6xxx_g1_irq_free(chip);
4433 mutex_unlock(&chip->reg_lock);
4439 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4441 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4442 struct mv88e6xxx_chip *chip = ds->priv;
4444 mv88e6xxx_phy_destroy(chip);
4445 mv88e6xxx_unregister_switch(chip);
4446 mv88e6xxx_mdios_unregister(chip);
4448 if (chip->irq > 0) {
4449 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4450 mv88e6xxx_g2_irq_free(chip);
4451 mv88e6xxx_g1_irq_free(chip);
4455 static const struct of_device_id mv88e6xxx_of_match[] = {
4457 .compatible = "marvell,mv88e6085",
4458 .data = &mv88e6xxx_table[MV88E6085],
4461 .compatible = "marvell,mv88e6190",
4462 .data = &mv88e6xxx_table[MV88E6190],
4467 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4469 static struct mdio_driver mv88e6xxx_driver = {
4470 .probe = mv88e6xxx_probe,
4471 .remove = mv88e6xxx_remove,
4473 .name = "mv88e6085",
4474 .of_match_table = mv88e6xxx_of_match,
4478 static int __init mv88e6xxx_init(void)
4480 register_switch_driver(&mv88e6xxx_switch_drv);
4481 return mdio_driver_register(&mv88e6xxx_driver);
4483 module_init(mv88e6xxx_init);
4485 static void __exit mv88e6xxx_cleanup(void)
4487 mdio_driver_unregister(&mv88e6xxx_driver);
4488 unregister_switch_driver(&mv88e6xxx_switch_drv);
4490 module_exit(mv88e6xxx_cleanup);
4492 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4493 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4494 MODULE_LICENSE("GPL");