1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
16 #include <linux/irq.h>
20 #define KSZ_MAX_NUM_PORTS 8
25 enum ksz_regmap_width {
37 struct mutex cnt_mutex; /* structure access */
40 struct rtnl_link_stats64 stats64;
41 struct ethtool_pause_stats pause_stats;
42 struct spinlock stats64_lock;
45 struct ksz_mib_names {
47 char string[ETH_GSTRING_LEN];
50 struct ksz_chip_data {
60 bool tc_cbs_supported;
61 bool tc_ets_supported;
62 const struct ksz_dev_ops *ops;
63 bool ksz87xx_eee_link_erratum;
64 const struct ksz_mib_names *mib_names;
73 int broadcast_ctrl_reg;
74 int multicast_ctrl_reg;
76 bool supports_mii[KSZ_MAX_NUM_PORTS];
77 bool supports_rmii[KSZ_MAX_NUM_PORTS];
78 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
79 bool internal_phy[KSZ_MAX_NUM_PORTS];
80 bool gbit_capable[KSZ_MAX_NUM_PORTS];
81 const struct regmap_access_table *wr_table;
82 const struct regmap_access_table *rd_table;
89 struct irq_domain *domain;
93 struct ksz_device *dev;
97 struct ksz_port *port;
105 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
108 struct phy_device phydev;
110 u32 fiber:1; /* port is fiber */
112 u32 read:1; /* read MIB counters in background */
113 u32 freeze:1; /* MIB counter freeze is enabled */
115 struct ksz_port_mib mib;
116 phy_interface_t interface;
119 struct ksz_device *ksz_dev;
123 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
124 struct hwtstamp_config tstamp_config;
127 struct ksz_irq ptpirq;
128 struct ksz_ptp_irq ptpmsg_irq[3];
130 struct completion tstamp_msg_comp;
135 struct dsa_switch *ds;
136 struct ksz_platform_data *pdata;
137 const struct ksz_chip_data *info;
139 struct mutex dev_mutex; /* device access */
140 struct mutex regmap_mutex; /* regmap access */
141 struct mutex alu_mutex; /* ALU access */
142 struct mutex vlan_mutex; /* vlan access */
143 const struct ksz_dev_ops *dev_ops;
146 struct regmap *regmap[__KSZ_NUM_REGMAPS];
151 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
153 /* chip specific data */
156 int cpu_port; /* port connected to CPU */
158 phy_interface_t compat_interface;
160 bool synclko_disable;
162 struct vlan_table *vlan_cache;
164 struct ksz_port *ports;
165 struct delayed_work mib_read;
166 unsigned long mib_read_interval;
170 struct mutex lock_irq; /* IRQ Access */
172 struct ksz_ptp_data ptp_data;
175 /* List of supported models */
196 KSZ8563_CHIP_ID = 0x8563,
197 KSZ8795_CHIP_ID = 0x8795,
198 KSZ8794_CHIP_ID = 0x8794,
199 KSZ8765_CHIP_ID = 0x8765,
200 KSZ8830_CHIP_ID = 0x8830,
201 KSZ9477_CHIP_ID = 0x00947700,
202 KSZ9896_CHIP_ID = 0x00989600,
203 KSZ9897_CHIP_ID = 0x00989700,
204 KSZ9893_CHIP_ID = 0x00989300,
205 KSZ9563_CHIP_ID = 0x00956300,
206 KSZ9567_CHIP_ID = 0x00956700,
207 LAN9370_CHIP_ID = 0x00937000,
208 LAN9371_CHIP_ID = 0x00937100,
209 LAN9372_CHIP_ID = 0x00937200,
210 LAN9373_CHIP_ID = 0x00937300,
211 LAN9374_CHIP_ID = 0x00937400,
239 PORT_802_1P_REMAPPING,
241 MIB_COUNTER_OVERFLOW,
244 VLAN_TABLE_MEMBERSHIP,
246 STATIC_MAC_TABLE_VALID,
247 STATIC_MAC_TABLE_USE_FID,
248 STATIC_MAC_TABLE_FID,
249 STATIC_MAC_TABLE_OVERRIDE,
250 STATIC_MAC_TABLE_FWD_PORTS,
251 DYNAMIC_MAC_TABLE_ENTRIES_H,
252 DYNAMIC_MAC_TABLE_MAC_EMPTY,
253 DYNAMIC_MAC_TABLE_NOT_READY,
254 DYNAMIC_MAC_TABLE_ENTRIES,
255 DYNAMIC_MAC_TABLE_FID,
256 DYNAMIC_MAC_TABLE_SRC_PORT,
257 DYNAMIC_MAC_TABLE_TIMESTAMP,
265 VLAN_TABLE_MEMBERSHIP_S,
267 STATIC_MAC_FWD_PORTS,
269 DYNAMIC_MAC_ENTRIES_H,
272 DYNAMIC_MAC_TIMESTAMP,
273 DYNAMIC_MAC_SRC_PORT,
277 enum ksz_xmii_ctrl0 {
284 enum ksz_xmii_ctrl1 {
313 int (*setup)(struct dsa_switch *ds);
314 void (*teardown)(struct dsa_switch *ds);
315 u32 (*get_port_addr)(int port, int offset);
316 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
317 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
318 void (*port_cleanup)(struct ksz_device *dev, int port);
319 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
320 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
321 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
322 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
323 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
325 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
326 u64 *dropped, u64 *cnt);
327 void (*r_mib_stat64)(struct ksz_device *dev, int port);
328 int (*vlan_filtering)(struct ksz_device *dev, int port,
329 bool flag, struct netlink_ext_ack *extack);
330 int (*vlan_add)(struct ksz_device *dev, int port,
331 const struct switchdev_obj_port_vlan *vlan,
332 struct netlink_ext_ack *extack);
333 int (*vlan_del)(struct ksz_device *dev, int port,
334 const struct switchdev_obj_port_vlan *vlan);
335 int (*mirror_add)(struct ksz_device *dev, int port,
336 struct dsa_mall_mirror_tc_entry *mirror,
337 bool ingress, struct netlink_ext_ack *extack);
338 void (*mirror_del)(struct ksz_device *dev, int port,
339 struct dsa_mall_mirror_tc_entry *mirror);
340 int (*fdb_add)(struct ksz_device *dev, int port,
341 const unsigned char *addr, u16 vid, struct dsa_db db);
342 int (*fdb_del)(struct ksz_device *dev, int port,
343 const unsigned char *addr, u16 vid, struct dsa_db db);
344 int (*fdb_dump)(struct ksz_device *dev, int port,
345 dsa_fdb_dump_cb_t *cb, void *data);
346 int (*mdb_add)(struct ksz_device *dev, int port,
347 const struct switchdev_obj_port_mdb *mdb,
349 int (*mdb_del)(struct ksz_device *dev, int port,
350 const struct switchdev_obj_port_mdb *mdb,
352 void (*get_caps)(struct ksz_device *dev, int port,
353 struct phylink_config *config);
354 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
355 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
356 void (*port_init_cnt)(struct ksz_device *dev, int port);
357 void (*phylink_mac_config)(struct ksz_device *dev, int port,
359 const struct phylink_link_state *state);
360 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
362 phy_interface_t interface,
363 struct phy_device *phydev, int speed,
364 int duplex, bool tx_pause, bool rx_pause);
365 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
366 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
367 void (*config_cpu_port)(struct dsa_switch *ds);
368 int (*enable_stp_addr)(struct ksz_device *dev);
369 int (*reset)(struct ksz_device *dev);
370 int (*init)(struct ksz_device *dev);
371 void (*exit)(struct ksz_device *dev);
374 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
375 int ksz_switch_register(struct ksz_device *dev);
376 void ksz_switch_remove(struct ksz_device *dev);
378 void ksz_init_mib_timer(struct ksz_device *dev);
379 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
380 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
381 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
382 bool ksz_get_gbit(struct ksz_device *dev, int port);
383 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
384 extern const struct ksz_chip_data ksz_switch_chips[];
386 /* Common register access functions */
387 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
389 return dev->regmap[KSZ_REGMAP_8];
392 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
394 return dev->regmap[KSZ_REGMAP_16];
397 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
399 return dev->regmap[KSZ_REGMAP_32];
402 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
405 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
408 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
415 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
418 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
421 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
428 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
431 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
434 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
441 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
446 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
448 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
451 *val = (u64)value[0] << 32 | value[1];
456 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
460 ret = regmap_write(ksz_regmap_8(dev), reg, value);
462 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
468 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
472 ret = regmap_write(ksz_regmap_16(dev), reg, value);
474 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
480 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
484 ret = regmap_write(ksz_regmap_32(dev), reg, value);
486 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
492 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
497 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
499 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
505 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
510 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
512 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
518 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
522 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
523 value = swab64(value);
524 val[0] = swab32(value & 0xffffffffULL);
525 val[1] = swab32(value >> 32ULL);
527 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
530 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
534 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
536 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
542 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
545 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
548 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
551 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
554 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
557 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
560 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
563 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
566 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
569 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
573 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
576 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
580 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
583 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
587 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
590 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
594 static inline void ksz_regmap_lock(void *__mtx)
596 struct mutex *mtx = __mtx;
600 static inline void ksz_regmap_unlock(void *__mtx)
602 struct mutex *mtx = __mtx;
606 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
608 return dev->chip_id == KSZ8795_CHIP_ID ||
609 dev->chip_id == KSZ8794_CHIP_ID ||
610 dev->chip_id == KSZ8765_CHIP_ID;
613 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
615 return dev->chip_id == KSZ8830_CHIP_ID;
618 static inline int is_lan937x(struct ksz_device *dev)
620 return dev->chip_id == LAN9370_CHIP_ID ||
621 dev->chip_id == LAN9371_CHIP_ID ||
622 dev->chip_id == LAN9372_CHIP_ID ||
623 dev->chip_id == LAN9373_CHIP_ID ||
624 dev->chip_id == LAN9374_CHIP_ID;
627 /* STP State Defines */
628 #define PORT_TX_ENABLE BIT(2)
629 #define PORT_RX_ENABLE BIT(1)
630 #define PORT_LEARN_DISABLE BIT(0)
632 /* Switch ID Defines */
633 #define REG_CHIP_ID0 0x00
635 #define SW_FAMILY_ID_M GENMASK(15, 8)
636 #define KSZ87_FAMILY_ID 0x87
637 #define KSZ88_FAMILY_ID 0x88
639 #define KSZ8_PORT_STATUS_0 0x08
640 #define KSZ8_PORT_FIBER_MODE BIT(7)
642 #define SW_CHIP_ID_M GENMASK(7, 4)
643 #define KSZ87_CHIP_ID_94 0x6
644 #define KSZ87_CHIP_ID_95 0x9
645 #define KSZ88_CHIP_ID_63 0x3
647 #define SW_REV_ID_M GENMASK(7, 4)
649 /* KSZ9893, KSZ9563, KSZ8563 specific register */
650 #define REG_CHIP_ID4 0x0f
651 #define SKU_ID_KSZ8563 0x3c
652 #define SKU_ID_KSZ9563 0x1c
654 /* Driver set switch broadcast storm protection at 10% rate. */
655 #define BROADCAST_STORM_PROT_RATE 10
657 /* 148,800 frames * 67 ms / 100 */
658 #define BROADCAST_STORM_VALUE 9969
660 #define BROADCAST_STORM_RATE_HI 0x07
661 #define BROADCAST_STORM_RATE_LO 0xFF
662 #define BROADCAST_STORM_RATE 0x07FF
664 #define MULTICAST_STORM_DISABLE BIT(6)
666 #define SW_START 0x01
668 /* xMII configuration */
669 #define P_MII_DUPLEX_M BIT(6)
670 #define P_MII_100MBIT_M BIT(4)
672 #define P_GMII_1GBIT_M BIT(6)
673 #define P_RGMII_ID_IG_ENABLE BIT(4)
674 #define P_RGMII_ID_EG_ENABLE BIT(3)
675 #define P_MII_MAC_MODE BIT(2)
676 #define P_MII_SEL_M 0x3
679 #define REG_SW_PORT_INT_STATUS__1 0x001B
680 #define REG_SW_PORT_INT_MASK__1 0x001F
682 #define REG_PORT_INT_STATUS 0x001B
683 #define REG_PORT_INT_MASK 0x001F
685 #define PORT_SRC_PHY_INT 1
686 #define PORT_SRC_PTP_INT 2
688 #define KSZ8795_HUGE_PACKET_SIZE 2000
689 #define KSZ8863_HUGE_PACKET_SIZE 1916
690 #define KSZ8863_NORMAL_PACKET_SIZE 1536
691 #define KSZ8_LEGAL_PACKET_SIZE 1518
692 #define KSZ9477_MAX_FRAME_SIZE 9000
694 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
695 /* Drive Strength of I/O Pad
698 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
700 #define KSZ8795_REG_SW_CTRL_20 0xa3
701 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d
702 #define SW_DRIVE_STRENGTH_M 0x7
703 #define SW_DRIVE_STRENGTH_2MA 0
704 #define SW_DRIVE_STRENGTH_4MA 1
705 #define SW_DRIVE_STRENGTH_8MA 2
706 #define SW_DRIVE_STRENGTH_12MA 3
707 #define SW_DRIVE_STRENGTH_16MA 4
708 #define SW_DRIVE_STRENGTH_20MA 5
709 #define SW_DRIVE_STRENGTH_24MA 6
710 #define SW_DRIVE_STRENGTH_28MA 7
711 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
712 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
714 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
715 #define KSZ9477_OUT_RATE_NO_LIMIT 0
717 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
719 #define KSZ9477_PORT_TC_MAP_S 4
720 #define KSZ9477_MAX_TC_PRIO 7
722 /* CBS related registers */
723 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
725 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
727 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
728 #define MTI_SCHEDULE_STRICT_PRIO 0
729 #define MTI_SCHEDULE_WRR 2
730 #define MTI_SHAPING_M GENMASK(5, 4)
731 #define MTI_SHAPING_OFF 0
732 #define MTI_SHAPING_SRP 1
733 #define MTI_SHAPING_TIME_AWARE 2
735 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
736 #define KSZ9477_DEFAULT_WRR_WEIGHT 1
738 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
739 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
741 /* Regmap tables generation */
742 #define KSZ_SPI_OP_RD 3
743 #define KSZ_SPI_OP_WR 2
745 #define swabnot_used(x) 0
747 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
748 swab##swp((opcode) << ((regbits) + (regpad)))
750 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
753 .val_bits = (width), \
755 .reg_bits = (regbits) + (regalign), \
756 .pad_bits = (regpad), \
757 .max_register = BIT(regbits) - 1, \
758 .cache_type = REGCACHE_NONE, \
760 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
763 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
765 .lock = ksz_regmap_lock, \
766 .unlock = ksz_regmap_unlock, \
767 .reg_format_endian = REGMAP_ENDIAN_BIG, \
768 .val_format_endian = REGMAP_ENDIAN_BIG \
771 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
772 static const struct regmap_config ksz##_regmap_config[] = { \
773 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
774 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
775 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \