1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
4 * Copyright (C) 2017-2019 Microchip Technology Inc.
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/regmap.h>
16 #include <linux/irq.h>
20 #define KSZ_MAX_NUM_PORTS 8
25 enum ksz_regmap_width {
37 struct mutex cnt_mutex; /* structure access */
40 struct rtnl_link_stats64 stats64;
41 struct ethtool_pause_stats pause_stats;
42 struct spinlock stats64_lock;
45 struct ksz_mib_names {
47 char string[ETH_GSTRING_LEN];
50 struct ksz_chip_data {
60 bool tc_cbs_supported;
61 bool tc_ets_supported;
62 const struct ksz_dev_ops *ops;
63 bool ksz87xx_eee_link_erratum;
64 const struct ksz_mib_names *mib_names;
73 int broadcast_ctrl_reg;
74 int multicast_ctrl_reg;
76 bool supports_mii[KSZ_MAX_NUM_PORTS];
77 bool supports_rmii[KSZ_MAX_NUM_PORTS];
78 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
79 bool internal_phy[KSZ_MAX_NUM_PORTS];
80 bool gbit_capable[KSZ_MAX_NUM_PORTS];
81 const struct regmap_access_table *wr_table;
82 const struct regmap_access_table *rd_table;
89 struct irq_domain *domain;
93 struct ksz_device *dev;
97 struct ksz_port *port;
104 struct ksz_switch_macaddr {
105 unsigned char addr[ETH_ALEN];
110 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
113 struct phy_device phydev;
115 u32 fiber:1; /* port is fiber */
117 u32 read:1; /* read MIB counters in background */
118 u32 freeze:1; /* MIB counter freeze is enabled */
120 struct ksz_port_mib mib;
121 phy_interface_t interface;
124 struct ksz_device *ksz_dev;
128 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
129 struct hwtstamp_config tstamp_config;
132 struct ksz_irq ptpirq;
133 struct ksz_ptp_irq ptpmsg_irq[3];
135 struct completion tstamp_msg_comp;
140 struct dsa_switch *ds;
141 struct ksz_platform_data *pdata;
142 const struct ksz_chip_data *info;
144 struct mutex dev_mutex; /* device access */
145 struct mutex regmap_mutex; /* regmap access */
146 struct mutex alu_mutex; /* ALU access */
147 struct mutex vlan_mutex; /* vlan access */
148 const struct ksz_dev_ops *dev_ops;
151 struct regmap *regmap[__KSZ_NUM_REGMAPS];
156 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
158 /* chip specific data */
161 int cpu_port; /* port connected to CPU */
163 phy_interface_t compat_interface;
165 bool synclko_disable;
167 struct vlan_table *vlan_cache;
169 struct ksz_port *ports;
170 struct delayed_work mib_read;
171 unsigned long mib_read_interval;
175 struct mutex lock_irq; /* IRQ Access */
177 struct ksz_ptp_data ptp_data;
179 struct ksz_switch_macaddr *switch_macaddr;
180 struct net_device *hsr_dev; /* HSR */
184 /* List of supported models */
205 KSZ8563_CHIP_ID = 0x8563,
206 KSZ8795_CHIP_ID = 0x8795,
207 KSZ8794_CHIP_ID = 0x8794,
208 KSZ8765_CHIP_ID = 0x8765,
209 KSZ8830_CHIP_ID = 0x8830,
210 KSZ9477_CHIP_ID = 0x00947700,
211 KSZ9896_CHIP_ID = 0x00989600,
212 KSZ9897_CHIP_ID = 0x00989700,
213 KSZ9893_CHIP_ID = 0x00989300,
214 KSZ9563_CHIP_ID = 0x00956300,
215 KSZ9567_CHIP_ID = 0x00956700,
216 LAN9370_CHIP_ID = 0x00937000,
217 LAN9371_CHIP_ID = 0x00937100,
218 LAN9372_CHIP_ID = 0x00937200,
219 LAN9373_CHIP_ID = 0x00937300,
220 LAN9374_CHIP_ID = 0x00937400,
248 PORT_802_1P_REMAPPING,
250 MIB_COUNTER_OVERFLOW,
253 VLAN_TABLE_MEMBERSHIP,
255 STATIC_MAC_TABLE_VALID,
256 STATIC_MAC_TABLE_USE_FID,
257 STATIC_MAC_TABLE_FID,
258 STATIC_MAC_TABLE_OVERRIDE,
259 STATIC_MAC_TABLE_FWD_PORTS,
260 DYNAMIC_MAC_TABLE_ENTRIES_H,
261 DYNAMIC_MAC_TABLE_MAC_EMPTY,
262 DYNAMIC_MAC_TABLE_NOT_READY,
263 DYNAMIC_MAC_TABLE_ENTRIES,
264 DYNAMIC_MAC_TABLE_FID,
265 DYNAMIC_MAC_TABLE_SRC_PORT,
266 DYNAMIC_MAC_TABLE_TIMESTAMP,
274 VLAN_TABLE_MEMBERSHIP_S,
276 STATIC_MAC_FWD_PORTS,
278 DYNAMIC_MAC_ENTRIES_H,
281 DYNAMIC_MAC_TIMESTAMP,
282 DYNAMIC_MAC_SRC_PORT,
286 enum ksz_xmii_ctrl0 {
293 enum ksz_xmii_ctrl1 {
322 int (*setup)(struct dsa_switch *ds);
323 void (*teardown)(struct dsa_switch *ds);
324 u32 (*get_port_addr)(int port, int offset);
325 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
326 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
327 void (*port_cleanup)(struct ksz_device *dev, int port);
328 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
329 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
330 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
331 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
332 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
334 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
335 u64 *dropped, u64 *cnt);
336 void (*r_mib_stat64)(struct ksz_device *dev, int port);
337 int (*vlan_filtering)(struct ksz_device *dev, int port,
338 bool flag, struct netlink_ext_ack *extack);
339 int (*vlan_add)(struct ksz_device *dev, int port,
340 const struct switchdev_obj_port_vlan *vlan,
341 struct netlink_ext_ack *extack);
342 int (*vlan_del)(struct ksz_device *dev, int port,
343 const struct switchdev_obj_port_vlan *vlan);
344 int (*mirror_add)(struct ksz_device *dev, int port,
345 struct dsa_mall_mirror_tc_entry *mirror,
346 bool ingress, struct netlink_ext_ack *extack);
347 void (*mirror_del)(struct ksz_device *dev, int port,
348 struct dsa_mall_mirror_tc_entry *mirror);
349 int (*fdb_add)(struct ksz_device *dev, int port,
350 const unsigned char *addr, u16 vid, struct dsa_db db);
351 int (*fdb_del)(struct ksz_device *dev, int port,
352 const unsigned char *addr, u16 vid, struct dsa_db db);
353 int (*fdb_dump)(struct ksz_device *dev, int port,
354 dsa_fdb_dump_cb_t *cb, void *data);
355 int (*mdb_add)(struct ksz_device *dev, int port,
356 const struct switchdev_obj_port_mdb *mdb,
358 int (*mdb_del)(struct ksz_device *dev, int port,
359 const struct switchdev_obj_port_mdb *mdb,
361 void (*get_caps)(struct ksz_device *dev, int port,
362 struct phylink_config *config);
363 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
364 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
365 void (*port_init_cnt)(struct ksz_device *dev, int port);
366 void (*phylink_mac_config)(struct ksz_device *dev, int port,
368 const struct phylink_link_state *state);
369 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
371 phy_interface_t interface,
372 struct phy_device *phydev, int speed,
373 int duplex, bool tx_pause, bool rx_pause);
374 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
375 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
376 void (*config_cpu_port)(struct dsa_switch *ds);
377 int (*enable_stp_addr)(struct ksz_device *dev);
378 int (*reset)(struct ksz_device *dev);
379 int (*init)(struct ksz_device *dev);
380 void (*exit)(struct ksz_device *dev);
383 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
384 int ksz_switch_register(struct ksz_device *dev);
385 void ksz_switch_remove(struct ksz_device *dev);
387 void ksz_init_mib_timer(struct ksz_device *dev);
388 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
389 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
390 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
391 bool ksz_get_gbit(struct ksz_device *dev, int port);
392 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
393 extern const struct ksz_chip_data ksz_switch_chips[];
395 /* Common register access functions */
396 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
398 return dev->regmap[KSZ_REGMAP_8];
401 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
403 return dev->regmap[KSZ_REGMAP_16];
406 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
408 return dev->regmap[KSZ_REGMAP_32];
411 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
414 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
417 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
424 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
427 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
430 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
437 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
440 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
443 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
450 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
455 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
457 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
460 *val = (u64)value[0] << 32 | value[1];
465 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
469 ret = regmap_write(ksz_regmap_8(dev), reg, value);
471 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
477 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
481 ret = regmap_write(ksz_regmap_16(dev), reg, value);
483 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
489 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
493 ret = regmap_write(ksz_regmap_32(dev), reg, value);
495 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
501 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
506 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
508 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
514 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
519 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
521 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
527 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
531 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
532 value = swab64(value);
533 val[0] = swab32(value & 0xffffffffULL);
534 val[1] = swab32(value >> 32ULL);
536 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
539 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
543 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
545 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
551 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
554 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
557 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
560 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
563 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
566 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
569 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
572 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
575 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
578 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
582 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
585 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
589 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
592 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
596 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
599 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
603 static inline void ksz_regmap_lock(void *__mtx)
605 struct mutex *mtx = __mtx;
609 static inline void ksz_regmap_unlock(void *__mtx)
611 struct mutex *mtx = __mtx;
615 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
617 return dev->chip_id == KSZ8795_CHIP_ID ||
618 dev->chip_id == KSZ8794_CHIP_ID ||
619 dev->chip_id == KSZ8765_CHIP_ID;
622 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
624 return dev->chip_id == KSZ8830_CHIP_ID;
627 static inline int is_lan937x(struct ksz_device *dev)
629 return dev->chip_id == LAN9370_CHIP_ID ||
630 dev->chip_id == LAN9371_CHIP_ID ||
631 dev->chip_id == LAN9372_CHIP_ID ||
632 dev->chip_id == LAN9373_CHIP_ID ||
633 dev->chip_id == LAN9374_CHIP_ID;
636 /* STP State Defines */
637 #define PORT_TX_ENABLE BIT(2)
638 #define PORT_RX_ENABLE BIT(1)
639 #define PORT_LEARN_DISABLE BIT(0)
641 /* Switch ID Defines */
642 #define REG_CHIP_ID0 0x00
644 #define SW_FAMILY_ID_M GENMASK(15, 8)
645 #define KSZ87_FAMILY_ID 0x87
646 #define KSZ88_FAMILY_ID 0x88
648 #define KSZ8_PORT_STATUS_0 0x08
649 #define KSZ8_PORT_FIBER_MODE BIT(7)
651 #define SW_CHIP_ID_M GENMASK(7, 4)
652 #define KSZ87_CHIP_ID_94 0x6
653 #define KSZ87_CHIP_ID_95 0x9
654 #define KSZ88_CHIP_ID_63 0x3
656 #define SW_REV_ID_M GENMASK(7, 4)
658 /* KSZ9893, KSZ9563, KSZ8563 specific register */
659 #define REG_CHIP_ID4 0x0f
660 #define SKU_ID_KSZ8563 0x3c
661 #define SKU_ID_KSZ9563 0x1c
663 /* Driver set switch broadcast storm protection at 10% rate. */
664 #define BROADCAST_STORM_PROT_RATE 10
666 /* 148,800 frames * 67 ms / 100 */
667 #define BROADCAST_STORM_VALUE 9969
669 #define BROADCAST_STORM_RATE_HI 0x07
670 #define BROADCAST_STORM_RATE_LO 0xFF
671 #define BROADCAST_STORM_RATE 0x07FF
673 #define MULTICAST_STORM_DISABLE BIT(6)
675 #define SW_START 0x01
677 /* xMII configuration */
678 #define P_MII_DUPLEX_M BIT(6)
679 #define P_MII_100MBIT_M BIT(4)
681 #define P_GMII_1GBIT_M BIT(6)
682 #define P_RGMII_ID_IG_ENABLE BIT(4)
683 #define P_RGMII_ID_EG_ENABLE BIT(3)
684 #define P_MII_MAC_MODE BIT(2)
685 #define P_MII_SEL_M 0x3
688 #define REG_SW_PORT_INT_STATUS__1 0x001B
689 #define REG_SW_PORT_INT_MASK__1 0x001F
691 #define REG_PORT_INT_STATUS 0x001B
692 #define REG_PORT_INT_MASK 0x001F
694 #define PORT_SRC_PHY_INT 1
695 #define PORT_SRC_PTP_INT 2
697 #define KSZ8795_HUGE_PACKET_SIZE 2000
698 #define KSZ8863_HUGE_PACKET_SIZE 1916
699 #define KSZ8863_NORMAL_PACKET_SIZE 1536
700 #define KSZ8_LEGAL_PACKET_SIZE 1518
701 #define KSZ9477_MAX_FRAME_SIZE 9000
703 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
704 /* Drive Strength of I/O Pad
707 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
709 #define KSZ8795_REG_SW_CTRL_20 0xa3
710 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d
711 #define SW_DRIVE_STRENGTH_M 0x7
712 #define SW_DRIVE_STRENGTH_2MA 0
713 #define SW_DRIVE_STRENGTH_4MA 1
714 #define SW_DRIVE_STRENGTH_8MA 2
715 #define SW_DRIVE_STRENGTH_12MA 3
716 #define SW_DRIVE_STRENGTH_16MA 4
717 #define SW_DRIVE_STRENGTH_20MA 5
718 #define SW_DRIVE_STRENGTH_24MA 6
719 #define SW_DRIVE_STRENGTH_28MA 7
720 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
721 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
723 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
724 #define KSZ9477_OUT_RATE_NO_LIMIT 0
726 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
728 #define KSZ9477_PORT_TC_MAP_S 4
729 #define KSZ9477_MAX_TC_PRIO 7
731 /* CBS related registers */
732 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
734 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
736 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
737 #define MTI_SCHEDULE_STRICT_PRIO 0
738 #define MTI_SCHEDULE_WRR 2
739 #define MTI_SHAPING_M GENMASK(5, 4)
740 #define MTI_SHAPING_OFF 0
741 #define MTI_SHAPING_SRP 1
742 #define MTI_SHAPING_TIME_AWARE 2
744 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
745 #define KSZ9477_DEFAULT_WRR_WEIGHT 1
747 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
748 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
750 /* Regmap tables generation */
751 #define KSZ_SPI_OP_RD 3
752 #define KSZ_SPI_OP_WR 2
754 #define swabnot_used(x) 0
756 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
757 swab##swp((opcode) << ((regbits) + (regpad)))
759 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
762 .val_bits = (width), \
764 .reg_bits = (regbits) + (regalign), \
765 .pad_bits = (regpad), \
766 .max_register = BIT(regbits) - 1, \
767 .cache_type = REGCACHE_NONE, \
769 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
772 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
774 .lock = ksz_regmap_lock, \
775 .unlock = ksz_regmap_unlock, \
776 .reg_format_endian = REGMAP_ENDIAN_BIG, \
777 .val_format_endian = REGMAP_ENDIAN_BIG \
780 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
781 static const struct regmap_config ksz##_regmap_config[] = { \
782 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
783 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
784 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \