drivers/net/dsa/microchip/ksz9477.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip KSZ9477 switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/platform_data/microchip-ksz.h>
  12 #include <linux/phy.h>
  13 #include <linux/if_bridge.h>
  14 #include <net/dsa.h>
  15 #include <net/switchdev.h>
  16
  17 #include "ksz9477_reg.h"
  18 #include "ksz_common.h"
  19
  20 /* Used with variable features to indicate capabilities. */
  21 #define GBIT_SUPPORT                    BIT(0)
  22 #define NEW_XMII                        BIT(1)
  23 #define IS_9893                         BIT(2)
  24
  25 static const struct {
  26         int index;
  27         char string[ETH_GSTRING_LEN];
  28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
  29         { 0x00, "rx_hi" },
  30         { 0x01, "rx_undersize" },
  31         { 0x02, "rx_fragments" },
  32         { 0x03, "rx_oversize" },
  33         { 0x04, "rx_jabbers" },
  34         { 0x05, "rx_symbol_err" },
  35         { 0x06, "rx_crc_err" },
  36         { 0x07, "rx_align_err" },
  37         { 0x08, "rx_mac_ctrl" },
  38         { 0x09, "rx_pause" },
  39         { 0x0A, "rx_bcast" },
  40         { 0x0B, "rx_mcast" },
  41         { 0x0C, "rx_ucast" },
  42         { 0x0D, "rx_64_or_less" },
  43         { 0x0E, "rx_65_127" },
  44         { 0x0F, "rx_128_255" },
  45         { 0x10, "rx_256_511" },
  46         { 0x11, "rx_512_1023" },
  47         { 0x12, "rx_1024_1522" },
  48         { 0x13, "rx_1523_2000" },
  49         { 0x14, "rx_2001" },
  50         { 0x15, "tx_hi" },
  51         { 0x16, "tx_late_col" },
  52         { 0x17, "tx_pause" },
  53         { 0x18, "tx_bcast" },
  54         { 0x19, "tx_mcast" },
  55         { 0x1A, "tx_ucast" },
  56         { 0x1B, "tx_deferred" },
  57         { 0x1C, "tx_total_col" },
  58         { 0x1D, "tx_exc_col" },
  59         { 0x1E, "tx_single_col" },
  60         { 0x1F, "tx_mult_col" },
  61         { 0x80, "rx_total" },
  62         { 0x81, "tx_total" },
  63         { 0x82, "rx_discards" },
  64         { 0x83, "tx_discards" },
  65 };
  66
  67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
  68 {
  69         regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
  70 }
  71
  72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
  73                          bool set)
  74 {
  75         regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
  76                            bits, set ? bits : 0);
  77 }
  78
  79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
  80 {
  81         regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
  82 }
  83
  84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
  85                                u32 bits, bool set)
  86 {
  87         regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
  88                            bits, set ? bits : 0);
  89 }
  90
  91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
  92 {
  93         unsigned int val;
  94
  95         return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
  96                                         val, !(val & VLAN_START), 10, 1000);
  97 }
  98
  99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
 100                                   u32 *vlan_table)
 101 {
 102         int ret;
 103
 104         mutex_lock(&dev->vlan_mutex);
 105
 106         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 107         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
 108
 109         /* wait to be cleared */
 110         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 111         if (ret) {
 112                 dev_dbg(dev->dev, "Failed to read vlan table\n");
 113                 goto exit;
 114         }
 115
 116         ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
 117         ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
 118         ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
 119
 120         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 121
 122 exit:
 123         mutex_unlock(&dev->vlan_mutex);
 124
 125         return ret;
 126 }
 127
 128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
 129                                   u32 *vlan_table)
 130 {
 131         int ret;
 132
 133         mutex_lock(&dev->vlan_mutex);
 134
 135         ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
 136         ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
 137         ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
 138
 139         ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
 140         ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
 141
 142         /* wait to be cleared */
 143         ret = ksz9477_wait_vlan_ctrl_ready(dev);
 144         if (ret) {
 145                 dev_dbg(dev->dev, "Failed to write vlan table\n");
 146                 goto exit;
 147         }
 148
 149         ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
 150
 151         /* update vlan cache table */
 152         dev->vlan_cache[vid].table[0] = vlan_table[0];
 153         dev->vlan_cache[vid].table[1] = vlan_table[1];
 154         dev->vlan_cache[vid].table[2] = vlan_table[2];
 155
 156 exit:
 157         mutex_unlock(&dev->vlan_mutex);
 158
 159         return ret;
 160 }
 161
 162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
 163 {
 164         ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
 165         ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
 166         ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
 167         ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
 168 }
 169
 170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
 171 {
 172         ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
 173         ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
 174         ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
 175         ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
 176 }
 177
 178 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
 179 {
 180         unsigned int val;
 181
 182         return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
 183                                         val, !(val & ALU_START), 10, 1000);
 184 }
 185
 186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
 187 {
 188         unsigned int val;
 189
 190         return regmap_read_poll_timeout(dev->regmap[2],
 191                                         REG_SW_ALU_STAT_CTRL__4,
 192                                         val, !(val & ALU_STAT_START),
 193                                         10, 1000);
 194 }
 195
 196 static int ksz9477_reset_switch(struct ksz_device *dev)
 197 {
 198         u8 data8;
 199         u32 data32;
 200
 201         /* reset switch */
 202         ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
 203
 204         /* turn off SPI DO Edge select */
 205         regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
 206                            SPI_AUTO_EDGE_DETECTION, 0);
 207
 208         /* default configuration */
 209         ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
 210         data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
 211               SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
 212         ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
 213
 214         /* disable interrupts */
 215         ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
 216         ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
 217         ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
 218
 219         /* set broadcast storm protection 10% rate */
 220         regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
 221                            BROADCAST_STORM_RATE,
 222                            (BROADCAST_STORM_VALUE *
 223                            BROADCAST_STORM_PROT_RATE) / 100);
 224
 225         if (dev->synclko_125)
 226                 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
 227                            SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
 228
 229         return 0;
 230 }
 231
 232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
 233                               u64 *cnt)
 234 {
 235         struct ksz_port *p = &dev->ports[port];
 236         unsigned int val;
 237         u32 data;
 238         int ret;
 239
 240         /* retain the flush/freeze bit */
 241         data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 242         data |= MIB_COUNTER_READ;
 243         data |= (addr << MIB_COUNTER_INDEX_S);
 244         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
 245
 246         ret = regmap_read_poll_timeout(dev->regmap[2],
 247                         PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
 248                         val, !(val & MIB_COUNTER_READ), 10, 1000);
 249         /* failed to read MIB. get out of loop */
 250         if (ret) {
 251                 dev_dbg(dev->dev, "Failed to get MIB\n");
 252                 return;
 253         }
 254
 255         /* count resets upon read */
 256         ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
 257         *cnt += data;
 258 }
 259
 260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
 261                               u64 *dropped, u64 *cnt)
 262 {
 263         addr = ksz9477_mib_names[addr].index;
 264         ksz9477_r_mib_cnt(dev, port, addr, cnt);
 265 }
 266
 267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
 268 {
 269         u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
 270         struct ksz_port *p = &dev->ports[port];
 271
 272         /* enable/disable the port for flush/freeze function */
 273         mutex_lock(&p->mib.cnt_mutex);
 274         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
 275
 276         /* used by MIB counter reading code to know freeze is enabled */
 277         p->freeze = freeze;
 278         mutex_unlock(&p->mib.cnt_mutex);
 279 }
 280
 281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
 282 {
 283         struct ksz_port_mib *mib = &dev->ports[port].mib;
 284
 285         /* flush all enabled port MIB counters */
 286         mutex_lock(&mib->cnt_mutex);
 287         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
 288                      MIB_COUNTER_FLUSH_FREEZE);
 289         ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
 290         ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
 291         mutex_unlock(&mib->cnt_mutex);
 292
 293         mib->cnt_ptr = 0;
 294         memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
 295 }
 296
 297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
 298                                                       int port,
 299                                                       enum dsa_tag_protocol mp)
 300 {
 301         enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
 302         struct ksz_device *dev = ds->priv;
 303
 304         if (dev->features & IS_9893)
 305                 proto = DSA_TAG_PROTO_KSZ9893;
 306         return proto;
 307 }
 308
 309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
 310 {
 311         struct ksz_device *dev = ds->priv;
 312         u16 val = 0xffff;
 313
 314         /* No real PHY after this. Simulate the PHY.
 315          * A fixed PHY can be setup in the device tree, but this function is
 316          * still called for that port during initialization.
 317          * For RGMII PHY there is no way to access it so the fixed PHY should
 318          * be used.  For SGMII PHY the supporting code will be added later.
 319          */
 320         if (addr >= dev->phy_port_cnt) {
 321                 struct ksz_port *p = &dev->ports[addr];
 322
 323                 switch (reg) {
 324                 case MII_BMCR:
 325                         val = 0x1140;
 326                         break;
 327                 case MII_BMSR:
 328                         val = 0x796d;
 329                         break;
 330                 case MII_PHYSID1:
 331                         val = 0x0022;
 332                         break;
 333                 case MII_PHYSID2:
 334                         val = 0x1631;
 335                         break;
 336                 case MII_ADVERTISE:
 337                         val = 0x05e1;
 338                         break;
 339                 case MII_LPA:
 340                         val = 0xc5e1;
 341                         break;
 342                 case MII_CTRL1000:
 343                         val = 0x0700;
 344                         break;
 345                 case MII_STAT1000:
 346                         if (p->phydev.speed == SPEED_1000)
 347                                 val = 0x3800;
 348                         else
 349                                 val = 0;
 350                         break;
 351                 }
 352         } else {
 353                 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
 354         }
 355
 356         return val;
 357 }
 358
 359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
 360                                u16 val)
 361 {
 362         struct ksz_device *dev = ds->priv;
 363
 364         /* No real PHY after this. */
 365         if (addr >= dev->phy_port_cnt)
 366                 return 0;
 367
 368         /* No gigabit support.  Do not write to this register. */
 369         if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
 370                 return 0;
 371         ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
 372
 373         return 0;
 374 }
 375
 376 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
 377                                 u32 stringset, uint8_t *buf)
 378 {
 379         int i;
 380
 381         if (stringset != ETH_SS_STATS)
 382                 return;
 383
 384         for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
 385                 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
 386                        ETH_GSTRING_LEN);
 387         }
 388 }
 389
 390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
 391                                     u8 member)
 392 {
 393         ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
 394         dev->ports[port].member = member;
 395 }
 396
 397 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
 398                                        u8 state)
 399 {
 400         struct ksz_device *dev = ds->priv;
 401         struct ksz_port *p = &dev->ports[port];
 402         u8 data;
 403         int member = -1;
 404         int forward = dev->member;
 405
 406         ksz_pread8(dev, port, P_STP_CTRL, &data);
 407         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 408
 409         switch (state) {
 410         case BR_STATE_DISABLED:
 411                 data |= PORT_LEARN_DISABLE;
 412                 if (port != dev->cpu_port)
 413                         member = 0;
 414                 break;
 415         case BR_STATE_LISTENING:
 416                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
 417                 if (port != dev->cpu_port &&
 418                     p->stp_state == BR_STATE_DISABLED)
 419                         member = dev->host_mask | p->vid_member;
 420                 break;
 421         case BR_STATE_LEARNING:
 422                 data |= PORT_RX_ENABLE;
 423                 break;
 424         case BR_STATE_FORWARDING:
 425                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
 426
 427                 /* This function is also used internally. */
 428                 if (port == dev->cpu_port)
 429                         break;
 430
 431                 member = dev->host_mask | p->vid_member;
 432                 mutex_lock(&dev->dev_mutex);
 433
 434                 /* Port is a member of a bridge. */
 435                 if (dev->br_member & (1 << port)) {
 436                         dev->member |= (1 << port);
 437                         member = dev->member;
 438                 }
 439                 mutex_unlock(&dev->dev_mutex);
 440                 break;
 441         case BR_STATE_BLOCKING:
 442                 data |= PORT_LEARN_DISABLE;
 443                 if (port != dev->cpu_port &&
 444                     p->stp_state == BR_STATE_DISABLED)
 445                         member = dev->host_mask | p->vid_member;
 446                 break;
 447         default:
 448                 dev_err(ds->dev, "invalid STP state: %d\n", state);
 449                 return;
 450         }
 451
 452         ksz_pwrite8(dev, port, P_STP_CTRL, data);
 453         p->stp_state = state;
 454         mutex_lock(&dev->dev_mutex);
 455         /* Port membership may share register with STP state. */
 456         if (member >= 0 && member != p->member)
 457                 ksz9477_cfg_port_member(dev, port, (u8)member);
 458
 459         /* Check if forwarding needs to be updated. */
 460         if (state != BR_STATE_FORWARDING) {
 461                 if (dev->br_member & (1 << port))
 462                         dev->member &= ~(1 << port);
 463         }
 464
 465         /* When topology has changed the function ksz_update_port_member
 466          * should be called to modify port forwarding behavior.
 467          */
 468         if (forward != dev->member)
 469                 ksz_update_port_member(dev, port);
 470         mutex_unlock(&dev->dev_mutex);
 471 }
 472
 473 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
 474 {
 475         u8 data;
 476
 477         regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
 478                            SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
 479                            SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
 480
 481         if (port < dev->mib_port_cnt) {
 482                 /* flush individual port */
 483                 ksz_pread8(dev, port, P_STP_CTRL, &data);
 484                 if (!(data & PORT_LEARN_DISABLE))
 485                         ksz_pwrite8(dev, port, P_STP_CTRL,
 486                                     data | PORT_LEARN_DISABLE);
 487                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
 488                 ksz_pwrite8(dev, port, P_STP_CTRL, data);
 489         } else {
 490                 /* flush all */
 491                 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
 492         }
 493 }
 494
 495 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
 496                                        bool flag)
 497 {
 498         struct ksz_device *dev = ds->priv;
 499
 500         if (flag) {
 501                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 502                              PORT_VLAN_LOOKUP_VID_0, true);
 503                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
 504         } else {
 505                 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
 506                 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
 507                              PORT_VLAN_LOOKUP_VID_0, false);
 508         }
 509
 510         return 0;
 511 }
 512
 513 static void ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
 514                                   const struct switchdev_obj_port_vlan *vlan)
 515 {
 516         struct ksz_device *dev = ds->priv;
 517         u32 vlan_table[3];
 518         u16 vid;
 519         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 520
 521         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 522                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 523                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 524                         return;
 525                 }
 526
 527                 vlan_table[0] = VLAN_VALID | (vid & VLAN_FID_M);
 528                 if (untagged)
 529                         vlan_table[1] |= BIT(port);
 530                 else
 531                         vlan_table[1] &= ~BIT(port);
 532                 vlan_table[1] &= ~(BIT(dev->cpu_port));
 533
 534                 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
 535
 536                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 537                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 538                         return;
 539                 }
 540
 541                 /* change PVID */
 542                 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
 543                         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vid);
 544         }
 545 }
 546
 547 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
 548                                  const struct switchdev_obj_port_vlan *vlan)
 549 {
 550         struct ksz_device *dev = ds->priv;
 551         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
 552         u32 vlan_table[3];
 553         u16 vid;
 554         u16 pvid;
 555
 556         ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
 557         pvid = pvid & 0xFFF;
 558
 559         for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
 560                 if (ksz9477_get_vlan_table(dev, vid, vlan_table)) {
 561                         dev_dbg(dev->dev, "Failed to get vlan table\n");
 562                         return -ETIMEDOUT;
 563                 }
 564
 565                 vlan_table[2] &= ~BIT(port);
 566
 567                 if (pvid == vid)
 568                         pvid = 1;
 569
 570                 if (untagged)
 571                         vlan_table[1] &= ~BIT(port);
 572
 573                 if (ksz9477_set_vlan_table(dev, vid, vlan_table)) {
 574                         dev_dbg(dev->dev, "Failed to set vlan table\n");
 575                         return -ETIMEDOUT;
 576                 }
 577         }
 578
 579         ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
 580
 581         return 0;
 582 }
 583
 584 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
 585                                 const unsigned char *addr, u16 vid)
 586 {
 587         struct ksz_device *dev = ds->priv;
 588         u32 alu_table[4];
 589         u32 data;
 590         int ret = 0;
 591
 592         mutex_lock(&dev->alu_mutex);
 593
 594         /* find any entry with mac & vid */
 595         data = vid << ALU_FID_INDEX_S;
 596         data |= ((addr[0] << 8) | addr[1]);
 597         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 598
 599         data = ((addr[2] << 24) | (addr[3] << 16));
 600         data |= ((addr[4] << 8) | addr[5]);
 601         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 602
 603         /* start read operation */
 604         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 605
 606         /* wait to be finished */
 607         ret = ksz9477_wait_alu_ready(dev);
 608         if (ret) {
 609                 dev_dbg(dev->dev, "Failed to read ALU\n");
 610                 goto exit;
 611         }
 612
 613         /* read ALU entry */
 614         ksz9477_read_table(dev, alu_table);
 615
 616         /* update ALU entry */
 617         alu_table[0] = ALU_V_STATIC_VALID;
 618         alu_table[1] |= BIT(port);
 619         if (vid)
 620                 alu_table[1] |= ALU_V_USE_FID;
 621         alu_table[2] = (vid << ALU_V_FID_S);
 622         alu_table[2] |= ((addr[0] << 8) | addr[1]);
 623         alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
 624         alu_table[3] |= ((addr[4] << 8) | addr[5]);
 625
 626         ksz9477_write_table(dev, alu_table);
 627
 628         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 629
 630         /* wait to be finished */
 631         ret = ksz9477_wait_alu_ready(dev);
 632         if (ret)
 633                 dev_dbg(dev->dev, "Failed to write ALU\n");
 634
 635 exit:
 636         mutex_unlock(&dev->alu_mutex);
 637
 638         return ret;
 639 }
 640
 641 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
 642                                 const unsigned char *addr, u16 vid)
 643 {
 644         struct ksz_device *dev = ds->priv;
 645         u32 alu_table[4];
 646         u32 data;
 647         int ret = 0;
 648
 649         mutex_lock(&dev->alu_mutex);
 650
 651         /* read any entry with mac & vid */
 652         data = vid << ALU_FID_INDEX_S;
 653         data |= ((addr[0] << 8) | addr[1]);
 654         ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
 655
 656         data = ((addr[2] << 24) | (addr[3] << 16));
 657         data |= ((addr[4] << 8) | addr[5]);
 658         ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
 659
 660         /* start read operation */
 661         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
 662
 663         /* wait to be finished */
 664         ret = ksz9477_wait_alu_ready(dev);
 665         if (ret) {
 666                 dev_dbg(dev->dev, "Failed to read ALU\n");
 667                 goto exit;
 668         }
 669
 670         ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
 671         if (alu_table[0] & ALU_V_STATIC_VALID) {
 672                 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
 673                 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
 674                 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
 675
 676                 /* clear forwarding port */
 677                 alu_table[2] &= ~BIT(port);
 678
 679                 /* if there is no port to forward, clear table */
 680                 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
 681                         alu_table[0] = 0;
 682                         alu_table[1] = 0;
 683                         alu_table[2] = 0;
 684                         alu_table[3] = 0;
 685                 }
 686         } else {
 687                 alu_table[0] = 0;
 688                 alu_table[1] = 0;
 689                 alu_table[2] = 0;
 690                 alu_table[3] = 0;
 691         }
 692
 693         ksz9477_write_table(dev, alu_table);
 694
 695         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
 696
 697         /* wait to be finished */
 698         ret = ksz9477_wait_alu_ready(dev);
 699         if (ret)
 700                 dev_dbg(dev->dev, "Failed to write ALU\n");
 701
 702 exit:
 703         mutex_unlock(&dev->alu_mutex);
 704
 705         return ret;
 706 }
 707
 708 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
 709 {
 710         alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
 711         alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
 712         alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
 713         alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
 714                         ALU_V_PRIO_AGE_CNT_M;
 715         alu->mstp = alu_table[0] & ALU_V_MSTP_M;
 716
 717         alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
 718         alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
 719         alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
 720
 721         alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
 722
 723         alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
 724         alu->mac[1] = alu_table[2] & 0xFF;
 725         alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
 726         alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
 727         alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
 728         alu->mac[5] = alu_table[3] & 0xFF;
 729 }
 730
 731 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
 732                                  dsa_fdb_dump_cb_t *cb, void *data)
 733 {
 734         struct ksz_device *dev = ds->priv;
 735         int ret = 0;
 736         u32 ksz_data;
 737         u32 alu_table[4];
 738         struct alu_struct alu;
 739         int timeout;
 740
 741         mutex_lock(&dev->alu_mutex);
 742
 743         /* start ALU search */
 744         ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
 745
 746         do {
 747                 timeout = 1000;
 748                 do {
 749                         ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
 750                         if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
 751                                 break;
 752                         usleep_range(1, 10);
 753                 } while (timeout-- > 0);
 754
 755                 if (!timeout) {
 756                         dev_dbg(dev->dev, "Failed to search ALU\n");
 757                         ret = -ETIMEDOUT;
 758                         goto exit;
 759                 }
 760
 761                 /* read ALU table */
 762                 ksz9477_read_table(dev, alu_table);
 763
 764                 ksz9477_convert_alu(&alu, alu_table);
 765
 766                 if (alu.port_forward & BIT(port)) {
 767                         ret = cb(alu.mac, alu.fid, alu.is_static, data);
 768                         if (ret)
 769                                 goto exit;
 770                 }
 771         } while (ksz_data & ALU_START);
 772
 773 exit:
 774
 775         /* stop ALU search */
 776         ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
 777
 778         mutex_unlock(&dev->alu_mutex);
 779
 780         return ret;
 781 }
 782
 783 static void ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
 784                                  const struct switchdev_obj_port_mdb *mdb)
 785 {
 786         struct ksz_device *dev = ds->priv;
 787         u32 static_table[4];
 788         u32 data;
 789         int index;
 790         u32 mac_hi, mac_lo;
 791
 792         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 793         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 794         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 795
 796         mutex_lock(&dev->alu_mutex);
 797
 798         for (index = 0; index < dev->num_statics; index++) {
 799                 /* find empty slot first */
 800                 data = (index << ALU_STAT_INDEX_S) |
 801                         ALU_STAT_READ | ALU_STAT_START;
 802                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 803
 804                 /* wait to be finished */
 805                 if (ksz9477_wait_alu_sta_ready(dev)) {
 806                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 807                         goto exit;
 808                 }
 809
 810                 /* read ALU static table */
 811                 ksz9477_read_table(dev, static_table);
 812
 813                 if (static_table[0] & ALU_V_STATIC_VALID) {
 814                         /* check this has same vid & mac address */
 815                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 816                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 817                             static_table[3] == mac_lo) {
 818                                 /* found matching one */
 819                                 break;
 820                         }
 821                 } else {
 822                         /* found empty one */
 823                         break;
 824                 }
 825         }
 826
 827         /* no available entry */
 828         if (index == dev->num_statics)
 829                 goto exit;
 830
 831         /* add entry */
 832         static_table[0] = ALU_V_STATIC_VALID;
 833         static_table[1] |= BIT(port);
 834         if (mdb->vid)
 835                 static_table[1] |= ALU_V_USE_FID;
 836         static_table[2] = (mdb->vid << ALU_V_FID_S);
 837         static_table[2] |= mac_hi;
 838         static_table[3] = mac_lo;
 839
 840         ksz9477_write_table(dev, static_table);
 841
 842         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 843         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 844
 845         /* wait to be finished */
 846         if (ksz9477_wait_alu_sta_ready(dev))
 847                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 848
 849 exit:
 850         mutex_unlock(&dev->alu_mutex);
 851 }
 852
 853 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
 854                                 const struct switchdev_obj_port_mdb *mdb)
 855 {
 856         struct ksz_device *dev = ds->priv;
 857         u32 static_table[4];
 858         u32 data;
 859         int index;
 860         int ret = 0;
 861         u32 mac_hi, mac_lo;
 862
 863         mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
 864         mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
 865         mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
 866
 867         mutex_lock(&dev->alu_mutex);
 868
 869         for (index = 0; index < dev->num_statics; index++) {
 870                 /* find empty slot first */
 871                 data = (index << ALU_STAT_INDEX_S) |
 872                         ALU_STAT_READ | ALU_STAT_START;
 873                 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 874
 875                 /* wait to be finished */
 876                 ret = ksz9477_wait_alu_sta_ready(dev);
 877                 if (ret) {
 878                         dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 879                         goto exit;
 880                 }
 881
 882                 /* read ALU static table */
 883                 ksz9477_read_table(dev, static_table);
 884
 885                 if (static_table[0] & ALU_V_STATIC_VALID) {
 886                         /* check this has same vid & mac address */
 887
 888                         if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
 889                             ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
 890                             static_table[3] == mac_lo) {
 891                                 /* found matching one */
 892                                 break;
 893                         }
 894                 }
 895         }
 896
 897         /* no available entry */
 898         if (index == dev->num_statics)
 899                 goto exit;
 900
 901         /* clear port */
 902         static_table[1] &= ~BIT(port);
 903
 904         if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
 905                 /* delete entry */
 906                 static_table[0] = 0;
 907                 static_table[1] = 0;
 908                 static_table[2] = 0;
 909                 static_table[3] = 0;
 910         }
 911
 912         ksz9477_write_table(dev, static_table);
 913
 914         data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
 915         ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
 916
 917         /* wait to be finished */
 918         ret = ksz9477_wait_alu_sta_ready(dev);
 919         if (ret)
 920                 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
 921
 922 exit:
 923         mutex_unlock(&dev->alu_mutex);
 924
 925         return ret;
 926 }
 927
 928 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
 929                                    struct dsa_mall_mirror_tc_entry *mirror,
 930                                    bool ingress)
 931 {
 932         struct ksz_device *dev = ds->priv;
 933
 934         if (ingress)
 935                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
 936         else
 937                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
 938
 939         ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
 940
 941         /* configure mirror port */
 942         ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 943                      PORT_MIRROR_SNIFFER, true);
 944
 945         ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
 946
 947         return 0;
 948 }
 949
 950 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
 951                                     struct dsa_mall_mirror_tc_entry *mirror)
 952 {
 953         struct ksz_device *dev = ds->priv;
 954         u8 data;
 955
 956         if (mirror->ingress)
 957                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
 958         else
 959                 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
 960
 961         ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
 962
 963         if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
 964                 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
 965                              PORT_MIRROR_SNIFFER, false);
 966 }
 967
 968 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
 969 {
 970         bool gbit;
 971
 972         if (dev->features & NEW_XMII)
 973                 gbit = !(data & PORT_MII_NOT_1GBIT);
 974         else
 975                 gbit = !!(data & PORT_MII_1000MBIT_S1);
 976         return gbit;
 977 }
 978
 979 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
 980 {
 981         if (dev->features & NEW_XMII) {
 982                 if (gbit)
 983                         *data &= ~PORT_MII_NOT_1GBIT;
 984                 else
 985                         *data |= PORT_MII_NOT_1GBIT;
 986         } else {
 987                 if (gbit)
 988                         *data |= PORT_MII_1000MBIT_S1;
 989                 else
 990                         *data &= ~PORT_MII_1000MBIT_S1;
 991         }
 992 }
 993
 994 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
 995 {
 996         int mode;
 997
 998         if (dev->features & NEW_XMII) {
 999                 switch (data & PORT_MII_SEL_M) {
1000                 case PORT_MII_SEL:
1001                         mode = 0;
1002                         break;
1003                 case PORT_RMII_SEL:
1004                         mode = 1;
1005                         break;
1006                 case PORT_GMII_SEL:
1007                         mode = 2;
1008                         break;
1009                 default:
1010                         mode = 3;
1011                 }
1012         } else {
1013                 switch (data & PORT_MII_SEL_M) {
1014                 case PORT_MII_SEL_S1:
1015                         mode = 0;
1016                         break;
1017                 case PORT_RMII_SEL_S1:
1018                         mode = 1;
1019                         break;
1020                 case PORT_GMII_SEL_S1:
1021                         mode = 2;
1022                         break;
1023                 default:
1024                         mode = 3;
1025                 }
1026         }
1027         return mode;
1028 }
1029
1030 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
1031 {
1032         u8 xmii;
1033
1034         if (dev->features & NEW_XMII) {
1035                 switch (mode) {
1036                 case 0:
1037                         xmii = PORT_MII_SEL;
1038                         break;
1039                 case 1:
1040                         xmii = PORT_RMII_SEL;
1041                         break;
1042                 case 2:
1043                         xmii = PORT_GMII_SEL;
1044                         break;
1045                 default:
1046                         xmii = PORT_RGMII_SEL;
1047                         break;
1048                 }
1049         } else {
1050                 switch (mode) {
1051                 case 0:
1052                         xmii = PORT_MII_SEL_S1;
1053                         break;
1054                 case 1:
1055                         xmii = PORT_RMII_SEL_S1;
1056                         break;
1057                 case 2:
1058                         xmii = PORT_GMII_SEL_S1;
1059                         break;
1060                 default:
1061                         xmii = PORT_RGMII_SEL_S1;
1062                         break;
1063                 }
1064         }
1065         *data &= ~PORT_MII_SEL_M;
1066         *data |= xmii;
1067 }
1068
1069 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1070 {
1071         phy_interface_t interface;
1072         bool gbit;
1073         int mode;
1074         u8 data8;
1075
1076         if (port < dev->phy_port_cnt)
1077                 return PHY_INTERFACE_MODE_NA;
1078         ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1079         gbit = ksz9477_get_gbit(dev, data8);
1080         mode = ksz9477_get_xmii(dev, data8);
1081         switch (mode) {
1082         case 2:
1083                 interface = PHY_INTERFACE_MODE_GMII;
1084                 if (gbit)
1085                         break;
1086                 fallthrough;
1087         case 0:
1088                 interface = PHY_INTERFACE_MODE_MII;
1089                 break;
1090         case 1:
1091                 interface = PHY_INTERFACE_MODE_RMII;
1092                 break;
1093         default:
1094                 interface = PHY_INTERFACE_MODE_RGMII;
1095                 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1096                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
1097                 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1098                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
1099                         if (data8 & PORT_RGMII_ID_EG_ENABLE)
1100                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
1101                 }
1102                 break;
1103         }
1104         return interface;
1105 }
1106
1107 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1108                                    u8 dev_addr, u16 reg_addr, u16 val)
1109 {
1110         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1111                      MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1112         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1113         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1114                      MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1115         ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1116 }
1117
1118 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1119 {
1120         /* Apply PHY settings to address errata listed in
1121          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1122          * Silicon Errata and Data Sheet Clarification documents:
1123          *
1124          * Register settings are needed to improve PHY receive performance
1125          */
1126         ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1127         ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1128         ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1129         ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1130         ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1131         ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1132         ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1133
1134         /* Transmit waveform amplitude can be improved
1135          * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1136          */
1137         ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1138
1139         /* Energy Efficient Ethernet (EEE) feature select must
1140          * be manually disabled (except on KSZ8565 which is 100Mbit)
1141          */
1142         if (dev->features & GBIT_SUPPORT)
1143                 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1144
1145         /* Register settings are required to meet data sheet
1146          * supply current specifications
1147          */
1148         ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1149         ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1150         ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1151         ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1152         ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1153         ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1154         ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1155         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1156         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1157         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1158         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1159         ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1160         ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1161 }
1162
1163 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1164 {
1165         u8 data8;
1166         u8 member;
1167         u16 data16;
1168         struct ksz_port *p = &dev->ports[port];
1169
1170         /* enable tag tail for host port */
1171         if (cpu_port)
1172                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1173                              true);
1174
1175         ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1176
1177         /* set back pressure */
1178         ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1179
1180         /* enable broadcast storm limit */
1181         ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1182
1183         /* disable DiffServ priority */
1184         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1185
1186         /* replace priority */
1187         ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1188                      false);
1189         ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1190                            MTI_PVID_REPLACE, false);
1191
1192         /* enable 802.1p priority */
1193         ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1194
1195         if (port < dev->phy_port_cnt) {
1196                 /* do not force flow control */
1197                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1198                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1199                              false);
1200
1201                 if (dev->phy_errata_9477)
1202                         ksz9477_phy_errata_setup(dev, port);
1203         } else {
1204                 /* force flow control */
1205                 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1206                              PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1207                              true);
1208
1209                 /* configure MAC to 1G & RGMII mode */
1210                 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1211                 switch (dev->interface) {
1212                 case PHY_INTERFACE_MODE_MII:
1213                         ksz9477_set_xmii(dev, 0, &data8);
1214                         ksz9477_set_gbit(dev, false, &data8);
1215                         p->phydev.speed = SPEED_100;
1216                         break;
1217                 case PHY_INTERFACE_MODE_RMII:
1218                         ksz9477_set_xmii(dev, 1, &data8);
1219                         ksz9477_set_gbit(dev, false, &data8);
1220                         p->phydev.speed = SPEED_100;
1221                         break;
1222                 case PHY_INTERFACE_MODE_GMII:
1223                         ksz9477_set_xmii(dev, 2, &data8);
1224                         ksz9477_set_gbit(dev, true, &data8);
1225                         p->phydev.speed = SPEED_1000;
1226                         break;
1227                 default:
1228                         ksz9477_set_xmii(dev, 3, &data8);
1229                         ksz9477_set_gbit(dev, true, &data8);
1230                         data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1231                         data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1232                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1233                             dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1234                                 data8 |= PORT_RGMII_ID_IG_ENABLE;
1235                         if (dev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1236                             dev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1237                                 data8 |= PORT_RGMII_ID_EG_ENABLE;
1238                         p->phydev.speed = SPEED_1000;
1239                         break;
1240                 }
1241                 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1242                 p->phydev.duplex = 1;
1243         }
1244         mutex_lock(&dev->dev_mutex);
1245         if (cpu_port)
1246                 member = dev->port_mask;
1247         else
1248                 member = dev->host_mask | p->vid_member;
1249         mutex_unlock(&dev->dev_mutex);
1250         ksz9477_cfg_port_member(dev, port, member);
1251
1252         /* clear pending interrupts */
1253         if (port < dev->phy_port_cnt)
1254                 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1255 }
1256
1257 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1258 {
1259         struct ksz_device *dev = ds->priv;
1260         struct ksz_port *p;
1261         int i;
1262
1263         ds->num_ports = dev->port_cnt;
1264
1265         for (i = 0; i < dev->port_cnt; i++) {
1266                 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1267                         phy_interface_t interface;
1268
1269                         dev->cpu_port = i;
1270                         dev->host_mask = (1 << dev->cpu_port);
1271                         dev->port_mask |= dev->host_mask;
1272
1273                         /* Read from XMII register to determine host port
1274                          * interface.  If set specifically in device tree
1275                          * note the difference to help debugging.
1276                          */
1277                         interface = ksz9477_get_interface(dev, i);
1278                         if (!dev->interface)
1279                                 dev->interface = interface;
1280                         if (interface && interface != dev->interface)
1281                                 dev_info(dev->dev,
1282                                          "use %s instead of %s\n",
1283                                           phy_modes(dev->interface),
1284                                           phy_modes(interface));
1285
1286                         /* enable cpu port */
1287                         ksz9477_port_setup(dev, i, true);
1288                         p = &dev->ports[dev->cpu_port];
1289                         p->vid_member = dev->port_mask;
1290                         p->on = 1;
1291                 }
1292         }
1293
1294         dev->member = dev->host_mask;
1295
1296         for (i = 0; i < dev->mib_port_cnt; i++) {
1297                 if (i == dev->cpu_port)
1298                         continue;
1299                 p = &dev->ports[i];
1300
1301                 /* Initialize to non-zero so that ksz_cfg_port_member() will
1302                  * be called.
1303                  */
1304                 p->vid_member = (1 << i);
1305                 p->member = dev->port_mask;
1306                 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1307                 p->on = 1;
1308                 if (i < dev->phy_port_cnt)
1309                         p->phy = 1;
1310                 if (dev->chip_id == 0x00947700 && i == 6) {
1311                         p->sgmii = 1;
1312
1313                         /* SGMII PHY detection code is not implemented yet. */
1314                         p->phy = 0;
1315                 }
1316         }
1317 }
1318
1319 static int ksz9477_setup(struct dsa_switch *ds)
1320 {
1321         struct ksz_device *dev = ds->priv;
1322         int ret = 0;
1323
1324         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1325                                        dev->num_vlans, GFP_KERNEL);
1326         if (!dev->vlan_cache)
1327                 return -ENOMEM;
1328
1329         ret = ksz9477_reset_switch(dev);
1330         if (ret) {
1331                 dev_err(ds->dev, "failed to reset switch\n");
1332                 return ret;
1333         }
1334
1335         /* Required for port partitioning. */
1336         ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1337                       true);
1338
1339         /* Do not work correctly with tail tagging. */
1340         ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1341
1342         /* accept packet up to 2000bytes */
1343         ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1344
1345         ksz9477_config_cpu_port(ds);
1346
1347         ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1348
1349         /* queue based egress rate limit */
1350         ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1351
1352         /* enable global MIB counter freeze function */
1353         ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1354
1355         /* start switch */
1356         ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1357
1358         ksz_init_mib_timer(dev);
1359
1360         return 0;
1361 }
1362
1363 static const struct dsa_switch_ops ksz9477_switch_ops = {
1364         .get_tag_protocol       = ksz9477_get_tag_protocol,
1365         .setup                  = ksz9477_setup,
1366         .phy_read               = ksz9477_phy_read16,
1367         .phy_write              = ksz9477_phy_write16,
1368         .phylink_mac_link_down  = ksz_mac_link_down,
1369         .port_enable            = ksz_enable_port,
1370         .get_strings            = ksz9477_get_strings,
1371         .get_ethtool_stats      = ksz_get_ethtool_stats,
1372         .get_sset_count         = ksz_sset_count,
1373         .port_bridge_join       = ksz_port_bridge_join,
1374         .port_bridge_leave      = ksz_port_bridge_leave,
1375         .port_stp_state_set     = ksz9477_port_stp_state_set,
1376         .port_fast_age          = ksz_port_fast_age,
1377         .port_vlan_filtering    = ksz9477_port_vlan_filtering,
1378         .port_vlan_prepare      = ksz_port_vlan_prepare,
1379         .port_vlan_add          = ksz9477_port_vlan_add,
1380         .port_vlan_del          = ksz9477_port_vlan_del,
1381         .port_fdb_dump          = ksz9477_port_fdb_dump,
1382         .port_fdb_add           = ksz9477_port_fdb_add,
1383         .port_fdb_del           = ksz9477_port_fdb_del,
1384         .port_mdb_prepare       = ksz_port_mdb_prepare,
1385         .port_mdb_add           = ksz9477_port_mdb_add,
1386         .port_mdb_del           = ksz9477_port_mdb_del,
1387         .port_mirror_add        = ksz9477_port_mirror_add,
1388         .port_mirror_del        = ksz9477_port_mirror_del,
1389 };
1390
1391 static u32 ksz9477_get_port_addr(int port, int offset)
1392 {
1393         return PORT_CTRL_ADDR(port, offset);
1394 }
1395
1396 static int ksz9477_switch_detect(struct ksz_device *dev)
1397 {
1398         u8 data8;
1399         u8 id_hi;
1400         u8 id_lo;
1401         u32 id32;
1402         int ret;
1403
1404         /* turn off SPI DO Edge select */
1405         ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1406         if (ret)
1407                 return ret;
1408
1409         data8 &= ~SPI_AUTO_EDGE_DETECTION;
1410         ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1411         if (ret)
1412                 return ret;
1413
1414         /* read chip id */
1415         ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1416         if (ret)
1417                 return ret;
1418         ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1419         if (ret)
1420                 return ret;
1421
1422         /* Number of ports can be reduced depending on chip. */
1423         dev->mib_port_cnt = TOTAL_PORT_NUM;
1424         dev->phy_port_cnt = 5;
1425
1426         /* Default capability is gigabit capable. */
1427         dev->features = GBIT_SUPPORT;
1428
1429         id_hi = (u8)(id32 >> 16);
1430         id_lo = (u8)(id32 >> 8);
1431         if ((id_lo & 0xf) == 3) {
1432                 /* Chip is from KSZ9893 design. */
1433                 dev->features |= IS_9893;
1434
1435                 /* Chip does not support gigabit. */
1436                 if (data8 & SW_QW_ABLE)
1437                         dev->features &= ~GBIT_SUPPORT;
1438                 dev->mib_port_cnt = 3;
1439                 dev->phy_port_cnt = 2;
1440         } else {
1441                 /* Chip uses new XMII register definitions. */
1442                 dev->features |= NEW_XMII;
1443
1444                 /* Chip does not support gigabit. */
1445                 if (!(data8 & SW_GIGABIT_ABLE))
1446                         dev->features &= ~GBIT_SUPPORT;
1447         }
1448
1449         /* Change chip id to known ones so it can be matched against them. */
1450         id32 = (id_hi << 16) | (id_lo << 8);
1451
1452         dev->chip_id = id32;
1453
1454         return 0;
1455 }
1456
1457 struct ksz_chip_data {
1458         u32 chip_id;
1459         const char *dev_name;
1460         int num_vlans;
1461         int num_alus;
1462         int num_statics;
1463         int cpu_ports;
1464         int port_cnt;
1465         bool phy_errata_9477;
1466 };
1467
1468 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1469         {
1470                 .chip_id = 0x00947700,
1471                 .dev_name = "KSZ9477",
1472                 .num_vlans = 4096,
1473                 .num_alus = 4096,
1474                 .num_statics = 16,
1475                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1476                 .port_cnt = 7,          /* total physical port count */
1477                 .phy_errata_9477 = true,
1478         },
1479         {
1480                 .chip_id = 0x00989700,
1481                 .dev_name = "KSZ9897",
1482                 .num_vlans = 4096,
1483                 .num_alus = 4096,
1484                 .num_statics = 16,
1485                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1486                 .port_cnt = 7,          /* total physical port count */
1487                 .phy_errata_9477 = true,
1488         },
1489         {
1490                 .chip_id = 0x00989300,
1491                 .dev_name = "KSZ9893",
1492                 .num_vlans = 4096,
1493                 .num_alus = 4096,
1494                 .num_statics = 16,
1495                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1496                 .port_cnt = 3,          /* total port count */
1497         },
1498         {
1499                 .chip_id = 0x00956700,
1500                 .dev_name = "KSZ9567",
1501                 .num_vlans = 4096,
1502                 .num_alus = 4096,
1503                 .num_statics = 16,
1504                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1505                 .port_cnt = 7,          /* total physical port count */
1506         },
1507 };
1508
1509 static int ksz9477_switch_init(struct ksz_device *dev)
1510 {
1511         int i;
1512
1513         dev->ds->ops = &ksz9477_switch_ops;
1514
1515         for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1516                 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1517
1518                 if (dev->chip_id == chip->chip_id) {
1519                         dev->name = chip->dev_name;
1520                         dev->num_vlans = chip->num_vlans;
1521                         dev->num_alus = chip->num_alus;
1522                         dev->num_statics = chip->num_statics;
1523                         dev->port_cnt = chip->port_cnt;
1524                         dev->cpu_ports = chip->cpu_ports;
1525                         dev->phy_errata_9477 = chip->phy_errata_9477;
1526
1527                         break;
1528                 }
1529         }
1530
1531         /* no switch found */
1532         if (!dev->port_cnt)
1533                 return -ENODEV;
1534
1535         dev->port_mask = (1 << dev->port_cnt) - 1;
1536
1537         dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1538         dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1539
1540         i = dev->mib_port_cnt;
1541         dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1542                                   GFP_KERNEL);
1543         if (!dev->ports)
1544                 return -ENOMEM;
1545         for (i = 0; i < dev->mib_port_cnt; i++) {
1546                 mutex_init(&dev->ports[i].mib.cnt_mutex);
1547                 dev->ports[i].mib.counters =
1548                         devm_kzalloc(dev->dev,
1549                                      sizeof(u64) *
1550                                      (TOTAL_SWITCH_COUNTER_NUM + 1),
1551                                      GFP_KERNEL);
1552                 if (!dev->ports[i].mib.counters)
1553                         return -ENOMEM;
1554         }
1555
1556         /* set the real number of ports */
1557         dev->ds->num_ports = dev->port_cnt;
1558
1559         return 0;
1560 }
1561
1562 static void ksz9477_switch_exit(struct ksz_device *dev)
1563 {
1564         ksz9477_reset_switch(dev);
1565 }
1566
1567 static const struct ksz_dev_ops ksz9477_dev_ops = {
1568         .get_port_addr = ksz9477_get_port_addr,
1569         .cfg_port_member = ksz9477_cfg_port_member,
1570         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1571         .port_setup = ksz9477_port_setup,
1572         .r_mib_cnt = ksz9477_r_mib_cnt,
1573         .r_mib_pkt = ksz9477_r_mib_pkt,
1574         .freeze_mib = ksz9477_freeze_mib,
1575         .port_init_cnt = ksz9477_port_init_cnt,
1576         .shutdown = ksz9477_reset_switch,
1577         .detect = ksz9477_switch_detect,
1578         .init = ksz9477_switch_init,
1579         .exit = ksz9477_switch_exit,
1580 };
1581
1582 int ksz9477_switch_register(struct ksz_device *dev)
1583 {
1584         int ret, i;
1585         struct phy_device *phydev;
1586
1587         ret = ksz_switch_register(dev, &ksz9477_dev_ops);
1588         if (ret)
1589                 return ret;
1590
1591         for (i = 0; i < dev->phy_port_cnt; ++i) {
1592                 if (!dsa_is_user_port(dev->ds, i))
1593                         continue;
1594
1595                 phydev = dsa_to_port(dev->ds, i)->slave->phydev;
1596
1597                 /* The MAC actually cannot run in 1000 half-duplex mode. */
1598                 phy_remove_link_mode(phydev,
1599                                      ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1600
1601                 /* PHY does not support gigabit. */
1602                 if (!(dev->features & GBIT_SUPPORT))
1603                         phy_remove_link_mode(phydev,
1604                                              ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1605         }
1606         return ret;
1607 }
1608 EXPORT_SYMBOL(ksz9477_switch_register);
1609
1610 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1611 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1612 MODULE_LICENSE("GPL");