1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Broadcom Starfighter 2 DSA switch driver
5 * Copyright (C) 2014, Broadcom Corporation
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_address.h>
20 #include <linux/of_net.h>
21 #include <linux/of_mdio.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_bridge.h>
25 #include <linux/brcmphy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/platform_data/b53.h>
30 #include "bcm_sf2_regs.h"
31 #include "b53/b53_priv.h"
32 #include "b53/b53_regs.h"
34 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
61 b53_brcm_hdr_setup(ds, port);
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
67 offset = CORE_STS_OVERRIDE_IMP2;
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 if (priv->type == BCM7278_DEVICE_ID)
73 reg |= GMII_SPEED_UP_2G;
74 core_writel(priv, reg, offset);
76 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
77 reg = core_readl(priv, CORE_IMP_CTL);
78 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
79 reg &= ~(RX_DIS | TX_DIS);
80 core_writel(priv, reg, CORE_IMP_CTL);
82 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
83 reg &= ~(RX_DIS | TX_DIS);
84 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
88 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
90 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
93 reg = reg_readl(priv, REG_SPHY_CNTRL);
96 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
97 reg_writel(priv, reg, REG_SPHY_CNTRL);
99 reg = reg_readl(priv, REG_SPHY_CNTRL);
102 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
103 reg_writel(priv, reg, REG_SPHY_CNTRL);
107 reg_writel(priv, reg, REG_SPHY_CNTRL);
109 /* Use PHY-driven LED signaling */
111 reg = reg_readl(priv, REG_LED_CNTRL(0));
112 reg |= SPDLNK_SRC_SEL;
113 reg_writel(priv, reg, REG_LED_CNTRL(0));
117 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
127 /* Port 0 interrupts are located on the first bank */
128 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
131 off = P_IRQ_OFF(port);
135 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
138 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
148 /* Port 0 interrupts are located on the first bank */
149 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
150 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
153 off = P_IRQ_OFF(port);
157 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
158 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
161 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
162 struct phy_device *phy)
164 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
168 if (!dsa_is_user_port(ds, port))
171 /* Clear the memory power down */
172 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
173 reg &= ~P_TXQ_PSM_VDD(port);
174 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
176 /* Enable learning */
177 reg = core_readl(priv, CORE_DIS_LEARN);
179 core_writel(priv, reg, CORE_DIS_LEARN);
181 /* Enable Broadcom tags for that port if requested */
182 if (priv->brcm_tag_mask & BIT(port))
183 b53_brcm_hdr_setup(ds, port);
185 /* Configure Traffic Class to QoS mapping, allow each priority to map
186 * to a different queue number
188 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
189 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
190 reg |= i << (PRT_TO_QID_SHIFT * i);
191 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
193 /* Re-enable the GPHY and re-apply workarounds */
194 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
195 bcm_sf2_gphy_enable_set(ds, true);
197 /* if phy_stop() has been called before, phy
198 * will be in halted state, and phy_start()
201 * the resume path does not configure back
202 * autoneg settings, and since we hard reset
203 * the phy manually here, we need to reset the
204 * state machine also.
206 phy->state = PHY_READY;
211 /* Enable MoCA port interrupts to get notified */
212 if (port == priv->moca_port)
213 bcm_sf2_port_intr_enable(priv, port);
215 /* Set per-queue pause threshold to 32 */
216 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
218 /* Set ACB threshold to 24 */
219 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
220 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
221 SF2_NUM_EGRESS_QUEUES + i));
222 reg &= ~XOFF_THRESHOLD_MASK;
224 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
225 SF2_NUM_EGRESS_QUEUES + i));
228 return b53_enable_port(ds, port, phy);
231 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
233 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
236 /* Disable learning while in WoL mode */
237 if (priv->wol_ports_mask & (1 << port)) {
238 reg = core_readl(priv, CORE_DIS_LEARN);
240 core_writel(priv, reg, CORE_DIS_LEARN);
244 if (port == priv->moca_port)
245 bcm_sf2_port_intr_disable(priv, port);
247 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
248 bcm_sf2_gphy_enable_set(ds, false);
250 b53_disable_port(ds, port);
252 /* Power down the port memory */
253 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
254 reg |= P_TXQ_PSM_VDD(port);
255 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
259 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
265 reg = reg_readl(priv, REG_SWITCH_CNTRL);
266 reg |= MDIO_MASTER_SEL;
267 reg_writel(priv, reg, REG_SWITCH_CNTRL);
269 /* Page << 8 | offset */
272 core_writel(priv, addr, reg);
274 /* Page << 8 | offset */
275 reg = 0x80 << 8 | regnum << 1;
279 ret = core_readl(priv, reg);
281 core_writel(priv, val, reg);
283 reg = reg_readl(priv, REG_SWITCH_CNTRL);
284 reg &= ~MDIO_MASTER_SEL;
285 reg_writel(priv, reg, REG_SWITCH_CNTRL);
290 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
292 struct bcm_sf2_priv *priv = bus->priv;
294 /* Intercept reads from Broadcom pseudo-PHY address, else, send
295 * them to our master MDIO bus controller
297 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
298 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
300 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
303 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
306 struct bcm_sf2_priv *priv = bus->priv;
308 /* Intercept writes to the Broadcom pseudo-PHY address, else,
309 * send them to our master MDIO bus controller
311 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
312 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
314 return mdiobus_write_nested(priv->master_mii_bus, addr,
318 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
320 struct dsa_switch *ds = dev_id;
321 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
323 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
325 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
330 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
332 struct dsa_switch *ds = dev_id;
333 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
335 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
337 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
339 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
340 priv->port_sts[7].link = true;
341 dsa_port_phylink_mac_change(ds, 7, true);
343 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
344 priv->port_sts[7].link = false;
345 dsa_port_phylink_mac_change(ds, 7, false);
351 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
353 unsigned int timeout = 1000;
357 /* The watchdog reset does not work on 7278, we need to hit the
358 * "external" reset line through the reset controller.
360 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
361 ret = reset_control_assert(priv->rcdev);
365 return reset_control_deassert(priv->rcdev);
368 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
369 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
370 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
373 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
374 if (!(reg & SOFTWARE_RESET))
377 usleep_range(1000, 2000);
378 } while (timeout-- > 0);
386 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
388 intrl2_0_mask_set(priv, 0xffffffff);
389 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
390 intrl2_1_mask_set(priv, 0xffffffff);
391 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
394 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
395 struct device_node *dn)
397 struct device_node *port;
398 unsigned int port_num;
399 phy_interface_t mode;
402 priv->moca_port = -1;
404 for_each_available_child_of_node(dn, port) {
405 if (of_property_read_u32(port, "reg", &port_num))
408 /* Internal PHYs get assigned a specific 'phy-mode' property
409 * value: "internal" to help flag them before MDIO probing
410 * has completed, since they might be turned off at that
413 err = of_get_phy_mode(port, &mode);
417 if (mode == PHY_INTERFACE_MODE_INTERNAL)
418 priv->int_phy_mask |= 1 << port_num;
420 if (mode == PHY_INTERFACE_MODE_MOCA)
421 priv->moca_port = port_num;
423 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
424 priv->brcm_tag_mask |= 1 << port_num;
428 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
430 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
431 struct device_node *dn;
435 /* Find our integrated MDIO bus node */
436 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
437 priv->master_mii_bus = of_mdio_find_bus(dn);
438 if (!priv->master_mii_bus)
439 return -EPROBE_DEFER;
441 get_device(&priv->master_mii_bus->dev);
442 priv->master_mii_dn = dn;
444 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
445 if (!priv->slave_mii_bus)
448 priv->slave_mii_bus->priv = priv;
449 priv->slave_mii_bus->name = "sf2 slave mii";
450 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
451 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
452 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
454 priv->slave_mii_bus->dev.of_node = dn;
456 /* Include the pseudo-PHY address to divert reads towards our
457 * workaround. This is only required for 7445D0, since 7445E0
458 * disconnects the internal switch pseudo-PHY such that we can use the
459 * regular SWITCH_MDIO master controller instead.
461 * Here we flag the pseudo PHY as needing special treatment and would
462 * otherwise make all other PHY read/writes go to the master MDIO bus
463 * controller that comes with this switch backed by the "mdio-unimac"
466 if (of_machine_is_compatible("brcm,bcm7445d0"))
467 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
469 priv->indir_phy_mask = 0;
471 ds->phys_mii_mask = priv->indir_phy_mask;
472 ds->slave_mii_bus = priv->slave_mii_bus;
473 priv->slave_mii_bus->parent = ds->dev->parent;
474 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
476 err = of_mdiobus_register(priv->slave_mii_bus, dn);
483 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
485 mdiobus_unregister(priv->slave_mii_bus);
486 of_node_put(priv->master_mii_dn);
489 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
491 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
493 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
494 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
495 * the REG_PHY_REVISION register layout is.
498 return priv->hw_params.gphy_rev;
501 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
502 unsigned long *supported,
503 struct phylink_link_state *state)
505 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
506 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
508 if (!phy_interface_mode_is_rgmii(state->interface) &&
509 state->interface != PHY_INTERFACE_MODE_MII &&
510 state->interface != PHY_INTERFACE_MODE_REVMII &&
511 state->interface != PHY_INTERFACE_MODE_GMII &&
512 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
513 state->interface != PHY_INTERFACE_MODE_MOCA) {
514 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
515 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
517 "Unsupported interface: %d for port %d\n",
518 state->interface, port);
522 /* Allow all the expected bits */
523 phylink_set(mask, Autoneg);
524 phylink_set_port_modes(mask);
525 phylink_set(mask, Pause);
526 phylink_set(mask, Asym_Pause);
528 /* With the exclusion of MII and Reverse MII, we support Gigabit,
529 * including Half duplex
531 if (state->interface != PHY_INTERFACE_MODE_MII &&
532 state->interface != PHY_INTERFACE_MODE_REVMII) {
533 phylink_set(mask, 1000baseT_Full);
534 phylink_set(mask, 1000baseT_Half);
537 phylink_set(mask, 10baseT_Half);
538 phylink_set(mask, 10baseT_Full);
539 phylink_set(mask, 100baseT_Half);
540 phylink_set(mask, 100baseT_Full);
542 bitmap_and(supported, supported, mask,
543 __ETHTOOL_LINK_MODE_MASK_NBITS);
544 bitmap_and(state->advertising, state->advertising, mask,
545 __ETHTOOL_LINK_MODE_MASK_NBITS);
548 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
550 const struct phylink_link_state *state)
552 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
553 u32 id_mode_dis = 0, port_mode;
556 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
559 if (priv->type == BCM7445_DEVICE_ID)
560 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
562 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
564 switch (state->interface) {
565 case PHY_INTERFACE_MODE_RGMII:
568 case PHY_INTERFACE_MODE_RGMII_TXID:
569 port_mode = EXT_GPHY;
571 case PHY_INTERFACE_MODE_MII:
572 port_mode = EXT_EPHY;
574 case PHY_INTERFACE_MODE_REVMII:
575 port_mode = EXT_REVMII;
578 /* all other PHYs: internal and MoCA */
582 /* Clear id_mode_dis bit, and the existing port mode, let
583 * RGMII_MODE_EN bet set by mac_link_{up,down}
585 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
587 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
588 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
594 if (state->pause & MLO_PAUSE_TXRX_MASK) {
595 if (state->pause & MLO_PAUSE_TX)
600 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
603 /* Force link settings detected from the PHY */
605 switch (state->speed) {
607 reg |= SPDSTS_1000 << SPEED_SHIFT;
610 reg |= SPDSTS_100 << SPEED_SHIFT;
616 if (state->duplex == DUPLEX_FULL)
619 core_writel(priv, reg, offset);
622 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
623 phy_interface_t interface, bool link)
625 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
628 if (!phy_interface_mode_is_rgmii(interface) &&
629 interface != PHY_INTERFACE_MODE_MII &&
630 interface != PHY_INTERFACE_MODE_REVMII)
633 /* If the link is down, just disable the interface to conserve power */
634 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
636 reg |= RGMII_MODE_EN;
638 reg &= ~RGMII_MODE_EN;
639 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
642 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
644 phy_interface_t interface)
646 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
649 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
651 phy_interface_t interface,
652 struct phy_device *phydev)
654 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
655 struct ethtool_eee *p = &priv->dev->ports[port].eee;
657 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
659 if (mode == MLO_AN_PHY && phydev)
660 p->eee_enabled = b53_eee_init(ds, port, phydev);
663 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
664 struct phylink_link_state *status)
666 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
668 status->link = false;
670 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
671 * which means that we need to force the link at the port override
672 * level to get the data to flow. We do use what the interrupt handler
673 * did determine before.
675 * For the other ports, we just force the link status, since this is
676 * a fixed PHY device.
678 if (port == priv->moca_port) {
679 status->link = priv->port_sts[port].link;
680 /* For MoCA interfaces, also force a link down notification
681 * since some version of the user-space daemon (mocad) use
682 * cmd->autoneg to force the link, which messes up the PHY
683 * state machine and make it go in PHY_FORCING state instead.
686 netif_carrier_off(dsa_to_port(ds, port)->slave);
687 status->duplex = DUPLEX_FULL;
693 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
695 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
698 /* Enable ACB globally */
699 reg = acb_readl(priv, ACB_CONTROL);
700 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
701 acb_writel(priv, reg, ACB_CONTROL);
702 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
703 reg |= ACB_EN | ACB_ALGORITHM;
704 acb_writel(priv, reg, ACB_CONTROL);
707 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
709 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
712 bcm_sf2_intr_disable(priv);
714 /* Disable all ports physically present including the IMP
715 * port, the other ones have already been disabled during
718 for (port = 0; port < ds->num_ports; port++) {
719 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
720 bcm_sf2_port_disable(ds, port);
726 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
728 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
731 ret = bcm_sf2_sw_rst(priv);
733 pr_err("%s: failed to software reset switch\n", __func__);
737 ret = bcm_sf2_cfp_resume(ds);
741 if (priv->hw_params.num_gphy == 1)
742 bcm_sf2_gphy_enable_set(ds, true);
749 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
750 struct ethtool_wolinfo *wol)
752 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
753 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
754 struct ethtool_wolinfo pwol = { };
756 /* Get the parent device WoL settings */
757 if (p->ethtool_ops->get_wol)
758 p->ethtool_ops->get_wol(p, &pwol);
760 /* Advertise the parent device supported settings */
761 wol->supported = pwol.supported;
762 memset(&wol->sopass, 0, sizeof(wol->sopass));
764 if (pwol.wolopts & WAKE_MAGICSECURE)
765 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
767 if (priv->wol_ports_mask & (1 << port))
768 wol->wolopts = pwol.wolopts;
773 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
774 struct ethtool_wolinfo *wol)
776 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
777 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
778 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
779 struct ethtool_wolinfo pwol = { };
781 if (p->ethtool_ops->get_wol)
782 p->ethtool_ops->get_wol(p, &pwol);
783 if (wol->wolopts & ~pwol.supported)
787 priv->wol_ports_mask |= (1 << port);
789 priv->wol_ports_mask &= ~(1 << port);
791 /* If we have at least one port enabled, make sure the CPU port
792 * is also enabled. If the CPU port is the last one enabled, we disable
793 * it since this configuration does not make sense.
795 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
796 priv->wol_ports_mask |= (1 << cpu_port);
798 priv->wol_ports_mask &= ~(1 << cpu_port);
800 return p->ethtool_ops->set_wol(p, wol);
803 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
805 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
808 /* Enable all valid ports and disable those unused */
809 for (port = 0; port < priv->hw_params.num_ports; port++) {
810 /* IMP port receives special treatment */
811 if (dsa_is_user_port(ds, port))
812 bcm_sf2_port_setup(ds, port, NULL);
813 else if (dsa_is_cpu_port(ds, port))
814 bcm_sf2_imp_setup(ds, port);
816 bcm_sf2_port_disable(ds, port);
819 b53_configure_vlan(ds);
820 bcm_sf2_enable_acb(ds);
825 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
826 * register basis so we need to translate that into an address that the
827 * bus-glue understands.
829 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
831 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
834 struct bcm_sf2_priv *priv = dev->priv;
836 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
841 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
844 struct bcm_sf2_priv *priv = dev->priv;
846 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
851 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
854 struct bcm_sf2_priv *priv = dev->priv;
856 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
861 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
864 struct bcm_sf2_priv *priv = dev->priv;
866 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
871 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
874 struct bcm_sf2_priv *priv = dev->priv;
876 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
881 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
884 struct bcm_sf2_priv *priv = dev->priv;
886 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
891 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
894 struct bcm_sf2_priv *priv = dev->priv;
896 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
901 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
904 struct bcm_sf2_priv *priv = dev->priv;
906 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
911 static const struct b53_io_ops bcm_sf2_io_ops = {
912 .read8 = bcm_sf2_core_read8,
913 .read16 = bcm_sf2_core_read16,
914 .read32 = bcm_sf2_core_read32,
915 .read48 = bcm_sf2_core_read64,
916 .read64 = bcm_sf2_core_read64,
917 .write8 = bcm_sf2_core_write8,
918 .write16 = bcm_sf2_core_write16,
919 .write32 = bcm_sf2_core_write32,
920 .write48 = bcm_sf2_core_write64,
921 .write64 = bcm_sf2_core_write64,
924 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
925 u32 stringset, uint8_t *data)
927 int cnt = b53_get_sset_count(ds, port, stringset);
929 b53_get_strings(ds, port, stringset, data);
930 bcm_sf2_cfp_get_strings(ds, port, stringset,
931 data + cnt * ETH_GSTRING_LEN);
934 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
937 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
939 b53_get_ethtool_stats(ds, port, data);
940 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
943 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
946 int cnt = b53_get_sset_count(ds, port, sset);
951 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
956 static const struct dsa_switch_ops bcm_sf2_ops = {
957 .get_tag_protocol = b53_get_tag_protocol,
958 .setup = bcm_sf2_sw_setup,
959 .get_strings = bcm_sf2_sw_get_strings,
960 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
961 .get_sset_count = bcm_sf2_sw_get_sset_count,
962 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
963 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
964 .phylink_validate = bcm_sf2_sw_validate,
965 .phylink_mac_config = bcm_sf2_sw_mac_config,
966 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
967 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
968 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
969 .suspend = bcm_sf2_sw_suspend,
970 .resume = bcm_sf2_sw_resume,
971 .get_wol = bcm_sf2_sw_get_wol,
972 .set_wol = bcm_sf2_sw_set_wol,
973 .port_enable = bcm_sf2_port_setup,
974 .port_disable = bcm_sf2_port_disable,
975 .get_mac_eee = b53_get_mac_eee,
976 .set_mac_eee = b53_set_mac_eee,
977 .port_bridge_join = b53_br_join,
978 .port_bridge_leave = b53_br_leave,
979 .port_stp_state_set = b53_br_set_stp_state,
980 .port_fast_age = b53_br_fast_age,
981 .port_vlan_filtering = b53_vlan_filtering,
982 .port_vlan_prepare = b53_vlan_prepare,
983 .port_vlan_add = b53_vlan_add,
984 .port_vlan_del = b53_vlan_del,
985 .port_fdb_dump = b53_fdb_dump,
986 .port_fdb_add = b53_fdb_add,
987 .port_fdb_del = b53_fdb_del,
988 .get_rxnfc = bcm_sf2_get_rxnfc,
989 .set_rxnfc = bcm_sf2_set_rxnfc,
990 .port_mirror_add = b53_mirror_add,
991 .port_mirror_del = b53_mirror_del,
992 .port_mdb_prepare = b53_mdb_prepare,
993 .port_mdb_add = b53_mdb_add,
994 .port_mdb_del = b53_mdb_del,
997 struct bcm_sf2_of_data {
999 const u16 *reg_offsets;
1000 unsigned int core_reg_align;
1001 unsigned int num_cfp_rules;
1004 /* Register offsets for the SWITCH_REG_* block */
1005 static const u16 bcm_sf2_7445_reg_offsets[] = {
1006 [REG_SWITCH_CNTRL] = 0x00,
1007 [REG_SWITCH_STATUS] = 0x04,
1008 [REG_DIR_DATA_WRITE] = 0x08,
1009 [REG_DIR_DATA_READ] = 0x0C,
1010 [REG_SWITCH_REVISION] = 0x18,
1011 [REG_PHY_REVISION] = 0x1C,
1012 [REG_SPHY_CNTRL] = 0x2C,
1013 [REG_RGMII_0_CNTRL] = 0x34,
1014 [REG_RGMII_1_CNTRL] = 0x40,
1015 [REG_RGMII_2_CNTRL] = 0x4c,
1016 [REG_LED_0_CNTRL] = 0x90,
1017 [REG_LED_1_CNTRL] = 0x94,
1018 [REG_LED_2_CNTRL] = 0x98,
1021 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1022 .type = BCM7445_DEVICE_ID,
1023 .core_reg_align = 0,
1024 .reg_offsets = bcm_sf2_7445_reg_offsets,
1025 .num_cfp_rules = 256,
1028 static const u16 bcm_sf2_7278_reg_offsets[] = {
1029 [REG_SWITCH_CNTRL] = 0x00,
1030 [REG_SWITCH_STATUS] = 0x04,
1031 [REG_DIR_DATA_WRITE] = 0x08,
1032 [REG_DIR_DATA_READ] = 0x0c,
1033 [REG_SWITCH_REVISION] = 0x10,
1034 [REG_PHY_REVISION] = 0x14,
1035 [REG_SPHY_CNTRL] = 0x24,
1036 [REG_RGMII_0_CNTRL] = 0xe0,
1037 [REG_RGMII_1_CNTRL] = 0xec,
1038 [REG_RGMII_2_CNTRL] = 0xf8,
1039 [REG_LED_0_CNTRL] = 0x40,
1040 [REG_LED_1_CNTRL] = 0x4c,
1041 [REG_LED_2_CNTRL] = 0x58,
1044 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1045 .type = BCM7278_DEVICE_ID,
1046 .core_reg_align = 1,
1047 .reg_offsets = bcm_sf2_7278_reg_offsets,
1048 .num_cfp_rules = 128,
1051 static const struct of_device_id bcm_sf2_of_match[] = {
1052 { .compatible = "brcm,bcm7445-switch-v4.0",
1053 .data = &bcm_sf2_7445_data
1055 { .compatible = "brcm,bcm7278-switch-v4.0",
1056 .data = &bcm_sf2_7278_data
1058 { .compatible = "brcm,bcm7278-switch-v4.8",
1059 .data = &bcm_sf2_7278_data
1063 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1065 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1067 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1068 struct device_node *dn = pdev->dev.of_node;
1069 const struct of_device_id *of_id = NULL;
1070 const struct bcm_sf2_of_data *data;
1071 struct b53_platform_data *pdata;
1072 struct dsa_switch_ops *ops;
1073 struct bcm_sf2_priv *priv;
1074 struct b53_device *dev;
1075 struct dsa_switch *ds;
1076 void __iomem **base;
1081 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1085 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1089 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1093 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1097 of_id = of_match_node(bcm_sf2_of_match, dn);
1098 if (!of_id || !of_id->data)
1103 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1104 priv->type = data->type;
1105 priv->reg_offsets = data->reg_offsets;
1106 priv->core_reg_align = data->core_reg_align;
1107 priv->num_cfp_rules = data->num_cfp_rules;
1109 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1111 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
1112 return PTR_ERR(priv->rcdev);
1114 /* Auto-detection using standard registers will not work, so
1115 * provide an indication of what kind of device we are for
1116 * b53_common to work with
1118 pdata->chip_id = priv->type;
1123 ds->ops = &bcm_sf2_ops;
1125 /* Advertise the 8 egress queues */
1126 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1128 dev_set_drvdata(&pdev->dev, priv);
1130 spin_lock_init(&priv->indir_lock);
1131 mutex_init(&priv->cfp.lock);
1132 INIT_LIST_HEAD(&priv->cfp.rules_list);
1134 /* CFP rule #0 cannot be used for specific classifications, flag it as
1137 set_bit(0, priv->cfp.used);
1138 set_bit(0, priv->cfp.unique);
1140 bcm_sf2_identify_ports(priv, dn->child);
1142 priv->irq0 = irq_of_parse_and_map(dn, 0);
1143 priv->irq1 = irq_of_parse_and_map(dn, 1);
1146 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1147 *base = devm_platform_ioremap_resource(pdev, i);
1148 if (IS_ERR(*base)) {
1149 pr_err("unable to find register: %s\n", reg_names[i]);
1150 return PTR_ERR(*base);
1155 ret = bcm_sf2_sw_rst(priv);
1157 pr_err("unable to software reset switch: %d\n", ret);
1161 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1163 ret = bcm_sf2_mdio_register(ds);
1165 pr_err("failed to register MDIO bus\n");
1169 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1171 ret = bcm_sf2_cfp_rst(priv);
1173 pr_err("failed to reset CFP\n");
1177 /* Disable all interrupts and request them */
1178 bcm_sf2_intr_disable(priv);
1180 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1183 pr_err("failed to request switch_0 IRQ\n");
1187 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1190 pr_err("failed to request switch_1 IRQ\n");
1194 /* Reset the MIB counters */
1195 reg = core_readl(priv, CORE_GMNCFGCFG);
1197 core_writel(priv, reg, CORE_GMNCFGCFG);
1198 reg &= ~RST_MIB_CNT;
1199 core_writel(priv, reg, CORE_GMNCFGCFG);
1201 /* Get the maximum number of ports for this switch */
1202 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1203 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1204 priv->hw_params.num_ports = DSA_MAX_PORTS;
1206 /* Assume a single GPHY setup if we can't read that property */
1207 if (of_property_read_u32(dn, "brcm,num-gphy",
1208 &priv->hw_params.num_gphy))
1209 priv->hw_params.num_gphy = 1;
1211 rev = reg_readl(priv, REG_SWITCH_REVISION);
1212 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1213 SWITCH_TOP_REV_MASK;
1214 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1216 rev = reg_readl(priv, REG_PHY_REVISION);
1217 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1219 ret = b53_switch_register(dev);
1223 dev_info(&pdev->dev,
1224 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1225 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1226 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1227 priv->irq0, priv->irq1);
1232 bcm_sf2_mdio_unregister(priv);
1236 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1238 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1240 priv->wol_ports_mask = 0;
1241 /* Disable interrupts */
1242 bcm_sf2_intr_disable(priv);
1243 dsa_unregister_switch(priv->dev->ds);
1244 bcm_sf2_cfp_exit(priv->dev->ds);
1245 bcm_sf2_mdio_unregister(priv);
1246 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
1247 reset_control_assert(priv->rcdev);
1252 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1254 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1256 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1257 * successful MDIO bus scan to occur. If we did turn off the GPHY
1258 * before (e.g: port_disable), this will also power it back on.
1260 * Do not rely on kexec_in_progress, just power the PHY on.
1262 if (priv->hw_params.num_gphy == 1)
1263 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1266 #ifdef CONFIG_PM_SLEEP
1267 static int bcm_sf2_suspend(struct device *dev)
1269 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1271 return dsa_switch_suspend(priv->dev->ds);
1274 static int bcm_sf2_resume(struct device *dev)
1276 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1278 return dsa_switch_resume(priv->dev->ds);
1280 #endif /* CONFIG_PM_SLEEP */
1282 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1283 bcm_sf2_suspend, bcm_sf2_resume);
1286 static struct platform_driver bcm_sf2_driver = {
1287 .probe = bcm_sf2_sw_probe,
1288 .remove = bcm_sf2_sw_remove,
1289 .shutdown = bcm_sf2_sw_shutdown,
1292 .of_match_table = bcm_sf2_of_match,
1293 .pm = &bcm_sf2_pm_ops,
1296 module_platform_driver(bcm_sf2_driver);
1298 MODULE_AUTHOR("Broadcom Corporation");
1299 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1300 MODULE_LICENSE("GPL");
1301 MODULE_ALIAS("platform:brcm-sf2");