2 * Broadcom Starfighter 2 DSA switch driver
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
18 #include <linux/phy.h>
19 #include <linux/phy_fixed.h>
20 #include <linux/mii.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
27 #include "bcm_sf2_regs.h"
29 /* String, offset, and register size in bytes if different from 4 bytes */
30 static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
31 { "TxOctets", 0x000, 8 },
32 { "TxDropPkts", 0x020 },
33 { "TxQPKTQ0", 0x030 },
34 { "TxBroadcastPkts", 0x040 },
35 { "TxMulticastPkts", 0x050 },
36 { "TxUnicastPKts", 0x060 },
37 { "TxCollisions", 0x070 },
38 { "TxSingleCollision", 0x080 },
39 { "TxMultipleCollision", 0x090 },
40 { "TxDeferredCollision", 0x0a0 },
41 { "TxLateCollision", 0x0b0 },
42 { "TxExcessiveCollision", 0x0c0 },
43 { "TxFrameInDisc", 0x0d0 },
44 { "TxPausePkts", 0x0e0 },
45 { "TxQPKTQ1", 0x0f0 },
46 { "TxQPKTQ2", 0x100 },
47 { "TxQPKTQ3", 0x110 },
48 { "TxQPKTQ4", 0x120 },
49 { "TxQPKTQ5", 0x130 },
50 { "RxOctets", 0x140, 8 },
51 { "RxUndersizePkts", 0x160 },
52 { "RxPausePkts", 0x170 },
53 { "RxPkts64Octets", 0x180 },
54 { "RxPkts65to127Octets", 0x190 },
55 { "RxPkts128to255Octets", 0x1a0 },
56 { "RxPkts256to511Octets", 0x1b0 },
57 { "RxPkts512to1023Octets", 0x1c0 },
58 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
59 { "RxOversizePkts", 0x1e0 },
60 { "RxJabbers", 0x1f0 },
61 { "RxAlignmentErrors", 0x200 },
62 { "RxFCSErrors", 0x210 },
63 { "RxGoodOctets", 0x220, 8 },
64 { "RxDropPkts", 0x240 },
65 { "RxUnicastPkts", 0x250 },
66 { "RxMulticastPkts", 0x260 },
67 { "RxBroadcastPkts", 0x270 },
68 { "RxSAChanges", 0x280 },
69 { "RxFragments", 0x290 },
70 { "RxJumboPkt", 0x2a0 },
71 { "RxSymblErr", 0x2b0 },
72 { "InRangeErrCount", 0x2c0 },
73 { "OutRangeErrCount", 0x2d0 },
74 { "EEELpiEvent", 0x2e0 },
75 { "EEELpiDuration", 0x2f0 },
76 { "RxDiscard", 0x300, 8 },
77 { "TxQPKTQ6", 0x320 },
78 { "TxQPKTQ7", 0x330 },
79 { "TxPkts64Octets", 0x340 },
80 { "TxPkts65to127Octets", 0x350 },
81 { "TxPkts128to255Octets", 0x360 },
82 { "TxPkts256to511Ocets", 0x370 },
83 { "TxPkts512to1023Ocets", 0x380 },
84 { "TxPkts1024toMaxPktOcets", 0x390 },
87 #define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
89 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
90 int port, uint8_t *data)
94 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
95 memcpy(data + i * ETH_GSTRING_LEN,
96 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
99 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
100 int port, uint64_t *data)
102 struct bcm_sf2_priv *priv = ds_to_priv(ds);
103 const struct bcm_sf2_hw_stats *s;
108 mutex_lock(&priv->stats_mutex);
110 /* Now fetch the per-port counters */
111 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
114 /* Do a latched 64-bit read if needed */
115 offset = s->reg + CORE_P_MIB_OFFSET(port);
116 if (s->sizeof_stat == 8)
117 val = core_readq(priv, offset);
119 val = core_readl(priv, offset);
124 mutex_unlock(&priv->stats_mutex);
127 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
129 return BCM_SF2_STATS_SIZE;
132 static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
134 return "Broadcom Starfighter 2";
137 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
139 struct bcm_sf2_priv *priv = ds_to_priv(ds);
143 /* Enable the port memories */
144 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
145 reg &= ~P_TXQ_PSM_VDD(port);
146 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
148 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
149 reg = core_readl(priv, CORE_IMP_CTL);
150 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
151 reg &= ~(RX_DIS | TX_DIS);
152 core_writel(priv, reg, CORE_IMP_CTL);
154 /* Enable forwarding */
155 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
157 /* Enable IMP port in dumb mode */
158 reg = core_readl(priv, CORE_SWITCH_CTRL);
159 reg |= MII_DUMB_FWDG_EN;
160 core_writel(priv, reg, CORE_SWITCH_CTRL);
162 /* Resolve which bit controls the Broadcom tag */
165 val = BRCM_HDR_EN_P8;
168 val = BRCM_HDR_EN_P7;
171 val = BRCM_HDR_EN_P5;
178 /* Enable Broadcom tags for IMP port */
179 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
181 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
183 /* Enable reception Broadcom tag for CPU TX (switch RX) to
184 * allow us to tag outgoing frames
186 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
188 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
190 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
191 * allow delivering frames to the per-port net_devices
193 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
195 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
197 /* Force link status for IMP port */
198 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
199 reg |= (MII_SW_OR | LINK_STS);
200 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
202 /* Enable the IMP Port to be in the same VLAN as the other ports
203 * on a per-port basis such that we only have Port i and IMP in
206 for (i = 0; i < priv->hw_params.num_ports; i++) {
207 if (!((1 << i) & ds->phys_port_mask))
210 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
212 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
216 static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
218 struct bcm_sf2_priv *priv = ds_to_priv(ds);
221 /* Clear the memory power down */
222 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
223 reg &= ~P_TXQ_PSM_VDD(port);
224 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
226 /* Clear the Rx and Tx disable bits and set to no spanning tree */
227 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
229 /* Enable port 7 interrupts to get notified */
231 intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
233 /* Set this port, and only this one to be in the default VLAN */
234 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
235 reg &= ~PORT_VLAN_CTRL_MASK;
237 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
240 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
242 struct bcm_sf2_priv *priv = ds_to_priv(ds);
245 if (dsa_is_cpu_port(ds, port))
248 off = CORE_G_PCTL_PORT(port);
250 reg = core_readl(priv, off);
251 reg |= RX_DIS | TX_DIS;
252 core_writel(priv, reg, off);
254 /* Power down the port memory */
255 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
256 reg |= P_TXQ_PSM_VDD(port);
257 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
260 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
262 struct bcm_sf2_priv *priv = dev_id;
264 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
266 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
271 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
273 struct bcm_sf2_priv *priv = dev_id;
275 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
277 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
279 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
280 priv->port_sts[7].link = 1;
281 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
282 priv->port_sts[7].link = 0;
287 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
289 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
290 struct bcm_sf2_priv *priv = ds_to_priv(ds);
291 struct device_node *dn;
298 spin_lock_init(&priv->indir_lock);
299 mutex_init(&priv->stats_mutex);
301 /* All the interesting properties are at the parent device_node
304 dn = ds->pd->of_node->parent;
306 priv->irq0 = irq_of_parse_and_map(dn, 0);
307 priv->irq1 = irq_of_parse_and_map(dn, 1);
310 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
311 *base = of_iomap(dn, i);
313 pr_err("unable to find register: %s\n", reg_names[i]);
319 /* Disable all interrupts and request them */
320 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
321 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
322 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
323 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
324 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
325 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
327 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
330 pr_err("failed to request switch_0 IRQ\n");
334 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
337 pr_err("failed to request switch_1 IRQ\n");
341 /* Reset the MIB counters */
342 reg = core_readl(priv, CORE_GMNCFGCFG);
344 core_writel(priv, reg, CORE_GMNCFGCFG);
346 core_writel(priv, reg, CORE_GMNCFGCFG);
348 /* Get the maximum number of ports for this switch */
349 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
350 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
351 priv->hw_params.num_ports = DSA_MAX_PORTS;
353 /* Assume a single GPHY setup if we can't read that property */
354 if (of_property_read_u32(dn, "brcm,num-gphy",
355 &priv->hw_params.num_gphy))
356 priv->hw_params.num_gphy = 1;
358 /* Enable all valid ports and disable those unused */
359 for (port = 0; port < priv->hw_params.num_ports; port++) {
360 /* IMP port receives special treatment */
361 if ((1 << port) & ds->phys_port_mask)
362 bcm_sf2_port_setup(ds, port);
363 else if (dsa_is_cpu_port(ds, port))
364 bcm_sf2_imp_setup(ds, port);
366 bcm_sf2_port_disable(ds, port);
369 /* Include the pseudo-PHY address and the broadcast PHY address to
370 * divert reads towards our workaround
372 ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
374 rev = reg_readl(priv, REG_SWITCH_REVISION);
375 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
377 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
379 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
380 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
381 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
382 priv->core, priv->irq0, priv->irq1);
387 free_irq(priv->irq0, priv);
390 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
397 static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
402 static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
405 struct bcm_sf2_priv *priv = ds_to_priv(ds);
409 reg = reg_readl(priv, REG_SWITCH_CNTRL);
410 reg |= MDIO_MASTER_SEL;
411 reg_writel(priv, reg, REG_SWITCH_CNTRL);
413 /* Page << 8 | offset */
416 core_writel(priv, addr, reg);
418 /* Page << 8 | offset */
419 reg = 0x80 << 8 | regnum << 1;
423 ret = core_readl(priv, reg);
425 core_writel(priv, val, reg);
427 reg = reg_readl(priv, REG_SWITCH_CNTRL);
428 reg &= ~MDIO_MASTER_SEL;
429 reg_writel(priv, reg, REG_SWITCH_CNTRL);
434 static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
436 /* Intercept reads from the MDIO broadcast address or Broadcom
442 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
448 static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
451 /* Intercept writes to the MDIO broadcast address or Broadcom
457 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
464 static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
465 struct phy_device *phydev)
467 struct bcm_sf2_priv *priv = ds_to_priv(ds);
468 u32 id_mode_dis = 0, port_mode;
469 const char *str = NULL;
472 switch (phydev->interface) {
473 case PHY_INTERFACE_MODE_RGMII:
474 str = "RGMII (no delay)";
476 case PHY_INTERFACE_MODE_RGMII_TXID:
478 str = "RGMII (TX delay)";
479 port_mode = EXT_GPHY;
481 case PHY_INTERFACE_MODE_MII:
483 port_mode = EXT_EPHY;
485 case PHY_INTERFACE_MODE_REVMII:
487 port_mode = EXT_REVMII;
493 /* Clear id_mode_dis bit, and the existing port mode, but
494 * make sure we enable the RGMII block for data to pass
496 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
498 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
499 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
501 reg |= port_mode | RGMII_MODE_EN;
506 if (phydev->asym_pause)
511 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
513 pr_info("Port %d configured for %s\n", port, str);
516 /* Force link settings detected from the PHY */
518 switch (phydev->speed) {
520 reg |= SPDSTS_1000 << SPEED_SHIFT;
523 reg |= SPDSTS_100 << SPEED_SHIFT;
529 if (phydev->duplex == DUPLEX_FULL)
532 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
535 static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
536 struct fixed_phy_status *status)
538 struct bcm_sf2_priv *priv = ds_to_priv(ds);
539 u32 link, duplex, pause, speed;
542 link = core_readl(priv, CORE_LNKSTS);
543 duplex = core_readl(priv, CORE_DUPSTS);
544 pause = core_readl(priv, CORE_PAUSESTS);
545 speed = core_readl(priv, CORE_SPDSTS);
547 speed >>= (port * SPDSTS_SHIFT);
548 speed &= SPDSTS_MASK;
552 /* Port 7 is special as we do not get link status from CORE_LNKSTS,
553 * which means that we need to force the link at the port override
554 * level to get the data to flow. We do use what the interrupt handler
555 * did determine before.
558 status->link = priv->port_sts[port].link;
559 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(7));
565 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(7));
568 status->link = !!(link & (1 << port));
569 status->duplex = !!(duplex & (1 << port));
574 status->speed = SPEED_10;
577 status->speed = SPEED_100;
580 status->speed = SPEED_1000;
584 if ((pause & (1 << port)) &&
585 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
586 status->asym_pause = 1;
590 if (pause & (1 << port))
594 static struct dsa_switch_driver bcm_sf2_switch_driver = {
595 .tag_protocol = DSA_TAG_PROTO_BRCM,
596 .priv_size = sizeof(struct bcm_sf2_priv),
597 .probe = bcm_sf2_sw_probe,
598 .setup = bcm_sf2_sw_setup,
599 .set_addr = bcm_sf2_sw_set_addr,
600 .phy_read = bcm_sf2_sw_phy_read,
601 .phy_write = bcm_sf2_sw_phy_write,
602 .get_strings = bcm_sf2_sw_get_strings,
603 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
604 .get_sset_count = bcm_sf2_sw_get_sset_count,
605 .adjust_link = bcm_sf2_sw_adjust_link,
606 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
609 static int __init bcm_sf2_init(void)
611 register_switch_driver(&bcm_sf2_switch_driver);
615 module_init(bcm_sf2_init);
617 static void __exit bcm_sf2_exit(void)
619 unregister_switch_driver(&bcm_sf2_switch_driver);
621 module_exit(bcm_sf2_exit);
623 MODULE_AUTHOR("Broadcom Corporation");
624 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
625 MODULE_LICENSE("GPL");
626 MODULE_ALIAS("platform:brcm-sf2");