1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
5 // Copyright (c) 2019, 2020, 2021 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
15 #include <linux/bitfield.h>
16 #include <linux/clk.h>
17 #include <linux/device.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/property.h>
23 #include "mcp251xfd.h"
25 #define DEVICE_NAME "mcp251xfd"
27 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
28 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
29 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
31 .model = MCP251XFD_MODEL_MCP2517FD,
34 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
35 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
36 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
37 .model = MCP251XFD_MODEL_MCP2518FD,
40 /* Autodetect model, start with CRC enabled. */
41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
44 .model = MCP251XFD_MODEL_MCP251XFD,
47 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
59 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
71 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
74 case MCP251XFD_MODEL_MCP2517FD:
76 case MCP251XFD_MODEL_MCP2518FD:
78 case MCP251XFD_MODEL_MCP251XFD:
85 static inline const char *
86 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
88 return __mcp251xfd_get_model_str(priv->devtype_data.model);
91 static const char *mcp251xfd_get_mode_str(const u8 mode)
94 case MCP251XFD_REG_CON_MODE_MIXED:
95 return "Mixed (CAN FD/CAN 2.0)";
96 case MCP251XFD_REG_CON_MODE_SLEEP:
98 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
99 return "Internal Loopback";
100 case MCP251XFD_REG_CON_MODE_LISTENONLY:
101 return "Listen Only";
102 case MCP251XFD_REG_CON_MODE_CONFIG:
103 return "Configuration";
104 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
105 return "External Loopback";
106 case MCP251XFD_REG_CON_MODE_CAN2_0:
108 case MCP251XFD_REG_CON_MODE_RESTRICTED:
109 return "Restricted Operation";
116 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
118 switch (~osc & osc_reference &
119 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
120 case MCP251XFD_REG_OSC_PLLRDY:
122 case MCP251XFD_REG_OSC_OSCRDY:
124 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
125 return "Oscillator/PLL";
131 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
136 return regulator_enable(priv->reg_vdd);
139 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
144 return regulator_disable(priv->reg_vdd);
148 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
150 if (!priv->reg_xceiver)
153 return regulator_enable(priv->reg_xceiver);
157 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
159 if (!priv->reg_xceiver)
162 return regulator_disable(priv->reg_xceiver);
165 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
169 err = clk_prepare_enable(priv->clk);
173 err = mcp251xfd_vdd_enable(priv);
175 clk_disable_unprepare(priv->clk);
177 /* Wait for oscillator stabilisation time after power up */
178 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
179 2 * MCP251XFD_OSC_STAB_SLEEP_US);
184 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
188 err = mcp251xfd_vdd_disable(priv);
192 clk_disable_unprepare(priv->clk);
197 static inline bool mcp251xfd_reg_invalid(u32 reg)
199 return reg == 0x0 || reg == 0xffffffff;
203 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
208 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
212 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
218 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
219 const u8 mode_req, bool nowait)
221 u32 con = 0, con_reqop, osc = 0;
225 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
226 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
227 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
228 if (err == -EBADMSG) {
229 netdev_err(priv->ndev,
230 "Failed to set Requested Operation Mode.\n");
237 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
240 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
241 !mcp251xfd_reg_invalid(con) &&
242 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
244 MCP251XFD_POLL_SLEEP_US,
245 MCP251XFD_POLL_TIMEOUT_US);
246 if (err != -ETIMEDOUT && err != -EBADMSG)
249 /* Ignore return value.
250 * Print below error messages, even if this fails.
252 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
254 if (mcp251xfd_reg_invalid(con)) {
255 netdev_err(priv->ndev,
256 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
262 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
263 netdev_err(priv->ndev,
264 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
265 mcp251xfd_get_mode_str(mode_req), mode_req,
266 mcp251xfd_get_mode_str(mode), mode,
273 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
276 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
279 static inline int __maybe_unused
280 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
283 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
287 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
288 u32 osc_reference, u32 osc_mask)
293 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
294 !mcp251xfd_reg_invalid(osc) &&
295 (osc & osc_mask) == osc_reference,
296 MCP251XFD_OSC_STAB_SLEEP_US,
297 MCP251XFD_OSC_STAB_TIMEOUT_US);
298 if (err != -ETIMEDOUT)
301 if (mcp251xfd_reg_invalid(osc)) {
302 netdev_err(priv->ndev,
303 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
308 netdev_err(priv->ndev,
309 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
310 mcp251xfd_get_osc_str(osc, osc_reference),
311 osc, osc_reference, osc_mask);
316 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
318 u32 osc, osc_reference, osc_mask;
321 /* For normal sleep on MCP2517FD and MCP2518FD, clearing
322 * "Oscillator Disable" will wake the chip. For low power mode
323 * on MCP2518FD, asserting the chip select will wake the
324 * chip. Writing to the Oscillator register will wake it in
327 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
328 MCP251XFD_REG_OSC_CLKODIV_10);
330 /* We cannot check for the PLL ready bit (either set or
331 * unset), as the PLL might be enabled. This can happen if the
332 * system reboots, while the mcp251xfd stays powered.
334 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
335 osc_mask = MCP251XFD_REG_OSC_OSCRDY;
337 /* If the controller is in Sleep Mode the following write only
338 * removes the "Oscillator Disable" bit and powers it up. All
339 * other bits are unaffected.
341 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
345 /* Sometimes the PLL is stuck enabled, the controller never
346 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
347 * caller takes care of retry.
349 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
352 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
354 if (priv->pll_enable) {
359 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
360 MCP251XFD_REG_OSC_CLKODIV_10);
361 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
363 netdev_err(priv->ndev,
364 "Failed to disable PLL.\n");
366 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
369 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
372 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
374 const __be16 cmd = mcp251xfd_cmd_reset();
377 /* The Set Mode and SPI Reset command only works if the
378 * controller is not in Sleep Mode.
380 err = mcp251xfd_chip_wake(priv);
384 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
388 /* spi_write_then_read() works with non DMA-safe buffers */
389 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
392 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
394 u32 osc_reference, osc_mask;
398 /* Check for reset defaults of OSC reg.
399 * This will take care of stabilization period.
401 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
402 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
403 MCP251XFD_REG_OSC_CLKODIV_10);
404 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
405 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
409 err = mcp251xfd_chip_get_mode(priv, &mode);
413 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
414 netdev_info(priv->ndev,
415 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
416 mcp251xfd_get_mode_str(mode), mode);
423 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
427 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
429 netdev_info(priv->ndev,
430 "Retrying to reset controller.\n");
432 err = mcp251xfd_chip_softreset_do(priv);
433 if (err == -ETIMEDOUT)
438 err = mcp251xfd_chip_softreset_check(priv);
439 if (err == -ETIMEDOUT)
450 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
452 u32 osc, osc_reference, osc_mask;
455 /* Activate Low Power Mode on Oscillator Disable. This only
456 * works on the MCP2518FD. The MCP2517FD will go into normal
457 * Sleep Mode instead.
459 osc = MCP251XFD_REG_OSC_LPMEN |
460 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
461 MCP251XFD_REG_OSC_CLKODIV_10);
462 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
463 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
465 if (priv->pll_enable) {
466 osc |= MCP251XFD_REG_OSC_PLLEN;
467 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
470 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
474 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
478 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
483 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
485 /* Set Time Base Counter Prescaler to 1.
487 * This means an overflow of the 32 bit Time Base Counter
488 * register at 40 MHz every 107 seconds.
490 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
491 MCP251XFD_REG_TSCON_TBCEN);
494 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
496 const struct can_bittiming *bt = &priv->can.bittiming;
497 const struct can_bittiming *dbt = &priv->can.data_bittiming;
502 /* CAN Control Register
504 * - no transmit bandwidth sharing
506 * - disable transmit queue
507 * - store in transmit FIFO event
508 * - transition to restricted operation mode on system error
509 * - ESI is transmitted recessive when ESI of message is high or
510 * CAN controller error passive
511 * - restricted retransmission attempts,
512 * use TQXCON_TXAT and FIFOCON_TXAT
513 * - wake-up filter bits T11FILTER
514 * - use CAN bus line filter for wakeup
515 * - protocol exception is treated as a form error
516 * - Do not compare data bytes
518 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
519 MCP251XFD_REG_CON_MODE_CONFIG) |
520 MCP251XFD_REG_CON_STEF |
521 MCP251XFD_REG_CON_ESIGM |
522 MCP251XFD_REG_CON_RTXAT |
523 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
524 MCP251XFD_REG_CON_WFT_T11FILTER) |
525 MCP251XFD_REG_CON_WAKFIL |
526 MCP251XFD_REG_CON_PXEDIS;
528 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
529 val |= MCP251XFD_REG_CON_ISOCRCEN;
531 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
535 /* Nominal Bit Time */
536 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
537 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
538 bt->prop_seg + bt->phase_seg1 - 1) |
539 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
540 bt->phase_seg2 - 1) |
541 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
543 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
547 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
551 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
552 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
553 dbt->prop_seg + dbt->phase_seg1 - 1) |
554 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
555 dbt->phase_seg2 - 1) |
556 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
558 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
562 /* Transmitter Delay Compensation */
563 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
565 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
566 MCP251XFD_REG_TDC_TDCMOD_AUTO) |
567 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
569 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
572 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
581 * - PIN1: GPIO Input/RX Interrupt
583 * PIN1 must be Input, otherwise there is a glitch on the
584 * rx-INT line. It happens between setting the PIN as output
585 * (in the first byte of the SPI transfer) and configuring the
586 * PIN as interrupt (in the last byte of the SPI transfer).
588 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
589 MCP251XFD_REG_IOCON_TRIS0;
590 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
593 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
604 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
605 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
606 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
609 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
611 struct mcp251xfd_ecc *ecc = &priv->ecc;
618 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
619 val = MCP251XFD_REG_ECCCON_ECCEN;
621 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
622 MCP251XFD_REG_ECCCON_ECCEN, val);
626 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
630 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
637 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
641 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
642 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
643 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
644 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
645 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
646 mode = MCP251XFD_REG_CON_MODE_MIXED;
648 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
654 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
659 mode = mcp251xfd_get_normal_mode(priv);
661 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
665 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
667 return __mcp251xfd_chip_set_normal_mode(priv, false);
671 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
673 return __mcp251xfd_chip_set_normal_mode(priv, true);
676 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
681 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
682 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
686 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
687 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
691 val = MCP251XFD_REG_INT_CERRIE |
692 MCP251XFD_REG_INT_SERRIE |
693 MCP251XFD_REG_INT_RXOVIE |
694 MCP251XFD_REG_INT_TXATIE |
695 MCP251XFD_REG_INT_SPICRCIE |
696 MCP251XFD_REG_INT_ECCIE |
697 MCP251XFD_REG_INT_TEFIE |
698 MCP251XFD_REG_INT_MODIE |
699 MCP251XFD_REG_INT_RXIE;
701 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
702 val |= MCP251XFD_REG_INT_IVMIE;
704 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
707 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
712 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
716 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
717 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
722 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
725 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
726 const enum can_state state)
728 priv->can.state = state;
730 mcp251xfd_chip_interrupts_disable(priv);
731 mcp251xfd_chip_rx_int_disable(priv);
732 mcp251xfd_chip_sleep(priv);
735 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
739 err = mcp251xfd_chip_softreset(priv);
743 err = mcp251xfd_chip_clock_init(priv);
747 err = mcp251xfd_chip_timestamp_init(priv);
751 err = mcp251xfd_set_bittiming(priv);
755 err = mcp251xfd_chip_rx_int_enable(priv);
759 err = mcp251xfd_chip_ecc_init(priv);
763 err = mcp251xfd_ring_init(priv);
767 err = mcp251xfd_chip_fifo_init(priv);
771 priv->can.state = CAN_STATE_ERROR_ACTIVE;
773 err = mcp251xfd_chip_set_normal_mode(priv);
780 mcp251xfd_dump(priv);
781 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
786 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
788 struct mcp251xfd_priv *priv = netdev_priv(ndev);
793 err = mcp251xfd_chip_start(priv);
797 err = mcp251xfd_chip_interrupts_enable(priv);
799 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
803 netif_wake_queue(ndev);
813 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
814 struct can_berr_counter *bec)
816 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
820 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
824 if (trec & MCP251XFD_REG_TREC_TXBO)
827 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
828 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
833 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
834 struct can_berr_counter *bec)
836 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
838 /* Avoid waking up the controller if the interface is down */
839 if (!(ndev->flags & IFF_UP))
842 /* The controller is powered down during Bus Off, use saved
845 if (priv->can.state == CAN_STATE_BUS_OFF) {
850 return __mcp251xfd_get_berr_counter(ndev, bec);
853 static struct sk_buff *
854 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
855 struct can_frame **cf, u32 *timestamp)
860 err = mcp251xfd_get_timestamp(priv, timestamp);
864 skb = alloc_can_err_skb(priv->ndev, cf);
866 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp);
871 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
873 struct net_device_stats *stats = &priv->ndev->stats;
874 struct mcp251xfd_rx_ring *ring;
876 struct can_frame *cf;
877 u32 timestamp, rxovif;
880 stats->rx_over_errors++;
883 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
887 mcp251xfd_for_each_rx_ring(priv, ring, i) {
888 if (!(rxovif & BIT(ring->fifo_nr)))
891 /* If SERRIF is active, there was a RX MAB overflow. */
892 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
894 netdev_dbg(priv->ndev,
895 "RX-%d: MAB overflow detected.\n",
899 netdev_dbg(priv->ndev,
900 "RX-%d: FIFO overflow.\n",
904 err = regmap_update_bits(priv->map_reg,
905 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
906 MCP251XFD_REG_FIFOSTA_RXOVIF,
912 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
916 cf->can_id |= CAN_ERR_CRTL;
917 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
919 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
921 stats->rx_fifo_errors++;
926 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
928 netdev_info(priv->ndev, "%s\n", __func__);
933 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
935 struct net_device_stats *stats = &priv->ndev->stats;
936 u32 bdiag1, timestamp;
938 struct can_frame *cf = NULL;
941 err = mcp251xfd_get_timestamp(priv, ×tamp);
945 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
949 /* Write 0s to clear error bits, don't write 1s to non active
950 * bits, as they will be set.
952 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
956 priv->can.can_stats.bus_error++;
958 skb = alloc_can_err_skb(priv->ndev, &cf);
960 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
962 /* Controller misconfiguration */
963 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
964 netdev_err(priv->ndev,
965 "recv'd DLC is larger than PLSIZE of FIFO element.");
968 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
969 MCP251XFD_REG_BDIAG1_NCRCERR)) {
970 netdev_dbg(priv->ndev, "CRC error\n");
974 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
976 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
977 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
978 netdev_dbg(priv->ndev, "Stuff error\n");
982 cf->data[2] |= CAN_ERR_PROT_STUFF;
984 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
985 MCP251XFD_REG_BDIAG1_NFORMERR)) {
986 netdev_dbg(priv->ndev, "Format error\n");
990 cf->data[2] |= CAN_ERR_PROT_FORM;
994 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
995 netdev_dbg(priv->ndev, "NACK error\n");
999 cf->can_id |= CAN_ERR_ACK;
1000 cf->data[2] |= CAN_ERR_PROT_TX;
1003 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1004 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1005 netdev_dbg(priv->ndev, "Bit1 error\n");
1009 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1011 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1012 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1013 netdev_dbg(priv->ndev, "Bit0 error\n");
1017 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1023 mcp251xfd_skb_set_timestamp(priv, skb, timestamp);
1024 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
1026 stats->rx_fifo_errors++;
1031 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1033 struct net_device_stats *stats = &priv->ndev->stats;
1034 struct sk_buff *skb;
1035 struct can_frame *cf = NULL;
1036 enum can_state new_state, rx_state, tx_state;
1037 u32 trec, timestamp;
1040 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1044 if (trec & MCP251XFD_REG_TREC_TXBO)
1045 tx_state = CAN_STATE_BUS_OFF;
1046 else if (trec & MCP251XFD_REG_TREC_TXBP)
1047 tx_state = CAN_STATE_ERROR_PASSIVE;
1048 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1049 tx_state = CAN_STATE_ERROR_WARNING;
1051 tx_state = CAN_STATE_ERROR_ACTIVE;
1053 if (trec & MCP251XFD_REG_TREC_RXBP)
1054 rx_state = CAN_STATE_ERROR_PASSIVE;
1055 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1056 rx_state = CAN_STATE_ERROR_WARNING;
1058 rx_state = CAN_STATE_ERROR_ACTIVE;
1060 new_state = max(tx_state, rx_state);
1061 if (new_state == priv->can.state)
1064 /* The skb allocation might fail, but can_change_state()
1065 * handles cf == NULL.
1067 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp);
1068 can_change_state(priv->ndev, cf, tx_state, rx_state);
1070 if (new_state == CAN_STATE_BUS_OFF) {
1071 /* As we're going to switch off the chip now, let's
1072 * save the error counters and return them to
1073 * userspace, if do_get_berr_counter() is called while
1074 * the chip is in Bus Off.
1076 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1080 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1081 can_bus_off(priv->ndev);
1087 if (new_state != CAN_STATE_BUS_OFF) {
1088 struct can_berr_counter bec;
1090 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1093 cf->data[6] = bec.txerr;
1094 cf->data[7] = bec.rxerr;
1097 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
1099 stats->rx_fifo_errors++;
1105 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1107 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1111 err = mcp251xfd_chip_get_mode(priv, &mode);
1115 if (mode == mode_reference) {
1116 netdev_dbg(priv->ndev,
1117 "Controller changed into %s Mode (%u).\n",
1118 mcp251xfd_get_mode_str(mode), mode);
1122 /* According to MCP2517FD errata DS80000792B 1., during a TX
1123 * MAB underflow, the controller will transition to Restricted
1124 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1126 * However this is not always the case. If SERR2LOM is
1127 * configured for Restricted Operation Mode (SERR2LOM not set)
1128 * the MCP2517FD will sometimes transition to Listen Only Mode
1129 * first. When polling this bit we see that it will transition
1130 * to Restricted Operation Mode shortly after.
1132 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1133 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1134 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1135 netdev_dbg(priv->ndev,
1136 "Controller changed into %s Mode (%u).\n",
1137 mcp251xfd_get_mode_str(mode), mode);
1139 netdev_err(priv->ndev,
1140 "Controller changed into %s Mode (%u).\n",
1141 mcp251xfd_get_mode_str(mode), mode);
1143 /* After the application requests Normal mode, the controller
1144 * will automatically attempt to retransmit the message that
1145 * caused the TX MAB underflow.
1147 * However, if there is an ECC error in the TX-RAM, we first
1148 * have to reload the tx-object before requesting Normal
1149 * mode. This is done later in mcp251xfd_handle_eccif().
1151 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1152 *set_normal_mode = true;
1156 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1159 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1161 struct mcp251xfd_ecc *ecc = &priv->ecc;
1162 struct net_device_stats *stats = &priv->ndev->stats;
1163 bool handled = false;
1167 * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1168 * underflow is indicated by SERRIF and MODIF.
1170 * In addition to the effects mentioned in the Errata, there
1171 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1172 * will be seen as well.
1174 * Sometimes there is an ECC error in the TX-RAM, which leads
1175 * to a TX MAB underflow.
1177 * However, probably due to a race condition, there is no
1178 * associated MODIF pending.
1180 * Further, there are situations, where the SERRIF is caused
1181 * by an ECC error in the TX-RAM, but not even the ECCIF is
1182 * set. This only seems to happen _after_ the first occurrence
1183 * of a ECCIF (which is tracked in ecc->cnt).
1185 * Treat all as a known system errors..
1187 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1188 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1189 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1193 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1195 msg = "TX MAB underflow due to ECC error detected.";
1197 msg = "TX MAB underflow detected.";
1199 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1200 netdev_dbg(priv->ndev, "%s\n", msg);
1202 netdev_info(priv->ndev, "%s\n", msg);
1204 stats->tx_aborted_errors++;
1211 * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1212 * overflow is indicated by SERRIF.
1214 * In addition to the effects mentioned in the Errata, (most
1215 * of the times) a RXOVIF is raised, if the FIFO that is being
1216 * received into has the RXOVIE activated (and we have enabled
1217 * RXOVIE on all FIFOs).
1219 * Sometimes there is no RXOVIF just a RXIF is pending.
1221 * Treat all as a known system errors..
1223 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1224 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1225 stats->rx_dropped++;
1230 netdev_err(priv->ndev,
1231 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1232 priv->regs_status.intf);
1238 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1240 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1241 struct mcp251xfd_ecc *ecc = &priv->ecc;
1242 struct mcp251xfd_tx_obj *tx_obj;
1243 u8 chip_tx_tail, tx_tail, offset;
1247 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1249 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1253 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1254 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1256 /* Bail out if one of the following is met:
1257 * - tx_tail information is inconsistent
1258 * - for mcp2517fd: offset not 0
1259 * - for mcp2518fd: offset not 0 or 1
1261 if (chip_tx_tail != tx_tail ||
1262 !(offset == 0 || (offset == 1 && mcp251xfd_is_2518(priv)))) {
1263 netdev_err(priv->ndev,
1264 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1265 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1270 netdev_info(priv->ndev,
1271 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1272 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1273 "Single" : "Double",
1274 addr, nr, tx_ring->tail, tx_tail, offset);
1276 /* reload tx_obj into controller RAM ... */
1277 tx_obj = &tx_ring->obj[nr];
1278 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1282 /* ... and trigger retransmit */
1283 return mcp251xfd_chip_set_normal_mode(priv);
1287 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1289 struct mcp251xfd_ecc *ecc = &priv->ecc;
1297 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1301 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1302 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1306 /* Check if ECC error occurred in TX-RAM */
1307 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1308 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1311 else if (err == -ENOENT)
1316 /* Errata Reference:
1317 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1319 * ECC single error correction does not work in all cases:
1322 * Enable single error correction and double error detection
1323 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1324 * detection interrupt and do not rely on the error
1325 * correction. Instead, handle both interrupts as a
1326 * notification that the RAM word at ERRADDR was corrupted.
1328 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1329 msg = "Single ECC Error detected at address";
1330 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1331 msg = "Double ECC Error detected at address";
1338 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1340 /* Re-occurring error? */
1341 if (ecc->ecc_stat == ecc_stat) {
1344 ecc->ecc_stat = ecc_stat;
1348 netdev_info(priv->ndev,
1349 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1350 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1352 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1353 return mcp251xfd_handle_eccif_recover(priv, nr);
1356 if (set_normal_mode)
1357 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1362 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1367 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1371 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1372 MCP251XFD_REG_CRC_IF_MASK,
1377 if (crc & MCP251XFD_REG_CRC_FERRIF)
1378 netdev_notice(priv->ndev, "CRC write command format error.\n");
1379 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1380 netdev_notice(priv->ndev,
1381 "CRC write error detected. CRC=0x%04lx.\n",
1382 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1387 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1389 const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1392 if (priv->rx_ring_num == 1)
1393 len = sizeof(priv->regs_status.intf);
1395 len = sizeof(priv->regs_status);
1397 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1398 &priv->regs_status, len / val_bytes);
1401 #define mcp251xfd_handle(priv, irq, ...) \
1403 struct mcp251xfd_priv *_priv = (priv); \
1406 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1408 netdev_err(_priv->ndev, \
1409 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1410 __stringify(irq), err); \
1414 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1416 struct mcp251xfd_priv *priv = dev_id;
1417 irqreturn_t handled = IRQ_NONE;
1424 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1428 /* Assume 1st RX-FIFO pending, if other FIFOs
1429 * are pending the main IRQ handler will take
1432 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1433 err = mcp251xfd_handle(priv, rxif);
1437 handled = IRQ_HANDLED;
1439 /* We don't know which RX-FIFO is pending, but only
1440 * handle the 1st RX-FIFO. Leave loop here if we have
1441 * more than 1 RX-FIFO to avoid starvation.
1443 } while (priv->rx_ring_num == 1);
1446 u32 intf_pending, intf_pending_clearable;
1447 bool set_normal_mode = false;
1449 err = mcp251xfd_read_regs_status(priv);
1453 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1454 priv->regs_status.intf) &
1455 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1456 priv->regs_status.intf);
1458 if (!(intf_pending)) {
1459 can_rx_offload_threaded_irq_finish(&priv->offload);
1463 /* Some interrupts must be ACKed in the
1464 * MCP251XFD_REG_INT register.
1465 * - First ACK then handle, to avoid lost-IRQ race
1466 * condition on fast re-occurring interrupts.
1467 * - Write "0" to clear active IRQs, "1" to all other,
1468 * to avoid r/m/w race condition on the
1469 * MCP251XFD_REG_INT register.
1471 intf_pending_clearable = intf_pending &
1472 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1473 if (intf_pending_clearable) {
1474 err = regmap_update_bits(priv->map_reg,
1476 MCP251XFD_REG_INT_IF_MASK,
1477 ~intf_pending_clearable);
1482 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1483 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1488 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1489 err = mcp251xfd_handle(priv, rxif);
1494 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1495 err = mcp251xfd_handle(priv, tefif);
1500 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1501 err = mcp251xfd_handle(priv, rxovif);
1506 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1507 err = mcp251xfd_handle(priv, txatif);
1512 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1513 err = mcp251xfd_handle(priv, ivmif);
1518 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1519 err = mcp251xfd_handle(priv, serrif);
1524 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1525 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1530 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1531 err = mcp251xfd_handle(priv, spicrcif);
1536 /* On the MCP2527FD and MCP2518FD, we don't get a
1537 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1540 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1541 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1542 err = mcp251xfd_handle(priv, cerrif);
1546 /* In Bus Off we completely shut down the
1547 * controller. Every subsequent register read
1548 * will read bogus data, and if
1549 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1550 * check will fail, too. So leave IRQ handler
1553 if (priv->can.state == CAN_STATE_BUS_OFF) {
1554 can_rx_offload_threaded_irq_finish(&priv->offload);
1559 handled = IRQ_HANDLED;
1563 can_rx_offload_threaded_irq_finish(&priv->offload);
1565 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1566 err, priv->regs_status.intf);
1567 mcp251xfd_dump(priv);
1568 mcp251xfd_chip_interrupts_disable(priv);
1569 mcp251xfd_timestamp_stop(priv);
1574 static int mcp251xfd_open(struct net_device *ndev)
1576 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1577 const struct spi_device *spi = priv->spi;
1580 err = open_candev(ndev);
1584 err = pm_runtime_resume_and_get(ndev->dev.parent);
1586 goto out_close_candev;
1588 err = mcp251xfd_ring_alloc(priv);
1590 goto out_pm_runtime_put;
1592 err = mcp251xfd_transceiver_enable(priv);
1594 goto out_mcp251xfd_ring_free;
1596 err = mcp251xfd_chip_start(priv);
1598 goto out_transceiver_disable;
1600 mcp251xfd_timestamp_init(priv);
1601 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1602 can_rx_offload_enable(&priv->offload);
1604 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1605 IRQF_SHARED | IRQF_ONESHOT,
1606 dev_name(&spi->dev), priv);
1608 goto out_can_rx_offload_disable;
1610 err = mcp251xfd_chip_interrupts_enable(priv);
1614 netif_start_queue(ndev);
1619 free_irq(spi->irq, priv);
1620 out_can_rx_offload_disable:
1621 can_rx_offload_disable(&priv->offload);
1622 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1623 mcp251xfd_timestamp_stop(priv);
1624 out_transceiver_disable:
1625 mcp251xfd_transceiver_disable(priv);
1626 out_mcp251xfd_ring_free:
1627 mcp251xfd_ring_free(priv);
1629 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1630 pm_runtime_put(ndev->dev.parent);
1637 static int mcp251xfd_stop(struct net_device *ndev)
1639 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1641 netif_stop_queue(ndev);
1642 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1643 hrtimer_cancel(&priv->rx_irq_timer);
1644 mcp251xfd_chip_interrupts_disable(priv);
1645 free_irq(ndev->irq, priv);
1646 can_rx_offload_disable(&priv->offload);
1647 mcp251xfd_timestamp_stop(priv);
1648 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1649 mcp251xfd_transceiver_disable(priv);
1650 mcp251xfd_ring_free(priv);
1653 pm_runtime_put(ndev->dev.parent);
1658 static const struct net_device_ops mcp251xfd_netdev_ops = {
1659 .ndo_open = mcp251xfd_open,
1660 .ndo_stop = mcp251xfd_stop,
1661 .ndo_start_xmit = mcp251xfd_start_xmit,
1662 .ndo_change_mtu = can_change_mtu,
1666 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1668 const struct spi_device *spi = priv->spi;
1669 const struct spi_controller *ctlr = spi->controller;
1671 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1672 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1675 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1677 const struct net_device *ndev = priv->ndev;
1678 const struct mcp251xfd_devtype_data *devtype_data;
1682 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to
1683 * autodetect the model.
1685 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1686 MCP251XFD_REG_OSC_LPMEN,
1687 MCP251XFD_REG_OSC_LPMEN);
1691 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1695 if (osc & MCP251XFD_REG_OSC_LPMEN)
1696 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1698 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1700 if (!mcp251xfd_is_251X(priv) &&
1701 priv->devtype_data.model != devtype_data->model) {
1703 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1704 __mcp251xfd_get_model_str(devtype_data->model),
1705 mcp251xfd_get_model_str(priv));
1707 priv->devtype_data = *devtype_data;
1709 /* We need to preserve the Half Duplex Quirk. */
1710 mcp251xfd_register_quirks(priv);
1712 /* Re-init regmap with quirks of detected model. */
1713 return mcp251xfd_regmap_init(priv);
1716 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1718 int err, rx_pending;
1723 err = mcp251xfd_chip_rx_int_enable(priv);
1727 /* Check if RX_INT is properly working. The RX_INT should not
1728 * be active after a softreset.
1730 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1732 err = mcp251xfd_chip_rx_int_disable(priv);
1739 netdev_info(priv->ndev,
1740 "RX_INT active after softreset, disabling RX_INT support.\n");
1741 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1742 priv->rx_int = NULL;
1748 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1749 u32 *effective_speed_hz_slow,
1750 u32 *effective_speed_hz_fast)
1752 struct mcp251xfd_map_buf_nocrc *buf_rx;
1753 struct mcp251xfd_map_buf_nocrc *buf_tx;
1754 struct spi_transfer xfer[2] = { };
1757 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1761 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1764 goto out_kfree_buf_rx;
1767 xfer[0].tx_buf = buf_tx;
1768 xfer[0].len = sizeof(buf_tx->cmd);
1769 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1770 xfer[1].rx_buf = buf_rx->data;
1771 xfer[1].len = sizeof(dev_id);
1772 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1774 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1776 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1778 goto out_kfree_buf_tx;
1780 *dev_id = be32_to_cpup((__be32 *)buf_rx->data);
1781 *effective_speed_hz_slow = xfer[0].effective_speed_hz;
1782 *effective_speed_hz_fast = xfer[1].effective_speed_hz;
1792 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
1793 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1796 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1798 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1799 unsigned long clk_rate;
1802 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1803 &effective_speed_hz_slow,
1804 &effective_speed_hz_fast);
1808 clk_rate = clk_get_rate(priv->clk);
1810 netdev_info(priv->ndev,
1811 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1812 mcp251xfd_get_model_str(priv),
1813 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1814 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1815 priv->rx_int ? '+' : '-',
1816 priv->pll_enable ? '+' : '-',
1817 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1818 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1819 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1820 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1821 MCP251XFD_QUIRK_ACTIVE(ECC),
1822 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1824 clk_rate % 1000000 / 1000 / 10,
1825 priv->can.clock.freq / 1000000,
1826 priv->can.clock.freq % 1000000 / 1000 / 10,
1827 priv->spi_max_speed_hz_orig / 1000000,
1828 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1829 priv->spi_max_speed_hz_slow / 1000000,
1830 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1831 effective_speed_hz_slow / 1000000,
1832 effective_speed_hz_slow % 1000000 / 1000 / 10,
1833 priv->spi_max_speed_hz_fast / 1000000,
1834 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1835 effective_speed_hz_fast / 1000000,
1836 effective_speed_hz_fast % 1000000 / 1000 / 10);
1841 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1843 struct net_device *ndev = priv->ndev;
1846 err = mcp251xfd_clks_and_vdd_enable(priv);
1850 pm_runtime_get_noresume(ndev->dev.parent);
1851 err = pm_runtime_set_active(ndev->dev.parent);
1853 goto out_runtime_put_noidle;
1854 pm_runtime_enable(ndev->dev.parent);
1856 mcp251xfd_register_quirks(priv);
1858 err = mcp251xfd_chip_softreset(priv);
1860 goto out_runtime_disable;
1862 goto out_chip_sleep;
1864 err = mcp251xfd_chip_clock_init(priv);
1866 goto out_runtime_disable;
1868 goto out_chip_sleep;
1870 err = mcp251xfd_register_chip_detect(priv);
1872 goto out_chip_sleep;
1874 err = mcp251xfd_register_check_rx_int(priv);
1876 goto out_chip_sleep;
1878 mcp251xfd_ethtool_init(priv);
1880 err = register_candev(ndev);
1882 goto out_chip_sleep;
1884 err = mcp251xfd_register_done(priv);
1886 goto out_unregister_candev;
1888 /* Put controller into sleep mode and let pm_runtime_put()
1889 * disable the clocks and vdd. If CONFIG_PM is not enabled,
1890 * the clocks and vdd will stay powered.
1892 err = mcp251xfd_chip_sleep(priv);
1894 goto out_unregister_candev;
1896 pm_runtime_put(ndev->dev.parent);
1900 out_unregister_candev:
1901 unregister_candev(ndev);
1903 mcp251xfd_chip_sleep(priv);
1904 out_runtime_disable:
1905 pm_runtime_disable(ndev->dev.parent);
1906 out_runtime_put_noidle:
1907 pm_runtime_put_noidle(ndev->dev.parent);
1908 mcp251xfd_clks_and_vdd_disable(priv);
1913 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1915 struct net_device *ndev = priv->ndev;
1917 unregister_candev(ndev);
1919 if (pm_runtime_enabled(ndev->dev.parent))
1920 pm_runtime_disable(ndev->dev.parent);
1922 mcp251xfd_clks_and_vdd_disable(priv);
1925 static const struct of_device_id mcp251xfd_of_match[] = {
1927 .compatible = "microchip,mcp2517fd",
1928 .data = &mcp251xfd_devtype_data_mcp2517fd,
1930 .compatible = "microchip,mcp2518fd",
1931 .data = &mcp251xfd_devtype_data_mcp2518fd,
1933 .compatible = "microchip,mcp251xfd",
1934 .data = &mcp251xfd_devtype_data_mcp251xfd,
1939 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
1941 static const struct spi_device_id mcp251xfd_id_table[] = {
1943 .name = "mcp2517fd",
1944 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
1946 .name = "mcp2518fd",
1947 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
1949 .name = "mcp251xfd",
1950 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
1955 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
1957 static int mcp251xfd_probe(struct spi_device *spi)
1960 struct net_device *ndev;
1961 struct mcp251xfd_priv *priv;
1962 struct gpio_desc *rx_int;
1963 struct regulator *reg_vdd, *reg_xceiver;
1965 bool pll_enable = false;
1970 return dev_err_probe(&spi->dev, -ENXIO,
1971 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
1973 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
1976 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
1977 "Failed to get RX-INT!\n");
1979 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
1980 if (PTR_ERR(reg_vdd) == -ENODEV)
1982 else if (IS_ERR(reg_vdd))
1983 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
1984 "Failed to get VDD regulator!\n");
1986 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1987 if (PTR_ERR(reg_xceiver) == -ENODEV)
1989 else if (IS_ERR(reg_xceiver))
1990 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
1991 "Failed to get Transceiver regulator!\n");
1993 clk = devm_clk_get_optional(&spi->dev, NULL);
1995 return dev_err_probe(&spi->dev, PTR_ERR(clk),
1996 "Failed to get Oscillator (clock)!\n");
1998 freq = clk_get_rate(clk);
2000 err = device_property_read_u32(&spi->dev, "clock-frequency",
2003 return dev_err_probe(&spi->dev, err,
2004 "Failed to get clock-frequency!\n");
2008 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2009 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2011 "Oscillator frequency (%u Hz) is too low or high.\n",
2016 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2019 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2020 MCP251XFD_TX_OBJ_NUM_MAX);
2024 SET_NETDEV_DEV(ndev, &spi->dev);
2026 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2027 ndev->irq = spi->irq;
2028 ndev->flags |= IFF_ECHO;
2030 priv = netdev_priv(ndev);
2031 spi_set_drvdata(spi, priv);
2032 priv->can.clock.freq = freq;
2034 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2035 priv->can.do_set_mode = mcp251xfd_set_mode;
2036 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2037 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2038 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2039 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2040 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2041 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2042 CAN_CTRLMODE_CC_LEN8_DLC;
2043 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2046 priv->rx_int = rx_int;
2048 priv->pll_enable = pll_enable;
2049 priv->reg_vdd = reg_vdd;
2050 priv->reg_xceiver = reg_xceiver;
2052 match = device_get_match_data(&spi->dev);
2054 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2056 priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2057 spi_get_device_id(spi)->driver_data;
2059 /* Errata Reference:
2060 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4.
2062 * The SPI can write corrupted data to the RAM at fast SPI
2065 * Simultaneous activity on the CAN bus while writing data to
2066 * RAM via the SPI interface, with high SCK frequency, can
2067 * lead to corrupted data being written to RAM.
2070 * Ensure that FSCK is less than or equal to 0.85 *
2073 * Known good combinations are:
2075 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2077 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2078 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2079 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2080 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2081 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2082 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2085 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2086 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2087 freq / 2 / 1000 * 850);
2088 if (priv->pll_enable)
2089 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2091 MCP251XFD_OSC_PLL_MULTIPLIER /
2094 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2095 spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2096 spi->bits_per_word = 8;
2098 err = spi_setup(spi);
2100 goto out_free_candev;
2102 err = mcp251xfd_regmap_init(priv);
2104 goto out_free_candev;
2106 err = can_rx_offload_add_manual(ndev, &priv->offload,
2107 MCP251XFD_NAPI_WEIGHT);
2109 goto out_free_candev;
2111 err = mcp251xfd_register(priv);
2113 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2114 mcp251xfd_get_model_str(priv));
2115 goto out_can_rx_offload_del;
2120 out_can_rx_offload_del:
2121 can_rx_offload_del(&priv->offload);
2123 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2130 static void mcp251xfd_remove(struct spi_device *spi)
2132 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2133 struct net_device *ndev = priv->ndev;
2135 can_rx_offload_del(&priv->offload);
2136 mcp251xfd_unregister(priv);
2137 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2141 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2143 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2145 return mcp251xfd_clks_and_vdd_disable(priv);
2148 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2150 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2152 return mcp251xfd_clks_and_vdd_enable(priv);
2155 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2156 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2157 mcp251xfd_runtime_resume, NULL)
2160 static struct spi_driver mcp251xfd_driver = {
2162 .name = DEVICE_NAME,
2163 .pm = &mcp251xfd_pm_ops,
2164 .of_match_table = mcp251xfd_of_match,
2166 .probe = mcp251xfd_probe,
2167 .remove = mcp251xfd_remove,
2168 .id_table = mcp251xfd_id_table,
2170 module_spi_driver(mcp251xfd_driver);
2172 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2173 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2174 MODULE_LICENSE("GPL v2");