2 * at91_can.c - CAN network driver for AT91 SoC CAN controller
4 * (C) 2007 by Hans J. Koch <hjk@linutronix.de>
5 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
7 * This software may be distributed under the terms of the GNU General
8 * Public License ("GPL") version 2 as distributed in the 'COPYING'
9 * file from the main directory of the linux kernel source.
11 * Send feedback to <socketcan-users@lists.berlios.de>
14 * Your platform definition file should specify something like:
16 * static struct at91_can_data ek_can_data = {
17 * transceiver_switch = sam9263ek_transceiver_switch,
20 * at91_add_device_can(&ek_can_data);
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <linux/if_arp.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/platform_device.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
35 #include <linux/string.h>
36 #include <linux/types.h>
38 #include <linux/can.h>
39 #include <linux/can/dev.h>
40 #include <linux/can/error.h>
42 #include <mach/board.h>
44 #define DRV_NAME "at91_can"
45 #define AT91_NAPI_WEIGHT 12
51 #define AT91_MB_RX_NUM 12
52 #define AT91_MB_TX_SHIFT 2
54 #define AT91_MB_RX_FIRST 0
55 #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
57 #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
58 #define AT91_MB_RX_SPLIT 8
59 #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
60 #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT))
62 #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
63 #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
64 #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
66 #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
67 #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
68 #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
69 #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
71 /* Common registers */
86 /* Mailbox registers (0 <= i <= 15) */
87 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
88 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
89 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
90 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
91 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
92 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
93 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
94 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
97 #define AT91_MR_CANEN BIT(0)
98 #define AT91_MR_LPM BIT(1)
99 #define AT91_MR_ABM BIT(2)
100 #define AT91_MR_OVL BIT(3)
101 #define AT91_MR_TEOF BIT(4)
102 #define AT91_MR_TTM BIT(5)
103 #define AT91_MR_TIMFRZ BIT(6)
104 #define AT91_MR_DRPT BIT(7)
106 #define AT91_SR_RBSY BIT(29)
108 #define AT91_MMR_PRIO_SHIFT (16)
110 #define AT91_MID_MIDE BIT(29)
112 #define AT91_MSR_MRTR BIT(20)
113 #define AT91_MSR_MABT BIT(22)
114 #define AT91_MSR_MRDY BIT(23)
115 #define AT91_MSR_MMI BIT(24)
117 #define AT91_MCR_MRTR BIT(20)
118 #define AT91_MCR_MTCR BIT(23)
122 AT91_MB_MODE_DISABLED = 0,
124 AT91_MB_MODE_RX_OVRWR = 2,
126 AT91_MB_MODE_CONSUMER = 4,
127 AT91_MB_MODE_PRODUCER = 5,
130 /* Interrupt mask bits */
131 #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
132 - (1 << AT91_MB_RX_FIRST))
133 #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
134 - (1 << AT91_MB_TX_FIRST))
135 #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
137 #define AT91_IRQ_ERRA (1 << 16)
138 #define AT91_IRQ_WARN (1 << 17)
139 #define AT91_IRQ_ERRP (1 << 18)
140 #define AT91_IRQ_BOFF (1 << 19)
141 #define AT91_IRQ_SLEEP (1 << 20)
142 #define AT91_IRQ_WAKEUP (1 << 21)
143 #define AT91_IRQ_TOVF (1 << 22)
144 #define AT91_IRQ_TSTP (1 << 23)
145 #define AT91_IRQ_CERR (1 << 24)
146 #define AT91_IRQ_SERR (1 << 25)
147 #define AT91_IRQ_AERR (1 << 26)
148 #define AT91_IRQ_FERR (1 << 27)
149 #define AT91_IRQ_BERR (1 << 28)
151 #define AT91_IRQ_ERR_ALL (0x1fff0000)
152 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
153 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
154 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
155 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
157 #define AT91_IRQ_ALL (0x1fffffff)
160 struct can_priv can; /* must be the first member! */
161 struct net_device *dev;
162 struct napi_struct napi;
164 void __iomem *reg_base;
167 unsigned int tx_next;
168 unsigned int tx_echo;
169 unsigned int rx_next;
172 struct at91_can_data *pdata;
175 static struct can_bittiming_const at91_bittiming_const = {
186 static inline int get_tx_next_mb(const struct at91_priv *priv)
188 return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
191 static inline int get_tx_next_prio(const struct at91_priv *priv)
193 return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
196 static inline int get_tx_echo_mb(const struct at91_priv *priv)
198 return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
201 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
203 return readl(priv->reg_base + reg);
206 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
209 writel(value, priv->reg_base + reg);
212 static inline void set_mb_mode_prio(const struct at91_priv *priv,
213 unsigned int mb, enum at91_mb_mode mode, int prio)
215 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
218 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
219 enum at91_mb_mode mode)
221 set_mb_mode_prio(priv, mb, mode, 0);
225 * Swtich transceiver on or off
227 static void at91_transceiver_switch(const struct at91_priv *priv, int on)
229 if (priv->pdata && priv->pdata->transceiver_switch)
230 priv->pdata->transceiver_switch(on);
233 static void at91_setup_mailboxes(struct net_device *dev)
235 struct at91_priv *priv = netdev_priv(dev);
239 * The first 12 mailboxes are used as a reception FIFO. The
240 * last mailbox is configured with overwrite option. The
241 * overwrite flag indicates a FIFO overflow.
243 for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
244 set_mb_mode(priv, i, AT91_MB_MODE_RX);
245 set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
247 /* The last 4 mailboxes are used for transmitting. */
248 for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
249 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
251 /* Reset tx and rx helper pointers */
252 priv->tx_next = priv->tx_echo = priv->rx_next = 0;
255 static int at91_set_bittiming(struct net_device *dev)
257 const struct at91_priv *priv = netdev_priv(dev);
258 const struct can_bittiming *bt = &priv->can.bittiming;
261 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) << 24) |
262 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
263 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
264 ((bt->phase_seg2 - 1) << 0);
266 dev_info(dev->dev.parent, "writing AT91_BR: 0x%08x\n", reg_br);
268 at91_write(priv, AT91_BR, reg_br);
273 static void at91_chip_start(struct net_device *dev)
275 struct at91_priv *priv = netdev_priv(dev);
278 /* disable interrupts */
279 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
282 reg_mr = at91_read(priv, AT91_MR);
283 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
285 at91_setup_mailboxes(dev);
286 at91_transceiver_switch(priv, 1);
289 at91_write(priv, AT91_MR, AT91_MR_CANEN);
291 priv->can.state = CAN_STATE_ERROR_ACTIVE;
293 /* Enable interrupts */
294 reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
295 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
296 at91_write(priv, AT91_IER, reg_ier);
299 static void at91_chip_stop(struct net_device *dev, enum can_state state)
301 struct at91_priv *priv = netdev_priv(dev);
304 /* disable interrupts */
305 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
307 reg_mr = at91_read(priv, AT91_MR);
308 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
310 at91_transceiver_switch(priv, 0);
311 priv->can.state = state;
315 * theory of operation:
317 * According to the datasheet priority 0 is the highest priority, 15
318 * is the lowest. If two mailboxes have the same priority level the
319 * message of the mailbox with the lowest number is sent first.
321 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
322 * the next mailbox with prio 0, and so on, until all mailboxes are
323 * used. Then we start from the beginning with mailbox
324 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
325 * prio 1. When we reach the last mailbox with prio 15, we have to
326 * stop sending, waiting for all messages to be delivered, then start
327 * again with mailbox AT91_MB_TX_FIRST prio 0.
329 * We use the priv->tx_next as counter for the next transmission
330 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
331 * encode the mailbox number, the upper 4 bits the mailbox priority:
333 * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) ||
334 * (mb - AT91_MB_TX_FIRST);
337 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
339 struct at91_priv *priv = netdev_priv(dev);
340 struct net_device_stats *stats = &dev->stats;
341 struct can_frame *cf = (struct can_frame *)skb->data;
342 unsigned int mb, prio;
343 u32 reg_mid, reg_mcr;
345 mb = get_tx_next_mb(priv);
346 prio = get_tx_next_prio(priv);
348 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
349 netif_stop_queue(dev);
351 dev_err(dev->dev.parent,
352 "BUG! TX buffer full when queue awake!\n");
353 return NETDEV_TX_BUSY;
356 if (cf->can_id & CAN_EFF_FLAG)
357 reg_mid = (cf->can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
359 reg_mid = (cf->can_id & CAN_SFF_MASK) << 18;
361 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
362 (cf->can_dlc << 16) | AT91_MCR_MTCR;
364 /* disable MB while writing ID (see datasheet) */
365 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
366 at91_write(priv, AT91_MID(mb), reg_mid);
367 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
369 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
370 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
372 /* This triggers transmission */
373 at91_write(priv, AT91_MCR(mb), reg_mcr);
375 stats->tx_bytes += cf->can_dlc;
376 dev->trans_start = jiffies;
378 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
379 can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
382 * we have to stop the queue and deliver all messages in case
383 * of a prio+mb counter wrap around. This is the case if
384 * tx_next buffer prio and mailbox equals 0.
386 * also stop the queue if next buffer is still in use
390 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
392 (priv->tx_next & AT91_NEXT_MASK) == 0)
393 netif_stop_queue(dev);
395 /* Enable interrupt for this mailbox */
396 at91_write(priv, AT91_IER, 1 << mb);
402 * at91_activate_rx_low - activate lower rx mailboxes
405 * Reenables the lower mailboxes for reception of new CAN messages
407 static inline void at91_activate_rx_low(const struct at91_priv *priv)
409 u32 mask = AT91_MB_RX_LOW_MASK;
410 at91_write(priv, AT91_TCR, mask);
414 * at91_activate_rx_mb - reactive single rx mailbox
416 * @mb: mailbox to reactivate
418 * Reenables given mailbox for reception of new CAN messages
420 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
424 at91_write(priv, AT91_TCR, mask);
428 * at91_rx_overflow_err - send error frame due to rx overflow
431 static void at91_rx_overflow_err(struct net_device *dev)
433 struct net_device_stats *stats = &dev->stats;
435 struct can_frame *cf;
437 dev_dbg(dev->dev.parent, "RX buffer overflow\n");
438 stats->rx_over_errors++;
441 skb = alloc_can_err_skb(dev, &cf);
445 cf->can_id |= CAN_ERR_CRTL;
446 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
447 netif_receive_skb(skb);
450 stats->rx_bytes += cf->can_dlc;
454 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
456 * @mb: mailbox number to read from
457 * @cf: can frame where to store message
459 * Reads a CAN message from the given mailbox and stores data into
460 * given can frame. "mb" and "cf" must be valid.
462 static void at91_read_mb(struct net_device *dev, unsigned int mb,
463 struct can_frame *cf)
465 const struct at91_priv *priv = netdev_priv(dev);
466 u32 reg_msr, reg_mid;
468 reg_mid = at91_read(priv, AT91_MID(mb));
469 if (reg_mid & AT91_MID_MIDE)
470 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
472 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
474 reg_msr = at91_read(priv, AT91_MSR(mb));
475 if (reg_msr & AT91_MSR_MRTR)
476 cf->can_id |= CAN_RTR_FLAG;
477 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
479 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
480 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
482 if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
483 at91_rx_overflow_err(dev);
487 * at91_read_msg - read CAN message from mailbox
489 * @mb: mail box to read from
491 * Reads a CAN message from given mailbox, and put into linux network
492 * RX queue, does all housekeeping chores (stats, ...)
494 static void at91_read_msg(struct net_device *dev, unsigned int mb)
496 struct net_device_stats *stats = &dev->stats;
497 struct can_frame *cf;
500 skb = alloc_can_skb(dev, &cf);
501 if (unlikely(!skb)) {
506 at91_read_mb(dev, mb, cf);
507 netif_receive_skb(skb);
510 stats->rx_bytes += cf->can_dlc;
514 * at91_poll_rx - read multiple CAN messages from mailboxes
516 * @quota: max number of pkgs we're allowed to receive
518 * Theory of Operation:
520 * 12 of the 16 mailboxes on the chip are reserved for RX. we split
521 * them into 2 groups. The lower group holds 8 and upper 4 mailboxes.
523 * Like it or not, but the chip always saves a received CAN message
524 * into the first free mailbox it finds (starting with the
525 * lowest). This makes it very difficult to read the messages in the
526 * right order from the chip. This is how we work around that problem:
528 * The first message goes into mb nr. 0 and issues an interrupt. All
529 * rx ints are disabled in the interrupt handler and a napi poll is
530 * scheduled. We read the mailbox, but do _not_ reenable the mb (to
531 * receive another message).
534 * ______^______ __^__
536 * +-+-+-+-+-+-+-+-++-+-+-+-+
537 * |x|x|x|x|x|x|x|x|| | | | |
538 * +-+-+-+-+-+-+-+-++-+-+-+-+
539 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
540 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
542 * The variable priv->rx_next points to the next mailbox to read a
543 * message from. As long we're in the lower mailboxes we just read the
544 * mailbox but not reenable it.
546 * With completion of the last of the lower mailboxes, we reenable the
547 * whole first group, but continue to look for filled mailboxes in the
548 * upper mailboxes. Imagine the second group like overflow mailboxes,
549 * which takes CAN messages if the lower goup is full. While in the
550 * upper group we reenable the mailbox right after reading it. Giving
551 * the chip more room to store messages.
553 * After finishing we look again in the lower group if we've still
557 static int at91_poll_rx(struct net_device *dev, int quota)
559 struct at91_priv *priv = netdev_priv(dev);
560 u32 reg_sr = at91_read(priv, AT91_SR);
561 const unsigned long *addr = (unsigned long *)®_sr;
565 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
566 reg_sr & AT91_MB_RX_LOW_MASK)
567 dev_info(dev->dev.parent,
568 "order of incoming frames cannot be guaranteed\n");
571 for (mb = find_next_bit(addr, AT91_MB_RX_NUM, priv->rx_next);
572 mb < AT91_MB_RX_NUM && quota > 0;
573 reg_sr = at91_read(priv, AT91_SR),
574 mb = find_next_bit(addr, AT91_MB_RX_NUM, ++priv->rx_next)) {
575 at91_read_msg(dev, mb);
577 /* reactivate mailboxes */
578 if (mb == AT91_MB_RX_LOW_LAST)
579 /* all lower mailboxed, if just finished it */
580 at91_activate_rx_low(priv);
581 else if (mb > AT91_MB_RX_LOW_LAST)
582 /* only the mailbox we read */
583 at91_activate_rx_mb(priv, mb);
589 /* upper group completed, look again in lower */
590 if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
591 quota > 0 && mb >= AT91_MB_RX_NUM) {
599 static void at91_poll_err_frame(struct net_device *dev,
600 struct can_frame *cf, u32 reg_sr)
602 struct at91_priv *priv = netdev_priv(dev);
605 if (reg_sr & AT91_IRQ_CERR) {
606 dev_dbg(dev->dev.parent, "CERR irq\n");
607 dev->stats.rx_errors++;
608 priv->can.can_stats.bus_error++;
609 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
613 if (reg_sr & AT91_IRQ_SERR) {
614 dev_dbg(dev->dev.parent, "SERR irq\n");
615 dev->stats.rx_errors++;
616 priv->can.can_stats.bus_error++;
617 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
618 cf->data[2] |= CAN_ERR_PROT_STUFF;
621 /* Acknowledgement Error */
622 if (reg_sr & AT91_IRQ_AERR) {
623 dev_dbg(dev->dev.parent, "AERR irq\n");
624 dev->stats.tx_errors++;
625 cf->can_id |= CAN_ERR_ACK;
629 if (reg_sr & AT91_IRQ_FERR) {
630 dev_dbg(dev->dev.parent, "FERR irq\n");
631 dev->stats.rx_errors++;
632 priv->can.can_stats.bus_error++;
633 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
634 cf->data[2] |= CAN_ERR_PROT_FORM;
638 if (reg_sr & AT91_IRQ_BERR) {
639 dev_dbg(dev->dev.parent, "BERR irq\n");
640 dev->stats.tx_errors++;
641 priv->can.can_stats.bus_error++;
642 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
643 cf->data[2] |= CAN_ERR_PROT_BIT;
647 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
650 struct can_frame *cf;
655 skb = alloc_can_err_skb(dev, &cf);
659 at91_poll_err_frame(dev, cf, reg_sr);
660 netif_receive_skb(skb);
662 dev->last_rx = jiffies;
663 dev->stats.rx_packets++;
664 dev->stats.rx_bytes += cf->can_dlc;
669 static int at91_poll(struct napi_struct *napi, int quota)
671 struct net_device *dev = napi->dev;
672 const struct at91_priv *priv = netdev_priv(dev);
673 u32 reg_sr = at91_read(priv, AT91_SR);
676 if (reg_sr & AT91_IRQ_MB_RX)
677 work_done += at91_poll_rx(dev, quota - work_done);
680 * The error bits are clear on read,
681 * so use saved value from irq handler.
683 reg_sr |= priv->reg_sr;
684 if (reg_sr & AT91_IRQ_ERR_FRAME)
685 work_done += at91_poll_err(dev, quota - work_done, reg_sr);
687 if (work_done < quota) {
688 /* enable IRQs for frame errors and all mailboxes >= rx_next */
689 u32 reg_ier = AT91_IRQ_ERR_FRAME;
690 reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
693 at91_write(priv, AT91_IER, reg_ier);
700 * theory of operation:
702 * priv->tx_echo holds the number of the oldest can_frame put for
703 * transmission into the hardware, but not yet ACKed by the CAN tx
706 * We iterate from priv->tx_echo to priv->tx_next and check if the
707 * packet has been transmitted, echo it back to the CAN framework. If
708 * we discover a not yet transmitted package, stop looking for more.
711 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
713 struct at91_priv *priv = netdev_priv(dev);
717 /* masking of reg_sr not needed, already done by at91_irq */
719 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
720 mb = get_tx_echo_mb(priv);
722 /* no event in mailbox? */
723 if (!(reg_sr & (1 << mb)))
726 /* Disable irq for this TX mailbox */
727 at91_write(priv, AT91_IDR, 1 << mb);
730 * only echo if mailbox signals us a transfer
731 * complete (MSR_MRDY). Otherwise it's a tansfer
732 * abort. "can_bus_off()" takes care about the skbs
733 * parked in the echo queue.
735 reg_msr = at91_read(priv, AT91_MSR(mb));
736 if (likely(reg_msr & AT91_MSR_MRDY &&
737 ~reg_msr & AT91_MSR_MABT)) {
738 /* _NOTE_: substract AT91_MB_TX_FIRST offset from mb! */
739 can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
740 dev->stats.tx_packets++;
745 * restart queue if we don't have a wrap around but restart if
746 * we get a TX int for the last can frame directly before a
749 if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
750 (priv->tx_echo & AT91_NEXT_MASK) == 0)
751 netif_wake_queue(dev);
754 static void at91_irq_err_state(struct net_device *dev,
755 struct can_frame *cf, enum can_state new_state)
757 struct at91_priv *priv = netdev_priv(dev);
758 u32 reg_idr, reg_ier, reg_ecr;
761 reg_ecr = at91_read(priv, AT91_ECR);
762 rec = reg_ecr & 0xff;
765 switch (priv->can.state) {
766 case CAN_STATE_ERROR_ACTIVE:
769 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
770 * => : there was a warning int
772 if (new_state >= CAN_STATE_ERROR_WARNING &&
773 new_state <= CAN_STATE_BUS_OFF) {
774 dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
775 priv->can.can_stats.error_warning++;
777 cf->can_id |= CAN_ERR_CRTL;
778 cf->data[1] = (tec > rec) ?
779 CAN_ERR_CRTL_TX_WARNING :
780 CAN_ERR_CRTL_RX_WARNING;
782 case CAN_STATE_ERROR_WARNING: /* fallthrough */
784 * from: ERROR_ACTIVE, ERROR_WARNING
785 * to : ERROR_PASSIVE, BUS_OFF
786 * => : error passive int
788 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
789 new_state <= CAN_STATE_BUS_OFF) {
790 dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
791 priv->can.can_stats.error_passive++;
793 cf->can_id |= CAN_ERR_CRTL;
794 cf->data[1] = (tec > rec) ?
795 CAN_ERR_CRTL_TX_PASSIVE :
796 CAN_ERR_CRTL_RX_PASSIVE;
799 case CAN_STATE_BUS_OFF:
802 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
804 if (new_state <= CAN_STATE_ERROR_PASSIVE) {
805 cf->can_id |= CAN_ERR_RESTARTED;
807 dev_dbg(dev->dev.parent, "restarted\n");
808 priv->can.can_stats.restarts++;
810 netif_carrier_on(dev);
811 netif_wake_queue(dev);
819 /* process state changes depending on the new state */
821 case CAN_STATE_ERROR_ACTIVE:
823 * actually we want to enable AT91_IRQ_WARN here, but
824 * it screws up the system under certain
825 * circumstances. so just enable AT91_IRQ_ERRP, thus
828 dev_dbg(dev->dev.parent, "Error Active\n");
829 cf->can_id |= CAN_ERR_PROT;
830 cf->data[2] = CAN_ERR_PROT_ACTIVE;
831 case CAN_STATE_ERROR_WARNING: /* fallthrough */
832 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
833 reg_ier = AT91_IRQ_ERRP;
835 case CAN_STATE_ERROR_PASSIVE:
836 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
837 reg_ier = AT91_IRQ_BOFF;
839 case CAN_STATE_BUS_OFF:
840 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
841 AT91_IRQ_WARN | AT91_IRQ_BOFF;
844 cf->can_id |= CAN_ERR_BUSOFF;
846 dev_dbg(dev->dev.parent, "bus-off\n");
847 netif_carrier_off(dev);
848 priv->can.can_stats.bus_off++;
850 /* turn off chip, if restart is disabled */
851 if (!priv->can.restart_ms) {
852 at91_chip_stop(dev, CAN_STATE_BUS_OFF);
860 at91_write(priv, AT91_IDR, reg_idr);
861 at91_write(priv, AT91_IER, reg_ier);
864 static void at91_irq_err(struct net_device *dev)
866 struct at91_priv *priv = netdev_priv(dev);
868 struct can_frame *cf;
869 enum can_state new_state;
872 reg_sr = at91_read(priv, AT91_SR);
874 /* we need to look at the unmasked reg_sr */
875 if (unlikely(reg_sr & AT91_IRQ_BOFF))
876 new_state = CAN_STATE_BUS_OFF;
877 else if (unlikely(reg_sr & AT91_IRQ_ERRP))
878 new_state = CAN_STATE_ERROR_PASSIVE;
879 else if (unlikely(reg_sr & AT91_IRQ_WARN))
880 new_state = CAN_STATE_ERROR_WARNING;
881 else if (likely(reg_sr & AT91_IRQ_ERRA))
882 new_state = CAN_STATE_ERROR_ACTIVE;
884 dev_err(dev->dev.parent, "BUG! hardware in undefined state\n");
888 /* state hasn't changed */
889 if (likely(new_state == priv->can.state))
892 skb = alloc_can_err_skb(dev, &cf);
896 at91_irq_err_state(dev, cf, new_state);
899 dev->last_rx = jiffies;
900 dev->stats.rx_packets++;
901 dev->stats.rx_bytes += cf->can_dlc;
903 priv->can.state = new_state;
909 static irqreturn_t at91_irq(int irq, void *dev_id)
911 struct net_device *dev = dev_id;
912 struct at91_priv *priv = netdev_priv(dev);
913 irqreturn_t handled = IRQ_NONE;
916 reg_sr = at91_read(priv, AT91_SR);
917 reg_imr = at91_read(priv, AT91_IMR);
919 /* Ignore masked interrupts */
924 handled = IRQ_HANDLED;
926 /* Receive or error interrupt? -> napi */
927 if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
929 * The error bits are clear on read,
930 * save for later use.
932 priv->reg_sr = reg_sr;
933 at91_write(priv, AT91_IDR,
934 AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
935 napi_schedule(&priv->napi);
938 /* Transmission complete interrupt */
939 if (reg_sr & AT91_IRQ_MB_TX)
940 at91_irq_tx(dev, reg_sr);
948 static int at91_open(struct net_device *dev)
950 struct at91_priv *priv = netdev_priv(dev);
953 clk_enable(priv->clk);
955 /* check or determine and set bittime */
956 err = open_candev(dev);
960 /* register interrupt handler */
961 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
967 /* start chip and queuing */
968 at91_chip_start(dev);
969 napi_enable(&priv->napi);
970 netif_start_queue(dev);
977 clk_disable(priv->clk);
983 * stop CAN bus activity
985 static int at91_close(struct net_device *dev)
987 struct at91_priv *priv = netdev_priv(dev);
989 netif_stop_queue(dev);
990 napi_disable(&priv->napi);
991 at91_chip_stop(dev, CAN_STATE_STOPPED);
993 free_irq(dev->irq, dev);
994 clk_disable(priv->clk);
1001 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1004 case CAN_MODE_START:
1005 at91_chip_start(dev);
1006 netif_wake_queue(dev);
1016 static const struct net_device_ops at91_netdev_ops = {
1017 .ndo_open = at91_open,
1018 .ndo_stop = at91_close,
1019 .ndo_start_xmit = at91_start_xmit,
1022 static int __init at91_can_probe(struct platform_device *pdev)
1024 struct net_device *dev;
1025 struct at91_priv *priv;
1026 struct resource *res;
1031 clk = clk_get(&pdev->dev, "can_clk");
1033 dev_err(&pdev->dev, "no clock defined\n");
1038 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 irq = platform_get_irq(pdev, 0);
1045 if (!request_mem_region(res->start,
1052 addr = ioremap_nocache(res->start, resource_size(res));
1058 dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
1064 dev->netdev_ops = &at91_netdev_ops;
1066 dev->flags |= IFF_ECHO;
1068 priv = netdev_priv(dev);
1069 priv->can.clock.freq = clk_get_rate(clk);
1070 priv->can.bittiming_const = &at91_bittiming_const;
1071 priv->can.do_set_bittiming = at91_set_bittiming;
1072 priv->can.do_set_mode = at91_set_mode;
1073 priv->reg_base = addr;
1076 priv->pdata = pdev->dev.platform_data;
1078 netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
1080 dev_set_drvdata(&pdev->dev, dev);
1081 SET_NETDEV_DEV(dev, &pdev->dev);
1083 err = register_candev(dev);
1085 dev_err(&pdev->dev, "registering netdev failed\n");
1089 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1090 priv->reg_base, dev->irq);
1099 release_mem_region(res->start, resource_size(res));
1106 static int __devexit at91_can_remove(struct platform_device *pdev)
1108 struct net_device *dev = platform_get_drvdata(pdev);
1109 struct at91_priv *priv = netdev_priv(dev);
1110 struct resource *res;
1112 unregister_netdev(dev);
1114 platform_set_drvdata(pdev, NULL);
1118 iounmap(priv->reg_base);
1120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 release_mem_region(res->start, resource_size(res));
1128 static struct platform_driver at91_can_driver = {
1129 .probe = at91_can_probe,
1130 .remove = __devexit_p(at91_can_remove),
1133 .owner = THIS_MODULE,
1137 static int __init at91_can_module_init(void)
1139 printk(KERN_INFO "%s netdevice driver\n", DRV_NAME);
1140 return platform_driver_register(&at91_can_driver);
1143 static void __exit at91_can_module_exit(void)
1145 platform_driver_unregister(&at91_can_driver);
1146 printk(KERN_INFO "%s: driver removed\n", DRV_NAME);
1149 module_init(at91_can_module_init);
1150 module_exit(at91_can_module_exit);
1152 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1153 MODULE_LICENSE("GPL v2");
1154 MODULE_DESCRIPTION(DRV_NAME " CAN netdevice driver");