drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /***********************************************************/
  49 /*                      Shortcut definitions               */
  50 /***********************************************************/
  51
  52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  53
  54 #define NIG_STATUS_EMAC0_MI_INT \
  55                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  56 #define NIG_STATUS_XGXS0_LINK10G \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  58 #define NIG_STATUS_XGXS0_LINK_STATUS \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  62 #define NIG_STATUS_SERDES0_LINK_STATUS \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  64 #define NIG_MASK_MI_INT \
  65                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  66 #define NIG_MASK_XGXS0_LINK10G \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  68 #define NIG_MASK_XGXS0_LINK_STATUS \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  70 #define NIG_MASK_SERDES0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  72
  73 #define MDIO_AN_CL73_OR_37_COMPLETE \
  74                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  75                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  76
  77 #define XGXS_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  83
  84 #define SERDES_RESET_BITS \
  85         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  89
  90 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  91 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  92 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  93 #define AUTONEG_PARALLEL \
  94                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  95 #define AUTONEG_SGMII_FIBER_AUTODET \
  96                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  97 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  98
  99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 100                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 103 #define GP_STATUS_SPEED_MASK \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 105 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 106 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 107 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 108 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 109 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 110 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 111 #define GP_STATUS_10G_HIG \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 113 #define GP_STATUS_10G_CX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 116 #define GP_STATUS_10G_KX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 119 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 121 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 122 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 123 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 124 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 125 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 126 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 127 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 128 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 129 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 130 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 131 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 132 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 133 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 134 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 135 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 136 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 137
 138
 139
 140 /* */
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163
 164 /* BRB thresholds for E2*/
 165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 167
 168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 170
 171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 173
 174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 176
 177 /* BRB thresholds for E3A0 */
 178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 180
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 183
 184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 189
 190
 191 /* BRB thresholds for E3B0 2 port mode*/
 192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 194
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 203
 204 /* only for E3B0*/
 205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 207
 208 /* Lossy +Lossless GUARANTIED == GUART */
 209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 210 /* Lossless +Lossless*/
 211 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 212 /* Lossy +Lossy*/
 213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 214
 215 /* Lossy +Lossless*/
 216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 217 /* Lossless +Lossless*/
 218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 219 /* Lossy +Lossy*/
 220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 222
 223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 225
 226 /* BRB thresholds for E3B0 4 port mode */
 227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 229
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 238
 239
 240 /* only for E3B0*/
 241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 243 #define PFC_E3B0_4P_LB_GUART                            120
 244
 245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 247
 248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 250
 251 #define DCBX_INVALID_COS                                        (0xFF)
 252
 253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 254 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 257 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 258
 259 #define MAX_PACKET_SIZE                                 (9700)
 260 #define WC_UC_TIMEOUT                                   100
 261
 262 /**********************************************************/
 263 /*                     INTERFACE                          */
 264 /**********************************************************/
 265
 266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 267         bnx2x_cl45_write(_bp, _phy, \
 268                 (_phy)->def_md_devad, \
 269                 (_bank + (_addr & 0xf)), \
 270                 _val)
 271
 272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 273         bnx2x_cl45_read(_bp, _phy, \
 274                 (_phy)->def_md_devad, \
 275                 (_bank + (_addr & 0xf)), \
 276                 _val)
 277
 278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 279 {
 280         u32 val = REG_RD(bp, reg);
 281
 282         val |= bits;
 283         REG_WR(bp, reg, val);
 284         return val;
 285 }
 286
 287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 288 {
 289         u32 val = REG_RD(bp, reg);
 290
 291         val &= ~bits;
 292         REG_WR(bp, reg, val);
 293         return val;
 294 }
 295
 296 /******************************************************************/
 297 /*                      EPIO/GPIO section                         */
 298 /******************************************************************/
 299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 300 {
 301         u32 epio_mask, gp_oenable;
 302         *en = 0;
 303         /* Sanity check */
 304         if (epio_pin > 31) {
 305                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 306                 return;
 307         }
 308
 309         epio_mask = 1 << epio_pin;
 310         /* Set this EPIO to output */
 311         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 312         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 313
 314         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 315 }
 316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 317 {
 318         u32 epio_mask, gp_output, gp_oenable;
 319
 320         /* Sanity check */
 321         if (epio_pin > 31) {
 322                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 323                 return;
 324         }
 325         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 326         epio_mask = 1 << epio_pin;
 327         /* Set this EPIO to output */
 328         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 329         if (en)
 330                 gp_output |= epio_mask;
 331         else
 332                 gp_output &= ~epio_mask;
 333
 334         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 335
 336         /* Set the value for this EPIO */
 337         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 338         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 339 }
 340
 341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 342 {
 343         if (pin_cfg == PIN_CFG_NA)
 344                 return;
 345         if (pin_cfg >= PIN_CFG_EPIO0) {
 346                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 347         } else {
 348                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 349                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 350                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 351         }
 352 }
 353
 354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 355 {
 356         if (pin_cfg == PIN_CFG_NA)
 357                 return -EINVAL;
 358         if (pin_cfg >= PIN_CFG_EPIO0) {
 359                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 360         } else {
 361                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 362                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 363                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 364         }
 365         return 0;
 366
 367 }
 368 /******************************************************************/
 369 /*                              ETS section                       */
 370 /******************************************************************/
 371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 372 {
 373         /* ETS disabled configuration*/
 374         struct bnx2x *bp = params->bp;
 375
 376         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 377
 378         /*
 379          * mapping between entry  priority to client number (0,1,2 -debug and
 380          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 381          * 3bits client num.
 382          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 383          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 384          */
 385
 386         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 387         /*
 388          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 389          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 390          * COS0 entry, 4 - COS1 entry.
 391          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 392          * bit4   bit3    bit2   bit1     bit0
 393          * MCP and debug are strict
 394          */
 395
 396         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 397         /* defines which entries (clients) are subjected to WFQ arbitration */
 398         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 399         /*
 400          * For strict priority entries defines the number of consecutive
 401          * slots for the highest priority.
 402          */
 403         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 404         /*
 405          * mapping between the CREDIT_WEIGHT registers and actual client
 406          * numbers
 407          */
 408         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 409         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 410         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 411
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 414         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 415         /* ETS mode disable */
 416         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 417         /*
 418          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 419          * weight for COS0/COS1.
 420          */
 421         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 422         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 423         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 424         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 425         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 426         /* Defines the number of consecutive slots for the strict priority */
 427         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 428 }
 429 /******************************************************************************
 430 * Description:
 431 *       Getting min_w_val will be set according to line speed .
 432 *.
 433 ******************************************************************************/
 434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 435 {
 436         u32 min_w_val = 0;
 437         /* Calculate min_w_val.*/
 438         if (vars->link_up) {
 439                 if (SPEED_20000 == vars->line_speed)
 440                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 441                 else
 442                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 443         } else
 444                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445         /**
 446          *  If the link isn't up (static configuration for example ) The
 447          *  link will be according to 20GBPS.
 448         */
 449         return min_w_val;
 450 }
 451 /******************************************************************************
 452 * Description:
 453 *       Getting credit upper bound form min_w_val.
 454 *.
 455 ******************************************************************************/
 456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 457 {
 458         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 459                                                 MAX_PACKET_SIZE);
 460         return credit_upper_bound;
 461 }
 462 /******************************************************************************
 463 * Description:
 464 *       Set credit upper bound for NIG.
 465 *.
 466 ******************************************************************************/
 467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 468         const struct link_params *params,
 469         const u32 min_w_val)
 470 {
 471         struct bnx2x *bp = params->bp;
 472         const u8 port = params->port;
 473         const u32 credit_upper_bound =
 474             bnx2x_ets_get_credit_upper_bound(min_w_val);
 475
 476         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 477                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 478         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 479                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 481                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 488
 489         if (0 == port) {
 490                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 491                         credit_upper_bound);
 492                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 493                         credit_upper_bound);
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 495                         credit_upper_bound);
 496         }
 497 }
 498 /******************************************************************************
 499 * Description:
 500 *       Will return the NIG ETS registers to init values.Except
 501 *       credit_upper_bound.
 502 *       That isn't used in this configuration (No WFQ is enabled) and will be
 503 *       configured acording to spec
 504 *.
 505 ******************************************************************************/
 506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 507                                         const struct link_vars *vars)
 508 {
 509         struct bnx2x *bp = params->bp;
 510         const u8 port = params->port;
 511         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 512         /**
 513          * mapping between entry  priority to client number (0,1,2 -debug and
 514          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 515          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 516          * reset value or init tool
 517          */
 518         if (port) {
 519                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 520                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 521         } else {
 522                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 524         }
 525         /**
 526         * For strict priority entries defines the number of consecutive
 527         * slots for the highest priority.
 528         */
 529         /* TODO_ETS - Should be done by reset value or init tool */
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 531                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 532         /**
 533          * mapping between the CREDIT_WEIGHT registers and actual client
 534          * numbers
 535          */
 536         /* TODO_ETS - Should be done by reset value or init tool */
 537         if (port) {
 538                 /*Port 1 has 6 COS*/
 539                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 541         } else {
 542                 /*Port 0 has 9 COS*/
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 544                        0x43210876);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 546         }
 547
 548         /**
 549          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 550          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 551          * COS0 entry, 4 - COS1 entry.
 552          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 553          * bit4   bit3    bit2   bit1     bit0
 554          * MCP and debug are strict
 555          */
 556         if (port)
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 558         else
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 560         /* defines which entries (clients) are subjected to WFQ arbitration */
 561         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 562                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 563
 564         /**
 565         * Please notice the register address are note continuous and a
 566         * for here is note appropriate.In 2 port mode port0 only COS0-5
 567         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 568         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 569         * are never used for WFQ
 570         */
 571         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 572                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 573         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 574                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 583         if (0 == port) {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 586                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 587         }
 588
 589         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 590 }
 591 /******************************************************************************
 592 * Description:
 593 *       Set credit upper bound for PBF.
 594 *.
 595 ******************************************************************************/
 596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 597         const struct link_params *params,
 598         const u32 min_w_val)
 599 {
 600         struct bnx2x *bp = params->bp;
 601         const u32 credit_upper_bound =
 602             bnx2x_ets_get_credit_upper_bound(min_w_val);
 603         const u8 port = params->port;
 604         u32 base_upper_bound = 0;
 605         u8 max_cos = 0;
 606         u8 i = 0;
 607         /**
 608         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 609         * port mode port1 has COS0-2 that can be used for WFQ.
 610         */
 611         if (0 == port) {
 612                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 613                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 614         } else {
 615                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 616                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 617         }
 618
 619         for (i = 0; i < max_cos; i++)
 620                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 621 }
 622
 623 /******************************************************************************
 624 * Description:
 625 *       Will return the PBF ETS registers to init values.Except
 626 *       credit_upper_bound.
 627 *       That isn't used in this configuration (No WFQ is enabled) and will be
 628 *       configured acording to spec
 629 *.
 630 ******************************************************************************/
 631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 632 {
 633         struct bnx2x *bp = params->bp;
 634         const u8 port = params->port;
 635         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 636         u8 i = 0;
 637         u32 base_weight = 0;
 638         u8 max_cos = 0;
 639
 640         /**
 641          * mapping between entry  priority to client number 0 - COS0
 642          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 643          * TODO_ETS - Should be done by reset value or init tool
 644          */
 645         if (port)
 646                 /*  0x688 (|011|0 10|00 1|000) */
 647                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 648         else
 649                 /*  (10 1|100 |011|0 10|00 1|000) */
 650                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 651
 652         /* TODO_ETS - Should be done by reset value or init tool */
 653         if (port)
 654                 /* 0x688 (|011|0 10|00 1|000)*/
 655                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 656         else
 657         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 658         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 659
 660         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 661                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 662
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 665                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 666
 667         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 668                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 669         /**
 670         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 671         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 672         */
 673         if (0 == port) {
 674                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 676         } else {
 677                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 678                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 679         }
 680
 681         for (i = 0; i < max_cos; i++)
 682                 REG_WR(bp, base_weight + (0x4 * i), 0);
 683
 684         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 685 }
 686 /******************************************************************************
 687 * Description:
 688 *       E3B0 disable will return basicly the values to init values.
 689 *.
 690 ******************************************************************************/
 691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 692                                    const struct link_vars *vars)
 693 {
 694         struct bnx2x *bp = params->bp;
 695
 696         if (!CHIP_IS_E3B0(bp)) {
 697                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
 698                                    "\n");
 699                 return -EINVAL;
 700         }
 701
 702         bnx2x_ets_e3b0_nig_disabled(params, vars);
 703
 704         bnx2x_ets_e3b0_pbf_disabled(params);
 705
 706         return 0;
 707 }
 708
 709 /******************************************************************************
 710 * Description:
 711 *       Disable will return basicly the values to init values.
 712 *.
 713 ******************************************************************************/
 714 int bnx2x_ets_disabled(struct link_params *params,
 715                       struct link_vars *vars)
 716 {
 717         struct bnx2x *bp = params->bp;
 718         int bnx2x_status = 0;
 719
 720         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 721                 bnx2x_ets_e2e3a0_disabled(params);
 722         else if (CHIP_IS_E3B0(bp))
 723                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 724         else {
 725                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 726                 return -EINVAL;
 727         }
 728
 729         return bnx2x_status;
 730 }
 731
 732 /******************************************************************************
 733 * Description
 734 *       Set the COS mappimg to SP and BW until this point all the COS are not
 735 *       set as SP or BW.
 736 ******************************************************************************/
 737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 738                                   const struct bnx2x_ets_params *ets_params,
 739                                   const u8 cos_sp_bitmap,
 740                                   const u8 cos_bw_bitmap)
 741 {
 742         struct bnx2x *bp = params->bp;
 743         const u8 port = params->port;
 744         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 745         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 746         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 747         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 748
 749         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 750                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 751
 752         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 753                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 754
 755         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 756                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 757                nig_cli_subject2wfq_bitmap);
 758
 759         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 760                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 761                pbf_cli_subject2wfq_bitmap);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 769 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 770 ******************************************************************************/
 771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 772                                      const u8 cos_entry,
 773                                      const u32 min_w_val_nig,
 774                                      const u32 min_w_val_pbf,
 775                                      const u16 total_bw,
 776                                      const u8 bw,
 777                                      const u8 port)
 778 {
 779         u32 nig_reg_adress_crd_weight = 0;
 780         u32 pbf_reg_adress_crd_weight = 0;
 781         /* Calculate and set BW for this COS*/
 782         const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
 783         const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
 784
 785         switch (cos_entry) {
 786         case 0:
 787             nig_reg_adress_crd_weight =
 788                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 789                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 790              pbf_reg_adress_crd_weight = (port) ?
 791                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 792              break;
 793         case 1:
 794              nig_reg_adress_crd_weight = (port) ?
 795                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 796                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 797              pbf_reg_adress_crd_weight = (port) ?
 798                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 799              break;
 800         case 2:
 801              nig_reg_adress_crd_weight = (port) ?
 802                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 803                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 804
 805                  pbf_reg_adress_crd_weight = (port) ?
 806                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 807              break;
 808         case 3:
 809             if (port)
 810                         return -EINVAL;
 811              nig_reg_adress_crd_weight =
 812                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 813              pbf_reg_adress_crd_weight =
 814                  PBF_REG_COS3_WEIGHT_P0;
 815              break;
 816         case 4:
 817             if (port)
 818                 return -EINVAL;
 819              nig_reg_adress_crd_weight =
 820                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 821              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 822              break;
 823         case 5:
 824             if (port)
 825                 return -EINVAL;
 826              nig_reg_adress_crd_weight =
 827                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 828              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 829              break;
 830         }
 831
 832         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 833
 834         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 835
 836         return 0;
 837 }
 838 /******************************************************************************
 839 * Description:
 840 *       Calculate the total BW.A value of 0 isn't legal.
 841 *.
 842 ******************************************************************************/
 843 static int bnx2x_ets_e3b0_get_total_bw(
 844         const struct link_params *params,
 845         const struct bnx2x_ets_params *ets_params,
 846         u16 *total_bw)
 847 {
 848         struct bnx2x *bp = params->bp;
 849         u8 cos_idx = 0;
 850
 851         *total_bw = 0 ;
 852         /* Calculate total BW requested */
 853         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 854                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 855
 856                         if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
 857                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 858                                                    "was set to 0\n");
 859                         return -EINVAL;
 860                 }
 861                 *total_bw +=
 862                     ets_params->cos[cos_idx].params.bw_params.bw;
 863             }
 864         }
 865
 866         /*Check taotl BW is valid */
 867         if ((100 != *total_bw) || (0 == *total_bw)) {
 868                 if (0 == *total_bw) {
 869                         DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
 870                                            "shouldn't be 0\n");
 871                         return -EINVAL;
 872                 }
 873                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
 874                                    "100\n");
 875                 /**
 876                 *   We can handle a case whre the BW isn't 100 this can happen
 877                 *   if the TC are joined.
 878                 */
 879         }
 880         return 0;
 881 }
 882
 883 /******************************************************************************
 884 * Description:
 885 *       Invalidate all the sp_pri_to_cos.
 886 *.
 887 ******************************************************************************/
 888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 889 {
 890         u8 pri = 0;
 891         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 892                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 893 }
 894 /******************************************************************************
 895 * Description:
 896 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 897 *       according to sp_pri_to_cos.
 898 *.
 899 ******************************************************************************/
 900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 901                                             u8 *sp_pri_to_cos, const u8 pri,
 902                                             const u8 cos_entry)
 903 {
 904         struct bnx2x *bp = params->bp;
 905         const u8 port = params->port;
 906         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 907                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 908
 909         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 910                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 911                                    "parameter There can't be two COS's with"
 912                                    "the same strict pri\n");
 913                 return -EINVAL;
 914         }
 915
 916         if (pri > max_num_of_cos) {
 917                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
 918                                "parameter Illegal strict priority\n");
 919             return -EINVAL;
 920         }
 921
 922         sp_pri_to_cos[pri] = cos_entry;
 923         return 0;
 924
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Returns the correct value according to COS and priority in
 930 *       the sp_pri_cli register.
 931 *.
 932 ******************************************************************************/
 933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 934                                          const u8 pri_set,
 935                                          const u8 pri_offset,
 936                                          const u8 entry_size)
 937 {
 938         u64 pri_cli_nig = 0;
 939         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 940                                                     (pri_set + pri_offset));
 941
 942         return pri_cli_nig;
 943 }
 944 /******************************************************************************
 945 * Description:
 946 *       Returns the correct value according to COS and priority in the
 947 *       sp_pri_cli register for NIG.
 948 *.
 949 ******************************************************************************/
 950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 951 {
 952         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 953         const u8 nig_cos_offset = 3;
 954         const u8 nig_pri_offset = 3;
 955
 956         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 957                 nig_pri_offset, 4);
 958
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for PBF.
 964 *.
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 967 {
 968         const u8 pbf_cos_offset = 0;
 969         const u8 pbf_pri_offset = 0;
 970
 971         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 972                 pbf_pri_offset, 3);
 973
 974 }
 975
 976 /******************************************************************************
 977 * Description:
 978 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 979 *       according to sp_pri_to_cos.(which COS has higher priority)
 980 *.
 981 ******************************************************************************/
 982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 983                                              u8 *sp_pri_to_cos)
 984 {
 985         struct bnx2x *bp = params->bp;
 986         u8 i = 0;
 987         const u8 port = params->port;
 988         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 989         u64 pri_cli_nig = 0x210;
 990         u32 pri_cli_pbf = 0x0;
 991         u8 pri_set = 0;
 992         u8 pri_bitmask = 0;
 993         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 994                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 995
 996         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 997
 998         /* Set all the strict priority first */
 999         for (i = 0; i < max_num_of_cos; i++) {
1000                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1002                                 DP(NETIF_MSG_LINK,
1003                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004                                            "invalid cos entry\n");
1005                                 return -EINVAL;
1006                         }
1007
1008                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009                             sp_pri_to_cos[i], pri_set);
1010
1011                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012                             sp_pri_to_cos[i], pri_set);
1013                         pri_bitmask = 1 << sp_pri_to_cos[i];
1014                         /* COS is used remove it from bitmap.*/
1015                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1016                                 DP(NETIF_MSG_LINK,
1017                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018                                         "invalid There can't be two COS's with"
1019                                         " the same strict pri\n");
1020                                 return -EINVAL;
1021                         }
1022                         cos_bit_to_set &= ~pri_bitmask;
1023                         pri_set++;
1024                 }
1025         }
1026
1027         /* Set all the Non strict priority i= COS*/
1028         for (i = 0; i < max_num_of_cos; i++) {
1029                 pri_bitmask = 1 << i;
1030                 /* Check if COS was already used for SP */
1031                 if (pri_bitmask & cos_bit_to_set) {
1032                         /* COS wasn't used for SP */
1033                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1034                             i, pri_set);
1035
1036                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1037                             i, pri_set);
1038                         /* COS is used remove it from bitmap.*/
1039                         cos_bit_to_set &= ~pri_bitmask;
1040                         pri_set++;
1041                 }
1042         }
1043
1044         if (pri_set != max_num_of_cos) {
1045                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046                                    "entries were set\n");
1047                 return -EINVAL;
1048         }
1049
1050         if (port) {
1051                 /* Only 6 usable clients*/
1052                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1053                        (u32)pri_cli_nig);
1054
1055                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1056         } else {
1057                 /* Only 9 usable clients*/
1058                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1060
1061                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1062                        pri_cli_nig_lsb);
1063                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1064                        pri_cli_nig_msb);
1065
1066                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1067         }
1068         return 0;
1069 }
1070
1071 /******************************************************************************
1072 * Description:
1073 *       Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076                          const struct link_vars *vars,
1077                          const struct bnx2x_ets_params *ets_params)
1078 {
1079         struct bnx2x *bp = params->bp;
1080         int bnx2x_status = 0;
1081         const u8 port = params->port;
1082         u16 total_bw = 0;
1083         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085         u8 cos_bw_bitmap = 0;
1086         u8 cos_sp_bitmap = 0;
1087         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1090         u8 cos_entry = 0;
1091
1092         if (!CHIP_IS_E3B0(bp)) {
1093                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1094                                    "\n");
1095                 return -EINVAL;
1096         }
1097
1098         if ((ets_params->num_of_cos > max_num_of_cos)) {
1099                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100                                    "isn't supported\n");
1101                 return -EINVAL;
1102         }
1103
1104         /* Prepare sp strict priority parameters*/
1105         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1106
1107         /* Prepare BW parameters*/
1108         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1109                                                    &total_bw);
1110         if (0 != bnx2x_status) {
1111                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1112                                    "\n");
1113                 return -EINVAL;
1114         }
1115
1116         /**
1117          *  Upper bound is set according to current link speed (min_w_val
1118          *  should be the same for upper bound and COS credit val).
1119          */
1120         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1122
1123
1124         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126                         cos_bw_bitmap |= (1 << cos_entry);
1127                         /**
1128                          * The function also sets the BW in HW(not the mappin
1129                          * yet)
1130                          */
1131                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1133                                 total_bw,
1134                                 ets_params->cos[cos_entry].params.bw_params.bw,
1135                                  port);
1136                 } else if (bnx2x_cos_state_strict ==
1137                         ets_params->cos[cos_entry].state){
1138                         cos_sp_bitmap |= (1 << cos_entry);
1139
1140                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1141                                 params,
1142                                 sp_pri_to_cos,
1143                                 ets_params->cos[cos_entry].params.sp_params.pri,
1144                                 cos_entry);
1145
1146                 } else {
1147                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1148                                            " valid\n");
1149                         return -EINVAL;
1150                 }
1151                 if (0 != bnx2x_status) {
1152                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1153                                            "failed\n");
1154                         return bnx2x_status;
1155                 }
1156         }
1157
1158         /* Set SP register (which COS has higher priority) */
1159         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1160                                                          sp_pri_to_cos);
1161
1162         if (0 != bnx2x_status) {
1163                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1164                                    "failed\n");
1165                 return bnx2x_status;
1166         }
1167
1168         /* Set client mapping of BW and strict */
1169         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1170                                               cos_sp_bitmap,
1171                                               cos_bw_bitmap);
1172
1173         if (0 != bnx2x_status) {
1174                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175                 return bnx2x_status;
1176         }
1177         return 0;
1178 }
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1180 {
1181         /* ETS disabled configuration */
1182         struct bnx2x *bp = params->bp;
1183         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1184         /*
1185          * defines which entries (clients) are subjected to WFQ arbitration
1186          * COS0 0x8
1187          * COS1 0x10
1188          */
1189         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1190         /*
1191          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192          * client numbers (WEIGHT_0 does not actually have to represent
1193          * client 0)
1194          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1195          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1196          */
1197         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1198
1199         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1203
1204         /* ETS mode enabled*/
1205         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1206
1207         /* Defines the number of consecutive slots for the strict priority */
1208         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1209         /*
1210          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1212          * entry, 4 - COS1 entry.
1213          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214          * bit4   bit3    bit2     bit1    bit0
1215          * MCP and debug are strict
1216          */
1217         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1218
1219         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1224 }
1225
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1227                         const u32 cos1_bw)
1228 {
1229         /* ETS disabled configuration*/
1230         struct bnx2x *bp = params->bp;
1231         const u32 total_bw = cos0_bw + cos1_bw;
1232         u32 cos0_credit_weight = 0;
1233         u32 cos1_credit_weight = 0;
1234
1235         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1236
1237         if ((0 == total_bw) ||
1238             (0 == cos0_bw) ||
1239             (0 == cos1_bw)) {
1240                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1241                 return;
1242         }
1243
1244         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245                 total_bw;
1246         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1247                 total_bw;
1248
1249         bnx2x_ets_bw_limit_common(params);
1250
1251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1253
1254         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1256 }
1257
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1259 {
1260         /* ETS disabled configuration*/
1261         struct bnx2x *bp = params->bp;
1262         u32 val = 0;
1263
1264         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1265         /*
1266          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267          * as strict.  Bits 0,1,2 - debug and management entries,
1268          * 3 - COS0 entry, 4 - COS1 entry.
1269          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270          *  bit4   bit3   bit2      bit1     bit0
1271          * MCP and debug are strict
1272          */
1273         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1274         /*
1275          * For strict priority entries defines the number of consecutive slots
1276          * for the highest priority.
1277          */
1278         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279         /* ETS mode disable */
1280         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281         /* Defines the number of consecutive slots for the strict priority */
1282         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1283
1284         /* Defines the number of consecutive slots for the strict priority */
1285         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1286
1287         /*
1288          * mapping between entry  priority to client number (0,1,2 -debug and
1289          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1290          * 3bits client num.
1291          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1292          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1293          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1294          */
1295         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1297
1298         return 0;
1299 }
1300 /******************************************************************/
1301 /*                      PFC section                               */
1302 /******************************************************************/
1303
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305                                   struct link_vars *vars,
1306                                   u8 is_lb)
1307 {
1308         struct bnx2x *bp = params->bp;
1309         u32 xmac_base;
1310         u32 pause_val, pfc0_val, pfc1_val;
1311
1312         /* XMAC base adrr */
1313         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1314
1315         /* Initialize pause and pfc registers */
1316         pause_val = 0x18000;
1317         pfc0_val = 0xFFFF8000;
1318         pfc1_val = 0x2;
1319
1320         /* No PFC support */
1321         if (!(params->feature_config_flags &
1322               FEATURE_CONFIG_PFC_ENABLED)) {
1323
1324                 /*
1325                  * RX flow control - Process pause frame in receive direction
1326                  */
1327                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1329
1330                 /*
1331                  * TX flow control - Send pause packet when buffer is full
1332                  */
1333                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335         } else {/* PFC support */
1336                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1340         }
1341
1342         /* Write pause and PFC registers */
1343         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1346
1347
1348         /* Set MAC address for source TX Pause/PFC frames */
1349         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350                ((params->mac_addr[2] << 24) |
1351                 (params->mac_addr[3] << 16) |
1352                 (params->mac_addr[4] << 8) |
1353                 (params->mac_addr[5])));
1354         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355                ((params->mac_addr[0] << 8) |
1356                 (params->mac_addr[1])));
1357
1358         udelay(30);
1359 }
1360
1361
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363                                     u32 pfc_frames_sent[2],
1364                                     u32 pfc_frames_received[2])
1365 {
1366         /* Read pfc statistic */
1367         struct bnx2x *bp = params->bp;
1368         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1369         u32 val_xon = 0;
1370         u32 val_xoff = 0;
1371
1372         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1373
1374         /* PFC received frames */
1375         val_xoff = REG_RD(bp, emac_base +
1376                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1380
1381         pfc_frames_received[0] = val_xon + val_xoff;
1382
1383         /* PFC received sent */
1384         val_xoff = REG_RD(bp, emac_base +
1385                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1389
1390         pfc_frames_sent[0] = val_xon + val_xoff;
1391 }
1392
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395                          u32 pfc_frames_sent[2],
1396                          u32 pfc_frames_received[2])
1397 {
1398         /* Read pfc statistic */
1399         struct bnx2x *bp = params->bp;
1400
1401         DP(NETIF_MSG_LINK, "pfc statistic\n");
1402
1403         if (!vars->link_up)
1404                 return;
1405
1406         if (MAC_TYPE_EMAC == vars->mac_type) {
1407                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409                                         pfc_frames_received);
1410         }
1411 }
1412 /******************************************************************/
1413 /*                      MAC/PBF section                           */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1416 {
1417         u32 mode, emac_base;
1418         /**
1419          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420          * (a value of 49==0x31) and make sure that the AUTO poll is off
1421          */
1422
1423         if (CHIP_IS_E2(bp))
1424                 emac_base = GRCBASE_EMAC0;
1425         else
1426                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429                   EMAC_MDIO_MODE_CLOCK_CNT);
1430         if (USES_WARPCORE(bp))
1431                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1432         else
1433                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1434
1435         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1437
1438         udelay(40);
1439 }
1440
1441 static void bnx2x_emac_init(struct link_params *params,
1442                             struct link_vars *vars)
1443 {
1444         /* reset and unreset the emac core */
1445         struct bnx2x *bp = params->bp;
1446         u8 port = params->port;
1447         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1448         u32 val;
1449         u16 timeout;
1450
1451         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1453         udelay(5);
1454         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1456
1457         /* init emac - use read-modify-write */
1458         /* self clear reset */
1459         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1461
1462         timeout = 200;
1463         do {
1464                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1466                 if (!timeout) {
1467                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1468                         return;
1469                 }
1470                 timeout--;
1471         } while (val & EMAC_MODE_RESET);
1472         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473         /* Set mac address */
1474         val = ((params->mac_addr[0] << 8) |
1475                 params->mac_addr[1]);
1476         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1477
1478         val = ((params->mac_addr[2] << 24) |
1479                (params->mac_addr[3] << 16) |
1480                (params->mac_addr[4] << 8) |
1481                 params->mac_addr[5]);
1482         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1483 }
1484
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1486                                 u16 tx_pause_en,
1487                                 u8 enable)
1488 {
1489         struct bnx2x *bp = params->bp;
1490
1491         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1492                enable);
1493         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1494                enable);
1495         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1497 }
1498
1499 static void bnx2x_umac_enable(struct link_params *params,
1500                             struct link_vars *vars, u8 lb)
1501 {
1502         u32 val;
1503         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504         struct bnx2x *bp = params->bp;
1505         /* Reset UMAC */
1506         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508         usleep_range(1000, 1000);
1509
1510         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1512
1513         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1514
1515         /**
1516          * This register determines on which events the MAC will assert
1517          * error on the i/f to the NIG along w/ EOP.
1518          */
1519
1520         /**
1521          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522          * params->port*0x14,      0xfffff.
1523          */
1524         /* This register opens the gate for the UMAC despite its name */
1525         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1526
1527         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531         switch (vars->line_speed) {
1532         case SPEED_10:
1533                 val |= (0<<2);
1534                 break;
1535         case SPEED_100:
1536                 val |= (1<<2);
1537                 break;
1538         case SPEED_1000:
1539                 val |= (2<<2);
1540                 break;
1541         case SPEED_2500:
1542                 val |= (3<<2);
1543                 break;
1544         default:
1545                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1546                                vars->line_speed);
1547                 break;
1548         }
1549         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1550                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1551
1552         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1553                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1554
1555         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1556         udelay(50);
1557
1558         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1559         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1560                ((params->mac_addr[2] << 24) |
1561                 (params->mac_addr[3] << 16) |
1562                 (params->mac_addr[4] << 8) |
1563                 (params->mac_addr[5])));
1564         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1565                ((params->mac_addr[0] << 8) |
1566                 (params->mac_addr[1])));
1567
1568         /* Enable RX and TX */
1569         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1570         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1571                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1572         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1573         udelay(50);
1574
1575         /* Remove SW Reset */
1576         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1577
1578         /* Check loopback mode */
1579         if (lb)
1580                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1581         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1582
1583         /*
1584          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1585          * length used by the MAC receive logic to check frames.
1586          */
1587         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1588         bnx2x_set_xumac_nig(params,
1589                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1590         vars->mac_type = MAC_TYPE_UMAC;
1591
1592 }
1593
1594 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1595 {
1596         u32 port4mode_ovwr_val;
1597         /* Check 4-port override enabled */
1598         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1599         if (port4mode_ovwr_val & (1<<0)) {
1600                 /* Return 4-port mode override value */
1601                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1602         }
1603         /* Return 4-port mode from input pin */
1604         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1605 }
1606
1607 /* Define the XMAC mode */
1608 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1609 {
1610         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1611
1612         /**
1613         * In 4-port mode, need to set the mode only once, so if XMAC is
1614         * already out of reset, it means the mode has already been set,
1615         * and it must not* reset the XMAC again, since it controls both
1616         * ports of the path
1617         **/
1618
1619         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1620              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1621                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1622                                    " in 4-port mode\n");
1623                 return;
1624         }
1625
1626         /* Hard reset */
1627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1628                MISC_REGISTERS_RESET_REG_2_XMAC);
1629         usleep_range(1000, 1000);
1630
1631         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1632                MISC_REGISTERS_RESET_REG_2_XMAC);
1633         if (is_port4mode) {
1634                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1635
1636                 /*  Set the number of ports on the system side to up to 2 */
1637                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1638
1639                 /* Set the number of ports on the Warp Core to 10G */
1640                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1641         } else {
1642                 /*  Set the number of ports on the system side to 1 */
1643                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1644                 if (max_speed == SPEED_10000) {
1645                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1646                                            " port per path\n");
1647                         /* Set the number of ports on the Warp Core to 10G */
1648                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1649                 } else {
1650                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1651                                            " per path\n");
1652                         /* Set the number of ports on the Warp Core to 20G */
1653                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1654                 }
1655         }
1656         /* Soft reset */
1657         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1658                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1659         usleep_range(1000, 1000);
1660
1661         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1662                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1663
1664 }
1665
1666 static void bnx2x_xmac_disable(struct link_params *params)
1667 {
1668         u8 port = params->port;
1669         struct bnx2x *bp = params->bp;
1670         u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1671
1672         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1673             MISC_REGISTERS_RESET_REG_2_XMAC) {
1674                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1675                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1676                 usleep_range(1000, 1000);
1677                 bnx2x_set_xumac_nig(params, 0, 0);
1678                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1679                        XMAC_CTRL_REG_SOFT_RESET);
1680         }
1681 }
1682
1683 static int bnx2x_xmac_enable(struct link_params *params,
1684                              struct link_vars *vars, u8 lb)
1685 {
1686         u32 val, xmac_base;
1687         struct bnx2x *bp = params->bp;
1688         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1689
1690         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1691
1692         bnx2x_xmac_init(bp, vars->line_speed);
1693
1694         /*
1695          * This register determines on which events the MAC will assert
1696          * error on the i/f to the NIG along w/ EOP.
1697          */
1698
1699         /*
1700          * This register tells the NIG whether to send traffic to UMAC
1701          * or XMAC
1702          */
1703         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1704
1705         /* Set Max packet size */
1706         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1707
1708         /* CRC append for Tx packets */
1709         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1710
1711         /* update PFC */
1712         bnx2x_update_pfc_xmac(params, vars, 0);
1713
1714         /* Enable TX and RX */
1715         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1716
1717         /* Check loopback mode */
1718         if (lb)
1719                 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1720         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1721         bnx2x_set_xumac_nig(params,
1722                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1723
1724         vars->mac_type = MAC_TYPE_XMAC;
1725
1726         return 0;
1727 }
1728 static int bnx2x_emac_enable(struct link_params *params,
1729                              struct link_vars *vars, u8 lb)
1730 {
1731         struct bnx2x *bp = params->bp;
1732         u8 port = params->port;
1733         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1734         u32 val;
1735
1736         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1737
1738         /* enable emac and not bmac */
1739         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1740
1741         /* ASIC */
1742         if (vars->phy_flags & PHY_XGXS_FLAG) {
1743                 u32 ser_lane = ((params->lane_config &
1744                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1745                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1746
1747                 DP(NETIF_MSG_LINK, "XGXS\n");
1748                 /* select the master lanes (out of 0-3) */
1749                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1750                 /* select XGXS */
1751                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1752
1753         } else { /* SerDes */
1754                 DP(NETIF_MSG_LINK, "SerDes\n");
1755                 /* select SerDes */
1756                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1757         }
1758
1759         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1760                       EMAC_RX_MODE_RESET);
1761         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1762                       EMAC_TX_MODE_RESET);
1763
1764         if (CHIP_REV_IS_SLOW(bp)) {
1765                 /* config GMII mode */
1766                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1767                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1768         } else { /* ASIC */
1769                 /* pause enable/disable */
1770                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1771                                EMAC_RX_MODE_FLOW_EN);
1772
1773                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1774                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1775                                 EMAC_TX_MODE_FLOW_EN));
1776                 if (!(params->feature_config_flags &
1777                       FEATURE_CONFIG_PFC_ENABLED)) {
1778                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1779                                 bnx2x_bits_en(bp, emac_base +
1780                                               EMAC_REG_EMAC_RX_MODE,
1781                                               EMAC_RX_MODE_FLOW_EN);
1782
1783                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1784                                 bnx2x_bits_en(bp, emac_base +
1785                                               EMAC_REG_EMAC_TX_MODE,
1786                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1787                                                EMAC_TX_MODE_FLOW_EN));
1788                 } else
1789                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1790                                       EMAC_TX_MODE_FLOW_EN);
1791         }
1792
1793         /* KEEP_VLAN_TAG, promiscuous */
1794         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1795         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1796
1797         /*
1798          * Setting this bit causes MAC control frames (except for pause
1799          * frames) to be passed on for processing. This setting has no
1800          * affect on the operation of the pause frames. This bit effects
1801          * all packets regardless of RX Parser packet sorting logic.
1802          * Turn the PFC off to make sure we are in Xon state before
1803          * enabling it.
1804          */
1805         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1806         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1807                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1808                 /* Enable PFC again */
1809                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1810                         EMAC_REG_RX_PFC_MODE_RX_EN |
1811                         EMAC_REG_RX_PFC_MODE_TX_EN |
1812                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1813
1814                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1815                         ((0x0101 <<
1816                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1817                          (0x00ff <<
1818                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1819                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1820         }
1821         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1822
1823         /* Set Loopback */
1824         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1825         if (lb)
1826                 val |= 0x810;
1827         else
1828                 val &= ~0x810;
1829         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1830
1831         /* enable emac */
1832         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1833
1834         /* enable emac for jumbo packets */
1835         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1836                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1837                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1838
1839         /* strip CRC */
1840         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1841
1842         /* disable the NIG in/out to the bmac */
1843         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1844         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1845         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1846
1847         /* enable the NIG in/out to the emac */
1848         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1849         val = 0;
1850         if ((params->feature_config_flags &
1851               FEATURE_CONFIG_PFC_ENABLED) ||
1852             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1853                 val = 1;
1854
1855         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1856         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1857
1858         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1859
1860         vars->mac_type = MAC_TYPE_EMAC;
1861         return 0;
1862 }
1863
1864 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1865                                    struct link_vars *vars)
1866 {
1867         u32 wb_data[2];
1868         struct bnx2x *bp = params->bp;
1869         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1870                 NIG_REG_INGRESS_BMAC0_MEM;
1871
1872         u32 val = 0x14;
1873         if ((!(params->feature_config_flags &
1874               FEATURE_CONFIG_PFC_ENABLED)) &&
1875                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1876                 /* Enable BigMAC to react on received Pause packets */
1877                 val |= (1<<5);
1878         wb_data[0] = val;
1879         wb_data[1] = 0;
1880         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1881
1882         /* tx control */
1883         val = 0xc0;
1884         if (!(params->feature_config_flags &
1885               FEATURE_CONFIG_PFC_ENABLED) &&
1886                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1887                 val |= 0x800000;
1888         wb_data[0] = val;
1889         wb_data[1] = 0;
1890         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1891 }
1892
1893 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1894                                    struct link_vars *vars,
1895                                    u8 is_lb)
1896 {
1897         /*
1898          * Set rx control: Strip CRC and enable BigMAC to relay
1899          * control packets to the system as well
1900          */
1901         u32 wb_data[2];
1902         struct bnx2x *bp = params->bp;
1903         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1904                 NIG_REG_INGRESS_BMAC0_MEM;
1905         u32 val = 0x14;
1906
1907         if ((!(params->feature_config_flags &
1908               FEATURE_CONFIG_PFC_ENABLED)) &&
1909                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1910                 /* Enable BigMAC to react on received Pause packets */
1911                 val |= (1<<5);
1912         wb_data[0] = val;
1913         wb_data[1] = 0;
1914         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1915         udelay(30);
1916
1917         /* Tx control */
1918         val = 0xc0;
1919         if (!(params->feature_config_flags &
1920                                 FEATURE_CONFIG_PFC_ENABLED) &&
1921             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1922                 val |= 0x800000;
1923         wb_data[0] = val;
1924         wb_data[1] = 0;
1925         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1926
1927         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1928                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1929                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1930                 wb_data[0] = 0x0;
1931                 wb_data[0] |= (1<<0);  /* RX */
1932                 wb_data[0] |= (1<<1);  /* TX */
1933                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1934                 wb_data[0] |= (1<<3);  /* 8 cos */
1935                 wb_data[0] |= (1<<5);  /* STATS */
1936                 wb_data[1] = 0;
1937                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1938                             wb_data, 2);
1939                 /* Clear the force Xon */
1940                 wb_data[0] &= ~(1<<2);
1941         } else {
1942                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1943                 /* disable PFC RX & TX & STATS and set 8 COS */
1944                 wb_data[0] = 0x8;
1945                 wb_data[1] = 0;
1946         }
1947
1948         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1949
1950         /*
1951          * Set Time (based unit is 512 bit time) between automatic
1952          * re-sending of PP packets amd enable automatic re-send of
1953          * Per-Priroity Packet as long as pp_gen is asserted and
1954          * pp_disable is low.
1955          */
1956         val = 0x8000;
1957         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1958                 val |= (1<<16); /* enable automatic re-send */
1959
1960         wb_data[0] = val;
1961         wb_data[1] = 0;
1962         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1963                     wb_data, 2);
1964
1965         /* mac control */
1966         val = 0x3; /* Enable RX and TX */
1967         if (is_lb) {
1968                 val |= 0x4; /* Local loopback */
1969                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1970         }
1971         /* When PFC enabled, Pass pause frames towards the NIG. */
1972         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1973                 val |= ((1<<6)|(1<<5));
1974
1975         wb_data[0] = val;
1976         wb_data[1] = 0;
1977         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1978 }
1979
1980
1981 /* PFC BRB internal port configuration params */
1982 struct bnx2x_pfc_brb_threshold_val {
1983         u32 pause_xoff;
1984         u32 pause_xon;
1985         u32 full_xoff;
1986         u32 full_xon;
1987 };
1988
1989 struct bnx2x_pfc_brb_e3b0_val {
1990         u32 full_lb_xoff_th;
1991         u32 full_lb_xon_threshold;
1992         u32 lb_guarantied;
1993         u32 mac_0_class_t_guarantied;
1994         u32 mac_0_class_t_guarantied_hyst;
1995         u32 mac_1_class_t_guarantied;
1996         u32 mac_1_class_t_guarantied_hyst;
1997 };
1998
1999 struct bnx2x_pfc_brb_th_val {
2000         struct bnx2x_pfc_brb_threshold_val pauseable_th;
2001         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
2002 };
2003 static int bnx2x_pfc_brb_get_config_params(
2004                                 struct link_params *params,
2005                                 struct bnx2x_pfc_brb_th_val *config_val)
2006 {
2007         struct bnx2x *bp = params->bp;
2008         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2009         if (CHIP_IS_E2(bp)) {
2010                 config_val->pauseable_th.pause_xoff =
2011                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2012                 config_val->pauseable_th.pause_xon =
2013                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2014                 config_val->pauseable_th.full_xoff =
2015                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2016                 config_val->pauseable_th.full_xon =
2017                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2018                 /* non pause able*/
2019                 config_val->non_pauseable_th.pause_xoff =
2020                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2021                 config_val->non_pauseable_th.pause_xon =
2022                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2023                 config_val->non_pauseable_th.full_xoff =
2024                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2025                 config_val->non_pauseable_th.full_xon =
2026                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2027         } else if (CHIP_IS_E3A0(bp)) {
2028                 config_val->pauseable_th.pause_xoff =
2029                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2030                 config_val->pauseable_th.pause_xon =
2031                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2032                 config_val->pauseable_th.full_xoff =
2033                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2034                 config_val->pauseable_th.full_xon =
2035                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2036                 /* non pause able*/
2037                 config_val->non_pauseable_th.pause_xoff =
2038                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2039                 config_val->non_pauseable_th.pause_xon =
2040                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2041                 config_val->non_pauseable_th.full_xoff =
2042                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2043                 config_val->non_pauseable_th.full_xon =
2044                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2045         } else if (CHIP_IS_E3B0(bp)) {
2046                 if (params->phy[INT_PHY].flags &
2047                     FLAGS_4_PORT_MODE) {
2048                         config_val->pauseable_th.pause_xoff =
2049                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2050                         config_val->pauseable_th.pause_xon =
2051                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2052                         config_val->pauseable_th.full_xoff =
2053                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2054                         config_val->pauseable_th.full_xon =
2055                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2056                         /* non pause able*/
2057                         config_val->non_pauseable_th.pause_xoff =
2058                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2059                         config_val->non_pauseable_th.pause_xon =
2060                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2061                         config_val->non_pauseable_th.full_xoff =
2062                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2063                         config_val->non_pauseable_th.full_xon =
2064                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2065             } else {
2066                 config_val->pauseable_th.pause_xoff =
2067                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2068                 config_val->pauseable_th.pause_xon =
2069                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2070                 config_val->pauseable_th.full_xoff =
2071                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2072                 config_val->pauseable_th.full_xon =
2073                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2074                 /* non pause able*/
2075                 config_val->non_pauseable_th.pause_xoff =
2076                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2077                 config_val->non_pauseable_th.pause_xon =
2078                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2079                 config_val->non_pauseable_th.full_xoff =
2080                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2081                 config_val->non_pauseable_th.full_xon =
2082                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2083             }
2084         } else
2085             return -EINVAL;
2086
2087         return 0;
2088 }
2089
2090
2091 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2092                                                  struct bnx2x_pfc_brb_e3b0_val
2093                                                  *e3b0_val,
2094                                                  u32 cos0_pauseable,
2095                                                  u32 cos1_pauseable)
2096 {
2097         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2098                 e3b0_val->full_lb_xoff_th =
2099                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2100                 e3b0_val->full_lb_xon_threshold =
2101                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2102                 e3b0_val->lb_guarantied =
2103                     PFC_E3B0_4P_LB_GUART;
2104                 e3b0_val->mac_0_class_t_guarantied =
2105                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2106                 e3b0_val->mac_0_class_t_guarantied_hyst =
2107                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2108                 e3b0_val->mac_1_class_t_guarantied =
2109                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2110                 e3b0_val->mac_1_class_t_guarantied_hyst =
2111                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2112         } else {
2113                 e3b0_val->full_lb_xoff_th =
2114                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2115                 e3b0_val->full_lb_xon_threshold =
2116                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2117                 e3b0_val->mac_0_class_t_guarantied_hyst =
2118                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2119                 e3b0_val->mac_1_class_t_guarantied =
2120                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2121                 e3b0_val->mac_1_class_t_guarantied_hyst =
2122                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2123
2124                 if (cos0_pauseable != cos1_pauseable) {
2125                         /* nonpauseable= Lossy + pauseable = Lossless*/
2126                         e3b0_val->lb_guarantied =
2127                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2128                         e3b0_val->mac_0_class_t_guarantied =
2129                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2130                 } else if (cos0_pauseable) {
2131                         /* Lossless +Lossless*/
2132                         e3b0_val->lb_guarantied =
2133                             PFC_E3B0_2P_PAUSE_LB_GUART;
2134                         e3b0_val->mac_0_class_t_guarantied =
2135                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2136                 } else {
2137                         /* Lossy +Lossy*/
2138                         e3b0_val->lb_guarantied =
2139                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2140                         e3b0_val->mac_0_class_t_guarantied =
2141                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2142                 }
2143         }
2144 }
2145 static int bnx2x_update_pfc_brb(struct link_params *params,
2146                                 struct link_vars *vars,
2147                                 struct bnx2x_nig_brb_pfc_port_params
2148                                 *pfc_params)
2149 {
2150         struct bnx2x *bp = params->bp;
2151         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2152         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2153             &config_val.pauseable_th;
2154         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2155         int set_pfc = params->feature_config_flags &
2156                 FEATURE_CONFIG_PFC_ENABLED;
2157         int bnx2x_status = 0;
2158         u8 port = params->port;
2159
2160         /* default - pause configuration */
2161         reg_th_config = &config_val.pauseable_th;
2162         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2163         if (0 != bnx2x_status)
2164                 return bnx2x_status;
2165
2166         if (set_pfc && pfc_params)
2167                 /* First COS */
2168                 if (!pfc_params->cos0_pauseable)
2169                         reg_th_config = &config_val.non_pauseable_th;
2170         /*
2171          * The number of free blocks below which the pause signal to class 0
2172          * of MAC #n is asserted. n=0,1
2173          */
2174         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2175                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2176                reg_th_config->pause_xoff);
2177         /*
2178          * The number of free blocks above which the pause signal to class 0
2179          * of MAC #n is de-asserted. n=0,1
2180          */
2181         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2182                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2183         /*
2184          * The number of free blocks below which the full signal to class 0
2185          * of MAC #n is asserted. n=0,1
2186          */
2187         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2188                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2189         /*
2190          * The number of free blocks above which the full signal to class 0
2191          * of MAC #n is de-asserted. n=0,1
2192          */
2193         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2194                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2195
2196         if (set_pfc && pfc_params) {
2197                 /* Second COS */
2198                 if (pfc_params->cos1_pauseable)
2199                         reg_th_config = &config_val.pauseable_th;
2200                 else
2201                         reg_th_config = &config_val.non_pauseable_th;
2202                 /*
2203                  * The number of free blocks below which the pause signal to
2204                  * class 1 of MAC #n is asserted. n=0,1
2205                 **/
2206                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2207                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2208                        reg_th_config->pause_xoff);
2209                 /*
2210                  * The number of free blocks above which the pause signal to
2211                  * class 1 of MAC #n is de-asserted. n=0,1
2212                  */
2213                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2214                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2215                        reg_th_config->pause_xon);
2216                 /*
2217                  * The number of free blocks below which the full signal to
2218                  * class 1 of MAC #n is asserted. n=0,1
2219                  */
2220                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2221                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2222                        reg_th_config->full_xoff);
2223                 /*
2224                  * The number of free blocks above which the full signal to
2225                  * class 1 of MAC #n is de-asserted. n=0,1
2226                  */
2227                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2228                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2229                        reg_th_config->full_xon);
2230
2231
2232                 if (CHIP_IS_E3B0(bp)) {
2233                         /*Should be done by init tool */
2234                         /*
2235                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2236                         * reset value
2237                         * 944
2238                         */
2239
2240                         /**
2241                          * The hysteresis on the guarantied buffer space for the Lb port
2242                          * before signaling XON.
2243                          **/
2244                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2245
2246                         bnx2x_pfc_brb_get_e3b0_config_params(
2247                             params,
2248                             &e3b0_val,
2249                             pfc_params->cos0_pauseable,
2250                             pfc_params->cos1_pauseable);
2251                         /**
2252                          * The number of free blocks below which the full signal to the
2253                          * LB port is asserted.
2254                         */
2255                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2256                                    e3b0_val.full_lb_xoff_th);
2257                         /**
2258                          * The number of free blocks above which the full signal to the
2259                          * LB port is de-asserted.
2260                         */
2261                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2262                                    e3b0_val.full_lb_xon_threshold);
2263                         /**
2264                         * The number of blocks guarantied for the MAC #n port. n=0,1
2265                         */
2266
2267                         /*The number of blocks guarantied for the LB port.*/
2268                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2269                                e3b0_val.lb_guarantied);
2270
2271                         /**
2272                          * The number of blocks guarantied for the MAC #n port.
2273                         */
2274                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2275                                    2 * e3b0_val.mac_0_class_t_guarantied);
2276                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2277                                    2 * e3b0_val.mac_1_class_t_guarantied);
2278                         /**
2279                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2280                         */
2281                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2282                                e3b0_val.mac_0_class_t_guarantied);
2283                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2284                                e3b0_val.mac_0_class_t_guarantied);
2285                         /**
2286                          * The hysteresis on the guarantied buffer space for class in
2287                          * MAC0.  t=0,1
2288                         */
2289                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2290                                e3b0_val.mac_0_class_t_guarantied_hyst);
2291                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2292                                e3b0_val.mac_0_class_t_guarantied_hyst);
2293
2294                         /**
2295                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2296                         */
2297                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2298                                e3b0_val.mac_1_class_t_guarantied);
2299                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2300                                e3b0_val.mac_1_class_t_guarantied);
2301                         /**
2302                          * The hysteresis on the guarantied buffer space for class #t
2303                         * in MAC1.  t=0,1
2304                         */
2305                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2306                                e3b0_val.mac_1_class_t_guarantied_hyst);
2307                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2308                                e3b0_val.mac_1_class_t_guarantied_hyst);
2309
2310             }
2311
2312         }
2313
2314         return bnx2x_status;
2315 }
2316
2317 /******************************************************************************
2318 * Description:
2319 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2320 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2321 ******************************************************************************/
2322 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2323                                               u8 cos_entry,
2324                                               u32 priority_mask, u8 port)
2325 {
2326         u32 nig_reg_rx_priority_mask_add = 0;
2327
2328         switch (cos_entry) {
2329         case 0:
2330              nig_reg_rx_priority_mask_add = (port) ?
2331                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2332                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2333              break;
2334         case 1:
2335             nig_reg_rx_priority_mask_add = (port) ?
2336                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2337                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2338             break;
2339         case 2:
2340             nig_reg_rx_priority_mask_add = (port) ?
2341                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2342                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2343             break;
2344         case 3:
2345             if (port)
2346                 return -EINVAL;
2347             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2348             break;
2349         case 4:
2350             if (port)
2351                 return -EINVAL;
2352             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2353             break;
2354         case 5:
2355             if (port)
2356                 return -EINVAL;
2357             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2358             break;
2359         }
2360
2361         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2362
2363         return 0;
2364 }
2365 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2366 {
2367         struct bnx2x *bp = params->bp;
2368
2369         REG_WR(bp, params->shmem_base +
2370                offsetof(struct shmem_region,
2371                         port_mb[params->port].link_status), link_status);
2372 }
2373
2374 static void bnx2x_update_pfc_nig(struct link_params *params,
2375                 struct link_vars *vars,
2376                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2377 {
2378         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2379         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2380         u32 pkt_priority_to_cos = 0;
2381         struct bnx2x *bp = params->bp;
2382         u8 port = params->port;
2383
2384         int set_pfc = params->feature_config_flags &
2385                 FEATURE_CONFIG_PFC_ENABLED;
2386         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2387
2388         /*
2389          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2390          * MAC control frames (that are not pause packets)
2391          * will be forwarded to the XCM.
2392          */
2393         xcm_mask = REG_RD(bp,
2394                                 port ? NIG_REG_LLH1_XCM_MASK :
2395                                 NIG_REG_LLH0_XCM_MASK);
2396         /*
2397          * nig params will override non PFC params, since it's possible to
2398          * do transition from PFC to SAFC
2399          */
2400         if (set_pfc) {
2401                 pause_enable = 0;
2402                 llfc_out_en = 0;
2403                 llfc_enable = 0;
2404                 if (CHIP_IS_E3(bp))
2405                         ppp_enable = 0;
2406                 else
2407                 ppp_enable = 1;
2408                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2409                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2410                 xcm0_out_en = 0;
2411                 p0_hwpfc_enable = 1;
2412         } else  {
2413                 if (nig_params) {
2414                         llfc_out_en = nig_params->llfc_out_en;
2415                         llfc_enable = nig_params->llfc_enable;
2416                         pause_enable = nig_params->pause_enable;
2417                 } else  /*defaul non PFC mode - PAUSE */
2418                         pause_enable = 1;
2419
2420                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2421                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2422                 xcm0_out_en = 1;
2423         }
2424
2425         if (CHIP_IS_E3(bp))
2426                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2427                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2428         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2429                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2430         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2431                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2432         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2433                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2434
2435         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2436                NIG_REG_PPP_ENABLE_0, ppp_enable);
2437
2438         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2439                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2440
2441         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2442
2443         /* output enable for RX_XCM # IF */
2444         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2445
2446         /* HW PFC TX enable */
2447         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2448
2449         if (nig_params) {
2450                 u8 i = 0;
2451                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2452
2453                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2454                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2455                 nig_params->rx_cos_priority_mask[i], port);
2456
2457                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2458                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2459                        nig_params->llfc_high_priority_classes);
2460
2461                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2462                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2463                        nig_params->llfc_low_priority_classes);
2464         }
2465         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2466                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2467                pkt_priority_to_cos);
2468 }
2469
2470 int bnx2x_update_pfc(struct link_params *params,
2471                       struct link_vars *vars,
2472                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2473 {
2474         /*
2475          * The PFC and pause are orthogonal to one another, meaning when
2476          * PFC is enabled, the pause are disabled, and when PFC is
2477          * disabled, pause are set according to the pause result.
2478          */
2479         u32 val;
2480         struct bnx2x *bp = params->bp;
2481         int bnx2x_status = 0;
2482         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2483
2484         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2485                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2486         else
2487                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2488
2489         bnx2x_update_mng(params, vars->link_status);
2490
2491         /* update NIG params */
2492         bnx2x_update_pfc_nig(params, vars, pfc_params);
2493
2494         /* update BRB params */
2495         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2496         if (0 != bnx2x_status)
2497                 return bnx2x_status;
2498
2499         if (!vars->link_up)
2500                 return bnx2x_status;
2501
2502         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2503         if (CHIP_IS_E3(bp))
2504                 bnx2x_update_pfc_xmac(params, vars, 0);
2505         else {
2506                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2507                 if ((val &
2508                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2509                     == 0) {
2510                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2511                         bnx2x_emac_enable(params, vars, 0);
2512                         return bnx2x_status;
2513                 }
2514
2515                 if (CHIP_IS_E2(bp))
2516                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2517                 else
2518                         bnx2x_update_pfc_bmac1(params, vars);
2519
2520                 val = 0;
2521                 if ((params->feature_config_flags &
2522                      FEATURE_CONFIG_PFC_ENABLED) ||
2523                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2524                         val = 1;
2525                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2526         }
2527         return bnx2x_status;
2528 }
2529
2530
2531 static int bnx2x_bmac1_enable(struct link_params *params,
2532                               struct link_vars *vars,
2533                               u8 is_lb)
2534 {
2535         struct bnx2x *bp = params->bp;
2536         u8 port = params->port;
2537         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2538                                NIG_REG_INGRESS_BMAC0_MEM;
2539         u32 wb_data[2];
2540         u32 val;
2541
2542         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2543
2544         /* XGXS control */
2545         wb_data[0] = 0x3c;
2546         wb_data[1] = 0;
2547         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2548                     wb_data, 2);
2549
2550         /* tx MAC SA */
2551         wb_data[0] = ((params->mac_addr[2] << 24) |
2552                        (params->mac_addr[3] << 16) |
2553                        (params->mac_addr[4] << 8) |
2554                         params->mac_addr[5]);
2555         wb_data[1] = ((params->mac_addr[0] << 8) |
2556                         params->mac_addr[1]);
2557         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2558
2559         /* mac control */
2560         val = 0x3;
2561         if (is_lb) {
2562                 val |= 0x4;
2563                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2564         }
2565         wb_data[0] = val;
2566         wb_data[1] = 0;
2567         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2568
2569         /* set rx mtu */
2570         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2571         wb_data[1] = 0;
2572         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2573
2574         bnx2x_update_pfc_bmac1(params, vars);
2575
2576         /* set tx mtu */
2577         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2578         wb_data[1] = 0;
2579         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2580
2581         /* set cnt max size */
2582         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2583         wb_data[1] = 0;
2584         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2585
2586         /* configure safc */
2587         wb_data[0] = 0x1000200;
2588         wb_data[1] = 0;
2589         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2590                     wb_data, 2);
2591
2592         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2593                 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2594                             wb_data, 2);
2595                 if (wb_data[0] > 0)
2596                         return -ESRCH;
2597         }
2598         return 0;
2599 }
2600
2601 static int bnx2x_bmac2_enable(struct link_params *params,
2602                               struct link_vars *vars,
2603                               u8 is_lb)
2604 {
2605         struct bnx2x *bp = params->bp;
2606         u8 port = params->port;
2607         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2608                                NIG_REG_INGRESS_BMAC0_MEM;
2609         u32 wb_data[2];
2610
2611         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2612
2613         wb_data[0] = 0;
2614         wb_data[1] = 0;
2615         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2616         udelay(30);
2617
2618         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2619         wb_data[0] = 0x3c;
2620         wb_data[1] = 0;
2621         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2622                     wb_data, 2);
2623
2624         udelay(30);
2625
2626         /* tx MAC SA */
2627         wb_data[0] = ((params->mac_addr[2] << 24) |
2628                        (params->mac_addr[3] << 16) |
2629                        (params->mac_addr[4] << 8) |
2630                         params->mac_addr[5]);
2631         wb_data[1] = ((params->mac_addr[0] << 8) |
2632                         params->mac_addr[1]);
2633         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2634                     wb_data, 2);
2635
2636         udelay(30);
2637
2638         /* Configure SAFC */
2639         wb_data[0] = 0x1000200;
2640         wb_data[1] = 0;
2641         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2642                     wb_data, 2);
2643         udelay(30);
2644
2645         /* set rx mtu */
2646         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2647         wb_data[1] = 0;
2648         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2649         udelay(30);
2650
2651         /* set tx mtu */
2652         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2653         wb_data[1] = 0;
2654         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2655         udelay(30);
2656         /* set cnt max size */
2657         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2658         wb_data[1] = 0;
2659         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2660         udelay(30);
2661         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2662
2663         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2664                 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2665                             wb_data, 2);
2666                 if (wb_data[0] > 0) {
2667                         DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2668                                        wb_data[0]);
2669                         return -ESRCH;
2670                 }
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int bnx2x_bmac_enable(struct link_params *params,
2677                              struct link_vars *vars,
2678                              u8 is_lb)
2679 {
2680         int rc = 0;
2681         u8 port = params->port;
2682         struct bnx2x *bp = params->bp;
2683         u32 val;
2684         /* reset and unreset the BigMac */
2685         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2686                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2687         msleep(1);
2688
2689         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2690                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2691
2692         /* enable access for bmac registers */
2693         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2694
2695         /* Enable BMAC according to BMAC type*/
2696         if (CHIP_IS_E2(bp))
2697                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2698         else
2699                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2700         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2701         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2702         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2703         val = 0;
2704         if ((params->feature_config_flags &
2705               FEATURE_CONFIG_PFC_ENABLED) ||
2706             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2707                 val = 1;
2708         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2709         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2710         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2711         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2712         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2713         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2714
2715         vars->mac_type = MAC_TYPE_BMAC;
2716         return rc;
2717 }
2718
2719 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2720 {
2721         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2722                         NIG_REG_INGRESS_BMAC0_MEM;
2723         u32 wb_data[2];
2724         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2725
2726         /* Only if the bmac is out of reset */
2727         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2728                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2729             nig_bmac_enable) {
2730
2731                 if (CHIP_IS_E2(bp)) {
2732                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2733                         REG_RD_DMAE(bp, bmac_addr +
2734                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2735                                     wb_data, 2);
2736                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2737                         REG_WR_DMAE(bp, bmac_addr +
2738                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2739                                     wb_data, 2);
2740                 } else {
2741                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2742                         REG_RD_DMAE(bp, bmac_addr +
2743                                         BIGMAC_REGISTER_BMAC_CONTROL,
2744                                         wb_data, 2);
2745                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2746                         REG_WR_DMAE(bp, bmac_addr +
2747                                         BIGMAC_REGISTER_BMAC_CONTROL,
2748                                         wb_data, 2);
2749                 }
2750                 msleep(1);
2751         }
2752 }
2753
2754 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2755                             u32 line_speed)
2756 {
2757         struct bnx2x *bp = params->bp;
2758         u8 port = params->port;
2759         u32 init_crd, crd;
2760         u32 count = 1000;
2761
2762         /* disable port */
2763         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2764
2765         /* wait for init credit */
2766         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2767         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2768         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2769
2770         while ((init_crd != crd) && count) {
2771                 msleep(5);
2772
2773                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2774                 count--;
2775         }
2776         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2777         if (init_crd != crd) {
2778                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2779                           init_crd, crd);
2780                 return -EINVAL;
2781         }
2782
2783         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2784             line_speed == SPEED_10 ||
2785             line_speed == SPEED_100 ||
2786             line_speed == SPEED_1000 ||
2787             line_speed == SPEED_2500) {
2788                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2789                 /* update threshold */
2790                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2791                 /* update init credit */
2792                 init_crd = 778;         /* (800-18-4) */
2793
2794         } else {
2795                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2796                               ETH_OVREHEAD)/16;
2797                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2798                 /* update threshold */
2799                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2800                 /* update init credit */
2801                 switch (line_speed) {
2802                 case SPEED_10000:
2803                         init_crd = thresh + 553 - 22;
2804                         break;
2805                 default:
2806                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2807                                   line_speed);
2808                         return -EINVAL;
2809                 }
2810         }
2811         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2812         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2813                  line_speed, init_crd);
2814
2815         /* probe the credit changes */
2816         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2817         msleep(5);
2818         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2819
2820         /* enable port */
2821         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2822         return 0;
2823 }
2824
2825 /**
2826  * bnx2x_get_emac_base - retrive emac base address
2827  *
2828  * @bp:                 driver handle
2829  * @mdc_mdio_access:    access type
2830  * @port:               port id
2831  *
2832  * This function selects the MDC/MDIO access (through emac0 or
2833  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2834  * phy has a default access mode, which could also be overridden
2835  * by nvram configuration. This parameter, whether this is the
2836  * default phy configuration, or the nvram overrun
2837  * configuration, is passed here as mdc_mdio_access and selects
2838  * the emac_base for the CL45 read/writes operations
2839  */
2840 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2841                                u32 mdc_mdio_access, u8 port)
2842 {
2843         u32 emac_base = 0;
2844         switch (mdc_mdio_access) {
2845         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2846                 break;
2847         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2848                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2849                         emac_base = GRCBASE_EMAC1;
2850                 else
2851                         emac_base = GRCBASE_EMAC0;
2852                 break;
2853         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2854                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2855                         emac_base = GRCBASE_EMAC0;
2856                 else
2857                         emac_base = GRCBASE_EMAC1;
2858                 break;
2859         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2860                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2861                 break;
2862         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2863                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2864                 break;
2865         default:
2866                 break;
2867         }
2868         return emac_base;
2869
2870 }
2871
2872 /******************************************************************/
2873 /*                      CL22 access functions                     */
2874 /******************************************************************/
2875 static int bnx2x_cl22_write(struct bnx2x *bp,
2876                                        struct bnx2x_phy *phy,
2877                                        u16 reg, u16 val)
2878 {
2879         u32 tmp, mode;
2880         u8 i;
2881         int rc = 0;
2882         /* Switch to CL22 */
2883         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2884         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2885                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2886
2887         /* address */
2888         tmp = ((phy->addr << 21) | (reg << 16) | val |
2889                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2890                EMAC_MDIO_COMM_START_BUSY);
2891         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2892
2893         for (i = 0; i < 50; i++) {
2894                 udelay(10);
2895
2896                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2897                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2898                         udelay(5);
2899                         break;
2900                 }
2901         }
2902         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2903                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2904                 rc = -EFAULT;
2905         }
2906         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2907         return rc;
2908 }
2909
2910 static int bnx2x_cl22_read(struct bnx2x *bp,
2911                                       struct bnx2x_phy *phy,
2912                                       u16 reg, u16 *ret_val)
2913 {
2914         u32 val, mode;
2915         u16 i;
2916         int rc = 0;
2917
2918         /* Switch to CL22 */
2919         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2920         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2921                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2922
2923         /* address */
2924         val = ((phy->addr << 21) | (reg << 16) |
2925                EMAC_MDIO_COMM_COMMAND_READ_22 |
2926                EMAC_MDIO_COMM_START_BUSY);
2927         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2928
2929         for (i = 0; i < 50; i++) {
2930                 udelay(10);
2931
2932                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2933                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2934                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2935                         udelay(5);
2936                         break;
2937                 }
2938         }
2939         if (val & EMAC_MDIO_COMM_START_BUSY) {
2940                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2941
2942                 *ret_val = 0;
2943                 rc = -EFAULT;
2944         }
2945         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2946         return rc;
2947 }
2948
2949 /******************************************************************/
2950 /*                      CL45 access functions                     */
2951 /******************************************************************/
2952 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2953                            u8 devad, u16 reg, u16 *ret_val)
2954 {
2955         u32 val;
2956         u16 i;
2957         int rc = 0;
2958
2959         /* address */
2960         val = ((phy->addr << 21) | (devad << 16) | reg |
2961                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2962                EMAC_MDIO_COMM_START_BUSY);
2963         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2964
2965         for (i = 0; i < 50; i++) {
2966                 udelay(10);
2967
2968                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2969                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2970                         udelay(5);
2971                         break;
2972                 }
2973         }
2974         if (val & EMAC_MDIO_COMM_START_BUSY) {
2975                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2976                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2977                 *ret_val = 0;
2978                 rc = -EFAULT;
2979         } else {
2980                 /* data */
2981                 val = ((phy->addr << 21) | (devad << 16) |
2982                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2983                        EMAC_MDIO_COMM_START_BUSY);
2984                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2985
2986                 for (i = 0; i < 50; i++) {
2987                         udelay(10);
2988
2989                         val = REG_RD(bp, phy->mdio_ctrl +
2990                                      EMAC_REG_EMAC_MDIO_COMM);
2991                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2992                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2993                                 break;
2994                         }
2995                 }
2996                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2997                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2998                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2999                         *ret_val = 0;
3000                         rc = -EFAULT;
3001                 }
3002         }
3003         /* Work around for E3 A0 */
3004         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3005                 phy->flags ^= FLAGS_DUMMY_READ;
3006                 if (phy->flags & FLAGS_DUMMY_READ) {
3007                         u16 temp_val;
3008                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3009                 }
3010         }
3011
3012         return rc;
3013 }
3014
3015 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3016                             u8 devad, u16 reg, u16 val)
3017 {
3018         u32 tmp;
3019         u8 i;
3020         int rc = 0;
3021
3022         /* address */
3023
3024         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3025                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3026                EMAC_MDIO_COMM_START_BUSY);
3027         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3028
3029         for (i = 0; i < 50; i++) {
3030                 udelay(10);
3031
3032                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3033                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3034                         udelay(5);
3035                         break;
3036                 }
3037         }
3038         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3039                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3040                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3041                 rc = -EFAULT;
3042
3043         } else {
3044                 /* data */
3045                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3046                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3047                        EMAC_MDIO_COMM_START_BUSY);
3048                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3049
3050                 for (i = 0; i < 50; i++) {
3051                         udelay(10);
3052
3053                         tmp = REG_RD(bp, phy->mdio_ctrl +
3054                                      EMAC_REG_EMAC_MDIO_COMM);
3055                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3056                                 udelay(5);
3057                                 break;
3058                         }
3059                 }
3060                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3061                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3062                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3063                         rc = -EFAULT;
3064                 }
3065         }
3066         /* Work around for E3 A0 */
3067         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3068                 phy->flags ^= FLAGS_DUMMY_READ;
3069                 if (phy->flags & FLAGS_DUMMY_READ) {
3070                         u16 temp_val;
3071                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3072                 }
3073         }
3074
3075         return rc;
3076 }
3077
3078
3079 /******************************************************************/
3080 /*                      BSC access functions from E3              */
3081 /******************************************************************/
3082 static void bnx2x_bsc_module_sel(struct link_params *params)
3083 {
3084         int idx;
3085         u32 board_cfg, sfp_ctrl;
3086         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3087         struct bnx2x *bp = params->bp;
3088         u8 port = params->port;
3089         /* Read I2C output PINs */
3090         board_cfg = REG_RD(bp, params->shmem_base +
3091                            offsetof(struct shmem_region,
3092                                     dev_info.shared_hw_config.board));
3093         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3094         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3095                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3096
3097         /* Read I2C output value */
3098         sfp_ctrl = REG_RD(bp, params->shmem_base +
3099                           offsetof(struct shmem_region,
3100                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3101         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3102         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3103         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3104         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3105                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3106 }
3107
3108 static int bnx2x_bsc_read(struct link_params *params,
3109                           struct bnx2x_phy *phy,
3110                           u8 sl_devid,
3111                           u16 sl_addr,
3112                           u8 lc_addr,
3113                           u8 xfer_cnt,
3114                           u32 *data_array)
3115 {
3116         u32 val, i;
3117         int rc = 0;
3118         struct bnx2x *bp = params->bp;
3119
3120         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3121                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3122                 return -EINVAL;
3123         }
3124
3125         if (xfer_cnt > 16) {
3126                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3127                                         xfer_cnt);
3128                 return -EINVAL;
3129         }
3130         bnx2x_bsc_module_sel(params);
3131
3132         xfer_cnt = 16 - lc_addr;
3133
3134         /* enable the engine */
3135         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3136         val |= MCPR_IMC_COMMAND_ENABLE;
3137         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3138
3139         /* program slave device ID */
3140         val = (sl_devid << 16) | sl_addr;
3141         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3142
3143         /* start xfer with 0 byte to update the address pointer ???*/
3144         val = (MCPR_IMC_COMMAND_ENABLE) |
3145               (MCPR_IMC_COMMAND_WRITE_OP <<
3146                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3147                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3148         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149
3150         /* poll for completion */
3151         i = 0;
3152         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3153         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3154                 udelay(10);
3155                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3156                 if (i++ > 1000) {
3157                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3158                                                                 i);
3159                         rc = -EFAULT;
3160                         break;
3161                 }
3162         }
3163         if (rc == -EFAULT)
3164                 return rc;
3165
3166         /* start xfer with read op */
3167         val = (MCPR_IMC_COMMAND_ENABLE) |
3168                 (MCPR_IMC_COMMAND_READ_OP <<
3169                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3170                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3171                   (xfer_cnt);
3172         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3173
3174         /* poll for completion */
3175         i = 0;
3176         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3177         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3178                 udelay(10);
3179                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3180                 if (i++ > 1000) {
3181                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3182                         rc = -EFAULT;
3183                         break;
3184                 }
3185         }
3186         if (rc == -EFAULT)
3187                 return rc;
3188
3189         for (i = (lc_addr >> 2); i < 4; i++) {
3190                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3191 #ifdef __BIG_ENDIAN
3192                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3193                                 ((data_array[i] & 0x0000ff00) << 8) |
3194                                 ((data_array[i] & 0x00ff0000) >> 8) |
3195                                 ((data_array[i] & 0xff000000) >> 24);
3196 #endif
3197         }
3198         return rc;
3199 }
3200
3201 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3202                                      u8 devad, u16 reg, u16 or_val)
3203 {
3204         u16 val;
3205         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3206         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3207 }
3208
3209 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3210                    u8 devad, u16 reg, u16 *ret_val)
3211 {
3212         u8 phy_index;
3213         /*
3214          * Probe for the phy according to the given phy_addr, and execute
3215          * the read request on it
3216          */
3217         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3218                 if (params->phy[phy_index].addr == phy_addr) {
3219                         return bnx2x_cl45_read(params->bp,
3220                                                &params->phy[phy_index], devad,
3221                                                reg, ret_val);
3222                 }
3223         }
3224         return -EINVAL;
3225 }
3226
3227 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3228                     u8 devad, u16 reg, u16 val)
3229 {
3230         u8 phy_index;
3231         /*
3232          * Probe for the phy according to the given phy_addr, and execute
3233          * the write request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_write(params->bp,
3238                                                 &params->phy[phy_index], devad,
3239                                                 reg, val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3245                                   struct link_params *params)
3246 {
3247         u8 lane = 0;
3248         struct bnx2x *bp = params->bp;
3249         u32 path_swap, path_swap_ovr;
3250         u8 path, port;
3251
3252         path = BP_PATH(bp);
3253         port = params->port;
3254
3255         if (bnx2x_is_4_port_mode(bp)) {
3256                 u32 port_swap, port_swap_ovr;
3257
3258                 /*figure out path swap value */
3259                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3260                 if (path_swap_ovr & 0x1)
3261                         path_swap = (path_swap_ovr & 0x2);
3262                 else
3263                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3264
3265                 if (path_swap)
3266                         path = path ^ 1;
3267
3268                 /*figure out port swap value */
3269                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3270                 if (port_swap_ovr & 0x1)
3271                         port_swap = (port_swap_ovr & 0x2);
3272                 else
3273                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3274
3275                 if (port_swap)
3276                         port = port ^ 1;
3277
3278                 lane = (port<<1) + path;
3279         } else { /* two port mode - no port swap */
3280
3281                 /*figure out path swap value */
3282                 path_swap_ovr =
3283                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3284                 if (path_swap_ovr & 0x1) {
3285                         path_swap = (path_swap_ovr & 0x2);
3286                 } else {
3287                         path_swap =
3288                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3289                 }
3290                 if (path_swap)
3291                         path = path ^ 1;
3292
3293                 lane = path << 1 ;
3294         }
3295         return lane;
3296 }
3297
3298 static void bnx2x_set_aer_mmd(struct link_params *params,
3299                               struct bnx2x_phy *phy)
3300 {
3301         u32 ser_lane;
3302         u16 offset, aer_val;
3303         struct bnx2x *bp = params->bp;
3304         ser_lane = ((params->lane_config &
3305                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3306                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3307
3308         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3309                 (phy->addr + ser_lane) : 0;
3310
3311         if (USES_WARPCORE(bp)) {
3312                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3313                 /*
3314                  * In Dual-lane mode, two lanes are joined together,
3315                  * so in order to configure them, the AER broadcast method is
3316                  * used here.
3317                  * 0x200 is the broadcast address for lanes 0,1
3318                  * 0x201 is the broadcast address for lanes 2,3
3319                  */
3320                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3321                         aer_val = (aer_val >> 1) | 0x200;
3322         } else if (CHIP_IS_E2(bp))
3323                 aer_val = 0x3800 + offset - 1;
3324         else
3325                 aer_val = 0x3800 + offset;
3326         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3327         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3328                           MDIO_AER_BLOCK_AER_REG, aer_val);
3329
3330 }
3331
3332 /******************************************************************/
3333 /*                      Internal phy section                      */
3334 /******************************************************************/
3335
3336 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3337 {
3338         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3339
3340         /* Set Clause 22 */
3341         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3342         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3343         udelay(500);
3344         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3345         udelay(500);
3346          /* Set Clause 45 */
3347         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3348 }
3349
3350 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3351 {
3352         u32 val;
3353
3354         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3355
3356         val = SERDES_RESET_BITS << (port*16);
3357
3358         /* reset and unreset the SerDes/XGXS */
3359         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3360         udelay(500);
3361         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3362
3363         bnx2x_set_serdes_access(bp, port);
3364
3365         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3366                DEFAULT_PHY_DEV_ADDR);
3367 }
3368
3369 static void bnx2x_xgxs_deassert(struct link_params *params)
3370 {
3371         struct bnx2x *bp = params->bp;
3372         u8 port;
3373         u32 val;
3374         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3375         port = params->port;
3376
3377         val = XGXS_RESET_BITS << (port*16);
3378
3379         /* reset and unreset the SerDes/XGXS */
3380         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3381         udelay(500);
3382         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3383
3384         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3385         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3386                params->phy[INT_PHY].def_md_devad);
3387 }
3388
3389 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3390                                      struct link_params *params, u16 *ieee_fc)
3391 {
3392         struct bnx2x *bp = params->bp;
3393         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3394         /**
3395          * resolve pause mode and advertisement Please refer to Table
3396          * 28B-3 of the 802.3ab-1999 spec
3397          */
3398
3399         switch (phy->req_flow_ctrl) {
3400         case BNX2X_FLOW_CTRL_AUTO:
3401                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3402                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3403                 else
3404                         *ieee_fc |=
3405                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3406                 break;
3407
3408         case BNX2X_FLOW_CTRL_TX:
3409                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3410                 break;
3411
3412         case BNX2X_FLOW_CTRL_RX:
3413         case BNX2X_FLOW_CTRL_BOTH:
3414                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3415                 break;
3416
3417         case BNX2X_FLOW_CTRL_NONE:
3418         default:
3419                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3420                 break;
3421         }
3422         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3423 }
3424
3425 static void set_phy_vars(struct link_params *params,
3426                          struct link_vars *vars)
3427 {
3428         struct bnx2x *bp = params->bp;
3429         u8 actual_phy_idx, phy_index, link_cfg_idx;
3430         u8 phy_config_swapped = params->multi_phy_config &
3431                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3432         for (phy_index = INT_PHY; phy_index < params->num_phys;
3433               phy_index++) {
3434                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3435                 actual_phy_idx = phy_index;
3436                 if (phy_config_swapped) {
3437                         if (phy_index == EXT_PHY1)
3438                                 actual_phy_idx = EXT_PHY2;
3439                         else if (phy_index == EXT_PHY2)
3440                                 actual_phy_idx = EXT_PHY1;
3441                 }
3442                 params->phy[actual_phy_idx].req_flow_ctrl =
3443                         params->req_flow_ctrl[link_cfg_idx];
3444
3445                 params->phy[actual_phy_idx].req_line_speed =
3446                         params->req_line_speed[link_cfg_idx];
3447
3448                 params->phy[actual_phy_idx].speed_cap_mask =
3449                         params->speed_cap_mask[link_cfg_idx];
3450
3451                 params->phy[actual_phy_idx].req_duplex =
3452                         params->req_duplex[link_cfg_idx];
3453
3454                 if (params->req_line_speed[link_cfg_idx] ==
3455                     SPEED_AUTO_NEG)
3456                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3457
3458                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3459                            " speed_cap_mask %x\n",
3460                            params->phy[actual_phy_idx].req_flow_ctrl,
3461                            params->phy[actual_phy_idx].req_line_speed,
3462                            params->phy[actual_phy_idx].speed_cap_mask);
3463         }
3464 }
3465
3466 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3467                                     struct bnx2x_phy *phy,
3468                                     struct link_vars *vars)
3469 {
3470         u16 val;
3471         struct bnx2x *bp = params->bp;
3472         /* read modify write pause advertizing */
3473         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3474
3475         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3476
3477         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3478         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3479         if ((vars->ieee_fc &
3480             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3481             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3482                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3483         }
3484         if ((vars->ieee_fc &
3485             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3486             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3487                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3488         }
3489         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3490         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3491 }
3492
3493 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3494 {                                               /*  LD      LP   */
3495         switch (pause_result) {                 /* ASYM P ASYM P */
3496         case 0xb:                               /*   1  0   1  1 */
3497                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3498                 break;
3499
3500         case 0xe:                               /*   1  1   1  0 */
3501                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3502                 break;
3503
3504         case 0x5:                               /*   0  1   0  1 */
3505         case 0x7:                               /*   0  1   1  1 */
3506         case 0xd:                               /*   1  1   0  1 */
3507         case 0xf:                               /*   1  1   1  1 */
3508                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3509                 break;
3510
3511         default:
3512                 break;
3513         }
3514         if (pause_result & (1<<0))
3515                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3516         if (pause_result & (1<<1))
3517                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3518 }
3519
3520 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3521                                    struct link_params *params,
3522                                    struct link_vars *vars)
3523 {
3524         struct bnx2x *bp = params->bp;
3525         u16 ld_pause;           /* local */
3526         u16 lp_pause;           /* link partner */
3527         u16 pause_result;
3528         u8 ret = 0;
3529         /* read twice */
3530
3531         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3532
3533         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3534                 vars->flow_ctrl = phy->req_flow_ctrl;
3535         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3536                 vars->flow_ctrl = params->req_fc_auto_adv;
3537         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3538                 ret = 1;
3539                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3540                         bnx2x_cl22_read(bp, phy,
3541                                         0x4, &ld_pause);
3542                         bnx2x_cl22_read(bp, phy,
3543                                         0x5, &lp_pause);
3544                 } else {
3545                         bnx2x_cl45_read(bp, phy,
3546                                         MDIO_AN_DEVAD,
3547                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3548                         bnx2x_cl45_read(bp, phy,
3549                                         MDIO_AN_DEVAD,
3550                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3551                 }
3552                 pause_result = (ld_pause &
3553                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3554                 pause_result |= (lp_pause &
3555                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3556                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3557                    pause_result);
3558                 bnx2x_pause_resolve(vars, pause_result);
3559         }
3560         return ret;
3561 }
3562 /******************************************************************/
3563 /*                      Warpcore section                          */
3564 /******************************************************************/
3565 /* The init_internal_warpcore should mirror the xgxs,
3566  * i.e. reset the lane (if needed), set aer for the
3567  * init configuration, and set/clear SGMII flag. Internal
3568  * phy init is done purely in phy_init stage.
3569  */
3570 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3571                                         struct link_params *params,
3572                                         struct link_vars *vars) {
3573         u16 val16 = 0, lane, bam37 = 0;
3574         struct bnx2x *bp = params->bp;
3575         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3576         /* Check adding advertisement for 1G KX */
3577         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3578              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3579             (vars->line_speed == SPEED_1000)) {
3580                 u16 sd_digital;
3581                 val16 |= (1<<5);
3582
3583                 /* Enable CL37 1G Parallel Detect */
3584                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3585                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3586                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3587                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3588                                  (sd_digital | 0x1));
3589
3590                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3591         }
3592         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3593              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3594             (vars->line_speed ==  SPEED_10000)) {
3595                 /* Check adding advertisement for 10G KR */
3596                 val16 |= (1<<7);
3597                 /* Enable 10G Parallel Detect */
3598                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3599                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3600
3601                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3602         }
3603
3604         /* Set Transmit PMD settings */
3605         lane = bnx2x_get_warpcore_lane(phy, params);
3606         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3607                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3608                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3609                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3610                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3611         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3612                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3613                          0x03f0);
3614         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3615                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3616                          0x03f0);
3617         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3618                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3619                          0x383f);
3620
3621         /* Advertised speeds */
3622         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3623                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3624
3625         /* Enable CL37 BAM */
3626         if (REG_RD(bp, params->shmem_base +
3627                    offsetof(struct shmem_region, dev_info.
3628                             port_hw_config[params->port].default_cfg)) &
3629             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3630                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3631                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3632                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3633                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3634                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3635         }
3636
3637         /* Advertise pause */
3638         bnx2x_ext_phy_set_pause(params, phy, vars);
3639
3640         /* Enable Autoneg */
3641         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3642                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3643
3644         /* Over 1G - AN local device user page 1 */
3645         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3646                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3647
3648         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3649                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3650
3651         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3652                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3653 }
3654
3655 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3656                                       struct link_params *params,
3657                                       struct link_vars *vars)
3658 {
3659         struct bnx2x *bp = params->bp;
3660         u16 val;
3661
3662         /* Disable Autoneg */
3663         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3664                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3665
3666         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3667                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3668
3669         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3670                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3671
3672         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3673                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3674
3675         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3676                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3677
3678         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3679                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3680
3681         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3682                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3683
3684         /* Disable CL36 PCS Tx */
3685         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3686                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3687
3688         /* Double Wide Single Data Rate @ pll rate */
3689         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3690                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3691
3692         /* Leave cl72 training enable, needed for KR */
3693         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3694                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3695                 0x2);
3696
3697         /* Leave CL72 enabled */
3698         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3699                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3700                          &val);
3701         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3702                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3703                          val | 0x3800);
3704
3705         /* Set speed via PMA/PMD register */
3706         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3707                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3708
3709         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3710                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3711
3712         /*Enable encoded forced speed */
3713         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3714                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3715
3716         /* Turn TX scramble payload only the 64/66 scrambler */
3717         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3718                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3719
3720         /* Turn RX scramble payload only the 64/66 scrambler */
3721         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3722                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3723
3724         /* set and clear loopback to cause a reset to 64/66 decoder */
3725         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3726                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3727         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3728                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3729
3730 }
3731
3732 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3733                                        struct link_params *params,
3734                                        u8 is_xfi)
3735 {
3736         struct bnx2x *bp = params->bp;
3737         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3738         /* Hold rxSeqStart */
3739         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3740                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3741         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3742                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3743
3744         /* Hold tx_fifo_reset */
3745         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3746                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3747         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3748                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3749
3750         /* Disable CL73 AN */
3751         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3752
3753         /* Disable 100FX Enable and Auto-Detect */
3754         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3755                         MDIO_WC_REG_FX100_CTRL1, &val);
3756         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3757                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3758
3759         /* Disable 100FX Idle detect */
3760         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3761                         MDIO_WC_REG_FX100_CTRL3, &val);
3762         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3764
3765         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3766         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3767                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3768         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3769                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3770
3771         /* Turn off auto-detect & fiber mode */
3772         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3773                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3774         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3775                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3776                          (val & 0xFFEE));
3777
3778         /* Set filter_force_link, disable_false_link and parallel_detect */
3779         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3780                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3781         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3782                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3783                          ((val | 0x0006) & 0xFFFE));
3784
3785         /* Set XFI / SFI */
3786         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3787                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3788
3789         misc1_val &= ~(0x1f);
3790
3791         if (is_xfi) {
3792                 misc1_val |= 0x5;
3793                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3794                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3795                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3796                 tx_driver_val =
3797                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3798                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3799                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3800
3801         } else {
3802                 misc1_val |= 0x9;
3803                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3804                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3805                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3806                 tx_driver_val =
3807                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3808                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3809                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3810         }
3811         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3812                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3813
3814         /* Set Transmit PMD settings */
3815         lane = bnx2x_get_warpcore_lane(phy, params);
3816         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3817                          MDIO_WC_REG_TX_FIR_TAP,
3818                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3821                          tx_driver_val);
3822
3823         /* Enable fiber mode, enable and invert sig_det */
3824         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3825                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3826         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3827                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3828
3829         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3830         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3831                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3832         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3833                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3834
3835         /* 10G XFI Full Duplex */
3836         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3838
3839         /* Release tx_fifo_reset */
3840         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3841                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3842         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3843                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3844
3845         /* Release rxSeqStart */
3846         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3847                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3848         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3849                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3850 }
3851
3852 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3853                                        struct bnx2x_phy *phy)
3854 {
3855         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3856 }
3857
3858 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3859                                          struct bnx2x_phy *phy,
3860                                          u16 lane)
3861 {
3862         /* Rx0 anaRxControl1G */
3863         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3864                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3865
3866         /* Rx2 anaRxControl1G */
3867         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3868                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3869
3870         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3872
3873         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3874                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3875
3876         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3878
3879         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3881
3882         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3883                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3884
3885         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3886                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3887
3888         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3889                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3890
3891         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3892                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3893
3894         /* Serdes Digital Misc1 */
3895         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3896                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3897
3898         /* Serdes Digital4 Misc3 */
3899         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3900                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3901
3902         /* Set Transmit PMD settings */
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                          MDIO_WC_REG_TX_FIR_TAP,
3905                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3906                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3907                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3908                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3909         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3910                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3911                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3912                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3913                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3914 }
3915
3916 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3917                                            struct link_params *params,
3918                                            u8 fiber_mode)
3919 {
3920         struct bnx2x *bp = params->bp;
3921         u16 val16, digctrl_kx1, digctrl_kx2;
3922         u8 lane;
3923
3924         lane = bnx2x_get_warpcore_lane(phy, params);
3925
3926         /* Clear XFI clock comp in non-10G single lane mode. */
3927         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3928                         MDIO_WC_REG_RX66_CONTROL, &val16);
3929         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3930                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3931
3932         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3933                 /* SGMII Autoneg */
3934                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3935                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3936                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3938                                  val16 | 0x1000);
3939                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3940         } else {
3941                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3942                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3943                 val16 &= 0xcfbf;
3944                 switch (phy->req_line_speed) {
3945                 case SPEED_10:
3946                         break;
3947                 case SPEED_100:
3948                         val16 |= 0x2000;
3949                         break;
3950                 case SPEED_1000:
3951                         val16 |= 0x0040;
3952                         break;
3953                 default:
3954                         DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3955                                            "\n", phy->req_line_speed);
3956                         return;
3957                 }
3958
3959                 if (phy->req_duplex == DUPLEX_FULL)
3960                         val16 |= 0x0100;
3961
3962                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3963                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3964
3965                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3966                                phy->req_line_speed);
3967                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3968                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3969                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3970         }
3971
3972         /* SGMII Slave mode and disable signal detect */
3973         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3974                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3975         if (fiber_mode)
3976                 digctrl_kx1 = 1;
3977         else
3978                 digctrl_kx1 &= 0xff4a;
3979
3980         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3981                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3982                         digctrl_kx1);
3983
3984         /* Turn off parallel detect */
3985         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3986                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3987         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3988                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3989                         (digctrl_kx2 & ~(1<<2)));
3990
3991         /* Re-enable parallel detect */
3992         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3993                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3994                         (digctrl_kx2 | (1<<2)));
3995
3996         /* Enable autodet */
3997         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3998                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3999                         (digctrl_kx1 | 0x10));
4000 }
4001
4002 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4003                                       struct bnx2x_phy *phy,
4004                                       u8 reset)
4005 {
4006         u16 val;
4007         /* Take lane out of reset after configuration is finished */
4008         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4009                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4010         if (reset)
4011                 val |= 0xC000;
4012         else
4013                 val &= 0x3FFF;
4014         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4016         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4017                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4018 }
4019
4020
4021         /* Clear SFI/XFI link settings registers */
4022 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4023                                       struct link_params *params,
4024                                       u16 lane)
4025 {
4026         struct bnx2x *bp = params->bp;
4027         u16 val16;
4028
4029         /* Set XFI clock comp as default. */
4030         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4031                         MDIO_WC_REG_RX66_CONTROL, &val16);
4032         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4033                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4034
4035         bnx2x_warpcore_reset_lane(bp, phy, 1);
4036         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4037         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4038                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4039         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4041         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4042                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4045         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4046                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4047         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4048                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4049         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4050                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4051         lane = bnx2x_get_warpcore_lane(phy, params);
4052         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4053                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4054         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4055                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4056         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4058         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4059                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4060         bnx2x_warpcore_reset_lane(bp, phy, 0);
4061 }
4062
4063 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4064                                                 u32 chip_id,
4065                                                 u32 shmem_base, u8 port,
4066                                                 u8 *gpio_num, u8 *gpio_port)
4067 {
4068         u32 cfg_pin;
4069         *gpio_num = 0;
4070         *gpio_port = 0;
4071         if (CHIP_IS_E3(bp)) {
4072                 cfg_pin = (REG_RD(bp, shmem_base +
4073                                 offsetof(struct shmem_region,
4074                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4075                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4076                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4077
4078                 /*
4079                  * Should not happen. This function called upon interrupt
4080                  * triggered by GPIO ( since EPIO can only generate interrupts
4081                  * to MCP).
4082                  * So if this function was called and none of the GPIOs was set,
4083                  * it means the shit hit the fan.
4084                  */
4085                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4086                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4087                         DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4088                                            "module detect indication\n",
4089                                        cfg_pin);
4090                         return -EINVAL;
4091                 }
4092
4093                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4094                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4095         } else {
4096                 *gpio_num = MISC_REGISTERS_GPIO_3;
4097                 *gpio_port = port;
4098         }
4099         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4100         return 0;
4101 }
4102
4103 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4104                                        struct link_params *params)
4105 {
4106         struct bnx2x *bp = params->bp;
4107         u8 gpio_num, gpio_port;
4108         u32 gpio_val;
4109         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4110                                       params->shmem_base, params->port,
4111                                       &gpio_num, &gpio_port) != 0)
4112                 return 0;
4113         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4114
4115         /* Call the handling function in case module is detected */
4116         if (gpio_val == 0)
4117                 return 1;
4118         else
4119                 return 0;
4120 }
4121
4122 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4123                                        struct link_params *params,
4124                                        struct link_vars *vars)
4125 {
4126         struct bnx2x *bp = params->bp;
4127         u32 serdes_net_if;
4128         u8 fiber_mode;
4129         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4130         serdes_net_if = (REG_RD(bp, params->shmem_base +
4131                          offsetof(struct shmem_region, dev_info.
4132                                   port_hw_config[params->port].default_cfg)) &
4133                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4134         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4135                            "serdes_net_if = 0x%x\n",
4136                        vars->line_speed, serdes_net_if);
4137         bnx2x_set_aer_mmd(params, phy);
4138
4139         vars->phy_flags |= PHY_XGXS_FLAG;
4140         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4141             (phy->req_line_speed &&
4142              ((phy->req_line_speed == SPEED_100) ||
4143               (phy->req_line_speed == SPEED_10)))) {
4144                 vars->phy_flags |= PHY_SGMII_FLAG;
4145                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4146                 bnx2x_warpcore_clear_regs(phy, params, lane);
4147                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4148         } else {
4149                 switch (serdes_net_if) {
4150                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4151                         /* Enable KR Auto Neg */
4152                         if (params->loopback_mode == LOOPBACK_NONE)
4153                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4154                         else {
4155                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4156                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4157                         }
4158                         break;
4159
4160                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4161                         bnx2x_warpcore_clear_regs(phy, params, lane);
4162                         if (vars->line_speed == SPEED_10000) {
4163                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4164                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4165                         } else {
4166                                 if (SINGLE_MEDIA_DIRECT(params)) {
4167                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4168                                         fiber_mode = 1;
4169                                 } else {
4170                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4171                                         fiber_mode = 0;
4172                                 }
4173                                 bnx2x_warpcore_set_sgmii_speed(phy,
4174                                                                 params,
4175                                                                 fiber_mode);
4176                         }
4177
4178                         break;
4179
4180                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4181
4182                         bnx2x_warpcore_clear_regs(phy, params, lane);
4183                         if (vars->line_speed == SPEED_10000) {
4184                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4185                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4186                         } else if (vars->line_speed == SPEED_1000) {
4187                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4188                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4189                         }
4190                         /* Issue Module detection */
4191                         if (bnx2x_is_sfp_module_plugged(phy, params))
4192                                 bnx2x_sfp_module_detection(phy, params);
4193                         break;
4194
4195                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4196                         if (vars->line_speed != SPEED_20000) {
4197                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4198                                 return;
4199                         }
4200                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4201                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4202                         /* Issue Module detection */
4203
4204                         bnx2x_sfp_module_detection(phy, params);
4205                         break;
4206
4207                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4208                         if (vars->line_speed != SPEED_20000) {
4209                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4210                                 return;
4211                         }
4212                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4213                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4214                         break;
4215
4216                 default:
4217                         DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4218                                            "0x%x\n", serdes_net_if);
4219                         return;
4220                 }
4221         }
4222
4223         /* Take lane out of reset after configuration is finished */
4224         bnx2x_warpcore_reset_lane(bp, phy, 0);
4225         DP(NETIF_MSG_LINK, "Exit config init\n");
4226 }
4227
4228 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4229                                          struct bnx2x_phy *phy,
4230                                          u8 tx_en)
4231 {
4232         struct bnx2x *bp = params->bp;
4233         u32 cfg_pin;
4234         u8 port = params->port;
4235
4236         cfg_pin = REG_RD(bp, params->shmem_base +
4237                                 offsetof(struct shmem_region,
4238                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4239                                 PORT_HW_CFG_TX_LASER_MASK;
4240         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4241         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4242         /* For 20G, the expected pin to be used is 3 pins after the current */
4243
4244         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4245         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4246                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4247 }
4248
4249 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4250                                       struct link_params *params)
4251 {
4252         struct bnx2x *bp = params->bp;
4253         u16 val16;
4254         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4255         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4256         bnx2x_set_aer_mmd(params, phy);
4257         /* Global register */
4258         bnx2x_warpcore_reset_lane(bp, phy, 1);
4259
4260         /* Clear loopback settings (if any) */
4261         /* 10G & 20G */
4262         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4263                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4264         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4266                          0xBFFF);
4267
4268         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4269                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4270         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4271                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4272
4273         /* Update those 1-copy registers */
4274         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4275                           MDIO_AER_BLOCK_AER_REG, 0);
4276                 /* Enable 1G MDIO (1-copy) */
4277         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4278                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4279                         &val16);
4280         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4281                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4282                          val16 & ~0x10);
4283
4284         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4285                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4286         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4287                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4288                          val16 & 0xff00);
4289
4290 }
4291
4292 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4293                                         struct link_params *params)
4294 {
4295         struct bnx2x *bp = params->bp;
4296         u16 val16;
4297         u32 lane;
4298         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4299                        params->loopback_mode, phy->req_line_speed);
4300
4301         if (phy->req_line_speed < SPEED_10000) {
4302                 /* 10/100/1000 */
4303
4304                 /* Update those 1-copy registers */
4305                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4306                                   MDIO_AER_BLOCK_AER_REG, 0);
4307                 /* Enable 1G MDIO (1-copy) */
4308                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4309                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4310                                 &val16);
4311                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4312                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4313                                 val16 | 0x10);
4314                 /* Set 1G loopback based on lane (1-copy) */
4315                 lane = bnx2x_get_warpcore_lane(phy, params);
4316                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4317                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4318                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4319                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4320                                 val16 | (1<<lane));
4321
4322                 /* Switch back to 4-copy registers */
4323                 bnx2x_set_aer_mmd(params, phy);
4324                 /* Global loopback, not recommended. */
4325                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4326                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4327                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4328                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4329                                 0x4000);
4330         } else {
4331                 /* 10G & 20G */
4332                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4333                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4334                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4335                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4336                                  0x4000);
4337
4338                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4339                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4340                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4341                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4342         }
4343 }
4344
4345
4346 void bnx2x_link_status_update(struct link_params *params,
4347                               struct link_vars *vars)
4348 {
4349         struct bnx2x *bp = params->bp;
4350         u8 link_10g_plus;
4351         u8 port = params->port;
4352         u32 sync_offset, media_types;
4353         /* Update PHY configuration */
4354         set_phy_vars(params, vars);
4355
4356         vars->link_status = REG_RD(bp, params->shmem_base +
4357                                    offsetof(struct shmem_region,
4358                                             port_mb[port].link_status));
4359
4360         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4361         vars->phy_flags = PHY_XGXS_FLAG;
4362         if (vars->link_up) {
4363                 DP(NETIF_MSG_LINK, "phy link up\n");
4364
4365                 vars->phy_link_up = 1;
4366                 vars->duplex = DUPLEX_FULL;
4367                 switch (vars->link_status &
4368                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4369                         case LINK_10THD:
4370                                 vars->duplex = DUPLEX_HALF;
4371                                 /* fall thru */
4372                         case LINK_10TFD:
4373                                 vars->line_speed = SPEED_10;
4374                                 break;
4375
4376                         case LINK_100TXHD:
4377                                 vars->duplex = DUPLEX_HALF;
4378                                 /* fall thru */
4379                         case LINK_100T4:
4380                         case LINK_100TXFD:
4381                                 vars->line_speed = SPEED_100;
4382                                 break;
4383
4384                         case LINK_1000THD:
4385                                 vars->duplex = DUPLEX_HALF;
4386                                 /* fall thru */
4387                         case LINK_1000TFD:
4388                                 vars->line_speed = SPEED_1000;
4389                                 break;
4390
4391                         case LINK_2500THD:
4392                                 vars->duplex = DUPLEX_HALF;
4393                                 /* fall thru */
4394                         case LINK_2500TFD:
4395                                 vars->line_speed = SPEED_2500;
4396                                 break;
4397
4398                         case LINK_10GTFD:
4399                                 vars->line_speed = SPEED_10000;
4400                                 break;
4401                         case LINK_20GTFD:
4402                                 vars->line_speed = SPEED_20000;
4403                                 break;
4404                         default:
4405                                 break;
4406                 }
4407                 vars->flow_ctrl = 0;
4408                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4409                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4410
4411                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4412                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4413
4414                 if (!vars->flow_ctrl)
4415                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4416
4417                 if (vars->line_speed &&
4418                     ((vars->line_speed == SPEED_10) ||
4419                      (vars->line_speed == SPEED_100))) {
4420                         vars->phy_flags |= PHY_SGMII_FLAG;
4421                 } else {
4422                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4423                 }
4424                 if (vars->line_speed &&
4425                     USES_WARPCORE(bp) &&
4426                     (vars->line_speed == SPEED_1000))
4427                         vars->phy_flags |= PHY_SGMII_FLAG;
4428                 /* anything 10 and over uses the bmac */
4429                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4430
4431                 if (link_10g_plus) {
4432                         if (USES_WARPCORE(bp))
4433                                 vars->mac_type = MAC_TYPE_XMAC;
4434                         else
4435                                 vars->mac_type = MAC_TYPE_BMAC;
4436                 } else {
4437                         if (USES_WARPCORE(bp))
4438                                 vars->mac_type = MAC_TYPE_UMAC;
4439                         else
4440                                 vars->mac_type = MAC_TYPE_EMAC;
4441                 }
4442         } else { /* link down */
4443                 DP(NETIF_MSG_LINK, "phy link down\n");
4444
4445                 vars->phy_link_up = 0;
4446
4447                 vars->line_speed = 0;
4448                 vars->duplex = DUPLEX_FULL;
4449                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4450
4451                 /* indicate no mac active */
4452                 vars->mac_type = MAC_TYPE_NONE;
4453         }
4454
4455         /* Sync media type */
4456         sync_offset = params->shmem_base +
4457                         offsetof(struct shmem_region,
4458                                  dev_info.port_hw_config[port].media_type);
4459         media_types = REG_RD(bp, sync_offset);
4460
4461         params->phy[INT_PHY].media_type =
4462                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4463                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4464         params->phy[EXT_PHY1].media_type =
4465                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4466                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4467         params->phy[EXT_PHY2].media_type =
4468                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4469                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4470         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4471
4472         /* Sync AEU offset */
4473         sync_offset = params->shmem_base +
4474                         offsetof(struct shmem_region,
4475                                  dev_info.port_hw_config[port].aeu_int_mask);
4476
4477         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4478
4479         /* Sync PFC status */
4480         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4481                 params->feature_config_flags |=
4482                                         FEATURE_CONFIG_PFC_ENABLED;
4483         else
4484                 params->feature_config_flags &=
4485                                         ~FEATURE_CONFIG_PFC_ENABLED;
4486
4487         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4488                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4489         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4490                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4491 }
4492
4493
4494 static void bnx2x_set_master_ln(struct link_params *params,
4495                                 struct bnx2x_phy *phy)
4496 {
4497         struct bnx2x *bp = params->bp;
4498         u16 new_master_ln, ser_lane;
4499         ser_lane = ((params->lane_config &
4500                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4501                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4502
4503         /* set the master_ln for AN */
4504         CL22_RD_OVER_CL45(bp, phy,
4505                           MDIO_REG_BANK_XGXS_BLOCK2,
4506                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4507                           &new_master_ln);
4508
4509         CL22_WR_OVER_CL45(bp, phy,
4510                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4511                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4512                           (new_master_ln | ser_lane));
4513 }
4514
4515 static int bnx2x_reset_unicore(struct link_params *params,
4516                                struct bnx2x_phy *phy,
4517                                u8 set_serdes)
4518 {
4519         struct bnx2x *bp = params->bp;
4520         u16 mii_control;
4521         u16 i;
4522         CL22_RD_OVER_CL45(bp, phy,
4523                           MDIO_REG_BANK_COMBO_IEEE0,
4524                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4525
4526         /* reset the unicore */
4527         CL22_WR_OVER_CL45(bp, phy,
4528                           MDIO_REG_BANK_COMBO_IEEE0,
4529                           MDIO_COMBO_IEEE0_MII_CONTROL,
4530                           (mii_control |
4531                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4532         if (set_serdes)
4533                 bnx2x_set_serdes_access(bp, params->port);
4534
4535         /* wait for the reset to self clear */
4536         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4537                 udelay(5);
4538
4539                 /* the reset erased the previous bank value */
4540                 CL22_RD_OVER_CL45(bp, phy,
4541                                   MDIO_REG_BANK_COMBO_IEEE0,
4542                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4543                                   &mii_control);
4544
4545                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4546                         udelay(5);
4547                         return 0;
4548                 }
4549         }
4550
4551         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4552                               " Port %d\n",
4553                          params->port);
4554         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4555         return -EINVAL;
4556
4557 }
4558
4559 static void bnx2x_set_swap_lanes(struct link_params *params,
4560                                  struct bnx2x_phy *phy)
4561 {
4562         struct bnx2x *bp = params->bp;
4563         /*
4564          *  Each two bits represents a lane number:
4565          *  No swap is 0123 => 0x1b no need to enable the swap
4566          */
4567         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4568
4569         ser_lane = ((params->lane_config &
4570                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4571                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4572         rx_lane_swap = ((params->lane_config &
4573                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4574                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4575         tx_lane_swap = ((params->lane_config &
4576                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4577                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4578
4579         if (rx_lane_swap != 0x1b) {
4580                 CL22_WR_OVER_CL45(bp, phy,
4581                                   MDIO_REG_BANK_XGXS_BLOCK2,
4582                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4583                                   (rx_lane_swap |
4584                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4585                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4586         } else {
4587                 CL22_WR_OVER_CL45(bp, phy,
4588                                   MDIO_REG_BANK_XGXS_BLOCK2,
4589                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4590         }
4591
4592         if (tx_lane_swap != 0x1b) {
4593                 CL22_WR_OVER_CL45(bp, phy,
4594                                   MDIO_REG_BANK_XGXS_BLOCK2,
4595                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4596                                   (tx_lane_swap |
4597                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4598         } else {
4599                 CL22_WR_OVER_CL45(bp, phy,
4600                                   MDIO_REG_BANK_XGXS_BLOCK2,
4601                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4602         }
4603 }
4604
4605 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4606                                          struct link_params *params)
4607 {
4608         struct bnx2x *bp = params->bp;
4609         u16 control2;
4610         CL22_RD_OVER_CL45(bp, phy,
4611                           MDIO_REG_BANK_SERDES_DIGITAL,
4612                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4613                           &control2);
4614         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4615                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4616         else
4617                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4618         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4619                 phy->speed_cap_mask, control2);
4620         CL22_WR_OVER_CL45(bp, phy,
4621                           MDIO_REG_BANK_SERDES_DIGITAL,
4622                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4623                           control2);
4624
4625         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4626              (phy->speed_cap_mask &
4627                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4628                 DP(NETIF_MSG_LINK, "XGXS\n");
4629
4630                 CL22_WR_OVER_CL45(bp, phy,
4631                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4632                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4633                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4634
4635                 CL22_RD_OVER_CL45(bp, phy,
4636                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4637                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4638                                   &control2);
4639
4640
4641                 control2 |=
4642                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4643
4644                 CL22_WR_OVER_CL45(bp, phy,
4645                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4646                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4647                                   control2);
4648
4649                 /* Disable parallel detection of HiG */
4650                 CL22_WR_OVER_CL45(bp, phy,
4651                                   MDIO_REG_BANK_XGXS_BLOCK2,
4652                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4653                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4654                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4655         }
4656 }
4657
4658 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4659                               struct link_params *params,
4660                               struct link_vars *vars,
4661                               u8 enable_cl73)
4662 {
4663         struct bnx2x *bp = params->bp;
4664         u16 reg_val;
4665
4666         /* CL37 Autoneg */
4667         CL22_RD_OVER_CL45(bp, phy,
4668                           MDIO_REG_BANK_COMBO_IEEE0,
4669                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4670
4671         /* CL37 Autoneg Enabled */
4672         if (vars->line_speed == SPEED_AUTO_NEG)
4673                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4674         else /* CL37 Autoneg Disabled */
4675                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4676                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4677
4678         CL22_WR_OVER_CL45(bp, phy,
4679                           MDIO_REG_BANK_COMBO_IEEE0,
4680                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4681
4682         /* Enable/Disable Autodetection */
4683
4684         CL22_RD_OVER_CL45(bp, phy,
4685                           MDIO_REG_BANK_SERDES_DIGITAL,
4686                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4687         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4688                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4689         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4690         if (vars->line_speed == SPEED_AUTO_NEG)
4691                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4692         else
4693                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4694
4695         CL22_WR_OVER_CL45(bp, phy,
4696                           MDIO_REG_BANK_SERDES_DIGITAL,
4697                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4698
4699         /* Enable TetonII and BAM autoneg */
4700         CL22_RD_OVER_CL45(bp, phy,
4701                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4702                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4703                           &reg_val);
4704         if (vars->line_speed == SPEED_AUTO_NEG) {
4705                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4706                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4707                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4708         } else {
4709                 /* TetonII and BAM Autoneg Disabled */
4710                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4711                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4712         }
4713         CL22_WR_OVER_CL45(bp, phy,
4714                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4715                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4716                           reg_val);
4717
4718         if (enable_cl73) {
4719                 /* Enable Cl73 FSM status bits */
4720                 CL22_WR_OVER_CL45(bp, phy,
4721                                   MDIO_REG_BANK_CL73_USERB0,
4722                                   MDIO_CL73_USERB0_CL73_UCTRL,
4723                                   0xe);
4724
4725                 /* Enable BAM Station Manager*/
4726                 CL22_WR_OVER_CL45(bp, phy,
4727                         MDIO_REG_BANK_CL73_USERB0,
4728                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4729                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4730                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4731                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4732
4733                 /* Advertise CL73 link speeds */
4734                 CL22_RD_OVER_CL45(bp, phy,
4735                                   MDIO_REG_BANK_CL73_IEEEB1,
4736                                   MDIO_CL73_IEEEB1_AN_ADV2,
4737                                   &reg_val);
4738                 if (phy->speed_cap_mask &
4739                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4740                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4741                 if (phy->speed_cap_mask &
4742                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4743                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4744
4745                 CL22_WR_OVER_CL45(bp, phy,
4746                                   MDIO_REG_BANK_CL73_IEEEB1,
4747                                   MDIO_CL73_IEEEB1_AN_ADV2,
4748                                   reg_val);
4749
4750                 /* CL73 Autoneg Enabled */
4751                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4752
4753         } else /* CL73 Autoneg Disabled */
4754                 reg_val = 0;
4755
4756         CL22_WR_OVER_CL45(bp, phy,
4757                           MDIO_REG_BANK_CL73_IEEEB0,
4758                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4759 }
4760
4761 /* program SerDes, forced speed */
4762 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4763                                  struct link_params *params,
4764                                  struct link_vars *vars)
4765 {
4766         struct bnx2x *bp = params->bp;
4767         u16 reg_val;
4768
4769         /* program duplex, disable autoneg and sgmii*/
4770         CL22_RD_OVER_CL45(bp, phy,
4771                           MDIO_REG_BANK_COMBO_IEEE0,
4772                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4773         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4774                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4775                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4776         if (phy->req_duplex == DUPLEX_FULL)
4777                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4778         CL22_WR_OVER_CL45(bp, phy,
4779                           MDIO_REG_BANK_COMBO_IEEE0,
4780                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4781
4782         /*
4783          * program speed
4784          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4785          */
4786         CL22_RD_OVER_CL45(bp, phy,
4787                           MDIO_REG_BANK_SERDES_DIGITAL,
4788                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4789         /* clearing the speed value before setting the right speed */
4790         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4791
4792         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4793                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4794
4795         if (!((vars->line_speed == SPEED_1000) ||
4796               (vars->line_speed == SPEED_100) ||
4797               (vars->line_speed == SPEED_10))) {
4798
4799                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4800                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4801                 if (vars->line_speed == SPEED_10000)
4802                         reg_val |=
4803                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4804         }
4805
4806         CL22_WR_OVER_CL45(bp, phy,
4807                           MDIO_REG_BANK_SERDES_DIGITAL,
4808                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4809
4810 }
4811
4812 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4813                                               struct link_params *params)
4814 {
4815         struct bnx2x *bp = params->bp;
4816         u16 val = 0;
4817
4818         /* configure the 48 bits for BAM AN */
4819
4820         /* set extended capabilities */
4821         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4822                 val |= MDIO_OVER_1G_UP1_2_5G;
4823         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4824                 val |= MDIO_OVER_1G_UP1_10G;
4825         CL22_WR_OVER_CL45(bp, phy,
4826                           MDIO_REG_BANK_OVER_1G,
4827                           MDIO_OVER_1G_UP1, val);
4828
4829         CL22_WR_OVER_CL45(bp, phy,
4830                           MDIO_REG_BANK_OVER_1G,
4831                           MDIO_OVER_1G_UP3, 0x400);
4832 }
4833
4834 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4835                                               struct link_params *params,
4836                                               u16 ieee_fc)
4837 {
4838         struct bnx2x *bp = params->bp;
4839         u16 val;
4840         /* for AN, we are always publishing full duplex */
4841
4842         CL22_WR_OVER_CL45(bp, phy,
4843                           MDIO_REG_BANK_COMBO_IEEE0,
4844                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4845         CL22_RD_OVER_CL45(bp, phy,
4846                           MDIO_REG_BANK_CL73_IEEEB1,
4847                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4848         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4849         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4850         CL22_WR_OVER_CL45(bp, phy,
4851                           MDIO_REG_BANK_CL73_IEEEB1,
4852                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4853 }
4854
4855 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4856                                   struct link_params *params,
4857                                   u8 enable_cl73)
4858 {
4859         struct bnx2x *bp = params->bp;
4860         u16 mii_control;
4861
4862         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4863         /* Enable and restart BAM/CL37 aneg */
4864
4865         if (enable_cl73) {
4866                 CL22_RD_OVER_CL45(bp, phy,
4867                                   MDIO_REG_BANK_CL73_IEEEB0,
4868                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4869                                   &mii_control);
4870
4871                 CL22_WR_OVER_CL45(bp, phy,
4872                                   MDIO_REG_BANK_CL73_IEEEB0,
4873                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4874                                   (mii_control |
4875                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4876                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4877         } else {
4878
4879                 CL22_RD_OVER_CL45(bp, phy,
4880                                   MDIO_REG_BANK_COMBO_IEEE0,
4881                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4882                                   &mii_control);
4883                 DP(NETIF_MSG_LINK,
4884                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4885                          mii_control);
4886                 CL22_WR_OVER_CL45(bp, phy,
4887                                   MDIO_REG_BANK_COMBO_IEEE0,
4888                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4889                                   (mii_control |
4890                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4891                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4892         }
4893 }
4894
4895 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4896                                            struct link_params *params,
4897                                            struct link_vars *vars)
4898 {
4899         struct bnx2x *bp = params->bp;
4900         u16 control1;
4901
4902         /* in SGMII mode, the unicore is always slave */
4903
4904         CL22_RD_OVER_CL45(bp, phy,
4905                           MDIO_REG_BANK_SERDES_DIGITAL,
4906                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4907                           &control1);
4908         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4909         /* set sgmii mode (and not fiber) */
4910         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4911                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4912                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4913         CL22_WR_OVER_CL45(bp, phy,
4914                           MDIO_REG_BANK_SERDES_DIGITAL,
4915                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4916                           control1);
4917
4918         /* if forced speed */
4919         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4920                 /* set speed, disable autoneg */
4921                 u16 mii_control;
4922
4923                 CL22_RD_OVER_CL45(bp, phy,
4924                                   MDIO_REG_BANK_COMBO_IEEE0,
4925                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4926                                   &mii_control);
4927                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4928                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4929                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4930
4931                 switch (vars->line_speed) {
4932                 case SPEED_100:
4933                         mii_control |=
4934                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4935                         break;
4936                 case SPEED_1000:
4937                         mii_control |=
4938                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4939                         break;
4940                 case SPEED_10:
4941                         /* there is nothing to set for 10M */
4942                         break;
4943                 default:
4944                         /* invalid speed for SGMII */
4945                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4946                                   vars->line_speed);
4947                         break;
4948                 }
4949
4950                 /* setting the full duplex */
4951                 if (phy->req_duplex == DUPLEX_FULL)
4952                         mii_control |=
4953                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4954                 CL22_WR_OVER_CL45(bp, phy,
4955                                   MDIO_REG_BANK_COMBO_IEEE0,
4956                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4957                                   mii_control);
4958
4959         } else { /* AN mode */
4960                 /* enable and restart AN */
4961                 bnx2x_restart_autoneg(phy, params, 0);
4962         }
4963 }
4964
4965
4966 /*
4967  * link management
4968  */
4969
4970 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4971                                              struct link_params *params)
4972 {
4973         struct bnx2x *bp = params->bp;
4974         u16 pd_10g, status2_1000x;
4975         if (phy->req_line_speed != SPEED_AUTO_NEG)
4976                 return 0;
4977         CL22_RD_OVER_CL45(bp, phy,
4978                           MDIO_REG_BANK_SERDES_DIGITAL,
4979                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4980                           &status2_1000x);
4981         CL22_RD_OVER_CL45(bp, phy,
4982                           MDIO_REG_BANK_SERDES_DIGITAL,
4983                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4984                           &status2_1000x);
4985         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4986                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4987                          params->port);
4988                 return 1;
4989         }
4990
4991         CL22_RD_OVER_CL45(bp, phy,
4992                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
4993                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4994                           &pd_10g);
4995
4996         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4997                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
4998                          params->port);
4999                 return 1;
5000         }
5001         return 0;
5002 }
5003
5004 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5005                                     struct link_params *params,
5006                                     struct link_vars *vars,
5007                                     u32 gp_status)
5008 {
5009         struct bnx2x *bp = params->bp;
5010         u16 ld_pause;   /* local driver */
5011         u16 lp_pause;   /* link partner */
5012         u16 pause_result;
5013
5014         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5015
5016         /* resolve from gp_status in case of AN complete and not sgmii */
5017         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5018                 vars->flow_ctrl = phy->req_flow_ctrl;
5019         else if (phy->req_line_speed != SPEED_AUTO_NEG)
5020                 vars->flow_ctrl = params->req_fc_auto_adv;
5021         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5022                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5023                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5024                         vars->flow_ctrl = params->req_fc_auto_adv;
5025                         return;
5026                 }
5027                 if ((gp_status &
5028                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5029                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5030                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5031                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5032
5033                         CL22_RD_OVER_CL45(bp, phy,
5034                                           MDIO_REG_BANK_CL73_IEEEB1,
5035                                           MDIO_CL73_IEEEB1_AN_ADV1,
5036                                           &ld_pause);
5037                         CL22_RD_OVER_CL45(bp, phy,
5038                                           MDIO_REG_BANK_CL73_IEEEB1,
5039                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5040                                           &lp_pause);
5041                         pause_result = (ld_pause &
5042                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5043                                         >> 8;
5044                         pause_result |= (lp_pause &
5045                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5046                                         >> 10;
5047                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5048                                  pause_result);
5049                 } else {
5050                         CL22_RD_OVER_CL45(bp, phy,
5051                                           MDIO_REG_BANK_COMBO_IEEE0,
5052                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5053                                           &ld_pause);
5054                         CL22_RD_OVER_CL45(bp, phy,
5055                                 MDIO_REG_BANK_COMBO_IEEE0,
5056                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5057                                 &lp_pause);
5058                         pause_result = (ld_pause &
5059                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5060                         pause_result |= (lp_pause &
5061                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5062                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5063                                  pause_result);
5064                 }
5065                 bnx2x_pause_resolve(vars, pause_result);
5066         }
5067         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5068 }
5069
5070 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5071                                          struct link_params *params)
5072 {
5073         struct bnx2x *bp = params->bp;
5074         u16 rx_status, ustat_val, cl37_fsm_received;
5075         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5076         /* Step 1: Make sure signal is detected */
5077         CL22_RD_OVER_CL45(bp, phy,
5078                           MDIO_REG_BANK_RX0,
5079                           MDIO_RX0_RX_STATUS,
5080                           &rx_status);
5081         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5082             (MDIO_RX0_RX_STATUS_SIGDET)) {
5083                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5084                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5085                 CL22_WR_OVER_CL45(bp, phy,
5086                                   MDIO_REG_BANK_CL73_IEEEB0,
5087                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5088                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5089                 return;
5090         }
5091         /* Step 2: Check CL73 state machine */
5092         CL22_RD_OVER_CL45(bp, phy,
5093                           MDIO_REG_BANK_CL73_USERB0,
5094                           MDIO_CL73_USERB0_CL73_USTAT1,
5095                           &ustat_val);
5096         if ((ustat_val &
5097              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5098               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5099             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5100               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5101                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5102                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5103                 return;
5104         }
5105         /*
5106          * Step 3: Check CL37 Message Pages received to indicate LP
5107          * supports only CL37
5108          */
5109         CL22_RD_OVER_CL45(bp, phy,
5110                           MDIO_REG_BANK_REMOTE_PHY,
5111                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5112                           &cl37_fsm_received);
5113         if ((cl37_fsm_received &
5114              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5115              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5116             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5117               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5118                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5119                              "misc_rx_status(0x8330) = 0x%x\n",
5120                          cl37_fsm_received);
5121                 return;
5122         }
5123         /*
5124          * The combined cl37/cl73 fsm state information indicating that
5125          * we are connected to a device which does not support cl73, but
5126          * does support cl37 BAM. In this case we disable cl73 and
5127          * restart cl37 auto-neg
5128          */
5129
5130         /* Disable CL73 */
5131         CL22_WR_OVER_CL45(bp, phy,
5132                           MDIO_REG_BANK_CL73_IEEEB0,
5133                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5134                           0);
5135         /* Restart CL37 autoneg */
5136         bnx2x_restart_autoneg(phy, params, 0);
5137         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5138 }
5139
5140 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5141                                   struct link_params *params,
5142                                   struct link_vars *vars,
5143                                   u32 gp_status)
5144 {
5145         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5146                 vars->link_status |=
5147                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5148
5149         if (bnx2x_direct_parallel_detect_used(phy, params))
5150                 vars->link_status |=
5151                         LINK_STATUS_PARALLEL_DETECTION_USED;
5152 }
5153 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5154                                      struct link_params *params,
5155                                       struct link_vars *vars,
5156                                       u16 is_link_up,
5157                                       u16 speed_mask,
5158                                       u16 is_duplex)
5159 {
5160         struct bnx2x *bp = params->bp;
5161         if (phy->req_line_speed == SPEED_AUTO_NEG)
5162                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5163         if (is_link_up) {
5164                 DP(NETIF_MSG_LINK, "phy link up\n");
5165
5166                 vars->phy_link_up = 1;
5167                 vars->link_status |= LINK_STATUS_LINK_UP;
5168
5169                 switch (speed_mask) {
5170                 case GP_STATUS_10M:
5171                         vars->line_speed = SPEED_10;
5172                         if (vars->duplex == DUPLEX_FULL)
5173                                 vars->link_status |= LINK_10TFD;
5174                         else
5175                                 vars->link_status |= LINK_10THD;
5176                         break;
5177
5178                 case GP_STATUS_100M:
5179                         vars->line_speed = SPEED_100;
5180                         if (vars->duplex == DUPLEX_FULL)
5181                                 vars->link_status |= LINK_100TXFD;
5182                         else
5183                                 vars->link_status |= LINK_100TXHD;
5184                         break;
5185
5186                 case GP_STATUS_1G:
5187                 case GP_STATUS_1G_KX:
5188                         vars->line_speed = SPEED_1000;
5189                         if (vars->duplex == DUPLEX_FULL)
5190                                 vars->link_status |= LINK_1000TFD;
5191                         else
5192                                 vars->link_status |= LINK_1000THD;
5193                         break;
5194
5195                 case GP_STATUS_2_5G:
5196                         vars->line_speed = SPEED_2500;
5197                         if (vars->duplex == DUPLEX_FULL)
5198                                 vars->link_status |= LINK_2500TFD;
5199                         else
5200                                 vars->link_status |= LINK_2500THD;
5201                         break;
5202
5203                 case GP_STATUS_5G:
5204                 case GP_STATUS_6G:
5205                         DP(NETIF_MSG_LINK,
5206                                  "link speed unsupported  gp_status 0x%x\n",
5207                                   speed_mask);
5208                         return -EINVAL;
5209
5210                 case GP_STATUS_10G_KX4:
5211                 case GP_STATUS_10G_HIG:
5212                 case GP_STATUS_10G_CX4:
5213                 case GP_STATUS_10G_KR:
5214                 case GP_STATUS_10G_SFI:
5215                 case GP_STATUS_10G_XFI:
5216                         vars->line_speed = SPEED_10000;
5217                         vars->link_status |= LINK_10GTFD;
5218                         break;
5219                 case GP_STATUS_20G_DXGXS:
5220                         vars->line_speed = SPEED_20000;
5221                         vars->link_status |= LINK_20GTFD;
5222                         break;
5223                 default:
5224                         DP(NETIF_MSG_LINK,
5225                                   "link speed unsupported gp_status 0x%x\n",
5226                                   speed_mask);
5227                         return -EINVAL;
5228                 }
5229         } else { /* link_down */
5230                 DP(NETIF_MSG_LINK, "phy link down\n");
5231
5232                 vars->phy_link_up = 0;
5233
5234                 vars->duplex = DUPLEX_FULL;
5235                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5236                 vars->mac_type = MAC_TYPE_NONE;
5237         }
5238         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5239                     vars->phy_link_up, vars->line_speed);
5240         return 0;
5241 }
5242
5243 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5244                                       struct link_params *params,
5245                                       struct link_vars *vars)
5246 {
5247
5248         struct bnx2x *bp = params->bp;
5249
5250         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5251         int rc = 0;
5252
5253         /* Read gp_status */
5254         CL22_RD_OVER_CL45(bp, phy,
5255                           MDIO_REG_BANK_GP_STATUS,
5256                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5257                           &gp_status);
5258         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5259                 duplex = DUPLEX_FULL;
5260         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5261                 link_up = 1;
5262         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5263         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5264                        gp_status, link_up, speed_mask);
5265         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5266                                          duplex);
5267         if (rc == -EINVAL)
5268                 return rc;
5269
5270         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5271                 if (SINGLE_MEDIA_DIRECT(params)) {
5272                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5273                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5274                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5275                                                       gp_status);
5276                 }
5277         } else { /* link_down */
5278                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5279                     SINGLE_MEDIA_DIRECT(params)) {
5280                         /* Check signal is detected */
5281                         bnx2x_check_fallback_to_cl37(phy, params);
5282                 }
5283         }
5284
5285         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5286                    vars->duplex, vars->flow_ctrl, vars->link_status);
5287         return rc;
5288 }
5289
5290 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5291                                      struct link_params *params,
5292                                      struct link_vars *vars)
5293 {
5294
5295         struct bnx2x *bp = params->bp;
5296
5297         u8 lane;
5298         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5299         int rc = 0;
5300         lane = bnx2x_get_warpcore_lane(phy, params);
5301         /* Read gp_status */
5302         if (phy->req_line_speed > SPEED_10000) {
5303                 u16 temp_link_up;
5304                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5305                                 1, &temp_link_up);
5306                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5307                                 1, &link_up);
5308                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5309                                temp_link_up, link_up);
5310                 link_up &= (1<<2);
5311                 if (link_up)
5312                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5313         } else {
5314                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5315                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5316                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5317                 /* Check for either KR or generic link up. */
5318                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5319                         ((gp_status1 >> 12) & 0xf);
5320                 link_up = gp_status1 & (1 << lane);
5321                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5322                         u16 pd, gp_status4;
5323                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5324                                 /* Check Autoneg complete */
5325                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5326                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5327                                                 &gp_status4);
5328                                 if (gp_status4 & ((1<<12)<<lane))
5329                                         vars->link_status |=
5330                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5331
5332                                 /* Check parallel detect used */
5333                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5334                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5335                                                 &pd);
5336                                 if (pd & (1<<15))
5337                                         vars->link_status |=
5338                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5339                         }
5340                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5341                 }
5342         }
5343
5344         if (lane < 2) {
5345                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5346                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5347         } else {
5348                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5349                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5350         }
5351         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5352
5353         if ((lane & 1) == 0)
5354                 gp_speed <<= 8;
5355         gp_speed &= 0x3f00;
5356
5357
5358         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5359                                          duplex);
5360
5361         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5362                    vars->duplex, vars->flow_ctrl, vars->link_status);
5363         return rc;
5364 }
5365 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5366 {
5367         struct bnx2x *bp = params->bp;
5368         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5369         u16 lp_up2;
5370         u16 tx_driver;
5371         u16 bank;
5372
5373         /* read precomp */
5374         CL22_RD_OVER_CL45(bp, phy,
5375                           MDIO_REG_BANK_OVER_1G,
5376                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5377
5378         /* bits [10:7] at lp_up2, positioned at [15:12] */
5379         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5380                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5381                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5382
5383         if (lp_up2 == 0)
5384                 return;
5385
5386         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5387               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5388                 CL22_RD_OVER_CL45(bp, phy,
5389                                   bank,
5390                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5391
5392                 /* replace tx_driver bits [15:12] */
5393                 if (lp_up2 !=
5394                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5395                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5396                         tx_driver |= lp_up2;
5397                         CL22_WR_OVER_CL45(bp, phy,
5398                                           bank,
5399                                           MDIO_TX0_TX_DRIVER, tx_driver);
5400                 }
5401         }
5402 }
5403
5404 static int bnx2x_emac_program(struct link_params *params,
5405                               struct link_vars *vars)
5406 {
5407         struct bnx2x *bp = params->bp;
5408         u8 port = params->port;
5409         u16 mode = 0;
5410
5411         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5412         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5413                        EMAC_REG_EMAC_MODE,
5414                        (EMAC_MODE_25G_MODE |
5415                         EMAC_MODE_PORT_MII_10M |
5416                         EMAC_MODE_HALF_DUPLEX));
5417         switch (vars->line_speed) {
5418         case SPEED_10:
5419                 mode |= EMAC_MODE_PORT_MII_10M;
5420                 break;
5421
5422         case SPEED_100:
5423                 mode |= EMAC_MODE_PORT_MII;
5424                 break;
5425
5426         case SPEED_1000:
5427                 mode |= EMAC_MODE_PORT_GMII;
5428                 break;
5429
5430         case SPEED_2500:
5431                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5432                 break;
5433
5434         default:
5435                 /* 10G not valid for EMAC */
5436                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5437                            vars->line_speed);
5438                 return -EINVAL;
5439         }
5440
5441         if (vars->duplex == DUPLEX_HALF)
5442                 mode |= EMAC_MODE_HALF_DUPLEX;
5443         bnx2x_bits_en(bp,
5444                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5445                       mode);
5446
5447         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5448         return 0;
5449 }
5450
5451 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5452                                   struct link_params *params)
5453 {
5454
5455         u16 bank, i = 0;
5456         struct bnx2x *bp = params->bp;
5457
5458         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5459               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5460                         CL22_WR_OVER_CL45(bp, phy,
5461                                           bank,
5462                                           MDIO_RX0_RX_EQ_BOOST,
5463                                           phy->rx_preemphasis[i]);
5464         }
5465
5466         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5467                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5468                         CL22_WR_OVER_CL45(bp, phy,
5469                                           bank,
5470                                           MDIO_TX0_TX_DRIVER,
5471                                           phy->tx_preemphasis[i]);
5472         }
5473 }
5474
5475 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5476                                    struct link_params *params,
5477                                    struct link_vars *vars)
5478 {
5479         struct bnx2x *bp = params->bp;
5480         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5481                           (params->loopback_mode == LOOPBACK_XGXS));
5482         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5483                 if (SINGLE_MEDIA_DIRECT(params) &&
5484                     (params->feature_config_flags &
5485                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5486                         bnx2x_set_preemphasis(phy, params);
5487
5488                 /* forced speed requested? */
5489                 if (vars->line_speed != SPEED_AUTO_NEG ||
5490                     (SINGLE_MEDIA_DIRECT(params) &&
5491                      params->loopback_mode == LOOPBACK_EXT)) {
5492                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5493
5494                         /* disable autoneg */
5495                         bnx2x_set_autoneg(phy, params, vars, 0);
5496
5497                         /* program speed and duplex */
5498                         bnx2x_program_serdes(phy, params, vars);
5499
5500                 } else { /* AN_mode */
5501                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5502
5503                         /* AN enabled */
5504                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5505
5506                         /* program duplex & pause advertisement (for aneg) */
5507                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5508                                                           vars->ieee_fc);
5509
5510                         /* enable autoneg */
5511                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5512
5513                         /* enable and restart AN */
5514                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5515                 }
5516
5517         } else { /* SGMII mode */
5518                 DP(NETIF_MSG_LINK, "SGMII\n");
5519
5520                 bnx2x_initialize_sgmii_process(phy, params, vars);
5521         }
5522 }
5523
5524 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5525                           struct link_params *params,
5526                           struct link_vars *vars)
5527 {
5528         int rc;
5529         vars->phy_flags |= PHY_XGXS_FLAG;
5530         if ((phy->req_line_speed &&
5531              ((phy->req_line_speed == SPEED_100) ||
5532               (phy->req_line_speed == SPEED_10))) ||
5533             (!phy->req_line_speed &&
5534              (phy->speed_cap_mask >=
5535               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5536              (phy->speed_cap_mask <
5537               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5538             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5539                 vars->phy_flags |= PHY_SGMII_FLAG;
5540         else
5541                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5542
5543         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5544         bnx2x_set_aer_mmd(params, phy);
5545         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5546                 bnx2x_set_master_ln(params, phy);
5547
5548         rc = bnx2x_reset_unicore(params, phy, 0);
5549         /* reset the SerDes and wait for reset bit return low */
5550         if (rc != 0)
5551                 return rc;
5552
5553         bnx2x_set_aer_mmd(params, phy);
5554         /* setting the masterLn_def again after the reset */
5555         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5556                 bnx2x_set_master_ln(params, phy);
5557                 bnx2x_set_swap_lanes(params, phy);
5558         }
5559
5560         return rc;
5561 }
5562
5563 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5564                                      struct bnx2x_phy *phy,
5565                                      struct link_params *params)
5566 {
5567         u16 cnt, ctrl;
5568         /* Wait for soft reset to get cleared up to 1 sec */
5569         for (cnt = 0; cnt < 1000; cnt++) {
5570                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5571                         bnx2x_cl22_read(bp, phy,
5572                                 MDIO_PMA_REG_CTRL, &ctrl);
5573                 else
5574                         bnx2x_cl45_read(bp, phy,
5575                                 MDIO_PMA_DEVAD,
5576                                 MDIO_PMA_REG_CTRL, &ctrl);
5577                 if (!(ctrl & (1<<15)))
5578                         break;
5579                 msleep(1);
5580         }
5581
5582         if (cnt == 1000)
5583                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5584                                       " Port %d\n",
5585                          params->port);
5586         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5587         return cnt;
5588 }
5589
5590 static void bnx2x_link_int_enable(struct link_params *params)
5591 {
5592         u8 port = params->port;
5593         u32 mask;
5594         struct bnx2x *bp = params->bp;
5595
5596         /* Setting the status to report on link up for either XGXS or SerDes */
5597         if (CHIP_IS_E3(bp)) {
5598                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5599                 if (!(SINGLE_MEDIA_DIRECT(params)))
5600                         mask |= NIG_MASK_MI_INT;
5601         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5602                 mask = (NIG_MASK_XGXS0_LINK10G |
5603                         NIG_MASK_XGXS0_LINK_STATUS);
5604                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5605                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5606                         params->phy[INT_PHY].type !=
5607                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5608                         mask |= NIG_MASK_MI_INT;
5609                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5610                 }
5611
5612         } else { /* SerDes */
5613                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5614                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5615                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5616                         params->phy[INT_PHY].type !=
5617                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5618                         mask |= NIG_MASK_MI_INT;
5619                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5620                 }
5621         }
5622         bnx2x_bits_en(bp,
5623                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5624                       mask);
5625
5626         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5627                  (params->switch_cfg == SWITCH_CFG_10G),
5628                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5629         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5630                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5631                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5632                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5633         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5634            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5635            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5636 }
5637
5638 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5639                                      u8 exp_mi_int)
5640 {
5641         u32 latch_status = 0;
5642
5643         /*
5644          * Disable the MI INT ( external phy int ) by writing 1 to the
5645          * status register. Link down indication is high-active-signal,
5646          * so in this case we need to write the status to clear the XOR
5647          */
5648         /* Read Latched signals */
5649         latch_status = REG_RD(bp,
5650                                     NIG_REG_LATCH_STATUS_0 + port*8);
5651         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5652         /* Handle only those with latched-signal=up.*/
5653         if (exp_mi_int)
5654                 bnx2x_bits_en(bp,
5655                               NIG_REG_STATUS_INTERRUPT_PORT0
5656                               + port*4,
5657                               NIG_STATUS_EMAC0_MI_INT);
5658         else
5659                 bnx2x_bits_dis(bp,
5660                                NIG_REG_STATUS_INTERRUPT_PORT0
5661                                + port*4,
5662                                NIG_STATUS_EMAC0_MI_INT);
5663
5664         if (latch_status & 1) {
5665
5666                 /* For all latched-signal=up : Re-Arm Latch signals */
5667                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5668                        (latch_status & 0xfffe) | (latch_status & 1));
5669         }
5670         /* For all latched-signal=up,Write original_signal to status */
5671 }
5672
5673 static void bnx2x_link_int_ack(struct link_params *params,
5674                                struct link_vars *vars, u8 is_10g_plus)
5675 {
5676         struct bnx2x *bp = params->bp;
5677         u8 port = params->port;
5678         u32 mask;
5679         /*
5680          * First reset all status we assume only one line will be
5681          * change at a time
5682          */
5683         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5684                        (NIG_STATUS_XGXS0_LINK10G |
5685                         NIG_STATUS_XGXS0_LINK_STATUS |
5686                         NIG_STATUS_SERDES0_LINK_STATUS));
5687         if (vars->phy_link_up) {
5688                 if (USES_WARPCORE(bp))
5689                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5690                 else {
5691                         if (is_10g_plus)
5692                                 mask = NIG_STATUS_XGXS0_LINK10G;
5693                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5694                                 /*
5695                                  * Disable the link interrupt by writing 1 to
5696                                  * the relevant lane in the status register
5697                                  */
5698                                 u32 ser_lane =
5699                                         ((params->lane_config &
5700                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5701                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5702                                 mask = ((1 << ser_lane) <<
5703                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5704                         } else
5705                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5706                 }
5707                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5708                                mask);
5709                 bnx2x_bits_en(bp,
5710                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5711                               mask);
5712         }
5713 }
5714
5715 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5716 {
5717         u8 *str_ptr = str;
5718         u32 mask = 0xf0000000;
5719         u8 shift = 8*4;
5720         u8 digit;
5721         u8 remove_leading_zeros = 1;
5722         if (*len < 10) {
5723                 /* Need more than 10chars for this format */
5724                 *str_ptr = '\0';
5725                 (*len)--;
5726                 return -EINVAL;
5727         }
5728         while (shift > 0) {
5729
5730                 shift -= 4;
5731                 digit = ((num & mask) >> shift);
5732                 if (digit == 0 && remove_leading_zeros) {
5733                         mask = mask >> 4;
5734                         continue;
5735                 } else if (digit < 0xa)
5736                         *str_ptr = digit + '0';
5737                 else
5738                         *str_ptr = digit - 0xa + 'a';
5739                 remove_leading_zeros = 0;
5740                 str_ptr++;
5741                 (*len)--;
5742                 mask = mask >> 4;
5743                 if (shift == 4*4) {
5744                         *str_ptr = '.';
5745                         str_ptr++;
5746                         (*len)--;
5747                         remove_leading_zeros = 1;
5748                 }
5749         }
5750         return 0;
5751 }
5752
5753
5754 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5755 {
5756         str[0] = '\0';
5757         (*len)--;
5758         return 0;
5759 }
5760
5761 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5762                                  u8 *version, u16 len)
5763 {
5764         struct bnx2x *bp;
5765         u32 spirom_ver = 0;
5766         int status = 0;
5767         u8 *ver_p = version;
5768         u16 remain_len = len;
5769         if (version == NULL || params == NULL)
5770                 return -EINVAL;
5771         bp = params->bp;
5772
5773         /* Extract first external phy*/
5774         version[0] = '\0';
5775         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5776
5777         if (params->phy[EXT_PHY1].format_fw_ver) {
5778                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5779                                                               ver_p,
5780                                                               &remain_len);
5781                 ver_p += (len - remain_len);
5782         }
5783         if ((params->num_phys == MAX_PHYS) &&
5784             (params->phy[EXT_PHY2].ver_addr != 0)) {
5785                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5786                 if (params->phy[EXT_PHY2].format_fw_ver) {
5787                         *ver_p = '/';
5788                         ver_p++;
5789                         remain_len--;
5790                         status |= params->phy[EXT_PHY2].format_fw_ver(
5791                                 spirom_ver,
5792                                 ver_p,
5793                                 &remain_len);
5794                         ver_p = version + (len - remain_len);
5795                 }
5796         }
5797         *ver_p = '\0';
5798         return status;
5799 }
5800
5801 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5802                                     struct link_params *params)
5803 {
5804         u8 port = params->port;
5805         struct bnx2x *bp = params->bp;
5806
5807         if (phy->req_line_speed != SPEED_1000) {
5808                 u32 md_devad = 0;
5809
5810                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5811
5812                 if (!CHIP_IS_E3(bp)) {
5813                         /* change the uni_phy_addr in the nig */
5814                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5815                                                port*0x18));
5816
5817                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5818                                0x5);
5819                 }
5820
5821                 bnx2x_cl45_write(bp, phy,
5822                                  5,
5823                                  (MDIO_REG_BANK_AER_BLOCK +
5824                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5825                                  0x2800);
5826
5827                 bnx2x_cl45_write(bp, phy,
5828                                  5,
5829                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5830                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5831                                  0x6041);
5832                 msleep(200);
5833                 /* set aer mmd back */
5834                 bnx2x_set_aer_mmd(params, phy);
5835
5836                 if (!CHIP_IS_E3(bp)) {
5837                         /* and md_devad */
5838                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5839                                md_devad);
5840                 }
5841         } else {
5842                 u16 mii_ctrl;
5843                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5844                 bnx2x_cl45_read(bp, phy, 5,
5845                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5846                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5847                                 &mii_ctrl);
5848                 bnx2x_cl45_write(bp, phy, 5,
5849                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5850                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5851                                  mii_ctrl |
5852                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5853         }
5854 }
5855
5856 int bnx2x_set_led(struct link_params *params,
5857                   struct link_vars *vars, u8 mode, u32 speed)
5858 {
5859         u8 port = params->port;
5860         u16 hw_led_mode = params->hw_led_mode;
5861         int rc = 0;
5862         u8 phy_idx;
5863         u32 tmp;
5864         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5865         struct bnx2x *bp = params->bp;
5866         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5867         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5868                  speed, hw_led_mode);
5869         /* In case */
5870         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5871                 if (params->phy[phy_idx].set_link_led) {
5872                         params->phy[phy_idx].set_link_led(
5873                                 &params->phy[phy_idx], params, mode);
5874                 }
5875         }
5876
5877         switch (mode) {
5878         case LED_MODE_FRONT_PANEL_OFF:
5879         case LED_MODE_OFF:
5880                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5881                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5882                        SHARED_HW_CFG_LED_MAC1);
5883
5884                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5885                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5886                 break;
5887
5888         case LED_MODE_OPER:
5889                 /*
5890                  * For all other phys, OPER mode is same as ON, so in case
5891                  * link is down, do nothing
5892                  */
5893                 if (!vars->link_up)
5894                         break;
5895         case LED_MODE_ON:
5896                 if (((params->phy[EXT_PHY1].type ==
5897                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5898                          (params->phy[EXT_PHY1].type ==
5899                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5900                     CHIP_IS_E2(bp) && params->num_phys == 2) {
5901                         /*
5902                          * This is a work-around for E2+8727 Configurations
5903                          */
5904                         if (mode == LED_MODE_ON ||
5905                                 speed == SPEED_10000){
5906                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5907                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5908
5909                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5910                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5911                                         (tmp | EMAC_LED_OVERRIDE));
5912                                 return rc;
5913                         }
5914                 } else if (SINGLE_MEDIA_DIRECT(params) &&
5915                            (CHIP_IS_E1x(bp) ||
5916                             CHIP_IS_E2(bp))) {
5917                         /*
5918                          * This is a work-around for HW issue found when link
5919                          * is up in CL73
5920                          */
5921                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5922                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5923                 } else {
5924                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5925                 }
5926
5927                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5928                 /* Set blinking rate to ~15.9Hz */
5929                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5930                        LED_BLINK_RATE_VAL);
5931                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5932                        port*4, 1);
5933                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5934                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5935
5936                 if (CHIP_IS_E1(bp) &&
5937                     ((speed == SPEED_2500) ||
5938                      (speed == SPEED_1000) ||
5939                      (speed == SPEED_100) ||
5940                      (speed == SPEED_10))) {
5941                         /*
5942                          * On Everest 1 Ax chip versions for speeds less than
5943                          * 10G LED scheme is different
5944                          */
5945                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5946                                + port*4, 1);
5947                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5948                                port*4, 0);
5949                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5950                                port*4, 1);
5951                 }
5952                 break;
5953
5954         default:
5955                 rc = -EINVAL;
5956                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5957                          mode);
5958                 break;
5959         }
5960         return rc;
5961
5962 }
5963
5964 /*
5965  * This function comes to reflect the actual link state read DIRECTLY from the
5966  * HW
5967  */
5968 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5969                     u8 is_serdes)
5970 {
5971         struct bnx2x *bp = params->bp;
5972         u16 gp_status = 0, phy_index = 0;
5973         u8 ext_phy_link_up = 0, serdes_phy_type;
5974         struct link_vars temp_vars;
5975         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
5976
5977         if (CHIP_IS_E3(bp)) {
5978                 u16 link_up;
5979                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5980                     > SPEED_10000) {
5981                         /* Check 20G link */
5982                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5983                                         1, &link_up);
5984                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5985                                         1, &link_up);
5986                         link_up &= (1<<2);
5987                 } else {
5988                         /* Check 10G link and below*/
5989                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5990                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5991                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
5992                                         &gp_status);
5993                         gp_status = ((gp_status >> 8) & 0xf) |
5994                                 ((gp_status >> 12) & 0xf);
5995                         link_up = gp_status & (1 << lane);
5996                 }
5997                 if (!link_up)
5998                         return -ESRCH;
5999         } else {
6000                 CL22_RD_OVER_CL45(bp, int_phy,
6001                           MDIO_REG_BANK_GP_STATUS,
6002                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6003                           &gp_status);
6004         /* link is up only if both local phy and external phy are up */
6005         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6006                 return -ESRCH;
6007         }
6008         /* In XGXS loopback mode, do not check external PHY */
6009         if (params->loopback_mode == LOOPBACK_XGXS)
6010                 return 0;
6011
6012         switch (params->num_phys) {
6013         case 1:
6014                 /* No external PHY */
6015                 return 0;
6016         case 2:
6017                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6018                         &params->phy[EXT_PHY1],
6019                         params, &temp_vars);
6020                 break;
6021         case 3: /* Dual Media */
6022                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6023                       phy_index++) {
6024                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6025                                             ETH_PHY_SFP_FIBER) ||
6026                                            (params->phy[phy_index].media_type ==
6027                                             ETH_PHY_XFP_FIBER) ||
6028                                            (params->phy[phy_index].media_type ==
6029                                             ETH_PHY_DA_TWINAX));
6030
6031                         if (is_serdes != serdes_phy_type)
6032                                 continue;
6033                         if (params->phy[phy_index].read_status) {
6034                                 ext_phy_link_up |=
6035                                         params->phy[phy_index].read_status(
6036                                                 &params->phy[phy_index],
6037                                                 params, &temp_vars);
6038                         }
6039                 }
6040                 break;
6041         }
6042         if (ext_phy_link_up)
6043                 return 0;
6044         return -ESRCH;
6045 }
6046
6047 static int bnx2x_link_initialize(struct link_params *params,
6048                                  struct link_vars *vars)
6049 {
6050         int rc = 0;
6051         u8 phy_index, non_ext_phy;
6052         struct bnx2x *bp = params->bp;
6053         /*
6054          * In case of external phy existence, the line speed would be the
6055          * line speed linked up by the external phy. In case it is direct
6056          * only, then the line_speed during initialization will be
6057          * equal to the req_line_speed
6058          */
6059         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6060
6061         /*
6062          * Initialize the internal phy in case this is a direct board
6063          * (no external phys), or this board has external phy which requires
6064          * to first.
6065          */
6066         if (!USES_WARPCORE(bp))
6067                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6068         /* init ext phy and enable link state int */
6069         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6070                        (params->loopback_mode == LOOPBACK_XGXS));
6071
6072         if (non_ext_phy ||
6073             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6074             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6075                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6076                 if (vars->line_speed == SPEED_AUTO_NEG &&
6077                     (CHIP_IS_E1x(bp) ||
6078                      CHIP_IS_E2(bp)))
6079                         bnx2x_set_parallel_detection(phy, params);
6080                         if (params->phy[INT_PHY].config_init)
6081                                 params->phy[INT_PHY].config_init(phy,
6082                                                                  params,
6083                                                                  vars);
6084         }
6085
6086         /* Init external phy*/
6087         if (non_ext_phy) {
6088                 if (params->phy[INT_PHY].supported &
6089                     SUPPORTED_FIBRE)
6090                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6091         } else {
6092                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6093                       phy_index++) {
6094                         /*
6095                          * No need to initialize second phy in case of first
6096                          * phy only selection. In case of second phy, we do
6097                          * need to initialize the first phy, since they are
6098                          * connected.
6099                          */
6100                         if (params->phy[phy_index].supported &
6101                             SUPPORTED_FIBRE)
6102                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6103
6104                         if (phy_index == EXT_PHY2 &&
6105                             (bnx2x_phy_selection(params) ==
6106                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6107                                 DP(NETIF_MSG_LINK, "Not initializing"
6108                                                 " second phy\n");
6109                                 continue;
6110                         }
6111                         params->phy[phy_index].config_init(
6112                                 &params->phy[phy_index],
6113                                 params, vars);
6114                 }
6115         }
6116         /* Reset the interrupt indication after phy was initialized */
6117         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6118                        params->port*4,
6119                        (NIG_STATUS_XGXS0_LINK10G |
6120                         NIG_STATUS_XGXS0_LINK_STATUS |
6121                         NIG_STATUS_SERDES0_LINK_STATUS |
6122                         NIG_MASK_MI_INT));
6123         bnx2x_update_mng(params, vars->link_status);
6124         return rc;
6125 }
6126
6127 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6128                                  struct link_params *params)
6129 {
6130         /* reset the SerDes/XGXS */
6131         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6132                (0x1ff << (params->port*16)));
6133 }
6134
6135 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6136                                         struct link_params *params)
6137 {
6138         struct bnx2x *bp = params->bp;
6139         u8 gpio_port;
6140         /* HW reset */
6141         if (CHIP_IS_E2(bp))
6142                 gpio_port = BP_PATH(bp);
6143         else
6144                 gpio_port = params->port;
6145         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6146                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6147                        gpio_port);
6148         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6149                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6150                        gpio_port);
6151         DP(NETIF_MSG_LINK, "reset external PHY\n");
6152 }
6153
6154 static int bnx2x_update_link_down(struct link_params *params,
6155                                   struct link_vars *vars)
6156 {
6157         struct bnx2x *bp = params->bp;
6158         u8 port = params->port;
6159
6160         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6161         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6162         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6163         /* indicate no mac active */
6164         vars->mac_type = MAC_TYPE_NONE;
6165
6166         /* update shared memory */
6167         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6168                                LINK_STATUS_LINK_UP |
6169                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6170                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6171                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6172                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6173         vars->line_speed = 0;
6174         bnx2x_update_mng(params, vars->link_status);
6175
6176         /* activate nig drain */
6177         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6178
6179         /* disable emac */
6180         if (!CHIP_IS_E3(bp))
6181                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6182
6183         msleep(10);
6184         /* reset BigMac/Xmac */
6185         if (CHIP_IS_E1x(bp) ||
6186             CHIP_IS_E2(bp)) {
6187                 bnx2x_bmac_rx_disable(bp, params->port);
6188                 REG_WR(bp, GRCBASE_MISC +
6189                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6190                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6191         }
6192         if (CHIP_IS_E3(bp))
6193                 bnx2x_xmac_disable(params);
6194
6195         return 0;
6196 }
6197
6198 static int bnx2x_update_link_up(struct link_params *params,
6199                                 struct link_vars *vars,
6200                                 u8 link_10g)
6201 {
6202         struct bnx2x *bp = params->bp;
6203         u8 port = params->port;
6204         int rc = 0;
6205
6206         vars->link_status |= LINK_STATUS_LINK_UP;
6207         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6208
6209         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6210                 vars->link_status |=
6211                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6212
6213         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6214                 vars->link_status |=
6215                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6216         if (USES_WARPCORE(bp)) {
6217                 if (link_10g) {
6218                         if (bnx2x_xmac_enable(params, vars, 0) ==
6219                             -ESRCH) {
6220                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6221                                 vars->link_up = 0;
6222                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6223                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6224                         }
6225                 } else
6226                         bnx2x_umac_enable(params, vars, 0);
6227                 bnx2x_set_led(params, vars,
6228                               LED_MODE_OPER, vars->line_speed);
6229         }
6230         if ((CHIP_IS_E1x(bp) ||
6231              CHIP_IS_E2(bp))) {
6232                 if (link_10g) {
6233                         if (bnx2x_bmac_enable(params, vars, 0) ==
6234                             -ESRCH) {
6235                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6236                                 vars->link_up = 0;
6237                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6238                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6239                         }
6240
6241                         bnx2x_set_led(params, vars,
6242                                       LED_MODE_OPER, SPEED_10000);
6243                 } else {
6244                         rc = bnx2x_emac_program(params, vars);
6245                         bnx2x_emac_enable(params, vars, 0);
6246
6247                         /* AN complete? */
6248                         if ((vars->link_status &
6249                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6250                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6251                             SINGLE_MEDIA_DIRECT(params))
6252                                 bnx2x_set_gmii_tx_driver(params);
6253                 }
6254         }
6255
6256         /* PBF - link up */
6257         if (CHIP_IS_E1x(bp))
6258                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6259                                        vars->line_speed);
6260
6261         /* disable drain */
6262         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6263
6264         /* update shared memory */
6265         bnx2x_update_mng(params, vars->link_status);
6266         msleep(20);
6267         return rc;
6268 }
6269 /*
6270  * The bnx2x_link_update function should be called upon link
6271  * interrupt.
6272  * Link is considered up as follows:
6273  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6274  *   to be up
6275  * - SINGLE_MEDIA - The link between the 577xx and the external
6276  *   phy (XGXS) need to up as well as the external link of the
6277  *   phy (PHY_EXT1)
6278  * - DUAL_MEDIA - The link between the 577xx and the first
6279  *   external phy needs to be up, and at least one of the 2
6280  *   external phy link must be up.
6281  */
6282 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6283 {
6284         struct bnx2x *bp = params->bp;
6285         struct link_vars phy_vars[MAX_PHYS];
6286         u8 port = params->port;
6287         u8 link_10g_plus, phy_index;
6288         u8 ext_phy_link_up = 0, cur_link_up;
6289         int rc = 0;
6290         u8 is_mi_int = 0;
6291         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6292         u8 active_external_phy = INT_PHY;
6293         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6294         for (phy_index = INT_PHY; phy_index < params->num_phys;
6295               phy_index++) {
6296                 phy_vars[phy_index].flow_ctrl = 0;
6297                 phy_vars[phy_index].link_status = 0;
6298                 phy_vars[phy_index].line_speed = 0;
6299                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6300                 phy_vars[phy_index].phy_link_up = 0;
6301                 phy_vars[phy_index].link_up = 0;
6302                 phy_vars[phy_index].fault_detected = 0;
6303         }
6304
6305         if (USES_WARPCORE(bp))
6306                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6307
6308         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6309                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6310                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6311
6312         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6313                                 port*0x18) > 0);
6314         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6315                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6316                  is_mi_int,
6317                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6318
6319         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6320           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6321           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6322
6323         /* disable emac */
6324         if (!CHIP_IS_E3(bp))
6325                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6326
6327         /*
6328          * Step 1:
6329          * Check external link change only for external phys, and apply
6330          * priority selection between them in case the link on both phys
6331          * is up. Note that instead of the common vars, a temporary
6332          * vars argument is used since each phy may have different link/
6333          * speed/duplex result
6334          */
6335         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6336               phy_index++) {
6337                 struct bnx2x_phy *phy = &params->phy[phy_index];
6338                 if (!phy->read_status)
6339                         continue;
6340                 /* Read link status and params of this ext phy */
6341                 cur_link_up = phy->read_status(phy, params,
6342                                                &phy_vars[phy_index]);
6343                 if (cur_link_up) {
6344                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6345                                    phy_index);
6346                 } else {
6347                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6348                                    phy_index);
6349                         continue;
6350                 }
6351
6352                 if (!ext_phy_link_up) {
6353                         ext_phy_link_up = 1;
6354                         active_external_phy = phy_index;
6355                 } else {
6356                         switch (bnx2x_phy_selection(params)) {
6357                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6358                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6359                         /*
6360                          * In this option, the first PHY makes sure to pass the
6361                          * traffic through itself only.
6362                          * Its not clear how to reset the link on the second phy
6363                          */
6364                                 active_external_phy = EXT_PHY1;
6365                                 break;
6366                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6367                         /*
6368                          * In this option, the first PHY makes sure to pass the
6369                          * traffic through the second PHY.
6370                          */
6371                                 active_external_phy = EXT_PHY2;
6372                                 break;
6373                         default:
6374                         /*
6375                          * Link indication on both PHYs with the following cases
6376                          * is invalid:
6377                          * - FIRST_PHY means that second phy wasn't initialized,
6378                          * hence its link is expected to be down
6379                          * - SECOND_PHY means that first phy should not be able
6380                          * to link up by itself (using configuration)
6381                          * - DEFAULT should be overriden during initialiazation
6382                          */
6383                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6384                                            "mpc=0x%x. DISABLING LINK !!!\n",
6385                                            params->multi_phy_config);
6386                                 ext_phy_link_up = 0;
6387                                 break;
6388                         }
6389                 }
6390         }
6391         prev_line_speed = vars->line_speed;
6392         /*
6393          * Step 2:
6394          * Read the status of the internal phy. In case of
6395          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6396          * otherwise this is the link between the 577xx and the first
6397          * external phy
6398          */
6399         if (params->phy[INT_PHY].read_status)
6400                 params->phy[INT_PHY].read_status(
6401                         &params->phy[INT_PHY],
6402                         params, vars);
6403         /*
6404          * The INT_PHY flow control reside in the vars. This include the
6405          * case where the speed or flow control are not set to AUTO.
6406          * Otherwise, the active external phy flow control result is set
6407          * to the vars. The ext_phy_line_speed is needed to check if the
6408          * speed is different between the internal phy and external phy.
6409          * This case may be result of intermediate link speed change.
6410          */
6411         if (active_external_phy > INT_PHY) {
6412                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6413                 /*
6414                  * Link speed is taken from the XGXS. AN and FC result from
6415                  * the external phy.
6416                  */
6417                 vars->link_status |= phy_vars[active_external_phy].link_status;
6418
6419                 /*
6420                  * if active_external_phy is first PHY and link is up - disable
6421                  * disable TX on second external PHY
6422                  */
6423                 if (active_external_phy == EXT_PHY1) {
6424                         if (params->phy[EXT_PHY2].phy_specific_func) {
6425                                 DP(NETIF_MSG_LINK, "Disabling TX on"
6426                                                    " EXT_PHY2\n");
6427                                 params->phy[EXT_PHY2].phy_specific_func(
6428                                         &params->phy[EXT_PHY2],
6429                                         params, DISABLE_TX);
6430                         }
6431                 }
6432
6433                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6434                 vars->duplex = phy_vars[active_external_phy].duplex;
6435                 if (params->phy[active_external_phy].supported &
6436                     SUPPORTED_FIBRE)
6437                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6438                 else
6439                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6440                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6441                            active_external_phy);
6442         }
6443
6444         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6445               phy_index++) {
6446                 if (params->phy[phy_index].flags &
6447                     FLAGS_REARM_LATCH_SIGNAL) {
6448                         bnx2x_rearm_latch_signal(bp, port,
6449                                                  phy_index ==
6450                                                  active_external_phy);
6451                         break;
6452                 }
6453         }
6454         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6455                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6456                    vars->link_status, ext_phy_line_speed);
6457         /*
6458          * Upon link speed change set the NIG into drain mode. Comes to
6459          * deals with possible FIFO glitch due to clk change when speed
6460          * is decreased without link down indicator
6461          */
6462
6463         if (vars->phy_link_up) {
6464                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6465                     (ext_phy_line_speed != vars->line_speed)) {
6466                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6467                                    " different than the external"
6468                                    " link speed %d\n", vars->line_speed,
6469                                    ext_phy_line_speed);
6470                         vars->phy_link_up = 0;
6471                 } else if (prev_line_speed != vars->line_speed) {
6472                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6473                                0);
6474                         msleep(1);
6475                 }
6476         }
6477
6478         /* anything 10 and over uses the bmac */
6479         link_10g_plus = (vars->line_speed >= SPEED_10000);
6480
6481         bnx2x_link_int_ack(params, vars, link_10g_plus);
6482
6483         /*
6484          * In case external phy link is up, and internal link is down
6485          * (not initialized yet probably after link initialization, it
6486          * needs to be initialized.
6487          * Note that after link down-up as result of cable plug, the xgxs
6488          * link would probably become up again without the need
6489          * initialize it
6490          */
6491         if (!(SINGLE_MEDIA_DIRECT(params))) {
6492                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6493                            " init_preceding = %d\n", ext_phy_link_up,
6494                            vars->phy_link_up,
6495                            params->phy[EXT_PHY1].flags &
6496                            FLAGS_INIT_XGXS_FIRST);
6497                 if (!(params->phy[EXT_PHY1].flags &
6498                       FLAGS_INIT_XGXS_FIRST)
6499                     && ext_phy_link_up && !vars->phy_link_up) {
6500                         vars->line_speed = ext_phy_line_speed;
6501                         if (vars->line_speed < SPEED_1000)
6502                                 vars->phy_flags |= PHY_SGMII_FLAG;
6503                         else
6504                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6505
6506                         if (params->phy[INT_PHY].config_init)
6507                                 params->phy[INT_PHY].config_init(
6508                                         &params->phy[INT_PHY], params,
6509                                                 vars);
6510                 }
6511         }
6512         /*
6513          * Link is up only if both local phy and external phy (in case of
6514          * non-direct board) are up and no fault detected on active PHY.
6515          */
6516         vars->link_up = (vars->phy_link_up &&
6517                          (ext_phy_link_up ||
6518                           SINGLE_MEDIA_DIRECT(params)) &&
6519                          (phy_vars[active_external_phy].fault_detected == 0));
6520
6521         if (vars->link_up)
6522                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6523         else
6524                 rc = bnx2x_update_link_down(params, vars);
6525
6526         return rc;
6527 }
6528
6529
6530 /*****************************************************************************/
6531 /*                          External Phy section                             */
6532 /*****************************************************************************/
6533 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6534 {
6535         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6536                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6537         msleep(1);
6538         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6539                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6540 }
6541
6542 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6543                                       u32 spirom_ver, u32 ver_addr)
6544 {
6545         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6546                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6547
6548         if (ver_addr)
6549                 REG_WR(bp, ver_addr, spirom_ver);
6550 }
6551
6552 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6553                                       struct bnx2x_phy *phy,
6554                                       u8 port)
6555 {
6556         u16 fw_ver1, fw_ver2;
6557
6558         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6559                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6560         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6561                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6562         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6563                                   phy->ver_addr);
6564 }
6565
6566 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6567                                        struct bnx2x_phy *phy,
6568                                        struct link_vars *vars)
6569 {
6570         u16 val;
6571         bnx2x_cl45_read(bp, phy,
6572                         MDIO_AN_DEVAD,
6573                         MDIO_AN_REG_STATUS, &val);
6574         bnx2x_cl45_read(bp, phy,
6575                         MDIO_AN_DEVAD,
6576                         MDIO_AN_REG_STATUS, &val);
6577         if (val & (1<<5))
6578                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6579         if ((val & (1<<0)) == 0)
6580                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6581 }
6582
6583 /******************************************************************/
6584 /*              common BCM8073/BCM8727 PHY SECTION                */
6585 /******************************************************************/
6586 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6587                                   struct link_params *params,
6588                                   struct link_vars *vars)
6589 {
6590         struct bnx2x *bp = params->bp;
6591         if (phy->req_line_speed == SPEED_10 ||
6592             phy->req_line_speed == SPEED_100) {
6593                 vars->flow_ctrl = phy->req_flow_ctrl;
6594                 return;
6595         }
6596
6597         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6598             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6599                 u16 pause_result;
6600                 u16 ld_pause;           /* local */
6601                 u16 lp_pause;           /* link partner */
6602                 bnx2x_cl45_read(bp, phy,
6603                                 MDIO_AN_DEVAD,
6604                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6605
6606                 bnx2x_cl45_read(bp, phy,
6607                                 MDIO_AN_DEVAD,
6608                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6609                 pause_result = (ld_pause &
6610                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6611                 pause_result |= (lp_pause &
6612                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6613
6614                 bnx2x_pause_resolve(vars, pause_result);
6615                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6616                            pause_result);
6617         }
6618 }
6619 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6620                                              struct bnx2x_phy *phy,
6621                                              u8 port)
6622 {
6623         u32 count = 0;
6624         u16 fw_ver1, fw_msgout;
6625         int rc = 0;
6626
6627         /* Boot port from external ROM  */
6628         /* EDC grst */
6629         bnx2x_cl45_write(bp, phy,
6630                          MDIO_PMA_DEVAD,
6631                          MDIO_PMA_REG_GEN_CTRL,
6632                          0x0001);
6633
6634         /* ucode reboot and rst */
6635         bnx2x_cl45_write(bp, phy,
6636                          MDIO_PMA_DEVAD,
6637                          MDIO_PMA_REG_GEN_CTRL,
6638                          0x008c);
6639
6640         bnx2x_cl45_write(bp, phy,
6641                          MDIO_PMA_DEVAD,
6642                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6643
6644         /* Reset internal microprocessor */
6645         bnx2x_cl45_write(bp, phy,
6646                          MDIO_PMA_DEVAD,
6647                          MDIO_PMA_REG_GEN_CTRL,
6648                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6649
6650         /* Release srst bit */
6651         bnx2x_cl45_write(bp, phy,
6652                          MDIO_PMA_DEVAD,
6653                          MDIO_PMA_REG_GEN_CTRL,
6654                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6655
6656         /* Delay 100ms per the PHY specifications */
6657         msleep(100);
6658
6659         /* 8073 sometimes taking longer to download */
6660         do {
6661                 count++;
6662                 if (count > 300) {
6663                         DP(NETIF_MSG_LINK,
6664                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6665                                  "Download failed. fw version = 0x%x\n",
6666                                  port, fw_ver1);
6667                         rc = -EINVAL;
6668                         break;
6669                 }
6670
6671                 bnx2x_cl45_read(bp, phy,
6672                                 MDIO_PMA_DEVAD,
6673                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6674                 bnx2x_cl45_read(bp, phy,
6675                                 MDIO_PMA_DEVAD,
6676                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6677
6678                 msleep(1);
6679         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6680                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6681                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6682
6683         /* Clear ser_boot_ctl bit */
6684         bnx2x_cl45_write(bp, phy,
6685                          MDIO_PMA_DEVAD,
6686                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6687         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6688
6689         DP(NETIF_MSG_LINK,
6690                  "bnx2x_8073_8727_external_rom_boot port %x:"
6691                  "Download complete. fw version = 0x%x\n",
6692                  port, fw_ver1);
6693
6694         return rc;
6695 }
6696
6697 /******************************************************************/
6698 /*                      BCM8073 PHY SECTION                       */
6699 /******************************************************************/
6700 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6701 {
6702         /* This is only required for 8073A1, version 102 only */
6703         u16 val;
6704
6705         /* Read 8073 HW revision*/
6706         bnx2x_cl45_read(bp, phy,
6707                         MDIO_PMA_DEVAD,
6708                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6709
6710         if (val != 1) {
6711                 /* No need to workaround in 8073 A1 */
6712                 return 0;
6713         }
6714
6715         bnx2x_cl45_read(bp, phy,
6716                         MDIO_PMA_DEVAD,
6717                         MDIO_PMA_REG_ROM_VER2, &val);
6718
6719         /* SNR should be applied only for version 0x102 */
6720         if (val != 0x102)
6721                 return 0;
6722
6723         return 1;
6724 }
6725
6726 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6727 {
6728         u16 val, cnt, cnt1 ;
6729
6730         bnx2x_cl45_read(bp, phy,
6731                         MDIO_PMA_DEVAD,
6732                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6733
6734         if (val > 0) {
6735                 /* No need to workaround in 8073 A1 */
6736                 return 0;
6737         }
6738         /* XAUI workaround in 8073 A0: */
6739
6740         /*
6741          * After loading the boot ROM and restarting Autoneg, poll
6742          * Dev1, Reg $C820:
6743          */
6744
6745         for (cnt = 0; cnt < 1000; cnt++) {
6746                 bnx2x_cl45_read(bp, phy,
6747                                 MDIO_PMA_DEVAD,
6748                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6749                                 &val);
6750                   /*
6751                    * If bit [14] = 0 or bit [13] = 0, continue on with
6752                    * system initialization (XAUI work-around not required, as
6753                    * these bits indicate 2.5G or 1G link up).
6754                    */
6755                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6756                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6757                         return 0;
6758                 } else if (!(val & (1<<15))) {
6759                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6760                         /*
6761                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6762                          * MSB (bit15) goes to 1 (indicating that the XAUI
6763                          * workaround has completed), then continue on with
6764                          * system initialization.
6765                          */
6766                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6767                                 bnx2x_cl45_read(bp, phy,
6768                                         MDIO_PMA_DEVAD,
6769                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6770                                 if (val & (1<<15)) {
6771                                         DP(NETIF_MSG_LINK,
6772                                           "XAUI workaround has completed\n");
6773                                         return 0;
6774                                  }
6775                                  msleep(3);
6776                         }
6777                         break;
6778                 }
6779                 msleep(3);
6780         }
6781         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6782         return -EINVAL;
6783 }
6784
6785 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6786 {
6787         /* Force KR or KX */
6788         bnx2x_cl45_write(bp, phy,
6789                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6790         bnx2x_cl45_write(bp, phy,
6791                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6792         bnx2x_cl45_write(bp, phy,
6793                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6794         bnx2x_cl45_write(bp, phy,
6795                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6796 }
6797
6798 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6799                                       struct bnx2x_phy *phy,
6800                                       struct link_vars *vars)
6801 {
6802         u16 cl37_val;
6803         struct bnx2x *bp = params->bp;
6804         bnx2x_cl45_read(bp, phy,
6805                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6806
6807         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6808         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6809         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6810         if ((vars->ieee_fc &
6811             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6812             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6813                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6814         }
6815         if ((vars->ieee_fc &
6816             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6817             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6818                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6819         }
6820         if ((vars->ieee_fc &
6821             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6822             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6823                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6824         }
6825         DP(NETIF_MSG_LINK,
6826                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6827
6828         bnx2x_cl45_write(bp, phy,
6829                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6830         msleep(500);
6831 }
6832
6833 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6834                                   struct link_params *params,
6835                                   struct link_vars *vars)
6836 {
6837         struct bnx2x *bp = params->bp;
6838         u16 val = 0, tmp1;
6839         u8 gpio_port;
6840         DP(NETIF_MSG_LINK, "Init 8073\n");
6841
6842         if (CHIP_IS_E2(bp))
6843                 gpio_port = BP_PATH(bp);
6844         else
6845                 gpio_port = params->port;
6846         /* Restore normal power mode*/
6847         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6848                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6849
6850         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6851                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6852
6853         /* enable LASI */
6854         bnx2x_cl45_write(bp, phy,
6855                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6856         bnx2x_cl45_write(bp, phy,
6857                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6858
6859         bnx2x_8073_set_pause_cl37(params, phy, vars);
6860
6861         bnx2x_cl45_read(bp, phy,
6862                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6863
6864         bnx2x_cl45_read(bp, phy,
6865                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6866
6867         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6868
6869         /* Swap polarity if required - Must be done only in non-1G mode */
6870         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6871                 /* Configure the 8073 to swap _P and _N of the KR lines */
6872                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6873                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6874                 bnx2x_cl45_read(bp, phy,
6875                                 MDIO_PMA_DEVAD,
6876                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6877                 bnx2x_cl45_write(bp, phy,
6878                                  MDIO_PMA_DEVAD,
6879                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6880                                  (val | (3<<9)));
6881         }
6882
6883
6884         /* Enable CL37 BAM */
6885         if (REG_RD(bp, params->shmem_base +
6886                          offsetof(struct shmem_region, dev_info.
6887                                   port_hw_config[params->port].default_cfg)) &
6888             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6889
6890                 bnx2x_cl45_read(bp, phy,
6891                                 MDIO_AN_DEVAD,
6892                                 MDIO_AN_REG_8073_BAM, &val);
6893                 bnx2x_cl45_write(bp, phy,
6894                                  MDIO_AN_DEVAD,
6895                                  MDIO_AN_REG_8073_BAM, val | 1);
6896                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6897         }
6898         if (params->loopback_mode == LOOPBACK_EXT) {
6899                 bnx2x_807x_force_10G(bp, phy);
6900                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6901                 return 0;
6902         } else {
6903                 bnx2x_cl45_write(bp, phy,
6904                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6905         }
6906         if (phy->req_line_speed != SPEED_AUTO_NEG) {
6907                 if (phy->req_line_speed == SPEED_10000) {
6908                         val = (1<<7);
6909                 } else if (phy->req_line_speed ==  SPEED_2500) {
6910                         val = (1<<5);
6911                         /*
6912                          * Note that 2.5G works only when used with 1G
6913                          * advertisement
6914                          */
6915                 } else
6916                         val = (1<<5);
6917         } else {
6918                 val = 0;
6919                 if (phy->speed_cap_mask &
6920                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6921                         val |= (1<<7);
6922
6923                 /* Note that 2.5G works only when used with 1G advertisement */
6924                 if (phy->speed_cap_mask &
6925                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6926                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6927                         val |= (1<<5);
6928                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6929         }
6930
6931         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6932         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6933
6934         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6935              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6936             (phy->req_line_speed == SPEED_2500)) {
6937                 u16 phy_ver;
6938                 /* Allow 2.5G for A1 and above */
6939                 bnx2x_cl45_read(bp, phy,
6940                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6941                                 &phy_ver);
6942                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6943                 if (phy_ver > 0)
6944                         tmp1 |= 1;
6945                 else
6946                         tmp1 &= 0xfffe;
6947         } else {
6948                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6949                 tmp1 &= 0xfffe;
6950         }
6951
6952         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6953         /* Add support for CL37 (passive mode) II */
6954
6955         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6956         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6957                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6958                                   0x20 : 0x40)));
6959
6960         /* Add support for CL37 (passive mode) III */
6961         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6962
6963         /*
6964          * The SNR will improve about 2db by changing BW and FEE main
6965          * tap. Rest commands are executed after link is up
6966          * Change FFE main cursor to 5 in EDC register
6967          */
6968         if (bnx2x_8073_is_snr_needed(bp, phy))
6969                 bnx2x_cl45_write(bp, phy,
6970                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6971                                  0xFB0C);
6972
6973         /* Enable FEC (Forware Error Correction) Request in the AN */
6974         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6975         tmp1 |= (1<<15);
6976         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6977
6978         bnx2x_ext_phy_set_pause(params, phy, vars);
6979
6980         /* Restart autoneg */
6981         msleep(500);
6982         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6983         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6984                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6985         return 0;
6986 }
6987
6988 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6989                                  struct link_params *params,
6990                                  struct link_vars *vars)
6991 {
6992         struct bnx2x *bp = params->bp;
6993         u8 link_up = 0;
6994         u16 val1, val2;
6995         u16 link_status = 0;
6996         u16 an1000_status = 0;
6997
6998         bnx2x_cl45_read(bp, phy,
6999                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7000
7001         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7002
7003         /* clear the interrupt LASI status register */
7004         bnx2x_cl45_read(bp, phy,
7005                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7006         bnx2x_cl45_read(bp, phy,
7007                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7008         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7009         /* Clear MSG-OUT */
7010         bnx2x_cl45_read(bp, phy,
7011                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7012
7013         /* Check the LASI */
7014         bnx2x_cl45_read(bp, phy,
7015                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7016
7017         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7018
7019         /* Check the link status */
7020         bnx2x_cl45_read(bp, phy,
7021                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7022         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7023
7024         bnx2x_cl45_read(bp, phy,
7025                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7026         bnx2x_cl45_read(bp, phy,
7027                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7028         link_up = ((val1 & 4) == 4);
7029         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7030
7031         if (link_up &&
7032              ((phy->req_line_speed != SPEED_10000))) {
7033                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7034                         return 0;
7035         }
7036         bnx2x_cl45_read(bp, phy,
7037                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7038         bnx2x_cl45_read(bp, phy,
7039                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7040
7041         /* Check the link status on 1.1.2 */
7042         bnx2x_cl45_read(bp, phy,
7043                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7044         bnx2x_cl45_read(bp, phy,
7045                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7046         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7047                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7048
7049         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7050         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7051                 /*
7052                  * The SNR will improve about 2dbby changing the BW and FEE main
7053                  * tap. The 1st write to change FFE main tap is set before
7054                  * restart AN. Change PLL Bandwidth in EDC register
7055                  */
7056                 bnx2x_cl45_write(bp, phy,
7057                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7058                                  0x26BC);
7059
7060                 /* Change CDR Bandwidth in EDC register */
7061                 bnx2x_cl45_write(bp, phy,
7062                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7063                                  0x0333);
7064         }
7065         bnx2x_cl45_read(bp, phy,
7066                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7067                         &link_status);
7068
7069         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7070         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7071                 link_up = 1;
7072                 vars->line_speed = SPEED_10000;
7073                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7074                            params->port);
7075         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7076                 link_up = 1;
7077                 vars->line_speed = SPEED_2500;
7078                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7079                            params->port);
7080         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7081                 link_up = 1;
7082                 vars->line_speed = SPEED_1000;
7083                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7084                            params->port);
7085         } else {
7086                 link_up = 0;
7087                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7088                            params->port);
7089         }
7090
7091         if (link_up) {
7092                 /* Swap polarity if required */
7093                 if (params->lane_config &
7094                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7095                         /* Configure the 8073 to swap P and N of the KR lines */
7096                         bnx2x_cl45_read(bp, phy,
7097                                         MDIO_XS_DEVAD,
7098                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7099                         /*
7100                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7101                          * when it`s in 10G mode.
7102                          */
7103                         if (vars->line_speed == SPEED_1000) {
7104                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7105                                               "the 8073\n");
7106                                 val1 |= (1<<3);
7107                         } else
7108                                 val1 &= ~(1<<3);
7109
7110                         bnx2x_cl45_write(bp, phy,
7111                                          MDIO_XS_DEVAD,
7112                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7113                                          val1);
7114                 }
7115                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7116                 bnx2x_8073_resolve_fc(phy, params, vars);
7117                 vars->duplex = DUPLEX_FULL;
7118         }
7119         return link_up;
7120 }
7121
7122 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7123                                   struct link_params *params)
7124 {
7125         struct bnx2x *bp = params->bp;
7126         u8 gpio_port;
7127         if (CHIP_IS_E2(bp))
7128                 gpio_port = BP_PATH(bp);
7129         else
7130                 gpio_port = params->port;
7131         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7132            gpio_port);
7133         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7134                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7135                        gpio_port);
7136 }
7137
7138 /******************************************************************/
7139 /*                      BCM8705 PHY SECTION                       */
7140 /******************************************************************/
7141 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7142                                   struct link_params *params,
7143                                   struct link_vars *vars)
7144 {
7145         struct bnx2x *bp = params->bp;
7146         DP(NETIF_MSG_LINK, "init 8705\n");
7147         /* Restore normal power mode*/
7148         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7149                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7150         /* HW reset */
7151         bnx2x_ext_phy_hw_reset(bp, params->port);
7152         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7153         bnx2x_wait_reset_complete(bp, phy, params);
7154
7155         bnx2x_cl45_write(bp, phy,
7156                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7157         bnx2x_cl45_write(bp, phy,
7158                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7159         bnx2x_cl45_write(bp, phy,
7160                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7161         bnx2x_cl45_write(bp, phy,
7162                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7163         /* BCM8705 doesn't have microcode, hence the 0 */
7164         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7165         return 0;
7166 }
7167
7168 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7169                                  struct link_params *params,
7170                                  struct link_vars *vars)
7171 {
7172         u8 link_up = 0;
7173         u16 val1, rx_sd;
7174         struct bnx2x *bp = params->bp;
7175         DP(NETIF_MSG_LINK, "read status 8705\n");
7176         bnx2x_cl45_read(bp, phy,
7177                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7178         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7179
7180         bnx2x_cl45_read(bp, phy,
7181                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7182         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7183
7184         bnx2x_cl45_read(bp, phy,
7185                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7186
7187         bnx2x_cl45_read(bp, phy,
7188                       MDIO_PMA_DEVAD, 0xc809, &val1);
7189         bnx2x_cl45_read(bp, phy,
7190                       MDIO_PMA_DEVAD, 0xc809, &val1);
7191
7192         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7193         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7194         if (link_up) {
7195                 vars->line_speed = SPEED_10000;
7196                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7197         }
7198         return link_up;
7199 }
7200
7201 /******************************************************************/
7202 /*                      SFP+ module Section                       */
7203 /******************************************************************/
7204 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7205                                            struct bnx2x_phy *phy,
7206                                            u8 pmd_dis)
7207 {
7208         struct bnx2x *bp = params->bp;
7209         /*
7210          * Disable transmitter only for bootcodes which can enable it afterwards
7211          * (for D3 link)
7212          */
7213         if (pmd_dis) {
7214                 if (params->feature_config_flags &
7215                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7216                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7217                 else {
7218                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7219                         return;
7220                 }
7221         } else
7222                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7223         bnx2x_cl45_write(bp, phy,
7224                          MDIO_PMA_DEVAD,
7225                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7226 }
7227
7228 static u8 bnx2x_get_gpio_port(struct link_params *params)
7229 {
7230         u8 gpio_port;
7231         u32 swap_val, swap_override;
7232         struct bnx2x *bp = params->bp;
7233         if (CHIP_IS_E2(bp))
7234                 gpio_port = BP_PATH(bp);
7235         else
7236                 gpio_port = params->port;
7237         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7238         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7239         return gpio_port ^ (swap_val && swap_override);
7240 }
7241
7242 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7243                                            struct bnx2x_phy *phy,
7244                                            u8 tx_en)
7245 {
7246         u16 val;
7247         u8 port = params->port;
7248         struct bnx2x *bp = params->bp;
7249         u32 tx_en_mode;
7250
7251         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7252         tx_en_mode = REG_RD(bp, params->shmem_base +
7253                             offsetof(struct shmem_region,
7254                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7255                 PORT_HW_CFG_TX_LASER_MASK;
7256         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7257                            "mode = %x\n", tx_en, port, tx_en_mode);
7258         switch (tx_en_mode) {
7259         case PORT_HW_CFG_TX_LASER_MDIO:
7260
7261                 bnx2x_cl45_read(bp, phy,
7262                                 MDIO_PMA_DEVAD,
7263                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7264                                 &val);
7265
7266                 if (tx_en)
7267                         val &= ~(1<<15);
7268                 else
7269                         val |= (1<<15);
7270
7271                 bnx2x_cl45_write(bp, phy,
7272                                  MDIO_PMA_DEVAD,
7273                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7274                                  val);
7275         break;
7276         case PORT_HW_CFG_TX_LASER_GPIO0:
7277         case PORT_HW_CFG_TX_LASER_GPIO1:
7278         case PORT_HW_CFG_TX_LASER_GPIO2:
7279         case PORT_HW_CFG_TX_LASER_GPIO3:
7280         {
7281                 u16 gpio_pin;
7282                 u8 gpio_port, gpio_mode;
7283                 if (tx_en)
7284                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7285                 else
7286                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7287
7288                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7289                 gpio_port = bnx2x_get_gpio_port(params);
7290                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7291                 break;
7292         }
7293         default:
7294                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7295                 break;
7296         }
7297 }
7298
7299 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7300                                       struct bnx2x_phy *phy,
7301                                       u8 tx_en)
7302 {
7303         struct bnx2x *bp = params->bp;
7304         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7305         if (CHIP_IS_E3(bp))
7306                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7307         else
7308                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7309 }
7310
7311 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7312                                              struct link_params *params,
7313                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7314 {
7315         struct bnx2x *bp = params->bp;
7316         u16 val = 0;
7317         u16 i;
7318         if (byte_cnt > 16) {
7319                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7320                             " is limited to 0xf\n");
7321                 return -EINVAL;
7322         }
7323         /* Set the read command byte count */
7324         bnx2x_cl45_write(bp, phy,
7325                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7326                          (byte_cnt | 0xa000));
7327
7328         /* Set the read command address */
7329         bnx2x_cl45_write(bp, phy,
7330                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7331                          addr);
7332
7333         /* Activate read command */
7334         bnx2x_cl45_write(bp, phy,
7335                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7336                          0x2c0f);
7337
7338         /* Wait up to 500us for command complete status */
7339         for (i = 0; i < 100; i++) {
7340                 bnx2x_cl45_read(bp, phy,
7341                                 MDIO_PMA_DEVAD,
7342                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7343                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7344                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7345                         break;
7346                 udelay(5);
7347         }
7348
7349         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7350                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7351                 DP(NETIF_MSG_LINK,
7352                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7353                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7354                 return -EINVAL;
7355         }
7356
7357         /* Read the buffer */
7358         for (i = 0; i < byte_cnt; i++) {
7359                 bnx2x_cl45_read(bp, phy,
7360                                 MDIO_PMA_DEVAD,
7361                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7362                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7363         }
7364
7365         for (i = 0; i < 100; i++) {
7366                 bnx2x_cl45_read(bp, phy,
7367                                 MDIO_PMA_DEVAD,
7368                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7369                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7370                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7371                         return 0;
7372                 msleep(1);
7373         }
7374         return -EINVAL;
7375 }
7376
7377 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7378                                                  struct link_params *params,
7379                                                  u16 addr, u8 byte_cnt,
7380                                                  u8 *o_buf)
7381 {
7382         int rc = 0;
7383         u8 i, j = 0, cnt = 0;
7384         u32 data_array[4];
7385         u16 addr32;
7386         struct bnx2x *bp = params->bp;
7387         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7388                                         " addr %d, cnt %d\n",
7389                                         addr, byte_cnt);*/
7390         if (byte_cnt > 16) {
7391                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7392                             " is limited to 16 bytes\n");
7393                 return -EINVAL;
7394         }
7395
7396         /* 4 byte aligned address */
7397         addr32 = addr & (~0x3);
7398         do {
7399                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7400                                     data_array);
7401         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7402
7403         if (rc == 0) {
7404                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7405                         o_buf[j] = *((u8 *)data_array + i);
7406                         j++;
7407                 }
7408         }
7409
7410         return rc;
7411 }
7412
7413 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7414                                              struct link_params *params,
7415                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7416 {
7417         struct bnx2x *bp = params->bp;
7418         u16 val, i;
7419
7420         if (byte_cnt > 16) {
7421                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7422                             " is limited to 0xf\n");
7423                 return -EINVAL;
7424         }
7425
7426         /* Need to read from 1.8000 to clear it */
7427         bnx2x_cl45_read(bp, phy,
7428                         MDIO_PMA_DEVAD,
7429                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7430                         &val);
7431
7432         /* Set the read command byte count */
7433         bnx2x_cl45_write(bp, phy,
7434                          MDIO_PMA_DEVAD,
7435                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7436                          ((byte_cnt < 2) ? 2 : byte_cnt));
7437
7438         /* Set the read command address */
7439         bnx2x_cl45_write(bp, phy,
7440                          MDIO_PMA_DEVAD,
7441                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7442                          addr);
7443         /* Set the destination address */
7444         bnx2x_cl45_write(bp, phy,
7445                          MDIO_PMA_DEVAD,
7446                          0x8004,
7447                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7448
7449         /* Activate read command */
7450         bnx2x_cl45_write(bp, phy,
7451                          MDIO_PMA_DEVAD,
7452                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7453                          0x8002);
7454         /*
7455          * Wait appropriate time for two-wire command to finish before
7456          * polling the status register
7457          */
7458         msleep(1);
7459
7460         /* Wait up to 500us for command complete status */
7461         for (i = 0; i < 100; i++) {
7462                 bnx2x_cl45_read(bp, phy,
7463                                 MDIO_PMA_DEVAD,
7464                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7465                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7466                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7467                         break;
7468                 udelay(5);
7469         }
7470
7471         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7472                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7473                 DP(NETIF_MSG_LINK,
7474                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7475                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7476                 return -EFAULT;
7477         }
7478
7479         /* Read the buffer */
7480         for (i = 0; i < byte_cnt; i++) {
7481                 bnx2x_cl45_read(bp, phy,
7482                                 MDIO_PMA_DEVAD,
7483                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7484                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7485         }
7486
7487         for (i = 0; i < 100; i++) {
7488                 bnx2x_cl45_read(bp, phy,
7489                                 MDIO_PMA_DEVAD,
7490                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7491                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7492                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7493                         return 0;
7494                 msleep(1);
7495         }
7496
7497         return -EINVAL;
7498 }
7499
7500 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7501                                  struct link_params *params, u16 addr,
7502                                  u8 byte_cnt, u8 *o_buf)
7503 {
7504         int rc = -EINVAL;
7505         switch (phy->type) {
7506         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7507                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7508                                                        byte_cnt, o_buf);
7509         break;
7510         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7511         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7512                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7513                                                        byte_cnt, o_buf);
7514         break;
7515         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7516                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7517                                                            byte_cnt, o_buf);
7518         break;
7519         }
7520         return rc;
7521 }
7522
7523 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7524                               struct link_params *params,
7525                               u16 *edc_mode)
7526 {
7527         struct bnx2x *bp = params->bp;
7528         u32 sync_offset = 0, phy_idx, media_types;
7529         u8 val, check_limiting_mode = 0;
7530         *edc_mode = EDC_MODE_LIMITING;
7531
7532         phy->media_type = ETH_PHY_UNSPECIFIED;
7533         /* First check for copper cable */
7534         if (bnx2x_read_sfp_module_eeprom(phy,
7535                                          params,
7536                                          SFP_EEPROM_CON_TYPE_ADDR,
7537                                          1,
7538                                          &val) != 0) {
7539                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7540                 return -EINVAL;
7541         }
7542
7543         switch (val) {
7544         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7545         {
7546                 u8 copper_module_type;
7547                 phy->media_type = ETH_PHY_DA_TWINAX;
7548                 /*
7549                  * Check if its active cable (includes SFP+ module)
7550                  * of passive cable
7551                  */
7552                 if (bnx2x_read_sfp_module_eeprom(phy,
7553                                                params,
7554                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7555                                                1,
7556                                                &copper_module_type) != 0) {
7557                         DP(NETIF_MSG_LINK,
7558                                 "Failed to read copper-cable-type"
7559                                 " from SFP+ EEPROM\n");
7560                         return -EINVAL;
7561                 }
7562
7563                 if (copper_module_type &
7564                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7565                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7566                         check_limiting_mode = 1;
7567                 } else if (copper_module_type &
7568                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7569                                 DP(NETIF_MSG_LINK, "Passive Copper"
7570                                             " cable detected\n");
7571                                 *edc_mode =
7572                                       EDC_MODE_PASSIVE_DAC;
7573                 } else {
7574                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7575                                      "type 0x%x !!!\n", copper_module_type);
7576                         return -EINVAL;
7577                 }
7578                 break;
7579         }
7580         case SFP_EEPROM_CON_TYPE_VAL_LC:
7581                 phy->media_type = ETH_PHY_SFP_FIBER;
7582                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7583                 check_limiting_mode = 1;
7584                 break;
7585         default:
7586                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7587                          val);
7588                 return -EINVAL;
7589         }
7590         sync_offset = params->shmem_base +
7591                 offsetof(struct shmem_region,
7592                          dev_info.port_hw_config[params->port].media_type);
7593         media_types = REG_RD(bp, sync_offset);
7594         /* Update media type for non-PMF sync */
7595         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7596                 if (&(params->phy[phy_idx]) == phy) {
7597                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7598                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7599                         media_types |= ((phy->media_type &
7600                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7601                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7602                         break;
7603                 }
7604         }
7605         REG_WR(bp, sync_offset, media_types);
7606         if (check_limiting_mode) {
7607                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7608                 if (bnx2x_read_sfp_module_eeprom(phy,
7609                                                  params,
7610                                                  SFP_EEPROM_OPTIONS_ADDR,
7611                                                  SFP_EEPROM_OPTIONS_SIZE,
7612                                                  options) != 0) {
7613                         DP(NETIF_MSG_LINK, "Failed to read Option"
7614                                 " field from module EEPROM\n");
7615                         return -EINVAL;
7616                 }
7617                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7618                         *edc_mode = EDC_MODE_LINEAR;
7619                 else
7620                         *edc_mode = EDC_MODE_LIMITING;
7621         }
7622         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7623         return 0;
7624 }
7625 /*
7626  * This function read the relevant field from the module (SFP+), and verify it
7627  * is compliant with this board
7628  */
7629 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7630                                    struct link_params *params)
7631 {
7632         struct bnx2x *bp = params->bp;
7633         u32 val, cmd;
7634         u32 fw_resp, fw_cmd_param;
7635         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7636         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7637         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7638         val = REG_RD(bp, params->shmem_base +
7639                          offsetof(struct shmem_region, dev_info.
7640                                   port_feature_config[params->port].config));
7641         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7642             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7643                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7644                 return 0;
7645         }
7646
7647         if (params->feature_config_flags &
7648             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7649                 /* Use specific phy request */
7650                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7651         } else if (params->feature_config_flags &
7652                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7653                 /* Use first phy request only in case of non-dual media*/
7654                 if (DUAL_MEDIA(params)) {
7655                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7656                            "verification\n");
7657                         return -EINVAL;
7658                 }
7659                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7660         } else {
7661                 /* No support in OPT MDL detection */
7662                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7663                           "verification\n");
7664                 return -EINVAL;
7665         }
7666
7667         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7668         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7669         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7670                 DP(NETIF_MSG_LINK, "Approved module\n");
7671                 return 0;
7672         }
7673
7674         /* format the warning message */
7675         if (bnx2x_read_sfp_module_eeprom(phy,
7676                                          params,
7677                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7678                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7679                                          (u8 *)vendor_name))
7680                 vendor_name[0] = '\0';
7681         else
7682                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7683         if (bnx2x_read_sfp_module_eeprom(phy,
7684                                          params,
7685                                          SFP_EEPROM_PART_NO_ADDR,
7686                                          SFP_EEPROM_PART_NO_SIZE,
7687                                          (u8 *)vendor_pn))
7688                 vendor_pn[0] = '\0';
7689         else
7690                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7691
7692         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7693                               " Port %d from %s part number %s\n",
7694                          params->port, vendor_name, vendor_pn);
7695         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7696         return -EINVAL;
7697 }
7698
7699 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7700                                                  struct link_params *params)
7701
7702 {
7703         u8 val;
7704         struct bnx2x *bp = params->bp;
7705         u16 timeout;
7706         /*
7707          * Initialization time after hot-plug may take up to 300ms for
7708          * some phys type ( e.g. JDSU )
7709          */
7710
7711         for (timeout = 0; timeout < 60; timeout++) {
7712                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7713                     == 0) {
7714                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
7715                                      "took %d ms\n", timeout * 5);
7716                         return 0;
7717                 }
7718                 msleep(5);
7719         }
7720         return -EINVAL;
7721 }
7722
7723 static void bnx2x_8727_power_module(struct bnx2x *bp,
7724                                     struct bnx2x_phy *phy,
7725                                     u8 is_power_up) {
7726         /* Make sure GPIOs are not using for LED mode */
7727         u16 val;
7728         /*
7729          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7730          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7731          * output
7732          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7733          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7734          * where the 1st bit is the over-current(only input), and 2nd bit is
7735          * for power( only output )
7736          *
7737          * In case of NOC feature is disabled and power is up, set GPIO control
7738          *  as input to enable listening of over-current indication
7739          */
7740         if (phy->flags & FLAGS_NOC)
7741                 return;
7742         if (is_power_up)
7743                 val = (1<<4);
7744         else
7745                 /*
7746                  * Set GPIO control to OUTPUT, and set the power bit
7747                  * to according to the is_power_up
7748                  */
7749                 val = (1<<1);
7750
7751         bnx2x_cl45_write(bp, phy,
7752                          MDIO_PMA_DEVAD,
7753                          MDIO_PMA_REG_8727_GPIO_CTRL,
7754                          val);
7755 }
7756
7757 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7758                                         struct bnx2x_phy *phy,
7759                                         u16 edc_mode)
7760 {
7761         u16 cur_limiting_mode;
7762
7763         bnx2x_cl45_read(bp, phy,
7764                         MDIO_PMA_DEVAD,
7765                         MDIO_PMA_REG_ROM_VER2,
7766                         &cur_limiting_mode);
7767         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7768                  cur_limiting_mode);
7769
7770         if (edc_mode == EDC_MODE_LIMITING) {
7771                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7772                 bnx2x_cl45_write(bp, phy,
7773                                  MDIO_PMA_DEVAD,
7774                                  MDIO_PMA_REG_ROM_VER2,
7775                                  EDC_MODE_LIMITING);
7776         } else { /* LRM mode ( default )*/
7777
7778                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7779
7780                 /*
7781                  * Changing to LRM mode takes quite few seconds. So do it only
7782                  * if current mode is limiting (default is LRM)
7783                  */
7784                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7785                         return 0;
7786
7787                 bnx2x_cl45_write(bp, phy,
7788                                  MDIO_PMA_DEVAD,
7789                                  MDIO_PMA_REG_LRM_MODE,
7790                                  0);
7791                 bnx2x_cl45_write(bp, phy,
7792                                  MDIO_PMA_DEVAD,
7793                                  MDIO_PMA_REG_ROM_VER2,
7794                                  0x128);
7795                 bnx2x_cl45_write(bp, phy,
7796                                  MDIO_PMA_DEVAD,
7797                                  MDIO_PMA_REG_MISC_CTRL0,
7798                                  0x4008);
7799                 bnx2x_cl45_write(bp, phy,
7800                                  MDIO_PMA_DEVAD,
7801                                  MDIO_PMA_REG_LRM_MODE,
7802                                  0xaaaa);
7803         }
7804         return 0;
7805 }
7806
7807 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7808                                         struct bnx2x_phy *phy,
7809                                         u16 edc_mode)
7810 {
7811         u16 phy_identifier;
7812         u16 rom_ver2_val;
7813         bnx2x_cl45_read(bp, phy,
7814                         MDIO_PMA_DEVAD,
7815                         MDIO_PMA_REG_PHY_IDENTIFIER,
7816                         &phy_identifier);
7817
7818         bnx2x_cl45_write(bp, phy,
7819                          MDIO_PMA_DEVAD,
7820                          MDIO_PMA_REG_PHY_IDENTIFIER,
7821                          (phy_identifier & ~(1<<9)));
7822
7823         bnx2x_cl45_read(bp, phy,
7824                         MDIO_PMA_DEVAD,
7825                         MDIO_PMA_REG_ROM_VER2,
7826                         &rom_ver2_val);
7827         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7828         bnx2x_cl45_write(bp, phy,
7829                          MDIO_PMA_DEVAD,
7830                          MDIO_PMA_REG_ROM_VER2,
7831                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7832
7833         bnx2x_cl45_write(bp, phy,
7834                          MDIO_PMA_DEVAD,
7835                          MDIO_PMA_REG_PHY_IDENTIFIER,
7836                          (phy_identifier | (1<<9)));
7837
7838         return 0;
7839 }
7840
7841 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7842                                      struct link_params *params,
7843                                      u32 action)
7844 {
7845         struct bnx2x *bp = params->bp;
7846
7847         switch (action) {
7848         case DISABLE_TX:
7849                 bnx2x_sfp_set_transmitter(params, phy, 0);
7850                 break;
7851         case ENABLE_TX:
7852                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7853                         bnx2x_sfp_set_transmitter(params, phy, 1);
7854                 break;
7855         default:
7856                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7857                    action);
7858                 return;
7859         }
7860 }
7861
7862 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7863                                            u8 gpio_mode)
7864 {
7865         struct bnx2x *bp = params->bp;
7866
7867         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7868                             offsetof(struct shmem_region,
7869                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
7870                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7871         switch (fault_led_gpio) {
7872         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7873                 return;
7874         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7875         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7876         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7877         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7878         {
7879                 u8 gpio_port = bnx2x_get_gpio_port(params);
7880                 u16 gpio_pin = fault_led_gpio -
7881                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7882                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7883                                    "pin %x port %x mode %x\n",
7884                                gpio_pin, gpio_port, gpio_mode);
7885                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7886         }
7887         break;
7888         default:
7889                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7890                                fault_led_gpio);
7891         }
7892 }
7893
7894 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7895                                           u8 gpio_mode)
7896 {
7897         u32 pin_cfg;
7898         u8 port = params->port;
7899         struct bnx2x *bp = params->bp;
7900         pin_cfg = (REG_RD(bp, params->shmem_base +
7901                          offsetof(struct shmem_region,
7902                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7903                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7904                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7905         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7906                        gpio_mode, pin_cfg);
7907         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7908 }
7909
7910 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7911                                            u8 gpio_mode)
7912 {
7913         struct bnx2x *bp = params->bp;
7914         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7915         if (CHIP_IS_E3(bp)) {
7916                 /*
7917                  * Low ==> if SFP+ module is supported otherwise
7918                  * High ==> if SFP+ module is not on the approved vendor list
7919                  */
7920                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7921         } else
7922                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7923 }
7924
7925 static void bnx2x_warpcore_power_module(struct link_params *params,
7926                                         struct bnx2x_phy *phy,
7927                                         u8 power)
7928 {
7929         u32 pin_cfg;
7930         struct bnx2x *bp = params->bp;
7931
7932         pin_cfg = (REG_RD(bp, params->shmem_base +
7933                           offsetof(struct shmem_region,
7934                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7935                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7936                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7937
7938         if (pin_cfg == PIN_CFG_NA)
7939                 return;
7940         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7941                        power, pin_cfg);
7942         /*
7943          * Low ==> corresponding SFP+ module is powered
7944          * high ==> the SFP+ module is powered down
7945          */
7946         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7947 }
7948
7949 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7950                                     struct link_params *params)
7951 {
7952         bnx2x_warpcore_power_module(params, phy, 0);
7953 }
7954
7955 static void bnx2x_power_sfp_module(struct link_params *params,
7956                                    struct bnx2x_phy *phy,
7957                                    u8 power)
7958 {
7959         struct bnx2x *bp = params->bp;
7960         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7961
7962         switch (phy->type) {
7963         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7964         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7965                 bnx2x_8727_power_module(params->bp, phy, power);
7966                 break;
7967         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7968                 bnx2x_warpcore_power_module(params, phy, power);
7969                 break;
7970         default:
7971                 break;
7972         }
7973 }
7974 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7975                                              struct bnx2x_phy *phy,
7976                                              u16 edc_mode)
7977 {
7978         u16 val = 0;
7979         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7980         struct bnx2x *bp = params->bp;
7981
7982         u8 lane = bnx2x_get_warpcore_lane(phy, params);
7983         /* This is a global register which controls all lanes */
7984         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7985                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7986         val &= ~(0xf << (lane << 2));
7987
7988         switch (edc_mode) {
7989         case EDC_MODE_LINEAR:
7990         case EDC_MODE_LIMITING:
7991                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7992                 break;
7993         case EDC_MODE_PASSIVE_DAC:
7994                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
7995                 break;
7996         default:
7997                 break;
7998         }
7999
8000         val |= (mode << (lane << 2));
8001         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8002                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8003         /* A must read */
8004         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8005                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8006
8007
8008 }
8009
8010 static void bnx2x_set_limiting_mode(struct link_params *params,
8011                                     struct bnx2x_phy *phy,
8012                                     u16 edc_mode)
8013 {
8014         switch (phy->type) {
8015         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8016                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8017                 break;
8018         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8019         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8020                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8021                 break;
8022         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8023                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8024                 break;
8025         }
8026 }
8027
8028 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8029                                struct link_params *params)
8030 {
8031         struct bnx2x *bp = params->bp;
8032         u16 edc_mode;
8033         int rc = 0;
8034
8035         u32 val = REG_RD(bp, params->shmem_base +
8036                              offsetof(struct shmem_region, dev_info.
8037                                      port_feature_config[params->port].config));
8038
8039         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8040                  params->port);
8041         /* Power up module */
8042         bnx2x_power_sfp_module(params, phy, 1);
8043         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8044                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8045                 return -EINVAL;
8046         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8047                 /* check SFP+ module compatibility */
8048                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8049                 rc = -EINVAL;
8050                 /* Turn on fault module-detected led */
8051                 bnx2x_set_sfp_module_fault_led(params,
8052                                                MISC_REGISTERS_GPIO_HIGH);
8053
8054                 /* Check if need to power down the SFP+ module */
8055                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8056                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8057                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8058                         bnx2x_power_sfp_module(params, phy, 0);
8059                         return rc;
8060                 }
8061         } else {
8062                 /* Turn off fault module-detected led */
8063                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8064         }
8065
8066         /*
8067          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8068          * is done automatically
8069          */
8070         bnx2x_set_limiting_mode(params, phy, edc_mode);
8071
8072         /*
8073          * Enable transmit for this module if the module is approved, or
8074          * if unapproved modules should also enable the Tx laser
8075          */
8076         if (rc == 0 ||
8077             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8078             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8079                 bnx2x_sfp_set_transmitter(params, phy, 1);
8080         else
8081                 bnx2x_sfp_set_transmitter(params, phy, 0);
8082
8083         return rc;
8084 }
8085
8086 void bnx2x_handle_module_detect_int(struct link_params *params)
8087 {
8088         struct bnx2x *bp = params->bp;
8089         struct bnx2x_phy *phy;
8090         u32 gpio_val;
8091         u8 gpio_num, gpio_port;
8092         if (CHIP_IS_E3(bp))
8093                 phy = &params->phy[INT_PHY];
8094         else
8095                 phy = &params->phy[EXT_PHY1];
8096
8097         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8098                                       params->port, &gpio_num, &gpio_port) ==
8099             -EINVAL) {
8100                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8101                 return;
8102         }
8103
8104         /* Set valid module led off */
8105         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8106
8107         /* Get current gpio val reflecting module plugged in / out*/
8108         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8109
8110         /* Call the handling function in case module is detected */
8111         if (gpio_val == 0) {
8112                 bnx2x_power_sfp_module(params, phy, 1);
8113                 bnx2x_set_gpio_int(bp, gpio_num,
8114                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8115                                    gpio_port);
8116                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8117                         bnx2x_sfp_module_detection(phy, params);
8118                 else
8119                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8120         } else {
8121                 u32 val = REG_RD(bp, params->shmem_base +
8122                                  offsetof(struct shmem_region, dev_info.
8123                                           port_feature_config[params->port].
8124                                           config));
8125
8126                 bnx2x_set_gpio_int(bp, gpio_num,
8127                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8128                                    gpio_port);
8129                 /*
8130                  * Module was plugged out.
8131                  * Disable transmit for this module
8132                  */
8133                 phy->media_type = ETH_PHY_NOT_PRESENT;
8134                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8135                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8136                         bnx2x_sfp_set_transmitter(params, phy, 0);
8137         }
8138 }
8139
8140 /******************************************************************/
8141 /*              Used by 8706 and 8727                             */
8142 /******************************************************************/
8143 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8144                                  struct bnx2x_phy *phy,
8145                                  u16 alarm_status_offset,
8146                                  u16 alarm_ctrl_offset)
8147 {
8148         u16 alarm_status, val;
8149         bnx2x_cl45_read(bp, phy,
8150                         MDIO_PMA_DEVAD, alarm_status_offset,
8151                         &alarm_status);
8152         bnx2x_cl45_read(bp, phy,
8153                         MDIO_PMA_DEVAD, alarm_status_offset,
8154                         &alarm_status);
8155         /* Mask or enable the fault event. */
8156         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8157         if (alarm_status & (1<<0))
8158                 val &= ~(1<<0);
8159         else
8160                 val |= (1<<0);
8161         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8162 }
8163 /******************************************************************/
8164 /*              common BCM8706/BCM8726 PHY SECTION                */
8165 /******************************************************************/
8166 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8167                                       struct link_params *params,
8168                                       struct link_vars *vars)
8169 {
8170         u8 link_up = 0;
8171         u16 val1, val2, rx_sd, pcs_status;
8172         struct bnx2x *bp = params->bp;
8173         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8174         /* Clear RX Alarm*/
8175         bnx2x_cl45_read(bp, phy,
8176                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8177
8178         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8179                              MDIO_PMA_LASI_TXCTRL);
8180
8181         /* clear LASI indication*/
8182         bnx2x_cl45_read(bp, phy,
8183                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8184         bnx2x_cl45_read(bp, phy,
8185                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8186         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8187
8188         bnx2x_cl45_read(bp, phy,
8189                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8190         bnx2x_cl45_read(bp, phy,
8191                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8192         bnx2x_cl45_read(bp, phy,
8193                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8194         bnx2x_cl45_read(bp, phy,
8195                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8196
8197         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8198                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8199         /*
8200          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8201          * are set, or if the autoneg bit 1 is set
8202          */
8203         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8204         if (link_up) {
8205                 if (val2 & (1<<1))
8206                         vars->line_speed = SPEED_1000;
8207                 else
8208                         vars->line_speed = SPEED_10000;
8209                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8210                 vars->duplex = DUPLEX_FULL;
8211         }
8212
8213         /* Capture 10G link fault. Read twice to clear stale value. */
8214         if (vars->line_speed == SPEED_10000) {
8215                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8216                             MDIO_PMA_LASI_TXSTAT, &val1);
8217                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8218                             MDIO_PMA_LASI_TXSTAT, &val1);
8219                 if (val1 & (1<<0))
8220                         vars->fault_detected = 1;
8221         }
8222
8223         return link_up;
8224 }
8225
8226 /******************************************************************/
8227 /*                      BCM8706 PHY SECTION                       */
8228 /******************************************************************/
8229 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8230                                  struct link_params *params,
8231                                  struct link_vars *vars)
8232 {
8233         u32 tx_en_mode;
8234         u16 cnt, val, tmp1;
8235         struct bnx2x *bp = params->bp;
8236
8237         /* SPF+ PHY: Set flag to check for Tx error */
8238         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8239
8240         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8241                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8242         /* HW reset */
8243         bnx2x_ext_phy_hw_reset(bp, params->port);
8244         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8245         bnx2x_wait_reset_complete(bp, phy, params);
8246
8247         /* Wait until fw is loaded */
8248         for (cnt = 0; cnt < 100; cnt++) {
8249                 bnx2x_cl45_read(bp, phy,
8250                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8251                 if (val)
8252                         break;
8253                 msleep(10);
8254         }
8255         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8256         if ((params->feature_config_flags &
8257              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8258                 u8 i;
8259                 u16 reg;
8260                 for (i = 0; i < 4; i++) {
8261                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8262                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8263                                    MDIO_XS_8706_REG_BANK_RX0);
8264                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8265                         /* Clear first 3 bits of the control */
8266                         val &= ~0x7;
8267                         /* Set control bits according to configuration */
8268                         val |= (phy->rx_preemphasis[i] & 0x7);
8269                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8270                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8271                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8272                 }
8273         }
8274         /* Force speed */
8275         if (phy->req_line_speed == SPEED_10000) {
8276                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8277
8278                 bnx2x_cl45_write(bp, phy,
8279                                  MDIO_PMA_DEVAD,
8280                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8281                 bnx2x_cl45_write(bp, phy,
8282                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8283                                  0);
8284                 /* Arm LASI for link and Tx fault. */
8285                 bnx2x_cl45_write(bp, phy,
8286                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8287         } else {
8288                 /* Force 1Gbps using autoneg with 1G advertisement */
8289
8290                 /* Allow CL37 through CL73 */
8291                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8292                 bnx2x_cl45_write(bp, phy,
8293                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8294
8295                 /* Enable Full-Duplex advertisement on CL37 */
8296                 bnx2x_cl45_write(bp, phy,
8297                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8298                 /* Enable CL37 AN */
8299                 bnx2x_cl45_write(bp, phy,
8300                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8301                 /* 1G support */
8302                 bnx2x_cl45_write(bp, phy,
8303                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8304
8305                 /* Enable clause 73 AN */
8306                 bnx2x_cl45_write(bp, phy,
8307                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8308                 bnx2x_cl45_write(bp, phy,
8309                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8310                                  0x0400);
8311                 bnx2x_cl45_write(bp, phy,
8312                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8313                                  0x0004);
8314         }
8315         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8316
8317         /*
8318          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8319          * power mode, if TX Laser is disabled
8320          */
8321
8322         tx_en_mode = REG_RD(bp, params->shmem_base +
8323                             offsetof(struct shmem_region,
8324                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8325                         & PORT_HW_CFG_TX_LASER_MASK;
8326
8327         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8328                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8329                 bnx2x_cl45_read(bp, phy,
8330                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8331                 tmp1 |= 0x1;
8332                 bnx2x_cl45_write(bp, phy,
8333                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8334         }
8335
8336         return 0;
8337 }
8338
8339 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8340                                   struct link_params *params,
8341                                   struct link_vars *vars)
8342 {
8343         return bnx2x_8706_8726_read_status(phy, params, vars);
8344 }
8345
8346 /******************************************************************/
8347 /*                      BCM8726 PHY SECTION                       */
8348 /******************************************************************/
8349 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8350                                        struct link_params *params)
8351 {
8352         struct bnx2x *bp = params->bp;
8353         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8354         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8355 }
8356
8357 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8358                                          struct link_params *params)
8359 {
8360         struct bnx2x *bp = params->bp;
8361         /* Need to wait 100ms after reset */
8362         msleep(100);
8363
8364         /* Micro controller re-boot */
8365         bnx2x_cl45_write(bp, phy,
8366                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8367
8368         /* Set soft reset */
8369         bnx2x_cl45_write(bp, phy,
8370                          MDIO_PMA_DEVAD,
8371                          MDIO_PMA_REG_GEN_CTRL,
8372                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8373
8374         bnx2x_cl45_write(bp, phy,
8375                          MDIO_PMA_DEVAD,
8376                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8377
8378         bnx2x_cl45_write(bp, phy,
8379                          MDIO_PMA_DEVAD,
8380                          MDIO_PMA_REG_GEN_CTRL,
8381                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8382
8383         /* wait for 150ms for microcode load */
8384         msleep(150);
8385
8386         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8387         bnx2x_cl45_write(bp, phy,
8388                          MDIO_PMA_DEVAD,
8389                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8390
8391         msleep(200);
8392         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8393 }
8394
8395 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8396                                  struct link_params *params,
8397                                  struct link_vars *vars)
8398 {
8399         struct bnx2x *bp = params->bp;
8400         u16 val1;
8401         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8402         if (link_up) {
8403                 bnx2x_cl45_read(bp, phy,
8404                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8405                                 &val1);
8406                 if (val1 & (1<<15)) {
8407                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8408                         link_up = 0;
8409                         vars->line_speed = 0;
8410                 }
8411         }
8412         return link_up;
8413 }
8414
8415
8416 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8417                                   struct link_params *params,
8418                                   struct link_vars *vars)
8419 {
8420         struct bnx2x *bp = params->bp;
8421         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8422
8423         /* SPF+ PHY: Set flag to check for Tx error */
8424         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8425
8426         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8427         bnx2x_wait_reset_complete(bp, phy, params);
8428
8429         bnx2x_8726_external_rom_boot(phy, params);
8430
8431         /*
8432          * Need to call module detected on initialization since the module
8433          * detection triggered by actual module insertion might occur before
8434          * driver is loaded, and when driver is loaded, it reset all
8435          * registers, including the transmitter
8436          */
8437         bnx2x_sfp_module_detection(phy, params);
8438
8439         if (phy->req_line_speed == SPEED_1000) {
8440                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8441                 bnx2x_cl45_write(bp, phy,
8442                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8443                 bnx2x_cl45_write(bp, phy,
8444                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8445                 bnx2x_cl45_write(bp, phy,
8446                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8447                 bnx2x_cl45_write(bp, phy,
8448                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8449                                  0x400);
8450         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8451                    (phy->speed_cap_mask &
8452                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8453                    ((phy->speed_cap_mask &
8454                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8455                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8456                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8457                 /* Set Flow control */
8458                 bnx2x_ext_phy_set_pause(params, phy, vars);
8459                 bnx2x_cl45_write(bp, phy,
8460                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8461                 bnx2x_cl45_write(bp, phy,
8462                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8463                 bnx2x_cl45_write(bp, phy,
8464                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8465                 bnx2x_cl45_write(bp, phy,
8466                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8467                 bnx2x_cl45_write(bp, phy,
8468                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8469                 /*
8470                  * Enable RX-ALARM control to receive interrupt for 1G speed
8471                  * change
8472                  */
8473                 bnx2x_cl45_write(bp, phy,
8474                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8475                 bnx2x_cl45_write(bp, phy,
8476                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8477                                  0x400);
8478
8479         } else { /* Default 10G. Set only LASI control */
8480                 bnx2x_cl45_write(bp, phy,
8481                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8482         }
8483
8484         /* Set TX PreEmphasis if needed */
8485         if ((params->feature_config_flags &
8486              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8487                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8488                          "TX_CTRL2 0x%x\n",
8489                          phy->tx_preemphasis[0],
8490                          phy->tx_preemphasis[1]);
8491                 bnx2x_cl45_write(bp, phy,
8492                                  MDIO_PMA_DEVAD,
8493                                  MDIO_PMA_REG_8726_TX_CTRL1,
8494                                  phy->tx_preemphasis[0]);
8495
8496                 bnx2x_cl45_write(bp, phy,
8497                                  MDIO_PMA_DEVAD,
8498                                  MDIO_PMA_REG_8726_TX_CTRL2,
8499                                  phy->tx_preemphasis[1]);
8500         }
8501
8502         return 0;
8503
8504 }
8505
8506 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8507                                   struct link_params *params)
8508 {
8509         struct bnx2x *bp = params->bp;
8510         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8511         /* Set serial boot control for external load */
8512         bnx2x_cl45_write(bp, phy,
8513                          MDIO_PMA_DEVAD,
8514                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8515 }
8516
8517 /******************************************************************/
8518 /*                      BCM8727 PHY SECTION                       */
8519 /******************************************************************/
8520
8521 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8522                                     struct link_params *params, u8 mode)
8523 {
8524         struct bnx2x *bp = params->bp;
8525         u16 led_mode_bitmask = 0;
8526         u16 gpio_pins_bitmask = 0;
8527         u16 val;
8528         /* Only NOC flavor requires to set the LED specifically */
8529         if (!(phy->flags & FLAGS_NOC))
8530                 return;
8531         switch (mode) {
8532         case LED_MODE_FRONT_PANEL_OFF:
8533         case LED_MODE_OFF:
8534                 led_mode_bitmask = 0;
8535                 gpio_pins_bitmask = 0x03;
8536                 break;
8537         case LED_MODE_ON:
8538                 led_mode_bitmask = 0;
8539                 gpio_pins_bitmask = 0x02;
8540                 break;
8541         case LED_MODE_OPER:
8542                 led_mode_bitmask = 0x60;
8543                 gpio_pins_bitmask = 0x11;
8544                 break;
8545         }
8546         bnx2x_cl45_read(bp, phy,
8547                         MDIO_PMA_DEVAD,
8548                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8549                         &val);
8550         val &= 0xff8f;
8551         val |= led_mode_bitmask;
8552         bnx2x_cl45_write(bp, phy,
8553                          MDIO_PMA_DEVAD,
8554                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8555                          val);
8556         bnx2x_cl45_read(bp, phy,
8557                         MDIO_PMA_DEVAD,
8558                         MDIO_PMA_REG_8727_GPIO_CTRL,
8559                         &val);
8560         val &= 0xffe0;
8561         val |= gpio_pins_bitmask;
8562         bnx2x_cl45_write(bp, phy,
8563                          MDIO_PMA_DEVAD,
8564                          MDIO_PMA_REG_8727_GPIO_CTRL,
8565                          val);
8566 }
8567 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8568                                 struct link_params *params) {
8569         u32 swap_val, swap_override;
8570         u8 port;
8571         /*
8572          * The PHY reset is controlled by GPIO 1. Fake the port number
8573          * to cancel the swap done in set_gpio()
8574          */
8575         struct bnx2x *bp = params->bp;
8576         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8577         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8578         port = (swap_val && swap_override) ^ 1;
8579         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8580                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8581 }
8582
8583 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8584                                   struct link_params *params,
8585                                   struct link_vars *vars)
8586 {
8587         u32 tx_en_mode;
8588         u16 tmp1, val, mod_abs, tmp2;
8589         u16 rx_alarm_ctrl_val;
8590         u16 lasi_ctrl_val;
8591         struct bnx2x *bp = params->bp;
8592         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8593
8594         /* SPF+ PHY: Set flag to check for Tx error */
8595         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8596
8597         bnx2x_wait_reset_complete(bp, phy, params);
8598         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8599         /* Should be 0x6 to enable XS on Tx side. */
8600         lasi_ctrl_val = 0x0006;
8601
8602         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8603         /* enable LASI */
8604         bnx2x_cl45_write(bp, phy,
8605                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8606                          rx_alarm_ctrl_val);
8607         bnx2x_cl45_write(bp, phy,
8608                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8609                          0);
8610         bnx2x_cl45_write(bp, phy,
8611                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8612
8613         /*
8614          * Initially configure MOD_ABS to interrupt when module is
8615          * presence( bit 8)
8616          */
8617         bnx2x_cl45_read(bp, phy,
8618                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8619         /*
8620          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8621          * When the EDC is off it locks onto a reference clock and avoids
8622          * becoming 'lost'
8623          */
8624         mod_abs &= ~(1<<8);
8625         if (!(phy->flags & FLAGS_NOC))
8626                 mod_abs &= ~(1<<9);
8627         bnx2x_cl45_write(bp, phy,
8628                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8629
8630
8631         /* Enable/Disable PHY transmitter output */
8632         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8633
8634         /* Make MOD_ABS give interrupt on change */
8635         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8636                         &val);
8637         val |= (1<<12);
8638         if (phy->flags & FLAGS_NOC)
8639                 val |= (3<<5);
8640
8641         /*
8642          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8643          * status which reflect SFP+ module over-current
8644          */
8645         if (!(phy->flags & FLAGS_NOC))
8646                 val &= 0xff8f; /* Reset bits 4-6 */
8647         bnx2x_cl45_write(bp, phy,
8648                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8649
8650         bnx2x_8727_power_module(bp, phy, 1);
8651
8652         bnx2x_cl45_read(bp, phy,
8653                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8654
8655         bnx2x_cl45_read(bp, phy,
8656                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8657
8658         /* Set option 1G speed */
8659         if (phy->req_line_speed == SPEED_1000) {
8660                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8661                 bnx2x_cl45_write(bp, phy,
8662                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8663                 bnx2x_cl45_write(bp, phy,
8664                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8665                 bnx2x_cl45_read(bp, phy,
8666                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8667                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8668                 /*
8669                  * Power down the XAUI until link is up in case of dual-media
8670                  * and 1G
8671                  */
8672                 if (DUAL_MEDIA(params)) {
8673                         bnx2x_cl45_read(bp, phy,
8674                                         MDIO_PMA_DEVAD,
8675                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8676                         val |= (3<<10);
8677                         bnx2x_cl45_write(bp, phy,
8678                                          MDIO_PMA_DEVAD,
8679                                          MDIO_PMA_REG_8727_PCS_GP, val);
8680                 }
8681         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8682                    ((phy->speed_cap_mask &
8683                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8684                    ((phy->speed_cap_mask &
8685                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8686                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8687
8688                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8689                 bnx2x_cl45_write(bp, phy,
8690                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8691                 bnx2x_cl45_write(bp, phy,
8692                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8693         } else {
8694                 /*
8695                  * Since the 8727 has only single reset pin, need to set the 10G
8696                  * registers although it is default
8697                  */
8698                 bnx2x_cl45_write(bp, phy,
8699                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8700                                  0x0020);
8701                 bnx2x_cl45_write(bp, phy,
8702                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8703                 bnx2x_cl45_write(bp, phy,
8704                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8705                 bnx2x_cl45_write(bp, phy,
8706                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8707                                  0x0008);
8708         }
8709
8710         /*
8711          * Set 2-wire transfer rate of SFP+ module EEPROM
8712          * to 100Khz since some DACs(direct attached cables) do
8713          * not work at 400Khz.
8714          */
8715         bnx2x_cl45_write(bp, phy,
8716                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8717                          0xa001);
8718
8719         /* Set TX PreEmphasis if needed */
8720         if ((params->feature_config_flags &
8721              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8722                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8723                            phy->tx_preemphasis[0],
8724                            phy->tx_preemphasis[1]);
8725                 bnx2x_cl45_write(bp, phy,
8726                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8727                                  phy->tx_preemphasis[0]);
8728
8729                 bnx2x_cl45_write(bp, phy,
8730                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8731                                  phy->tx_preemphasis[1]);
8732         }
8733
8734         /*
8735          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8736          * power mode, if TX Laser is disabled
8737          */
8738         tx_en_mode = REG_RD(bp, params->shmem_base +
8739                             offsetof(struct shmem_region,
8740                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8741                         & PORT_HW_CFG_TX_LASER_MASK;
8742
8743         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8744
8745                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8746                 bnx2x_cl45_read(bp, phy,
8747                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8748                 tmp2 |= 0x1000;
8749                 tmp2 &= 0xFFEF;
8750                 bnx2x_cl45_write(bp, phy,
8751                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8752         }
8753
8754         return 0;
8755 }
8756
8757 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8758                                       struct link_params *params)
8759 {
8760         struct bnx2x *bp = params->bp;
8761         u16 mod_abs, rx_alarm_status;
8762         u32 val = REG_RD(bp, params->shmem_base +
8763                              offsetof(struct shmem_region, dev_info.
8764                                       port_feature_config[params->port].
8765                                       config));
8766         bnx2x_cl45_read(bp, phy,
8767                         MDIO_PMA_DEVAD,
8768                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8769         if (mod_abs & (1<<8)) {
8770
8771                 /* Module is absent */
8772                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8773                             "show module is absent\n");
8774                 phy->media_type = ETH_PHY_NOT_PRESENT;
8775                 /*
8776                  * 1. Set mod_abs to detect next module
8777                  *    presence event
8778                  * 2. Set EDC off by setting OPTXLOS signal input to low
8779                  *    (bit 9).
8780                  *    When the EDC is off it locks onto a reference clock and
8781                  *    avoids becoming 'lost'.
8782                  */
8783                 mod_abs &= ~(1<<8);
8784                 if (!(phy->flags & FLAGS_NOC))
8785                         mod_abs &= ~(1<<9);
8786                 bnx2x_cl45_write(bp, phy,
8787                                  MDIO_PMA_DEVAD,
8788                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8789
8790                 /*
8791                  * Clear RX alarm since it stays up as long as
8792                  * the mod_abs wasn't changed
8793                  */
8794                 bnx2x_cl45_read(bp, phy,
8795                                 MDIO_PMA_DEVAD,
8796                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8797
8798         } else {
8799                 /* Module is present */
8800                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8801                             "show module is present\n");
8802                 /*
8803                  * First disable transmitter, and if the module is ok, the
8804                  * module_detection will enable it
8805                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8806                  * 2. Restore the default polarity of the OPRXLOS signal and
8807                  * this signal will then correctly indicate the presence or
8808                  * absence of the Rx signal. (bit 9)
8809                  */
8810                 mod_abs |= (1<<8);
8811                 if (!(phy->flags & FLAGS_NOC))
8812                         mod_abs |= (1<<9);
8813                 bnx2x_cl45_write(bp, phy,
8814                                  MDIO_PMA_DEVAD,
8815                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8816
8817                 /*
8818                  * Clear RX alarm since it stays up as long as the mod_abs
8819                  * wasn't changed. This is need to be done before calling the
8820                  * module detection, otherwise it will clear* the link update
8821                  * alarm
8822                  */
8823                 bnx2x_cl45_read(bp, phy,
8824                                 MDIO_PMA_DEVAD,
8825                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8826
8827
8828                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8829                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8830                         bnx2x_sfp_set_transmitter(params, phy, 0);
8831
8832                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8833                         bnx2x_sfp_module_detection(phy, params);
8834                 else
8835                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8836         }
8837
8838         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8839                    rx_alarm_status);
8840         /* No need to check link status in case of module plugged in/out */
8841 }
8842
8843 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8844                                  struct link_params *params,
8845                                  struct link_vars *vars)
8846
8847 {
8848         struct bnx2x *bp = params->bp;
8849         u8 link_up = 0, oc_port = params->port;
8850         u16 link_status = 0;
8851         u16 rx_alarm_status, lasi_ctrl, val1;
8852
8853         /* If PHY is not initialized, do not check link status */
8854         bnx2x_cl45_read(bp, phy,
8855                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8856                         &lasi_ctrl);
8857         if (!lasi_ctrl)
8858                 return 0;
8859
8860         /* Check the LASI on Rx */
8861         bnx2x_cl45_read(bp, phy,
8862                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8863                         &rx_alarm_status);
8864         vars->line_speed = 0;
8865         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8866
8867         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8868                              MDIO_PMA_LASI_TXCTRL);
8869
8870         bnx2x_cl45_read(bp, phy,
8871                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8872
8873         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8874
8875         /* Clear MSG-OUT */
8876         bnx2x_cl45_read(bp, phy,
8877                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8878
8879         /*
8880          * If a module is present and there is need to check
8881          * for over current
8882          */
8883         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8884                 /* Check over-current using 8727 GPIO0 input*/
8885                 bnx2x_cl45_read(bp, phy,
8886                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8887                                 &val1);
8888
8889                 if ((val1 & (1<<8)) == 0) {
8890                         if (!CHIP_IS_E1x(bp))
8891                                 oc_port = BP_PATH(bp) + (params->port << 1);
8892                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8893                                        " on port %d\n", oc_port);
8894                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
8895                                             " been detected and the power to "
8896                                             "that SFP+ module has been removed"
8897                                             " to prevent failure of the card."
8898                                             " Please remove the SFP+ module and"
8899                                             " restart the system to clear this"
8900                                             " error.\n",
8901                          oc_port);
8902                         /* Disable all RX_ALARMs except for mod_abs */
8903                         bnx2x_cl45_write(bp, phy,
8904                                          MDIO_PMA_DEVAD,
8905                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
8906
8907                         bnx2x_cl45_read(bp, phy,
8908                                         MDIO_PMA_DEVAD,
8909                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8910                         /* Wait for module_absent_event */
8911                         val1 |= (1<<8);
8912                         bnx2x_cl45_write(bp, phy,
8913                                          MDIO_PMA_DEVAD,
8914                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8915                         /* Clear RX alarm */
8916                         bnx2x_cl45_read(bp, phy,
8917                                 MDIO_PMA_DEVAD,
8918                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8919                         return 0;
8920                 }
8921         } /* Over current check */
8922
8923         /* When module absent bit is set, check module */
8924         if (rx_alarm_status & (1<<5)) {
8925                 bnx2x_8727_handle_mod_abs(phy, params);
8926                 /* Enable all mod_abs and link detection bits */
8927                 bnx2x_cl45_write(bp, phy,
8928                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8929                                  ((1<<5) | (1<<2)));
8930         }
8931         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8932         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8933         /* If transmitter is disabled, ignore false link up indication */
8934         bnx2x_cl45_read(bp, phy,
8935                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8936         if (val1 & (1<<15)) {
8937                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8938                 return 0;
8939         }
8940
8941         bnx2x_cl45_read(bp, phy,
8942                         MDIO_PMA_DEVAD,
8943                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8944
8945         /*
8946          * Bits 0..2 --> speed detected,
8947          * Bits 13..15--> link is down
8948          */
8949         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8950                 link_up = 1;
8951                 vars->line_speed = SPEED_10000;
8952                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8953                            params->port);
8954         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8955                 link_up = 1;
8956                 vars->line_speed = SPEED_1000;
8957                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8958                            params->port);
8959         } else {
8960                 link_up = 0;
8961                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8962                            params->port);
8963         }
8964
8965         /* Capture 10G link fault. */
8966         if (vars->line_speed == SPEED_10000) {
8967                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8968                             MDIO_PMA_LASI_TXSTAT, &val1);
8969
8970                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8971                             MDIO_PMA_LASI_TXSTAT, &val1);
8972
8973                 if (val1 & (1<<0)) {
8974                         vars->fault_detected = 1;
8975                 }
8976         }
8977
8978         if (link_up) {
8979                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8980                 vars->duplex = DUPLEX_FULL;
8981                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8982         }
8983
8984         if ((DUAL_MEDIA(params)) &&
8985             (phy->req_line_speed == SPEED_1000)) {
8986                 bnx2x_cl45_read(bp, phy,
8987                                 MDIO_PMA_DEVAD,
8988                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
8989                 /*
8990                  * In case of dual-media board and 1G, power up the XAUI side,
8991                  * otherwise power it down. For 10G it is done automatically
8992                  */
8993                 if (link_up)
8994                         val1 &= ~(3<<10);
8995                 else
8996                         val1 |= (3<<10);
8997                 bnx2x_cl45_write(bp, phy,
8998                                  MDIO_PMA_DEVAD,
8999                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9000         }
9001         return link_up;
9002 }
9003
9004 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9005                                   struct link_params *params)
9006 {
9007         struct bnx2x *bp = params->bp;
9008
9009         /* Enable/Disable PHY transmitter output */
9010         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9011
9012         /* Disable Transmitter */
9013         bnx2x_sfp_set_transmitter(params, phy, 0);
9014         /* Clear LASI */
9015         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9016
9017 }
9018
9019 /******************************************************************/
9020 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9021 /******************************************************************/
9022 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9023                                            struct link_params *params)
9024 {
9025         u16 val, fw_ver1, fw_ver2, cnt;
9026         u8 port;
9027         struct bnx2x *bp = params->bp;
9028
9029         port = params->port;
9030
9031         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9032         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9033         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9034         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9035         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9036         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9037         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9038
9039         for (cnt = 0; cnt < 100; cnt++) {
9040                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9041                 if (val & 1)
9042                         break;
9043                 udelay(5);
9044         }
9045         if (cnt == 100) {
9046                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9047                 bnx2x_save_spirom_version(bp, port, 0,
9048                                           phy->ver_addr);
9049                 return;
9050         }
9051
9052
9053         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9054         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9055         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9056         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9057         for (cnt = 0; cnt < 100; cnt++) {
9058                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9059                 if (val & 1)
9060                         break;
9061                 udelay(5);
9062         }
9063         if (cnt == 100) {
9064                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9065                 bnx2x_save_spirom_version(bp, port, 0,
9066                                           phy->ver_addr);
9067                 return;
9068         }
9069
9070         /* lower 16 bits of the register SPI_FW_STATUS */
9071         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9072         /* upper 16 bits of register SPI_FW_STATUS */
9073         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9074
9075         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9076                                   phy->ver_addr);
9077 }
9078
9079 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9080                                 struct bnx2x_phy *phy)
9081 {
9082         u16 val;
9083
9084         /* PHYC_CTL_LED_CTL */
9085         bnx2x_cl45_read(bp, phy,
9086                         MDIO_PMA_DEVAD,
9087                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9088         val &= 0xFE00;
9089         val |= 0x0092;
9090
9091         bnx2x_cl45_write(bp, phy,
9092                          MDIO_PMA_DEVAD,
9093                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9094
9095         bnx2x_cl45_write(bp, phy,
9096                          MDIO_PMA_DEVAD,
9097                          MDIO_PMA_REG_8481_LED1_MASK,
9098                          0x80);
9099
9100         bnx2x_cl45_write(bp, phy,
9101                          MDIO_PMA_DEVAD,
9102                          MDIO_PMA_REG_8481_LED2_MASK,
9103                          0x18);
9104
9105         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9106         bnx2x_cl45_write(bp, phy,
9107                          MDIO_PMA_DEVAD,
9108                          MDIO_PMA_REG_8481_LED3_MASK,
9109                          0x0006);
9110
9111         /* Select the closest activity blink rate to that in 10/100/1000 */
9112         bnx2x_cl45_write(bp, phy,
9113                         MDIO_PMA_DEVAD,
9114                         MDIO_PMA_REG_8481_LED3_BLINK,
9115                         0);
9116
9117         bnx2x_cl45_read(bp, phy,
9118                         MDIO_PMA_DEVAD,
9119                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9120         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9121
9122         bnx2x_cl45_write(bp, phy,
9123                          MDIO_PMA_DEVAD,
9124                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9125
9126         /* 'Interrupt Mask' */
9127         bnx2x_cl45_write(bp, phy,
9128                          MDIO_AN_DEVAD,
9129                          0xFFFB, 0xFFFD);
9130 }
9131
9132 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9133                                        struct link_params *params,
9134                                        struct link_vars *vars)
9135 {
9136         struct bnx2x *bp = params->bp;
9137         u16 autoneg_val, an_1000_val, an_10_100_val;
9138         u16 tmp_req_line_speed;
9139
9140         tmp_req_line_speed = phy->req_line_speed;
9141         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9142                 if (phy->req_line_speed == SPEED_10000)
9143                         phy->req_line_speed = SPEED_AUTO_NEG;
9144
9145         /*
9146          * This phy uses the NIG latch mechanism since link indication
9147          * arrives through its LED4 and not via its LASI signal, so we
9148          * get steady signal instead of clear on read
9149          */
9150         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9151                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9152
9153         bnx2x_cl45_write(bp, phy,
9154                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9155
9156         bnx2x_848xx_set_led(bp, phy);
9157
9158         /* set 1000 speed advertisement */
9159         bnx2x_cl45_read(bp, phy,
9160                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9161                         &an_1000_val);
9162
9163         bnx2x_ext_phy_set_pause(params, phy, vars);
9164         bnx2x_cl45_read(bp, phy,
9165                         MDIO_AN_DEVAD,
9166                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9167                         &an_10_100_val);
9168         bnx2x_cl45_read(bp, phy,
9169                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9170                         &autoneg_val);
9171         /* Disable forced speed */
9172         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9173         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9174
9175         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176              (phy->speed_cap_mask &
9177              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9178             (phy->req_line_speed == SPEED_1000)) {
9179                 an_1000_val |= (1<<8);
9180                 autoneg_val |= (1<<9 | 1<<12);
9181                 if (phy->req_duplex == DUPLEX_FULL)
9182                         an_1000_val |= (1<<9);
9183                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9184         } else
9185                 an_1000_val &= ~((1<<8) | (1<<9));
9186
9187         bnx2x_cl45_write(bp, phy,
9188                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9189                          an_1000_val);
9190
9191         /* set 100 speed advertisement */
9192         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9193              (phy->speed_cap_mask &
9194               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9195                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9196              (phy->supported &
9197               (SUPPORTED_100baseT_Half |
9198                SUPPORTED_100baseT_Full)))) {
9199                 an_10_100_val |= (1<<7);
9200                 /* Enable autoneg and restart autoneg for legacy speeds */
9201                 autoneg_val |= (1<<9 | 1<<12);
9202
9203                 if (phy->req_duplex == DUPLEX_FULL)
9204                         an_10_100_val |= (1<<8);
9205                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9206         }
9207         /* set 10 speed advertisement */
9208         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9209              (phy->speed_cap_mask &
9210               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9211                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9212              (phy->supported &
9213               (SUPPORTED_10baseT_Half |
9214                SUPPORTED_10baseT_Full)))) {
9215                 an_10_100_val |= (1<<5);
9216                 autoneg_val |= (1<<9 | 1<<12);
9217                 if (phy->req_duplex == DUPLEX_FULL)
9218                         an_10_100_val |= (1<<6);
9219                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9220         }
9221
9222         /* Only 10/100 are allowed to work in FORCE mode */
9223         if ((phy->req_line_speed == SPEED_100) &&
9224             (phy->supported &
9225              (SUPPORTED_100baseT_Half |
9226               SUPPORTED_100baseT_Full))) {
9227                 autoneg_val |= (1<<13);
9228                 /* Enabled AUTO-MDIX when autoneg is disabled */
9229                 bnx2x_cl45_write(bp, phy,
9230                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9231                                  (1<<15 | 1<<9 | 7<<0));
9232                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9233         }
9234         if ((phy->req_line_speed == SPEED_10) &&
9235             (phy->supported &
9236              (SUPPORTED_10baseT_Half |
9237               SUPPORTED_10baseT_Full))) {
9238                 /* Enabled AUTO-MDIX when autoneg is disabled */
9239                 bnx2x_cl45_write(bp, phy,
9240                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9241                                  (1<<15 | 1<<9 | 7<<0));
9242                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9243         }
9244
9245         bnx2x_cl45_write(bp, phy,
9246                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9247                          an_10_100_val);
9248
9249         if (phy->req_duplex == DUPLEX_FULL)
9250                 autoneg_val |= (1<<8);
9251
9252         bnx2x_cl45_write(bp, phy,
9253                          MDIO_AN_DEVAD,
9254                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9255
9256         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9257             (phy->speed_cap_mask &
9258              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9259                 (phy->req_line_speed == SPEED_10000)) {
9260                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9261                         /* Restart autoneg for 10G*/
9262
9263                         bnx2x_cl45_write(bp, phy,
9264                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9265                                  0x3200);
9266         } else if (phy->req_line_speed != SPEED_10 &&
9267                    phy->req_line_speed != SPEED_100) {
9268                 bnx2x_cl45_write(bp, phy,
9269                                  MDIO_AN_DEVAD,
9270                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9271                                  1);
9272         }
9273         /* Save spirom version */
9274         bnx2x_save_848xx_spirom_version(phy, params);
9275
9276         phy->req_line_speed = tmp_req_line_speed;
9277
9278         return 0;
9279 }
9280
9281 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9282                                   struct link_params *params,
9283                                   struct link_vars *vars)
9284 {
9285         struct bnx2x *bp = params->bp;
9286         /* Restore normal power mode*/
9287         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9288                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9289
9290         /* HW reset */
9291         bnx2x_ext_phy_hw_reset(bp, params->port);
9292         bnx2x_wait_reset_complete(bp, phy, params);
9293
9294         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9295         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9296 }
9297
9298
9299 #define PHY84833_HDSHK_WAIT 300
9300 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9301                                    struct link_params *params,
9302                                    struct link_vars *vars)
9303 {
9304         u32 idx;
9305         u32 pair_swap;
9306         u16 val;
9307         u16 data;
9308         struct bnx2x *bp = params->bp;
9309         /* Do pair swap */
9310
9311         /* Check for configuration. */
9312         pair_swap = REG_RD(bp, params->shmem_base +
9313                            offsetof(struct shmem_region,
9314                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9315                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9316
9317         if (pair_swap == 0)
9318                 return 0;
9319
9320         data = (u16)pair_swap;
9321
9322         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9323         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9324                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9325                         PHY84833_CMD_OPEN_OVERRIDE);
9326         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9327                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9328                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9329                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9330                         break;
9331                 msleep(1);
9332         }
9333         if (idx >= PHY84833_HDSHK_WAIT) {
9334                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9335                 return -EINVAL;
9336         }
9337
9338         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9339                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9340                         data);
9341         /* Issue pair swap command */
9342         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9343                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9344                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9345         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9346                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9347                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9348                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9349                         (val == PHY84833_CMD_COMPLETE_ERROR))
9350                         break;
9351                 msleep(1);
9352         }
9353         if ((idx >= PHY84833_HDSHK_WAIT) ||
9354                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9355                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9356                 return -EINVAL;
9357         }
9358         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9359                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9360                         PHY84833_CMD_CLEAR_COMPLETE);
9361         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9362         return 0;
9363 }
9364
9365
9366 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9367                                       u32 shmem_base_path[],
9368                                       u32 chip_id)
9369 {
9370         u32 reset_pin[2];
9371         u32 idx;
9372         u8 reset_gpios;
9373         if (CHIP_IS_E3(bp)) {
9374                 /* Assume that these will be GPIOs, not EPIOs. */
9375                 for (idx = 0; idx < 2; idx++) {
9376                         /* Map config param to register bit. */
9377                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9378                                 offsetof(struct shmem_region,
9379                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9380                         reset_pin[idx] = (reset_pin[idx] &
9381                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9382                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9383                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9384                         reset_pin[idx] = (1 << reset_pin[idx]);
9385                 }
9386                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9387         } else {
9388                 /* E2, look from diff place of shmem. */
9389                 for (idx = 0; idx < 2; idx++) {
9390                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9391                                 offsetof(struct shmem_region,
9392                                 dev_info.port_hw_config[0].default_cfg));
9393                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9394                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9395                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9396                         reset_pin[idx] = (1 << reset_pin[idx]);
9397                 }
9398                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9399         }
9400
9401         return reset_gpios;
9402 }
9403
9404 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9405                                 struct link_params *params)
9406 {
9407         struct bnx2x *bp = params->bp;
9408         u8 reset_gpios;
9409         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9410                                 offsetof(struct shmem2_region,
9411                                 other_shmem_base_addr));
9412
9413         u32 shmem_base_path[2];
9414         shmem_base_path[0] = params->shmem_base;
9415         shmem_base_path[1] = other_shmem_base_addr;
9416
9417         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9418                                                   params->chip_id);
9419
9420         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9421         udelay(10);
9422         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9423                 reset_gpios);
9424
9425         return 0;
9426 }
9427
9428 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9429                                                 u32 shmem_base_path[],
9430                                                 u32 chip_id)
9431 {
9432         u8 reset_gpios;
9433
9434         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9435
9436         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9437         udelay(10);
9438         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9439         msleep(800);
9440         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9441                 reset_gpios);
9442
9443         return 0;
9444 }
9445
9446 #define PHY84833_CONSTANT_LATENCY 1193
9447 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9448                                    struct link_params *params,
9449                                    struct link_vars *vars)
9450 {
9451         struct bnx2x *bp = params->bp;
9452         u8 port, initialize = 1;
9453         u16 val;
9454         u16 temp;
9455         u32 actual_phy_selection, cms_enable, idx;
9456         int rc = 0;
9457
9458         msleep(1);
9459
9460         if (!(CHIP_IS_E1(bp)))
9461                 port = BP_PATH(bp);
9462         else
9463                 port = params->port;
9464
9465         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9466                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9467                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9468                                port);
9469         } else {
9470                 /* MDIO reset */
9471                 bnx2x_cl45_write(bp, phy,
9472                                 MDIO_PMA_DEVAD,
9473                                 MDIO_PMA_REG_CTRL, 0x8000);
9474                 /* Bring PHY out of super isolate mode */
9475                 bnx2x_cl45_read(bp, phy,
9476                                 MDIO_CTL_DEVAD,
9477                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9478                 val &= ~MDIO_84833_SUPER_ISOLATE;
9479                 bnx2x_cl45_write(bp, phy,
9480                                 MDIO_CTL_DEVAD,
9481                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9482         }
9483
9484         bnx2x_wait_reset_complete(bp, phy, params);
9485
9486         /* Wait for GPHY to come out of reset */
9487         msleep(50);
9488
9489         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9490                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9491
9492         /*
9493          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9494          */
9495         temp = vars->line_speed;
9496         vars->line_speed = SPEED_10000;
9497         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9498         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9499         vars->line_speed = temp;
9500
9501         /* Set dual-media configuration according to configuration */
9502
9503         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9504                         MDIO_CTL_REG_84823_MEDIA, &val);
9505         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9506                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9507                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9508                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9509                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9510
9511         if (CHIP_IS_E3(bp)) {
9512                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9513                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9514         } else {
9515                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9516                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9517         }
9518
9519         actual_phy_selection = bnx2x_phy_selection(params);
9520
9521         switch (actual_phy_selection) {
9522         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9523                 /* Do nothing. Essentially this is like the priority copper */
9524                 break;
9525         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9526                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9527                 break;
9528         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9529                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9530                 break;
9531         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9532                 /* Do nothing here. The first PHY won't be initialized at all */
9533                 break;
9534         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9535                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9536                 initialize = 0;
9537                 break;
9538         }
9539         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9540                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9541
9542         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9543                          MDIO_CTL_REG_84823_MEDIA, val);
9544         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9545                    params->multi_phy_config, val);
9546
9547         /* AutogrEEEn */
9548         if (params->feature_config_flags &
9549                 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9550                 /* Ensure that f/w is ready */
9551                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9552                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9553                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9554                         if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9555                                 break;
9556                         usleep_range(1000, 1000);
9557                 }
9558                 if (idx >= PHY84833_HDSHK_WAIT) {
9559                         DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9560                         return -EINVAL;
9561                 }
9562
9563                 /* Select EEE mode */
9564                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9565                                 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9566                                 0x2);
9567
9568                 /* Set Idle and Latency */
9569                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9570                                 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9571                                 PHY84833_CONSTANT_LATENCY + 1);
9572
9573                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9574                                 MDIO_84833_TOP_CFG_DATA3_REG,
9575                                 PHY84833_CONSTANT_LATENCY + 1);
9576
9577                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9578                                 MDIO_84833_TOP_CFG_DATA4_REG,
9579                                 PHY84833_CONSTANT_LATENCY);
9580
9581                 /* Send EEE instruction to command register */
9582                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9583                                 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9584                                 PHY84833_DIAG_CMD_SET_EEE_MODE);
9585
9586                 /* Ensure that the command has completed */
9587                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9588                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9589                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9590                         if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9591                                 (val == PHY84833_CMD_COMPLETE_ERROR))
9592                                 break;
9593                         usleep_range(1000, 1000);
9594                 }
9595                 if ((idx >= PHY84833_HDSHK_WAIT) ||
9596                         (val == PHY84833_CMD_COMPLETE_ERROR)) {
9597                         DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9598                         return -EINVAL;
9599                 }
9600
9601                 /* Reset command handler */
9602                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9603                             MDIO_84833_TOP_CFG_SCRATCH_REG2,
9604                             PHY84833_CMD_CLEAR_COMPLETE);
9605         }
9606
9607         if (initialize)
9608                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9609         else
9610                 bnx2x_save_848xx_spirom_version(phy, params);
9611         /* 84833 PHY has a better feature and doesn't need to support this. */
9612         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9613                 cms_enable = REG_RD(bp, params->shmem_base +
9614                         offsetof(struct shmem_region,
9615                         dev_info.port_hw_config[params->port].default_cfg)) &
9616                         PORT_HW_CFG_ENABLE_CMS_MASK;
9617
9618                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9619                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9620                 if (cms_enable)
9621                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9622                 else
9623                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9624                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9625                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9626         }
9627
9628         return rc;
9629 }
9630
9631 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9632                                   struct link_params *params,
9633                                   struct link_vars *vars)
9634 {
9635         struct bnx2x *bp = params->bp;
9636         u16 val, val1, val2;
9637         u8 link_up = 0;
9638
9639
9640         /* Check 10G-BaseT link status */
9641         /* Check PMD signal ok */
9642         bnx2x_cl45_read(bp, phy,
9643                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9644         bnx2x_cl45_read(bp, phy,
9645                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9646                         &val2);
9647         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9648
9649         /* Check link 10G */
9650         if (val2 & (1<<11)) {
9651                 vars->line_speed = SPEED_10000;
9652                 vars->duplex = DUPLEX_FULL;
9653                 link_up = 1;
9654                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9655         } else { /* Check Legacy speed link */
9656                 u16 legacy_status, legacy_speed;
9657
9658                 /* Enable expansion register 0x42 (Operation mode status) */
9659                 bnx2x_cl45_write(bp, phy,
9660                                  MDIO_AN_DEVAD,
9661                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9662
9663                 /* Get legacy speed operation status */
9664                 bnx2x_cl45_read(bp, phy,
9665                                 MDIO_AN_DEVAD,
9666                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9667                                 &legacy_status);
9668
9669                 DP(NETIF_MSG_LINK, "Legacy speed status"
9670                              " = 0x%x\n", legacy_status);
9671                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9672                 if (link_up) {
9673                         legacy_speed = (legacy_status & (3<<9));
9674                         if (legacy_speed == (0<<9))
9675                                 vars->line_speed = SPEED_10;
9676                         else if (legacy_speed == (1<<9))
9677                                 vars->line_speed = SPEED_100;
9678                         else if (legacy_speed == (2<<9))
9679                                 vars->line_speed = SPEED_1000;
9680                         else /* Should not happen */
9681                                 vars->line_speed = 0;
9682
9683                         if (legacy_status & (1<<8))
9684                                 vars->duplex = DUPLEX_FULL;
9685                         else
9686                                 vars->duplex = DUPLEX_HALF;
9687
9688                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9689                                    " is_duplex_full= %d\n", vars->line_speed,
9690                                    (vars->duplex == DUPLEX_FULL));
9691                         /* Check legacy speed AN resolution */
9692                         bnx2x_cl45_read(bp, phy,
9693                                         MDIO_AN_DEVAD,
9694                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9695                                         &val);
9696                         if (val & (1<<5))
9697                                 vars->link_status |=
9698                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9699                         bnx2x_cl45_read(bp, phy,
9700                                         MDIO_AN_DEVAD,
9701                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9702                                         &val);
9703                         if ((val & (1<<0)) == 0)
9704                                 vars->link_status |=
9705                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9706                 }
9707         }
9708         if (link_up) {
9709                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9710                            vars->line_speed);
9711                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9712         }
9713
9714         return link_up;
9715 }
9716
9717
9718 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9719 {
9720         int status = 0;
9721         u32 spirom_ver;
9722         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9723         status = bnx2x_format_ver(spirom_ver, str, len);
9724         return status;
9725 }
9726
9727 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9728                                 struct link_params *params)
9729 {
9730         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9731                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9732         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9733                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9734 }
9735
9736 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9737                                         struct link_params *params)
9738 {
9739         bnx2x_cl45_write(params->bp, phy,
9740                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9741         bnx2x_cl45_write(params->bp, phy,
9742                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9743 }
9744
9745 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9746                                    struct link_params *params)
9747 {
9748         struct bnx2x *bp = params->bp;
9749         u8 port;
9750         u16 val16;
9751
9752         if (!(CHIP_IS_E1(bp)))
9753                 port = BP_PATH(bp);
9754         else
9755                 port = params->port;
9756
9757         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9758                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9759                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9760                                port);
9761         } else {
9762                 bnx2x_cl45_read(bp, phy,
9763                                 MDIO_CTL_DEVAD,
9764                                 0x400f, &val16);
9765                 /* Put to low power mode on newer FW */
9766                 if ((val16 & 0x303f) > 0x1009)
9767                         bnx2x_cl45_write(bp, phy,
9768                                         MDIO_PMA_DEVAD,
9769                                         MDIO_PMA_REG_CTRL, 0x800);
9770         }
9771 }
9772
9773 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9774                                      struct link_params *params, u8 mode)
9775 {
9776         struct bnx2x *bp = params->bp;
9777         u16 val;
9778         u8 port;
9779
9780         if (!(CHIP_IS_E1(bp)))
9781                 port = BP_PATH(bp);
9782         else
9783                 port = params->port;
9784
9785         switch (mode) {
9786         case LED_MODE_OFF:
9787
9788                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9789
9790                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9791                     SHARED_HW_CFG_LED_EXTPHY1) {
9792
9793                         /* Set LED masks */
9794                         bnx2x_cl45_write(bp, phy,
9795                                         MDIO_PMA_DEVAD,
9796                                         MDIO_PMA_REG_8481_LED1_MASK,
9797                                         0x0);
9798
9799                         bnx2x_cl45_write(bp, phy,
9800                                         MDIO_PMA_DEVAD,
9801                                         MDIO_PMA_REG_8481_LED2_MASK,
9802                                         0x0);
9803
9804                         bnx2x_cl45_write(bp, phy,
9805                                         MDIO_PMA_DEVAD,
9806                                         MDIO_PMA_REG_8481_LED3_MASK,
9807                                         0x0);
9808
9809                         bnx2x_cl45_write(bp, phy,
9810                                         MDIO_PMA_DEVAD,
9811                                         MDIO_PMA_REG_8481_LED5_MASK,
9812                                         0x0);
9813
9814                 } else {
9815                         bnx2x_cl45_write(bp, phy,
9816                                          MDIO_PMA_DEVAD,
9817                                          MDIO_PMA_REG_8481_LED1_MASK,
9818                                          0x0);
9819                 }
9820                 break;
9821         case LED_MODE_FRONT_PANEL_OFF:
9822
9823                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9824                    port);
9825
9826                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9827                     SHARED_HW_CFG_LED_EXTPHY1) {
9828
9829                         /* Set LED masks */
9830                         bnx2x_cl45_write(bp, phy,
9831                                          MDIO_PMA_DEVAD,
9832                                          MDIO_PMA_REG_8481_LED1_MASK,
9833                                          0x0);
9834
9835                         bnx2x_cl45_write(bp, phy,
9836                                          MDIO_PMA_DEVAD,
9837                                          MDIO_PMA_REG_8481_LED2_MASK,
9838                                          0x0);
9839
9840                         bnx2x_cl45_write(bp, phy,
9841                                          MDIO_PMA_DEVAD,
9842                                          MDIO_PMA_REG_8481_LED3_MASK,
9843                                          0x0);
9844
9845                         bnx2x_cl45_write(bp, phy,
9846                                          MDIO_PMA_DEVAD,
9847                                          MDIO_PMA_REG_8481_LED5_MASK,
9848                                          0x20);
9849
9850                 } else {
9851                         bnx2x_cl45_write(bp, phy,
9852                                          MDIO_PMA_DEVAD,
9853                                          MDIO_PMA_REG_8481_LED1_MASK,
9854                                          0x0);
9855                 }
9856                 break;
9857         case LED_MODE_ON:
9858
9859                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9860
9861                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9862                     SHARED_HW_CFG_LED_EXTPHY1) {
9863                         /* Set control reg */
9864                         bnx2x_cl45_read(bp, phy,
9865                                         MDIO_PMA_DEVAD,
9866                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9867                                         &val);
9868                         val &= 0x8000;
9869                         val |= 0x2492;
9870
9871                         bnx2x_cl45_write(bp, phy,
9872                                          MDIO_PMA_DEVAD,
9873                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9874                                          val);
9875
9876                         /* Set LED masks */
9877                         bnx2x_cl45_write(bp, phy,
9878                                          MDIO_PMA_DEVAD,
9879                                          MDIO_PMA_REG_8481_LED1_MASK,
9880                                          0x0);
9881
9882                         bnx2x_cl45_write(bp, phy,
9883                                          MDIO_PMA_DEVAD,
9884                                          MDIO_PMA_REG_8481_LED2_MASK,
9885                                          0x20);
9886
9887                         bnx2x_cl45_write(bp, phy,
9888                                          MDIO_PMA_DEVAD,
9889                                          MDIO_PMA_REG_8481_LED3_MASK,
9890                                          0x20);
9891
9892                         bnx2x_cl45_write(bp, phy,
9893                                          MDIO_PMA_DEVAD,
9894                                          MDIO_PMA_REG_8481_LED5_MASK,
9895                                          0x0);
9896                 } else {
9897                         bnx2x_cl45_write(bp, phy,
9898                                          MDIO_PMA_DEVAD,
9899                                          MDIO_PMA_REG_8481_LED1_MASK,
9900                                          0x20);
9901                 }
9902                 break;
9903
9904         case LED_MODE_OPER:
9905
9906                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9907
9908                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9909                     SHARED_HW_CFG_LED_EXTPHY1) {
9910
9911                         /* Set control reg */
9912                         bnx2x_cl45_read(bp, phy,
9913                                         MDIO_PMA_DEVAD,
9914                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9915                                         &val);
9916
9917                         if (!((val &
9918                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9919                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9920                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9921                                 bnx2x_cl45_write(bp, phy,
9922                                                  MDIO_PMA_DEVAD,
9923                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
9924                                                  0xa492);
9925                         }
9926
9927                         /* Set LED masks */
9928                         bnx2x_cl45_write(bp, phy,
9929                                          MDIO_PMA_DEVAD,
9930                                          MDIO_PMA_REG_8481_LED1_MASK,
9931                                          0x10);
9932
9933                         bnx2x_cl45_write(bp, phy,
9934                                          MDIO_PMA_DEVAD,
9935                                          MDIO_PMA_REG_8481_LED2_MASK,
9936                                          0x80);
9937
9938                         bnx2x_cl45_write(bp, phy,
9939                                          MDIO_PMA_DEVAD,
9940                                          MDIO_PMA_REG_8481_LED3_MASK,
9941                                          0x98);
9942
9943                         bnx2x_cl45_write(bp, phy,
9944                                          MDIO_PMA_DEVAD,
9945                                          MDIO_PMA_REG_8481_LED5_MASK,
9946                                          0x40);
9947
9948                 } else {
9949                         bnx2x_cl45_write(bp, phy,
9950                                          MDIO_PMA_DEVAD,
9951                                          MDIO_PMA_REG_8481_LED1_MASK,
9952                                          0x80);
9953
9954                         /* Tell LED3 to blink on source */
9955                         bnx2x_cl45_read(bp, phy,
9956                                         MDIO_PMA_DEVAD,
9957                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9958                                         &val);
9959                         val &= ~(7<<6);
9960                         val |= (1<<6); /* A83B[8:6]= 1 */
9961                         bnx2x_cl45_write(bp, phy,
9962                                          MDIO_PMA_DEVAD,
9963                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9964                                          val);
9965                 }
9966                 break;
9967         }
9968
9969         /*
9970          * This is a workaround for E3+84833 until autoneg
9971          * restart is fixed in f/w
9972          */
9973         if (CHIP_IS_E3(bp)) {
9974                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9975                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9976         }
9977 }
9978
9979 /******************************************************************/
9980 /*                      54618SE PHY SECTION                       */
9981 /******************************************************************/
9982 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
9983                                                struct link_params *params,
9984                                                struct link_vars *vars)
9985 {
9986         struct bnx2x *bp = params->bp;
9987         u8 port;
9988         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9989         u32 cfg_pin;
9990
9991         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
9992         usleep_range(1000, 1000);
9993
9994         /* This works with E3 only, no need to check the chip
9995            before determining the port. */
9996         port = params->port;
9997
9998         cfg_pin = (REG_RD(bp, params->shmem_base +
9999                         offsetof(struct shmem_region,
10000                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10001                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10002                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10003
10004         /* Drive pin high to bring the GPHY out of reset. */
10005         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10006
10007         /* wait for GPHY to reset */
10008         msleep(50);
10009
10010         /* reset phy */
10011         bnx2x_cl22_write(bp, phy,
10012                          MDIO_PMA_REG_CTRL, 0x8000);
10013         bnx2x_wait_reset_complete(bp, phy, params);
10014
10015         /*wait for GPHY to reset */
10016         msleep(50);
10017
10018         /* Configure LED4: set to INTR (0x6). */
10019         /* Accessing shadow register 0xe. */
10020         bnx2x_cl22_write(bp, phy,
10021                         MDIO_REG_GPHY_SHADOW,
10022                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10023         bnx2x_cl22_read(bp, phy,
10024                         MDIO_REG_GPHY_SHADOW,
10025                         &temp);
10026         temp &= ~(0xf << 4);
10027         temp |= (0x6 << 4);
10028         bnx2x_cl22_write(bp, phy,
10029                         MDIO_REG_GPHY_SHADOW,
10030                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10031         /* Configure INTR based on link status change. */
10032         bnx2x_cl22_write(bp, phy,
10033                         MDIO_REG_INTR_MASK,
10034                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10035
10036         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10037         bnx2x_cl22_write(bp, phy,
10038                         MDIO_REG_GPHY_SHADOW,
10039                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10040         bnx2x_cl22_read(bp, phy,
10041                         MDIO_REG_GPHY_SHADOW,
10042                         &temp);
10043         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10044         bnx2x_cl22_write(bp, phy,
10045                         MDIO_REG_GPHY_SHADOW,
10046                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10047
10048         /* Set up fc */
10049         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10050         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10051         fc_val = 0;
10052         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10053                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10054                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10055
10056         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10057                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10058                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10059
10060         /* read all advertisement */
10061         bnx2x_cl22_read(bp, phy,
10062                         0x09,
10063                         &an_1000_val);
10064
10065         bnx2x_cl22_read(bp, phy,
10066                         0x04,
10067                         &an_10_100_val);
10068
10069         bnx2x_cl22_read(bp, phy,
10070                         MDIO_PMA_REG_CTRL,
10071                         &autoneg_val);
10072
10073         /* Disable forced speed */
10074         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10075         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10076                            (1<<11));
10077
10078         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10079                         (phy->speed_cap_mask &
10080                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10081                         (phy->req_line_speed == SPEED_1000)) {
10082                 an_1000_val |= (1<<8);
10083                 autoneg_val |= (1<<9 | 1<<12);
10084                 if (phy->req_duplex == DUPLEX_FULL)
10085                         an_1000_val |= (1<<9);
10086                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10087         } else
10088                 an_1000_val &= ~((1<<8) | (1<<9));
10089
10090         bnx2x_cl22_write(bp, phy,
10091                         0x09,
10092                         an_1000_val);
10093         bnx2x_cl22_read(bp, phy,
10094                         0x09,
10095                         &an_1000_val);
10096
10097         /* set 100 speed advertisement */
10098         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10099                         (phy->speed_cap_mask &
10100                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10101                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10102                 an_10_100_val |= (1<<7);
10103                 /* Enable autoneg and restart autoneg for legacy speeds */
10104                 autoneg_val |= (1<<9 | 1<<12);
10105
10106                 if (phy->req_duplex == DUPLEX_FULL)
10107                         an_10_100_val |= (1<<8);
10108                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10109         }
10110
10111         /* set 10 speed advertisement */
10112         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10113                         (phy->speed_cap_mask &
10114                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10115                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10116                 an_10_100_val |= (1<<5);
10117                 autoneg_val |= (1<<9 | 1<<12);
10118                 if (phy->req_duplex == DUPLEX_FULL)
10119                         an_10_100_val |= (1<<6);
10120                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10121         }
10122
10123         /* Only 10/100 are allowed to work in FORCE mode */
10124         if (phy->req_line_speed == SPEED_100) {
10125                 autoneg_val |= (1<<13);
10126                 /* Enabled AUTO-MDIX when autoneg is disabled */
10127                 bnx2x_cl22_write(bp, phy,
10128                                 0x18,
10129                                 (1<<15 | 1<<9 | 7<<0));
10130                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10131         }
10132         if (phy->req_line_speed == SPEED_10) {
10133                 /* Enabled AUTO-MDIX when autoneg is disabled */
10134                 bnx2x_cl22_write(bp, phy,
10135                                 0x18,
10136                                 (1<<15 | 1<<9 | 7<<0));
10137                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10138         }
10139
10140         /* Check if we should turn on Auto-GrEEEn */
10141         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10142         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10143                 if (params->feature_config_flags &
10144                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10145                         temp = 6;
10146                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10147                 } else {
10148                         temp = 0;
10149                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10150                 }
10151                 bnx2x_cl22_write(bp, phy,
10152                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10153                 bnx2x_cl22_write(bp, phy,
10154                                  MDIO_REG_GPHY_CL45_DATA_REG,
10155                                  MDIO_REG_GPHY_EEE_ADV);
10156                 bnx2x_cl22_write(bp, phy,
10157                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10158                                  (0x1 << 14) | MDIO_AN_DEVAD);
10159                 bnx2x_cl22_write(bp, phy,
10160                                  MDIO_REG_GPHY_CL45_DATA_REG,
10161                                  temp);
10162         }
10163
10164         bnx2x_cl22_write(bp, phy,
10165                         0x04,
10166                         an_10_100_val | fc_val);
10167
10168         if (phy->req_duplex == DUPLEX_FULL)
10169                 autoneg_val |= (1<<8);
10170
10171         bnx2x_cl22_write(bp, phy,
10172                         MDIO_PMA_REG_CTRL, autoneg_val);
10173
10174         return 0;
10175 }
10176
10177 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10178                                        struct link_params *params, u8 mode)
10179 {
10180         struct bnx2x *bp = params->bp;
10181         DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10182         switch (mode) {
10183         case LED_MODE_FRONT_PANEL_OFF:
10184         case LED_MODE_OFF:
10185         case LED_MODE_OPER:
10186         case LED_MODE_ON:
10187         default:
10188                 break;
10189         }
10190         return;
10191 }
10192
10193 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10194                                      struct link_params *params)
10195 {
10196         struct bnx2x *bp = params->bp;
10197         u32 cfg_pin;
10198         u8 port;
10199
10200         /* This works with E3 only, no need to check the chip
10201            before determining the port. */
10202         port = params->port;
10203         cfg_pin = (REG_RD(bp, params->shmem_base +
10204                         offsetof(struct shmem_region,
10205                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10206                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10207                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10208
10209         /* Drive pin low to put GPHY in reset. */
10210         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10211 }
10212
10213 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10214                                     struct link_params *params,
10215                                     struct link_vars *vars)
10216 {
10217         struct bnx2x *bp = params->bp;
10218         u16 val;
10219         u8 link_up = 0;
10220         u16 legacy_status, legacy_speed;
10221
10222         /* Get speed operation status */
10223         bnx2x_cl22_read(bp, phy,
10224                         0x19,
10225                         &legacy_status);
10226         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10227
10228         /* Read status to clear the PHY interrupt. */
10229         bnx2x_cl22_read(bp, phy,
10230                         MDIO_REG_INTR_STATUS,
10231                         &val);
10232
10233         link_up = ((legacy_status & (1<<2)) == (1<<2));
10234
10235         if (link_up) {
10236                 legacy_speed = (legacy_status & (7<<8));
10237                 if (legacy_speed == (7<<8)) {
10238                         vars->line_speed = SPEED_1000;
10239                         vars->duplex = DUPLEX_FULL;
10240                 } else if (legacy_speed == (6<<8)) {
10241                         vars->line_speed = SPEED_1000;
10242                         vars->duplex = DUPLEX_HALF;
10243                 } else if (legacy_speed == (5<<8)) {
10244                         vars->line_speed = SPEED_100;
10245                         vars->duplex = DUPLEX_FULL;
10246                 }
10247                 /* Omitting 100Base-T4 for now */
10248                 else if (legacy_speed == (3<<8)) {
10249                         vars->line_speed = SPEED_100;
10250                         vars->duplex = DUPLEX_HALF;
10251                 } else if (legacy_speed == (2<<8)) {
10252                         vars->line_speed = SPEED_10;
10253                         vars->duplex = DUPLEX_FULL;
10254                 } else if (legacy_speed == (1<<8)) {
10255                         vars->line_speed = SPEED_10;
10256                         vars->duplex = DUPLEX_HALF;
10257                 } else /* Should not happen */
10258                         vars->line_speed = 0;
10259
10260                 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10261                            " is_duplex_full= %d\n", vars->line_speed,
10262                            (vars->duplex == DUPLEX_FULL));
10263
10264                 /* Check legacy speed AN resolution */
10265                 bnx2x_cl22_read(bp, phy,
10266                                 0x01,
10267                                 &val);
10268                 if (val & (1<<5))
10269                         vars->link_status |=
10270                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10271                 bnx2x_cl22_read(bp, phy,
10272                                 0x06,
10273                                 &val);
10274                 if ((val & (1<<0)) == 0)
10275                         vars->link_status |=
10276                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10277
10278                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10279                            vars->line_speed);
10280
10281                 /* Report whether EEE is resolved. */
10282                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10283                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10284                         if (vars->link_status &
10285                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10286                                 val = 0;
10287                         else {
10288                                 bnx2x_cl22_write(bp, phy,
10289                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10290                                         MDIO_AN_DEVAD);
10291                                 bnx2x_cl22_write(bp, phy,
10292                                         MDIO_REG_GPHY_CL45_DATA_REG,
10293                                         MDIO_REG_GPHY_EEE_RESOLVED);
10294                                 bnx2x_cl22_write(bp, phy,
10295                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10296                                         (0x1 << 14) | MDIO_AN_DEVAD);
10297                                 bnx2x_cl22_read(bp, phy,
10298                                         MDIO_REG_GPHY_CL45_DATA_REG,
10299                                         &val);
10300                         }
10301                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10302                 }
10303
10304                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10305         }
10306         return link_up;
10307 }
10308
10309 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10310                                           struct link_params *params)
10311 {
10312         struct bnx2x *bp = params->bp;
10313         u16 val;
10314         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10315
10316         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10317
10318         /* Enable master/slave manual mmode and set to master */
10319         /* mii write 9 [bits set 11 12] */
10320         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10321
10322         /* forced 1G and disable autoneg */
10323         /* set val [mii read 0] */
10324         /* set val [expr $val & [bits clear 6 12 13]] */
10325         /* set val [expr $val | [bits set 6 8]] */
10326         /* mii write 0 $val */
10327         bnx2x_cl22_read(bp, phy, 0x00, &val);
10328         val &= ~((1<<6) | (1<<12) | (1<<13));
10329         val |= (1<<6) | (1<<8);
10330         bnx2x_cl22_write(bp, phy, 0x00, val);
10331
10332         /* Set external loopback and Tx using 6dB coding */
10333         /* mii write 0x18 7 */
10334         /* set val [mii read 0x18] */
10335         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10336         bnx2x_cl22_write(bp, phy, 0x18, 7);
10337         bnx2x_cl22_read(bp, phy, 0x18, &val);
10338         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10339
10340         /* This register opens the gate for the UMAC despite its name */
10341         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10342
10343         /*
10344          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10345          * length used by the MAC receive logic to check frames.
10346          */
10347         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10348 }
10349
10350 /******************************************************************/
10351 /*                      SFX7101 PHY SECTION                       */
10352 /******************************************************************/
10353 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10354                                        struct link_params *params)
10355 {
10356         struct bnx2x *bp = params->bp;
10357         /* SFX7101_XGXS_TEST1 */
10358         bnx2x_cl45_write(bp, phy,
10359                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10360 }
10361
10362 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10363                                   struct link_params *params,
10364                                   struct link_vars *vars)
10365 {
10366         u16 fw_ver1, fw_ver2, val;
10367         struct bnx2x *bp = params->bp;
10368         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10369
10370         /* Restore normal power mode*/
10371         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10372                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10373         /* HW reset */
10374         bnx2x_ext_phy_hw_reset(bp, params->port);
10375         bnx2x_wait_reset_complete(bp, phy, params);
10376
10377         bnx2x_cl45_write(bp, phy,
10378                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10379         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10380         bnx2x_cl45_write(bp, phy,
10381                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10382
10383         bnx2x_ext_phy_set_pause(params, phy, vars);
10384         /* Restart autoneg */
10385         bnx2x_cl45_read(bp, phy,
10386                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10387         val |= 0x200;
10388         bnx2x_cl45_write(bp, phy,
10389                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10390
10391         /* Save spirom version */
10392         bnx2x_cl45_read(bp, phy,
10393                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10394
10395         bnx2x_cl45_read(bp, phy,
10396                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10397         bnx2x_save_spirom_version(bp, params->port,
10398                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10399         return 0;
10400 }
10401
10402 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10403                                  struct link_params *params,
10404                                  struct link_vars *vars)
10405 {
10406         struct bnx2x *bp = params->bp;
10407         u8 link_up;
10408         u16 val1, val2;
10409         bnx2x_cl45_read(bp, phy,
10410                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10411         bnx2x_cl45_read(bp, phy,
10412                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10413         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10414                    val2, val1);
10415         bnx2x_cl45_read(bp, phy,
10416                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10417         bnx2x_cl45_read(bp, phy,
10418                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10419         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10420                    val2, val1);
10421         link_up = ((val1 & 4) == 4);
10422         /* if link is up print the AN outcome of the SFX7101 PHY */
10423         if (link_up) {
10424                 bnx2x_cl45_read(bp, phy,
10425                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10426                                 &val2);
10427                 vars->line_speed = SPEED_10000;
10428                 vars->duplex = DUPLEX_FULL;
10429                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10430                            val2, (val2 & (1<<14)));
10431                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10432                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10433         }
10434         return link_up;
10435 }
10436
10437 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10438 {
10439         if (*len < 5)
10440                 return -EINVAL;
10441         str[0] = (spirom_ver & 0xFF);
10442         str[1] = (spirom_ver & 0xFF00) >> 8;
10443         str[2] = (spirom_ver & 0xFF0000) >> 16;
10444         str[3] = (spirom_ver & 0xFF000000) >> 24;
10445         str[4] = '\0';
10446         *len -= 5;
10447         return 0;
10448 }
10449
10450 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10451 {
10452         u16 val, cnt;
10453
10454         bnx2x_cl45_read(bp, phy,
10455                         MDIO_PMA_DEVAD,
10456                         MDIO_PMA_REG_7101_RESET, &val);
10457
10458         for (cnt = 0; cnt < 10; cnt++) {
10459                 msleep(50);
10460                 /* Writes a self-clearing reset */
10461                 bnx2x_cl45_write(bp, phy,
10462                                  MDIO_PMA_DEVAD,
10463                                  MDIO_PMA_REG_7101_RESET,
10464                                  (val | (1<<15)));
10465                 /* Wait for clear */
10466                 bnx2x_cl45_read(bp, phy,
10467                                 MDIO_PMA_DEVAD,
10468                                 MDIO_PMA_REG_7101_RESET, &val);
10469
10470                 if ((val & (1<<15)) == 0)
10471                         break;
10472         }
10473 }
10474
10475 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10476                                 struct link_params *params) {
10477         /* Low power mode is controlled by GPIO 2 */
10478         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10479                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10480         /* The PHY reset is controlled by GPIO 1 */
10481         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10482                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10483 }
10484
10485 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10486                                     struct link_params *params, u8 mode)
10487 {
10488         u16 val = 0;
10489         struct bnx2x *bp = params->bp;
10490         switch (mode) {
10491         case LED_MODE_FRONT_PANEL_OFF:
10492         case LED_MODE_OFF:
10493                 val = 2;
10494                 break;
10495         case LED_MODE_ON:
10496                 val = 1;
10497                 break;
10498         case LED_MODE_OPER:
10499                 val = 0;
10500                 break;
10501         }
10502         bnx2x_cl45_write(bp, phy,
10503                          MDIO_PMA_DEVAD,
10504                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10505                          val);
10506 }
10507
10508 /******************************************************************/
10509 /*                      STATIC PHY DECLARATION                    */
10510 /******************************************************************/
10511
10512 static struct bnx2x_phy phy_null = {
10513         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10514         .addr           = 0,
10515         .def_md_devad   = 0,
10516         .flags          = FLAGS_INIT_XGXS_FIRST,
10517         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10518         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10519         .mdio_ctrl      = 0,
10520         .supported      = 0,
10521         .media_type     = ETH_PHY_NOT_PRESENT,
10522         .ver_addr       = 0,
10523         .req_flow_ctrl  = 0,
10524         .req_line_speed = 0,
10525         .speed_cap_mask = 0,
10526         .req_duplex     = 0,
10527         .rsrv           = 0,
10528         .config_init    = (config_init_t)NULL,
10529         .read_status    = (read_status_t)NULL,
10530         .link_reset     = (link_reset_t)NULL,
10531         .config_loopback = (config_loopback_t)NULL,
10532         .format_fw_ver  = (format_fw_ver_t)NULL,
10533         .hw_reset       = (hw_reset_t)NULL,
10534         .set_link_led   = (set_link_led_t)NULL,
10535         .phy_specific_func = (phy_specific_func_t)NULL
10536 };
10537
10538 static struct bnx2x_phy phy_serdes = {
10539         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10540         .addr           = 0xff,
10541         .def_md_devad   = 0,
10542         .flags          = 0,
10543         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10544         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10545         .mdio_ctrl      = 0,
10546         .supported      = (SUPPORTED_10baseT_Half |
10547                            SUPPORTED_10baseT_Full |
10548                            SUPPORTED_100baseT_Half |
10549                            SUPPORTED_100baseT_Full |
10550                            SUPPORTED_1000baseT_Full |
10551                            SUPPORTED_2500baseX_Full |
10552                            SUPPORTED_TP |
10553                            SUPPORTED_Autoneg |
10554                            SUPPORTED_Pause |
10555                            SUPPORTED_Asym_Pause),
10556         .media_type     = ETH_PHY_BASE_T,
10557         .ver_addr       = 0,
10558         .req_flow_ctrl  = 0,
10559         .req_line_speed = 0,
10560         .speed_cap_mask = 0,
10561         .req_duplex     = 0,
10562         .rsrv           = 0,
10563         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10564         .read_status    = (read_status_t)bnx2x_link_settings_status,
10565         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10566         .config_loopback = (config_loopback_t)NULL,
10567         .format_fw_ver  = (format_fw_ver_t)NULL,
10568         .hw_reset       = (hw_reset_t)NULL,
10569         .set_link_led   = (set_link_led_t)NULL,
10570         .phy_specific_func = (phy_specific_func_t)NULL
10571 };
10572
10573 static struct bnx2x_phy phy_xgxs = {
10574         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10575         .addr           = 0xff,
10576         .def_md_devad   = 0,
10577         .flags          = 0,
10578         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10579         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10580         .mdio_ctrl      = 0,
10581         .supported      = (SUPPORTED_10baseT_Half |
10582                            SUPPORTED_10baseT_Full |
10583                            SUPPORTED_100baseT_Half |
10584                            SUPPORTED_100baseT_Full |
10585                            SUPPORTED_1000baseT_Full |
10586                            SUPPORTED_2500baseX_Full |
10587                            SUPPORTED_10000baseT_Full |
10588                            SUPPORTED_FIBRE |
10589                            SUPPORTED_Autoneg |
10590                            SUPPORTED_Pause |
10591                            SUPPORTED_Asym_Pause),
10592         .media_type     = ETH_PHY_CX4,
10593         .ver_addr       = 0,
10594         .req_flow_ctrl  = 0,
10595         .req_line_speed = 0,
10596         .speed_cap_mask = 0,
10597         .req_duplex     = 0,
10598         .rsrv           = 0,
10599         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10600         .read_status    = (read_status_t)bnx2x_link_settings_status,
10601         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10602         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10603         .format_fw_ver  = (format_fw_ver_t)NULL,
10604         .hw_reset       = (hw_reset_t)NULL,
10605         .set_link_led   = (set_link_led_t)NULL,
10606         .phy_specific_func = (phy_specific_func_t)NULL
10607 };
10608 static struct bnx2x_phy phy_warpcore = {
10609         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10610         .addr           = 0xff,
10611         .def_md_devad   = 0,
10612         .flags          = FLAGS_HW_LOCK_REQUIRED,
10613         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10614         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10615         .mdio_ctrl      = 0,
10616         .supported      = (SUPPORTED_10baseT_Half |
10617                              SUPPORTED_10baseT_Full |
10618                              SUPPORTED_100baseT_Half |
10619                              SUPPORTED_100baseT_Full |
10620                              SUPPORTED_1000baseT_Full |
10621                              SUPPORTED_10000baseT_Full |
10622                              SUPPORTED_20000baseKR2_Full |
10623                              SUPPORTED_20000baseMLD2_Full |
10624                              SUPPORTED_FIBRE |
10625                              SUPPORTED_Autoneg |
10626                              SUPPORTED_Pause |
10627                              SUPPORTED_Asym_Pause),
10628         .media_type     = ETH_PHY_UNSPECIFIED,
10629         .ver_addr       = 0,
10630         .req_flow_ctrl  = 0,
10631         .req_line_speed = 0,
10632         .speed_cap_mask = 0,
10633         /* req_duplex = */0,
10634         /* rsrv = */0,
10635         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10636         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10637         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10638         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10639         .format_fw_ver  = (format_fw_ver_t)NULL,
10640         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10641         .set_link_led   = (set_link_led_t)NULL,
10642         .phy_specific_func = (phy_specific_func_t)NULL
10643 };
10644
10645
10646 static struct bnx2x_phy phy_7101 = {
10647         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10648         .addr           = 0xff,
10649         .def_md_devad   = 0,
10650         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10651         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10652         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10653         .mdio_ctrl      = 0,
10654         .supported      = (SUPPORTED_10000baseT_Full |
10655                            SUPPORTED_TP |
10656                            SUPPORTED_Autoneg |
10657                            SUPPORTED_Pause |
10658                            SUPPORTED_Asym_Pause),
10659         .media_type     = ETH_PHY_BASE_T,
10660         .ver_addr       = 0,
10661         .req_flow_ctrl  = 0,
10662         .req_line_speed = 0,
10663         .speed_cap_mask = 0,
10664         .req_duplex     = 0,
10665         .rsrv           = 0,
10666         .config_init    = (config_init_t)bnx2x_7101_config_init,
10667         .read_status    = (read_status_t)bnx2x_7101_read_status,
10668         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10669         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10670         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10671         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10672         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10673         .phy_specific_func = (phy_specific_func_t)NULL
10674 };
10675 static struct bnx2x_phy phy_8073 = {
10676         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10677         .addr           = 0xff,
10678         .def_md_devad   = 0,
10679         .flags          = FLAGS_HW_LOCK_REQUIRED,
10680         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10681         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10682         .mdio_ctrl      = 0,
10683         .supported      = (SUPPORTED_10000baseT_Full |
10684                            SUPPORTED_2500baseX_Full |
10685                            SUPPORTED_1000baseT_Full |
10686                            SUPPORTED_FIBRE |
10687                            SUPPORTED_Autoneg |
10688                            SUPPORTED_Pause |
10689                            SUPPORTED_Asym_Pause),
10690         .media_type     = ETH_PHY_KR,
10691         .ver_addr       = 0,
10692         .req_flow_ctrl  = 0,
10693         .req_line_speed = 0,
10694         .speed_cap_mask = 0,
10695         .req_duplex     = 0,
10696         .rsrv           = 0,
10697         .config_init    = (config_init_t)bnx2x_8073_config_init,
10698         .read_status    = (read_status_t)bnx2x_8073_read_status,
10699         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10700         .config_loopback = (config_loopback_t)NULL,
10701         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10702         .hw_reset       = (hw_reset_t)NULL,
10703         .set_link_led   = (set_link_led_t)NULL,
10704         .phy_specific_func = (phy_specific_func_t)NULL
10705 };
10706 static struct bnx2x_phy phy_8705 = {
10707         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10708         .addr           = 0xff,
10709         .def_md_devad   = 0,
10710         .flags          = FLAGS_INIT_XGXS_FIRST,
10711         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10712         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10713         .mdio_ctrl      = 0,
10714         .supported      = (SUPPORTED_10000baseT_Full |
10715                            SUPPORTED_FIBRE |
10716                            SUPPORTED_Pause |
10717                            SUPPORTED_Asym_Pause),
10718         .media_type     = ETH_PHY_XFP_FIBER,
10719         .ver_addr       = 0,
10720         .req_flow_ctrl  = 0,
10721         .req_line_speed = 0,
10722         .speed_cap_mask = 0,
10723         .req_duplex     = 0,
10724         .rsrv           = 0,
10725         .config_init    = (config_init_t)bnx2x_8705_config_init,
10726         .read_status    = (read_status_t)bnx2x_8705_read_status,
10727         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10728         .config_loopback = (config_loopback_t)NULL,
10729         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10730         .hw_reset       = (hw_reset_t)NULL,
10731         .set_link_led   = (set_link_led_t)NULL,
10732         .phy_specific_func = (phy_specific_func_t)NULL
10733 };
10734 static struct bnx2x_phy phy_8706 = {
10735         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10736         .addr           = 0xff,
10737         .def_md_devad   = 0,
10738         .flags          = FLAGS_INIT_XGXS_FIRST,
10739         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10740         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10741         .mdio_ctrl      = 0,
10742         .supported      = (SUPPORTED_10000baseT_Full |
10743                            SUPPORTED_1000baseT_Full |
10744                            SUPPORTED_FIBRE |
10745                            SUPPORTED_Pause |
10746                            SUPPORTED_Asym_Pause),
10747         .media_type     = ETH_PHY_SFP_FIBER,
10748         .ver_addr       = 0,
10749         .req_flow_ctrl  = 0,
10750         .req_line_speed = 0,
10751         .speed_cap_mask = 0,
10752         .req_duplex     = 0,
10753         .rsrv           = 0,
10754         .config_init    = (config_init_t)bnx2x_8706_config_init,
10755         .read_status    = (read_status_t)bnx2x_8706_read_status,
10756         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10757         .config_loopback = (config_loopback_t)NULL,
10758         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10759         .hw_reset       = (hw_reset_t)NULL,
10760         .set_link_led   = (set_link_led_t)NULL,
10761         .phy_specific_func = (phy_specific_func_t)NULL
10762 };
10763
10764 static struct bnx2x_phy phy_8726 = {
10765         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10766         .addr           = 0xff,
10767         .def_md_devad   = 0,
10768         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10769                            FLAGS_INIT_XGXS_FIRST),
10770         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10771         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10772         .mdio_ctrl      = 0,
10773         .supported      = (SUPPORTED_10000baseT_Full |
10774                            SUPPORTED_1000baseT_Full |
10775                            SUPPORTED_Autoneg |
10776                            SUPPORTED_FIBRE |
10777                            SUPPORTED_Pause |
10778                            SUPPORTED_Asym_Pause),
10779         .media_type     = ETH_PHY_NOT_PRESENT,
10780         .ver_addr       = 0,
10781         .req_flow_ctrl  = 0,
10782         .req_line_speed = 0,
10783         .speed_cap_mask = 0,
10784         .req_duplex     = 0,
10785         .rsrv           = 0,
10786         .config_init    = (config_init_t)bnx2x_8726_config_init,
10787         .read_status    = (read_status_t)bnx2x_8726_read_status,
10788         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10789         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10790         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10791         .hw_reset       = (hw_reset_t)NULL,
10792         .set_link_led   = (set_link_led_t)NULL,
10793         .phy_specific_func = (phy_specific_func_t)NULL
10794 };
10795
10796 static struct bnx2x_phy phy_8727 = {
10797         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10798         .addr           = 0xff,
10799         .def_md_devad   = 0,
10800         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10801         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10802         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10803         .mdio_ctrl      = 0,
10804         .supported      = (SUPPORTED_10000baseT_Full |
10805                            SUPPORTED_1000baseT_Full |
10806                            SUPPORTED_FIBRE |
10807                            SUPPORTED_Pause |
10808                            SUPPORTED_Asym_Pause),
10809         .media_type     = ETH_PHY_NOT_PRESENT,
10810         .ver_addr       = 0,
10811         .req_flow_ctrl  = 0,
10812         .req_line_speed = 0,
10813         .speed_cap_mask = 0,
10814         .req_duplex     = 0,
10815         .rsrv           = 0,
10816         .config_init    = (config_init_t)bnx2x_8727_config_init,
10817         .read_status    = (read_status_t)bnx2x_8727_read_status,
10818         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10819         .config_loopback = (config_loopback_t)NULL,
10820         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10821         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10822         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10823         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10824 };
10825 static struct bnx2x_phy phy_8481 = {
10826         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10827         .addr           = 0xff,
10828         .def_md_devad   = 0,
10829         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10830                           FLAGS_REARM_LATCH_SIGNAL,
10831         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10832         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10833         .mdio_ctrl      = 0,
10834         .supported      = (SUPPORTED_10baseT_Half |
10835                            SUPPORTED_10baseT_Full |
10836                            SUPPORTED_100baseT_Half |
10837                            SUPPORTED_100baseT_Full |
10838                            SUPPORTED_1000baseT_Full |
10839                            SUPPORTED_10000baseT_Full |
10840                            SUPPORTED_TP |
10841                            SUPPORTED_Autoneg |
10842                            SUPPORTED_Pause |
10843                            SUPPORTED_Asym_Pause),
10844         .media_type     = ETH_PHY_BASE_T,
10845         .ver_addr       = 0,
10846         .req_flow_ctrl  = 0,
10847         .req_line_speed = 0,
10848         .speed_cap_mask = 0,
10849         .req_duplex     = 0,
10850         .rsrv           = 0,
10851         .config_init    = (config_init_t)bnx2x_8481_config_init,
10852         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10853         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10854         .config_loopback = (config_loopback_t)NULL,
10855         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10856         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
10857         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10858         .phy_specific_func = (phy_specific_func_t)NULL
10859 };
10860
10861 static struct bnx2x_phy phy_84823 = {
10862         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10863         .addr           = 0xff,
10864         .def_md_devad   = 0,
10865         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10866                           FLAGS_REARM_LATCH_SIGNAL,
10867         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10868         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10869         .mdio_ctrl      = 0,
10870         .supported      = (SUPPORTED_10baseT_Half |
10871                            SUPPORTED_10baseT_Full |
10872                            SUPPORTED_100baseT_Half |
10873                            SUPPORTED_100baseT_Full |
10874                            SUPPORTED_1000baseT_Full |
10875                            SUPPORTED_10000baseT_Full |
10876                            SUPPORTED_TP |
10877                            SUPPORTED_Autoneg |
10878                            SUPPORTED_Pause |
10879                            SUPPORTED_Asym_Pause),
10880         .media_type     = ETH_PHY_BASE_T,
10881         .ver_addr       = 0,
10882         .req_flow_ctrl  = 0,
10883         .req_line_speed = 0,
10884         .speed_cap_mask = 0,
10885         .req_duplex     = 0,
10886         .rsrv           = 0,
10887         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10888         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10889         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10890         .config_loopback = (config_loopback_t)NULL,
10891         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10892         .hw_reset       = (hw_reset_t)NULL,
10893         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10894         .phy_specific_func = (phy_specific_func_t)NULL
10895 };
10896
10897 static struct bnx2x_phy phy_84833 = {
10898         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10899         .addr           = 0xff,
10900         .def_md_devad   = 0,
10901         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10902                             FLAGS_REARM_LATCH_SIGNAL,
10903         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10904         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10905         .mdio_ctrl      = 0,
10906         .supported      = (SUPPORTED_100baseT_Half |
10907                            SUPPORTED_100baseT_Full |
10908                            SUPPORTED_1000baseT_Full |
10909                            SUPPORTED_10000baseT_Full |
10910                            SUPPORTED_TP |
10911                            SUPPORTED_Autoneg |
10912                            SUPPORTED_Pause |
10913                            SUPPORTED_Asym_Pause),
10914         .media_type     = ETH_PHY_BASE_T,
10915         .ver_addr       = 0,
10916         .req_flow_ctrl  = 0,
10917         .req_line_speed = 0,
10918         .speed_cap_mask = 0,
10919         .req_duplex     = 0,
10920         .rsrv           = 0,
10921         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10922         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10923         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10924         .config_loopback = (config_loopback_t)NULL,
10925         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10926         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10927         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10928         .phy_specific_func = (phy_specific_func_t)NULL
10929 };
10930
10931 static struct bnx2x_phy phy_54618se = {
10932         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10933         .addr           = 0xff,
10934         .def_md_devad   = 0,
10935         .flags          = FLAGS_INIT_XGXS_FIRST,
10936         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10937         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10938         .mdio_ctrl      = 0,
10939         .supported      = (SUPPORTED_10baseT_Half |
10940                            SUPPORTED_10baseT_Full |
10941                            SUPPORTED_100baseT_Half |
10942                            SUPPORTED_100baseT_Full |
10943                            SUPPORTED_1000baseT_Full |
10944                            SUPPORTED_TP |
10945                            SUPPORTED_Autoneg |
10946                            SUPPORTED_Pause |
10947                            SUPPORTED_Asym_Pause),
10948         .media_type     = ETH_PHY_BASE_T,
10949         .ver_addr       = 0,
10950         .req_flow_ctrl  = 0,
10951         .req_line_speed = 0,
10952         .speed_cap_mask = 0,
10953         /* req_duplex = */0,
10954         /* rsrv = */0,
10955         .config_init    = (config_init_t)bnx2x_54618se_config_init,
10956         .read_status    = (read_status_t)bnx2x_54618se_read_status,
10957         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
10958         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10959         .format_fw_ver  = (format_fw_ver_t)NULL,
10960         .hw_reset       = (hw_reset_t)NULL,
10961         .set_link_led   = (set_link_led_t)bnx2x_54618se_set_link_led,
10962         .phy_specific_func = (phy_specific_func_t)NULL
10963 };
10964 /*****************************************************************/
10965 /*                                                               */
10966 /* Populate the phy according. Main function: bnx2x_populate_phy   */
10967 /*                                                               */
10968 /*****************************************************************/
10969
10970 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10971                                      struct bnx2x_phy *phy, u8 port,
10972                                      u8 phy_index)
10973 {
10974         /* Get the 4 lanes xgxs config rx and tx */
10975         u32 rx = 0, tx = 0, i;
10976         for (i = 0; i < 2; i++) {
10977                 /*
10978                  * INT_PHY and EXT_PHY1 share the same value location in the
10979                  * shmem. When num_phys is greater than 1, than this value
10980                  * applies only to EXT_PHY1
10981                  */
10982                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10983                         rx = REG_RD(bp, shmem_base +
10984                                     offsetof(struct shmem_region,
10985                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10986
10987                         tx = REG_RD(bp, shmem_base +
10988                                     offsetof(struct shmem_region,
10989                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10990                 } else {
10991                         rx = REG_RD(bp, shmem_base +
10992                                     offsetof(struct shmem_region,
10993                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10994
10995                         tx = REG_RD(bp, shmem_base +
10996                                     offsetof(struct shmem_region,
10997                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10998                 }
10999
11000                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11001                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11002
11003                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11004                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11005         }
11006 }
11007
11008 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11009                                     u8 phy_index, u8 port)
11010 {
11011         u32 ext_phy_config = 0;
11012         switch (phy_index) {
11013         case EXT_PHY1:
11014                 ext_phy_config = REG_RD(bp, shmem_base +
11015                                               offsetof(struct shmem_region,
11016                         dev_info.port_hw_config[port].external_phy_config));
11017                 break;
11018         case EXT_PHY2:
11019                 ext_phy_config = REG_RD(bp, shmem_base +
11020                                               offsetof(struct shmem_region,
11021                         dev_info.port_hw_config[port].external_phy_config2));
11022                 break;
11023         default:
11024                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11025                 return -EINVAL;
11026         }
11027
11028         return ext_phy_config;
11029 }
11030 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11031                                   struct bnx2x_phy *phy)
11032 {
11033         u32 phy_addr;
11034         u32 chip_id;
11035         u32 switch_cfg = (REG_RD(bp, shmem_base +
11036                                        offsetof(struct shmem_region,
11037                         dev_info.port_feature_config[port].link_config)) &
11038                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11039         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11040         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11041         if (USES_WARPCORE(bp)) {
11042                 u32 serdes_net_if;
11043                 phy_addr = REG_RD(bp,
11044                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11045                 *phy = phy_warpcore;
11046                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11047                         phy->flags |= FLAGS_4_PORT_MODE;
11048                 else
11049                         phy->flags &= ~FLAGS_4_PORT_MODE;
11050                         /* Check Dual mode */
11051                 serdes_net_if = (REG_RD(bp, shmem_base +
11052                                         offsetof(struct shmem_region, dev_info.
11053                                         port_hw_config[port].default_cfg)) &
11054                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11055                 /*
11056                  * Set the appropriate supported and flags indications per
11057                  * interface type of the chip
11058                  */
11059                 switch (serdes_net_if) {
11060                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11061                         phy->supported &= (SUPPORTED_10baseT_Half |
11062                                            SUPPORTED_10baseT_Full |
11063                                            SUPPORTED_100baseT_Half |
11064                                            SUPPORTED_100baseT_Full |
11065                                            SUPPORTED_1000baseT_Full |
11066                                            SUPPORTED_FIBRE |
11067                                            SUPPORTED_Autoneg |
11068                                            SUPPORTED_Pause |
11069                                            SUPPORTED_Asym_Pause);
11070                         phy->media_type = ETH_PHY_BASE_T;
11071                         break;
11072                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11073                         phy->media_type = ETH_PHY_XFP_FIBER;
11074                         break;
11075                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11076                         phy->supported &= (SUPPORTED_1000baseT_Full |
11077                                            SUPPORTED_10000baseT_Full |
11078                                            SUPPORTED_FIBRE |
11079                                            SUPPORTED_Pause |
11080                                            SUPPORTED_Asym_Pause);
11081                         phy->media_type = ETH_PHY_SFP_FIBER;
11082                         break;
11083                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11084                         phy->media_type = ETH_PHY_KR;
11085                         phy->supported &= (SUPPORTED_1000baseT_Full |
11086                                            SUPPORTED_10000baseT_Full |
11087                                            SUPPORTED_FIBRE |
11088                                            SUPPORTED_Autoneg |
11089                                            SUPPORTED_Pause |
11090                                            SUPPORTED_Asym_Pause);
11091                         break;
11092                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11093                         phy->media_type = ETH_PHY_KR;
11094                         phy->flags |= FLAGS_WC_DUAL_MODE;
11095                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11096                                            SUPPORTED_FIBRE |
11097                                            SUPPORTED_Pause |
11098                                            SUPPORTED_Asym_Pause);
11099                         break;
11100                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11101                         phy->media_type = ETH_PHY_KR;
11102                         phy->flags |= FLAGS_WC_DUAL_MODE;
11103                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11104                                            SUPPORTED_FIBRE |
11105                                            SUPPORTED_Pause |
11106                                            SUPPORTED_Asym_Pause);
11107                         break;
11108                 default:
11109                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11110                                        serdes_net_if);
11111                         break;
11112                 }
11113
11114                 /*
11115                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11116                  * was not set as expected. For B0, ECO will be enabled so there
11117                  * won't be an issue there
11118                  */
11119                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11120                         phy->flags |= FLAGS_MDC_MDIO_WA;
11121         } else {
11122                 switch (switch_cfg) {
11123                 case SWITCH_CFG_1G:
11124                         phy_addr = REG_RD(bp,
11125                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11126                                           port * 0x10);
11127                         *phy = phy_serdes;
11128                         break;
11129                 case SWITCH_CFG_10G:
11130                         phy_addr = REG_RD(bp,
11131                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11132                                           port * 0x18);
11133                         *phy = phy_xgxs;
11134                         break;
11135                 default:
11136                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11137                         return -EINVAL;
11138                 }
11139         }
11140         phy->addr = (u8)phy_addr;
11141         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11142                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11143                                             port);
11144         if (CHIP_IS_E2(bp))
11145                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11146         else
11147                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11148
11149         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11150                    port, phy->addr, phy->mdio_ctrl);
11151
11152         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11153         return 0;
11154 }
11155
11156 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11157                                   u8 phy_index,
11158                                   u32 shmem_base,
11159                                   u32 shmem2_base,
11160                                   u8 port,
11161                                   struct bnx2x_phy *phy)
11162 {
11163         u32 ext_phy_config, phy_type, config2;
11164         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11165         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11166                                                   phy_index, port);
11167         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11168         /* Select the phy type */
11169         switch (phy_type) {
11170         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11171                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11172                 *phy = phy_8073;
11173                 break;
11174         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11175                 *phy = phy_8705;
11176                 break;
11177         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11178                 *phy = phy_8706;
11179                 break;
11180         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11181                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11182                 *phy = phy_8726;
11183                 break;
11184         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11185                 /* BCM8727_NOC => BCM8727 no over current */
11186                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11187                 *phy = phy_8727;
11188                 phy->flags |= FLAGS_NOC;
11189                 break;
11190         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11191         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11192                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11193                 *phy = phy_8727;
11194                 break;
11195         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11196                 *phy = phy_8481;
11197                 break;
11198         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11199                 *phy = phy_84823;
11200                 break;
11201         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11202                 *phy = phy_84833;
11203                 break;
11204         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11205                 *phy = phy_54618se;
11206                 break;
11207         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11208                 *phy = phy_7101;
11209                 break;
11210         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11211                 *phy = phy_null;
11212                 return -EINVAL;
11213         default:
11214                 *phy = phy_null;
11215                 return 0;
11216         }
11217
11218         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11219         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11220
11221         /*
11222          * The shmem address of the phy version is located on different
11223          * structures. In case this structure is too old, do not set
11224          * the address
11225          */
11226         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11227                                         dev_info.shared_hw_config.config2));
11228         if (phy_index == EXT_PHY1) {
11229                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11230                                 port_mb[port].ext_phy_fw_version);
11231
11232                 /* Check specific mdc mdio settings */
11233                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11234                         mdc_mdio_access = config2 &
11235                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11236         } else {
11237                 u32 size = REG_RD(bp, shmem2_base);
11238
11239                 if (size >
11240                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11241                         phy->ver_addr = shmem2_base +
11242                             offsetof(struct shmem2_region,
11243                                      ext_phy_fw_version2[port]);
11244                 }
11245                 /* Check specific mdc mdio settings */
11246                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11247                         mdc_mdio_access = (config2 &
11248                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11249                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11250                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11251         }
11252         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11253
11254         /*
11255          * In case mdc/mdio_access of the external phy is different than the
11256          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11257          * to prevent one port interfere with another port's CL45 operations.
11258          */
11259         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11260                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11261         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11262                    phy_type, port, phy_index);
11263         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11264                    phy->addr, phy->mdio_ctrl);
11265         return 0;
11266 }
11267
11268 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11269                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11270 {
11271         int status = 0;
11272         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11273         if (phy_index == INT_PHY)
11274                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11275         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11276                                         port, phy);
11277         return status;
11278 }
11279
11280 static void bnx2x_phy_def_cfg(struct link_params *params,
11281                               struct bnx2x_phy *phy,
11282                               u8 phy_index)
11283 {
11284         struct bnx2x *bp = params->bp;
11285         u32 link_config;
11286         /* Populate the default phy configuration for MF mode */
11287         if (phy_index == EXT_PHY2) {
11288                 link_config = REG_RD(bp, params->shmem_base +
11289                                      offsetof(struct shmem_region, dev_info.
11290                         port_feature_config[params->port].link_config2));
11291                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11292                                              offsetof(struct shmem_region,
11293                                                       dev_info.
11294                         port_hw_config[params->port].speed_capability_mask2));
11295         } else {
11296                 link_config = REG_RD(bp, params->shmem_base +
11297                                      offsetof(struct shmem_region, dev_info.
11298                                 port_feature_config[params->port].link_config));
11299                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11300                                              offsetof(struct shmem_region,
11301                                                       dev_info.
11302                         port_hw_config[params->port].speed_capability_mask));
11303         }
11304         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11305                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11306
11307         phy->req_duplex = DUPLEX_FULL;
11308         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11309         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11310                 phy->req_duplex = DUPLEX_HALF;
11311         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11312                 phy->req_line_speed = SPEED_10;
11313                 break;
11314         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11315                 phy->req_duplex = DUPLEX_HALF;
11316         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11317                 phy->req_line_speed = SPEED_100;
11318                 break;
11319         case PORT_FEATURE_LINK_SPEED_1G:
11320                 phy->req_line_speed = SPEED_1000;
11321                 break;
11322         case PORT_FEATURE_LINK_SPEED_2_5G:
11323                 phy->req_line_speed = SPEED_2500;
11324                 break;
11325         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11326                 phy->req_line_speed = SPEED_10000;
11327                 break;
11328         default:
11329                 phy->req_line_speed = SPEED_AUTO_NEG;
11330                 break;
11331         }
11332
11333         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11334         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11335                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11336                 break;
11337         case PORT_FEATURE_FLOW_CONTROL_TX:
11338                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11339                 break;
11340         case PORT_FEATURE_FLOW_CONTROL_RX:
11341                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11342                 break;
11343         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11344                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11345                 break;
11346         default:
11347                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11348                 break;
11349         }
11350 }
11351
11352 u32 bnx2x_phy_selection(struct link_params *params)
11353 {
11354         u32 phy_config_swapped, prio_cfg;
11355         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11356
11357         phy_config_swapped = params->multi_phy_config &
11358                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11359
11360         prio_cfg = params->multi_phy_config &
11361                         PORT_HW_CFG_PHY_SELECTION_MASK;
11362
11363         if (phy_config_swapped) {
11364                 switch (prio_cfg) {
11365                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11366                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11367                      break;
11368                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11369                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11370                      break;
11371                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11372                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11373                      break;
11374                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11375                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11376                      break;
11377                 }
11378         } else
11379                 return_cfg = prio_cfg;
11380
11381         return return_cfg;
11382 }
11383
11384
11385 int bnx2x_phy_probe(struct link_params *params)
11386 {
11387         u8 phy_index, actual_phy_idx, link_cfg_idx;
11388         u32 phy_config_swapped, sync_offset, media_types;
11389         struct bnx2x *bp = params->bp;
11390         struct bnx2x_phy *phy;
11391         params->num_phys = 0;
11392         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11393         phy_config_swapped = params->multi_phy_config &
11394                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11395
11396         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11397               phy_index++) {
11398                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11399                 actual_phy_idx = phy_index;
11400                 if (phy_config_swapped) {
11401                         if (phy_index == EXT_PHY1)
11402                                 actual_phy_idx = EXT_PHY2;
11403                         else if (phy_index == EXT_PHY2)
11404                                 actual_phy_idx = EXT_PHY1;
11405                 }
11406                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11407                                " actual_phy_idx %x\n", phy_config_swapped,
11408                            phy_index, actual_phy_idx);
11409                 phy = &params->phy[actual_phy_idx];
11410                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11411                                        params->shmem2_base, params->port,
11412                                        phy) != 0) {
11413                         params->num_phys = 0;
11414                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11415                                    phy_index);
11416                         for (phy_index = INT_PHY;
11417                               phy_index < MAX_PHYS;
11418                               phy_index++)
11419                                 *phy = phy_null;
11420                         return -EINVAL;
11421                 }
11422                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11423                         break;
11424
11425                 sync_offset = params->shmem_base +
11426                         offsetof(struct shmem_region,
11427                         dev_info.port_hw_config[params->port].media_type);
11428                 media_types = REG_RD(bp, sync_offset);
11429
11430                 /*
11431                  * Update media type for non-PMF sync only for the first time
11432                  * In case the media type changes afterwards, it will be updated
11433                  * using the update_status function
11434                  */
11435                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11436                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11437                                      actual_phy_idx))) == 0) {
11438                         media_types |= ((phy->media_type &
11439                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11440                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11441                                  actual_phy_idx));
11442                 }
11443                 REG_WR(bp, sync_offset, media_types);
11444
11445                 bnx2x_phy_def_cfg(params, phy, phy_index);
11446                 params->num_phys++;
11447         }
11448
11449         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11450         return 0;
11451 }
11452
11453 void bnx2x_init_bmac_loopback(struct link_params *params,
11454                               struct link_vars *vars)
11455 {
11456         struct bnx2x *bp = params->bp;
11457                 vars->link_up = 1;
11458                 vars->line_speed = SPEED_10000;
11459                 vars->duplex = DUPLEX_FULL;
11460                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11461                 vars->mac_type = MAC_TYPE_BMAC;
11462
11463                 vars->phy_flags = PHY_XGXS_FLAG;
11464
11465                 bnx2x_xgxs_deassert(params);
11466
11467                 /* set bmac loopback */
11468                 bnx2x_bmac_enable(params, vars, 1);
11469
11470                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11471 }
11472
11473 void bnx2x_init_emac_loopback(struct link_params *params,
11474                               struct link_vars *vars)
11475 {
11476         struct bnx2x *bp = params->bp;
11477                 vars->link_up = 1;
11478                 vars->line_speed = SPEED_1000;
11479                 vars->duplex = DUPLEX_FULL;
11480                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11481                 vars->mac_type = MAC_TYPE_EMAC;
11482
11483                 vars->phy_flags = PHY_XGXS_FLAG;
11484
11485                 bnx2x_xgxs_deassert(params);
11486                 /* set bmac loopback */
11487                 bnx2x_emac_enable(params, vars, 1);
11488                 bnx2x_emac_program(params, vars);
11489                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11490 }
11491
11492 void bnx2x_init_xmac_loopback(struct link_params *params,
11493                               struct link_vars *vars)
11494 {
11495         struct bnx2x *bp = params->bp;
11496         vars->link_up = 1;
11497         if (!params->req_line_speed[0])
11498                 vars->line_speed = SPEED_10000;
11499         else
11500                 vars->line_speed = params->req_line_speed[0];
11501         vars->duplex = DUPLEX_FULL;
11502         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11503         vars->mac_type = MAC_TYPE_XMAC;
11504         vars->phy_flags = PHY_XGXS_FLAG;
11505         /*
11506          * Set WC to loopback mode since link is required to provide clock
11507          * to the XMAC in 20G mode
11508          */
11509         if (vars->line_speed == SPEED_20000) {
11510                 bnx2x_set_aer_mmd(params, &params->phy[0]);
11511                 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11512                 params->phy[INT_PHY].config_loopback(
11513                         &params->phy[INT_PHY],
11514                         params);
11515         }
11516         bnx2x_xmac_enable(params, vars, 1);
11517         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11518 }
11519
11520 void bnx2x_init_umac_loopback(struct link_params *params,
11521                               struct link_vars *vars)
11522 {
11523         struct bnx2x *bp = params->bp;
11524         vars->link_up = 1;
11525         vars->line_speed = SPEED_1000;
11526         vars->duplex = DUPLEX_FULL;
11527         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11528         vars->mac_type = MAC_TYPE_UMAC;
11529         vars->phy_flags = PHY_XGXS_FLAG;
11530         bnx2x_umac_enable(params, vars, 1);
11531
11532         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11533 }
11534
11535 void bnx2x_init_xgxs_loopback(struct link_params *params,
11536                               struct link_vars *vars)
11537 {
11538         struct bnx2x *bp = params->bp;
11539                 vars->link_up = 1;
11540                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11541                 vars->duplex = DUPLEX_FULL;
11542         if (params->req_line_speed[0] == SPEED_1000)
11543                         vars->line_speed = SPEED_1000;
11544         else
11545                         vars->line_speed = SPEED_10000;
11546
11547         if (!USES_WARPCORE(bp))
11548                 bnx2x_xgxs_deassert(params);
11549         bnx2x_link_initialize(params, vars);
11550
11551         if (params->req_line_speed[0] == SPEED_1000) {
11552                 if (USES_WARPCORE(bp))
11553                         bnx2x_umac_enable(params, vars, 0);
11554                 else {
11555                         bnx2x_emac_program(params, vars);
11556                         bnx2x_emac_enable(params, vars, 0);
11557                 }
11558         } else {
11559                 if (USES_WARPCORE(bp))
11560                         bnx2x_xmac_enable(params, vars, 0);
11561                 else
11562                         bnx2x_bmac_enable(params, vars, 0);
11563         }
11564
11565                 if (params->loopback_mode == LOOPBACK_XGXS) {
11566                         /* set 10G XGXS loopback */
11567                         params->phy[INT_PHY].config_loopback(
11568                                 &params->phy[INT_PHY],
11569                                 params);
11570
11571                 } else {
11572                         /* set external phy loopback */
11573                         u8 phy_index;
11574                         for (phy_index = EXT_PHY1;
11575                               phy_index < params->num_phys; phy_index++) {
11576                                 if (params->phy[phy_index].config_loopback)
11577                                         params->phy[phy_index].config_loopback(
11578                                                 &params->phy[phy_index],
11579                                                 params);
11580                         }
11581                 }
11582                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11583
11584         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11585 }
11586
11587 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11588 {
11589         struct bnx2x *bp = params->bp;
11590         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11591         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11592                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11593         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11594                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11595         vars->link_status = 0;
11596         vars->phy_link_up = 0;
11597         vars->link_up = 0;
11598         vars->line_speed = 0;
11599         vars->duplex = DUPLEX_FULL;
11600         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11601         vars->mac_type = MAC_TYPE_NONE;
11602         vars->phy_flags = 0;
11603
11604         /* disable attentions */
11605         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11606                        (NIG_MASK_XGXS0_LINK_STATUS |
11607                         NIG_MASK_XGXS0_LINK10G |
11608                         NIG_MASK_SERDES0_LINK_STATUS |
11609                         NIG_MASK_MI_INT));
11610
11611         bnx2x_emac_init(params, vars);
11612
11613         if (params->num_phys == 0) {
11614                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11615                 return -EINVAL;
11616         }
11617         set_phy_vars(params, vars);
11618
11619         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11620         switch (params->loopback_mode) {
11621         case LOOPBACK_BMAC:
11622                 bnx2x_init_bmac_loopback(params, vars);
11623                 break;
11624         case LOOPBACK_EMAC:
11625                 bnx2x_init_emac_loopback(params, vars);
11626                 break;
11627         case LOOPBACK_XMAC:
11628                 bnx2x_init_xmac_loopback(params, vars);
11629                 break;
11630         case LOOPBACK_UMAC:
11631                 bnx2x_init_umac_loopback(params, vars);
11632                 break;
11633         case LOOPBACK_XGXS:
11634         case LOOPBACK_EXT_PHY:
11635                 bnx2x_init_xgxs_loopback(params, vars);
11636                 break;
11637         default:
11638                 if (!CHIP_IS_E3(bp)) {
11639                         if (params->switch_cfg == SWITCH_CFG_10G)
11640                                 bnx2x_xgxs_deassert(params);
11641                         else
11642                                 bnx2x_serdes_deassert(bp, params->port);
11643                 }
11644                 bnx2x_link_initialize(params, vars);
11645                 msleep(30);
11646                 bnx2x_link_int_enable(params);
11647                 break;
11648         }
11649         return 0;
11650 }
11651
11652 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11653                      u8 reset_ext_phy)
11654 {
11655         struct bnx2x *bp = params->bp;
11656         u8 phy_index, port = params->port, clear_latch_ind = 0;
11657         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11658         /* disable attentions */
11659         vars->link_status = 0;
11660         bnx2x_update_mng(params, vars->link_status);
11661         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11662                        (NIG_MASK_XGXS0_LINK_STATUS |
11663                         NIG_MASK_XGXS0_LINK10G |
11664                         NIG_MASK_SERDES0_LINK_STATUS |
11665                         NIG_MASK_MI_INT));
11666
11667         /* activate nig drain */
11668         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11669
11670         /* disable nig egress interface */
11671         if (!CHIP_IS_E3(bp)) {
11672                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11673                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11674         }
11675
11676         /* Stop BigMac rx */
11677         if (!CHIP_IS_E3(bp))
11678                 bnx2x_bmac_rx_disable(bp, port);
11679         else
11680                 bnx2x_xmac_disable(params);
11681         /* disable emac */
11682         if (!CHIP_IS_E3(bp))
11683                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11684
11685         msleep(10);
11686         /* The PHY reset is controlled by GPIO 1
11687          * Hold it as vars low
11688          */
11689          /* clear link led */
11690         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11691
11692         if (reset_ext_phy) {
11693                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11694                       phy_index++) {
11695                         if (params->phy[phy_index].link_reset)
11696                                 params->phy[phy_index].link_reset(
11697                                         &params->phy[phy_index],
11698                                         params);
11699                         if (params->phy[phy_index].flags &
11700                             FLAGS_REARM_LATCH_SIGNAL)
11701                                 clear_latch_ind = 1;
11702                 }
11703         }
11704
11705         if (clear_latch_ind) {
11706                 /* Clear latching indication */
11707                 bnx2x_rearm_latch_signal(bp, port, 0);
11708                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11709                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11710         }
11711         if (params->phy[INT_PHY].link_reset)
11712                 params->phy[INT_PHY].link_reset(
11713                         &params->phy[INT_PHY], params);
11714         /* reset BigMac */
11715         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11716                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11717
11718         /* disable nig ingress interface */
11719         if (!CHIP_IS_E3(bp)) {
11720                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11721                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11722         }
11723         vars->link_up = 0;
11724         vars->phy_flags = 0;
11725         return 0;
11726 }
11727
11728 /****************************************************************************/
11729 /*                              Common function                             */
11730 /****************************************************************************/
11731 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11732                                       u32 shmem_base_path[],
11733                                       u32 shmem2_base_path[], u8 phy_index,
11734                                       u32 chip_id)
11735 {
11736         struct bnx2x_phy phy[PORT_MAX];
11737         struct bnx2x_phy *phy_blk[PORT_MAX];
11738         u16 val;
11739         s8 port = 0;
11740         s8 port_of_path = 0;
11741         u32 swap_val, swap_override;
11742         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11743         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11744         port ^= (swap_val && swap_override);
11745         bnx2x_ext_phy_hw_reset(bp, port);
11746         /* PART1 - Reset both phys */
11747         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11748                 u32 shmem_base, shmem2_base;
11749                 /* In E2, same phy is using for port0 of the two paths */
11750                 if (CHIP_IS_E1x(bp)) {
11751                         shmem_base = shmem_base_path[0];
11752                         shmem2_base = shmem2_base_path[0];
11753                         port_of_path = port;
11754                 } else {
11755                         shmem_base = shmem_base_path[port];
11756                         shmem2_base = shmem2_base_path[port];
11757                         port_of_path = 0;
11758                 }
11759
11760                 /* Extract the ext phy address for the port */
11761                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11762                                        port_of_path, &phy[port]) !=
11763                     0) {
11764                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11765                         return -EINVAL;
11766                 }
11767                 /* disable attentions */
11768                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11769                                port_of_path*4,
11770                                (NIG_MASK_XGXS0_LINK_STATUS |
11771                                 NIG_MASK_XGXS0_LINK10G |
11772                                 NIG_MASK_SERDES0_LINK_STATUS |
11773                                 NIG_MASK_MI_INT));
11774
11775                 /* Need to take the phy out of low power mode in order
11776                         to write to access its registers */
11777                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11778                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11779                                port);
11780
11781                 /* Reset the phy */
11782                 bnx2x_cl45_write(bp, &phy[port],
11783                                  MDIO_PMA_DEVAD,
11784                                  MDIO_PMA_REG_CTRL,
11785                                  1<<15);
11786         }
11787
11788         /* Add delay of 150ms after reset */
11789         msleep(150);
11790
11791         if (phy[PORT_0].addr & 0x1) {
11792                 phy_blk[PORT_0] = &(phy[PORT_1]);
11793                 phy_blk[PORT_1] = &(phy[PORT_0]);
11794         } else {
11795                 phy_blk[PORT_0] = &(phy[PORT_0]);
11796                 phy_blk[PORT_1] = &(phy[PORT_1]);
11797         }
11798
11799         /* PART2 - Download firmware to both phys */
11800         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11801                 if (CHIP_IS_E1x(bp))
11802                         port_of_path = port;
11803                 else
11804                         port_of_path = 0;
11805
11806                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11807                            phy_blk[port]->addr);
11808                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11809                                                       port_of_path))
11810                         return -EINVAL;
11811
11812                 /* Only set bit 10 = 1 (Tx power down) */
11813                 bnx2x_cl45_read(bp, phy_blk[port],
11814                                 MDIO_PMA_DEVAD,
11815                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11816
11817                 /* Phase1 of TX_POWER_DOWN reset */
11818                 bnx2x_cl45_write(bp, phy_blk[port],
11819                                  MDIO_PMA_DEVAD,
11820                                  MDIO_PMA_REG_TX_POWER_DOWN,
11821                                  (val | 1<<10));
11822         }
11823
11824         /*
11825          * Toggle Transmitter: Power down and then up with 600ms delay
11826          * between
11827          */
11828         msleep(600);
11829
11830         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11831         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11832                 /* Phase2 of POWER_DOWN_RESET */
11833                 /* Release bit 10 (Release Tx power down) */
11834                 bnx2x_cl45_read(bp, phy_blk[port],
11835                                 MDIO_PMA_DEVAD,
11836                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11837
11838                 bnx2x_cl45_write(bp, phy_blk[port],
11839                                 MDIO_PMA_DEVAD,
11840                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11841                 msleep(15);
11842
11843                 /* Read modify write the SPI-ROM version select register */
11844                 bnx2x_cl45_read(bp, phy_blk[port],
11845                                 MDIO_PMA_DEVAD,
11846                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11847                 bnx2x_cl45_write(bp, phy_blk[port],
11848                                  MDIO_PMA_DEVAD,
11849                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11850
11851                 /* set GPIO2 back to LOW */
11852                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11853                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11854         }
11855         return 0;
11856 }
11857 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11858                                       u32 shmem_base_path[],
11859                                       u32 shmem2_base_path[], u8 phy_index,
11860                                       u32 chip_id)
11861 {
11862         u32 val;
11863         s8 port;
11864         struct bnx2x_phy phy;
11865         /* Use port1 because of the static port-swap */
11866         /* Enable the module detection interrupt */
11867         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11868         val |= ((1<<MISC_REGISTERS_GPIO_3)|
11869                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11870         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11871
11872         bnx2x_ext_phy_hw_reset(bp, 0);
11873         msleep(5);
11874         for (port = 0; port < PORT_MAX; port++) {
11875                 u32 shmem_base, shmem2_base;
11876
11877                 /* In E2, same phy is using for port0 of the two paths */
11878                 if (CHIP_IS_E1x(bp)) {
11879                         shmem_base = shmem_base_path[0];
11880                         shmem2_base = shmem2_base_path[0];
11881                 } else {
11882                         shmem_base = shmem_base_path[port];
11883                         shmem2_base = shmem2_base_path[port];
11884                 }
11885                 /* Extract the ext phy address for the port */
11886                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11887                                        port, &phy) !=
11888                     0) {
11889                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11890                         return -EINVAL;
11891                 }
11892
11893                 /* Reset phy*/
11894                 bnx2x_cl45_write(bp, &phy,
11895                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11896
11897
11898                 /* Set fault module detected LED on */
11899                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11900                                MISC_REGISTERS_GPIO_HIGH,
11901                                port);
11902         }
11903
11904         return 0;
11905 }
11906 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11907                                          u8 *io_gpio, u8 *io_port)
11908 {
11909
11910         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11911                                           offsetof(struct shmem_region,
11912                                 dev_info.port_hw_config[PORT_0].default_cfg));
11913         switch (phy_gpio_reset) {
11914         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11915                 *io_gpio = 0;
11916                 *io_port = 0;
11917                 break;
11918         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11919                 *io_gpio = 1;
11920                 *io_port = 0;
11921                 break;
11922         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11923                 *io_gpio = 2;
11924                 *io_port = 0;
11925                 break;
11926         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11927                 *io_gpio = 3;
11928                 *io_port = 0;
11929                 break;
11930         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11931                 *io_gpio = 0;
11932                 *io_port = 1;
11933                 break;
11934         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11935                 *io_gpio = 1;
11936                 *io_port = 1;
11937                 break;
11938         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11939                 *io_gpio = 2;
11940                 *io_port = 1;
11941                 break;
11942         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11943                 *io_gpio = 3;
11944                 *io_port = 1;
11945                 break;
11946         default:
11947                 /* Don't override the io_gpio and io_port */
11948                 break;
11949         }
11950 }
11951
11952 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11953                                       u32 shmem_base_path[],
11954                                       u32 shmem2_base_path[], u8 phy_index,
11955                                       u32 chip_id)
11956 {
11957         s8 port, reset_gpio;
11958         u32 swap_val, swap_override;
11959         struct bnx2x_phy phy[PORT_MAX];
11960         struct bnx2x_phy *phy_blk[PORT_MAX];
11961         s8 port_of_path;
11962         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11963         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11964
11965         reset_gpio = MISC_REGISTERS_GPIO_1;
11966         port = 1;
11967
11968         /*
11969          * Retrieve the reset gpio/port which control the reset.
11970          * Default is GPIO1, PORT1
11971          */
11972         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11973                                      (u8 *)&reset_gpio, (u8 *)&port);
11974
11975         /* Calculate the port based on port swap */
11976         port ^= (swap_val && swap_override);
11977
11978         /* Initiate PHY reset*/
11979         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11980                        port);
11981         msleep(1);
11982         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11983                        port);
11984
11985         msleep(5);
11986
11987         /* PART1 - Reset both phys */
11988         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11989                 u32 shmem_base, shmem2_base;
11990
11991                 /* In E2, same phy is using for port0 of the two paths */
11992                 if (CHIP_IS_E1x(bp)) {
11993                         shmem_base = shmem_base_path[0];
11994                         shmem2_base = shmem2_base_path[0];
11995                         port_of_path = port;
11996                 } else {
11997                         shmem_base = shmem_base_path[port];
11998                         shmem2_base = shmem2_base_path[port];
11999                         port_of_path = 0;
12000                 }
12001
12002                 /* Extract the ext phy address for the port */
12003                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12004                                        port_of_path, &phy[port]) !=
12005                                        0) {
12006                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12007                         return -EINVAL;
12008                 }
12009                 /* disable attentions */
12010                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12011                                port_of_path*4,
12012                                (NIG_MASK_XGXS0_LINK_STATUS |
12013                                 NIG_MASK_XGXS0_LINK10G |
12014                                 NIG_MASK_SERDES0_LINK_STATUS |
12015                                 NIG_MASK_MI_INT));
12016
12017
12018                 /* Reset the phy */
12019                 bnx2x_cl45_write(bp, &phy[port],
12020                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12021         }
12022
12023         /* Add delay of 150ms after reset */
12024         msleep(150);
12025         if (phy[PORT_0].addr & 0x1) {
12026                 phy_blk[PORT_0] = &(phy[PORT_1]);
12027                 phy_blk[PORT_1] = &(phy[PORT_0]);
12028         } else {
12029                 phy_blk[PORT_0] = &(phy[PORT_0]);
12030                 phy_blk[PORT_1] = &(phy[PORT_1]);
12031         }
12032         /* PART2 - Download firmware to both phys */
12033         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12034                 if (CHIP_IS_E1x(bp))
12035                         port_of_path = port;
12036                 else
12037                         port_of_path = 0;
12038                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12039                            phy_blk[port]->addr);
12040                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12041                                                       port_of_path))
12042                         return -EINVAL;
12043                 /* Disable PHY transmitter output */
12044                 bnx2x_cl45_write(bp, phy_blk[port],
12045                                  MDIO_PMA_DEVAD,
12046                                  MDIO_PMA_REG_TX_DISABLE, 1);
12047
12048         }
12049         return 0;
12050 }
12051
12052 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12053                                      u32 shmem2_base_path[], u8 phy_index,
12054                                      u32 ext_phy_type, u32 chip_id)
12055 {
12056         int rc = 0;
12057
12058         switch (ext_phy_type) {
12059         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12060                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12061                                                 shmem2_base_path,
12062                                                 phy_index, chip_id);
12063                 break;
12064         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12065         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12066         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12067                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12068                                                 shmem2_base_path,
12069                                                 phy_index, chip_id);
12070                 break;
12071
12072         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12073                 /*
12074                  * GPIO1 affects both ports, so there's need to pull
12075                  * it for single port alone
12076                  */
12077                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12078                                                 shmem2_base_path,
12079                                                 phy_index, chip_id);
12080                 break;
12081         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12082                 /*
12083                  * GPIO3's are linked, and so both need to be toggled
12084                  * to obtain required 2us pulse.
12085                  */
12086                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12087                 break;
12088         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12089                 rc = -EINVAL;
12090                 break;
12091         default:
12092                 DP(NETIF_MSG_LINK,
12093                            "ext_phy 0x%x common init not required\n",
12094                            ext_phy_type);
12095                 break;
12096         }
12097
12098         if (rc != 0)
12099                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12100                                       " Port %d\n",
12101                          0);
12102         return rc;
12103 }
12104
12105 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12106                           u32 shmem2_base_path[], u32 chip_id)
12107 {
12108         int rc = 0;
12109         u32 phy_ver, val;
12110         u8 phy_index = 0;
12111         u32 ext_phy_type, ext_phy_config;
12112         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12113         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12114         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12115         if (CHIP_IS_E3(bp)) {
12116                 /* Enable EPIO */
12117                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12118                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12119         }
12120         /* Check if common init was already done */
12121         phy_ver = REG_RD(bp, shmem_base_path[0] +
12122                          offsetof(struct shmem_region,
12123                                   port_mb[PORT_0].ext_phy_fw_version));
12124         if (phy_ver) {
12125                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12126                                phy_ver);
12127                 return 0;
12128         }
12129
12130         /* Read the ext_phy_type for arbitrary port(0) */
12131         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12132               phy_index++) {
12133                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12134                                                           shmem_base_path[0],
12135                                                           phy_index, 0);
12136                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12137                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12138                                                 shmem2_base_path,
12139                                                 phy_index, ext_phy_type,
12140                                                 chip_id);
12141         }
12142         return rc;
12143 }
12144
12145 static void bnx2x_check_over_curr(struct link_params *params,
12146                                   struct link_vars *vars)
12147 {
12148         struct bnx2x *bp = params->bp;
12149         u32 cfg_pin;
12150         u8 port = params->port;
12151         u32 pin_val;
12152
12153         cfg_pin = (REG_RD(bp, params->shmem_base +
12154                           offsetof(struct shmem_region,
12155                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12156                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12157                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12158
12159         /* Ignore check if no external input PIN available */
12160         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12161                 return;
12162
12163         if (!pin_val) {
12164                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12165                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12166                                             " been detected and the power to "
12167                                             "that SFP+ module has been removed"
12168                                             " to prevent failure of the card."
12169                                             " Please remove the SFP+ module and"
12170                                             " restart the system to clear this"
12171                                             " error.\n",
12172                          params->port);
12173                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12174                 }
12175         } else
12176                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12177 }
12178
12179 static void bnx2x_analyze_link_error(struct link_params *params,
12180                                      struct link_vars *vars, u32 lss_status)
12181 {
12182         struct bnx2x *bp = params->bp;
12183         /* Compare new value with previous value */
12184         u8 led_mode;
12185         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12186
12187         /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
12188                        vars->link_up,
12189                        half_open_conn, lss_status);*/
12190
12191         if ((lss_status ^ half_open_conn) == 0)
12192                 return;
12193
12194         /* If values differ */
12195         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12196                        half_open_conn, lss_status);
12197
12198         /*
12199          * a. Update shmem->link_status accordingly
12200          * b. Update link_vars->link_up
12201          */
12202         if (lss_status) {
12203                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12204                 vars->link_up = 0;
12205                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12206                 /*
12207                  * Set LED mode to off since the PHY doesn't know about these
12208                  * errors
12209                  */
12210                 led_mode = LED_MODE_OFF;
12211         } else {
12212                 vars->link_status |= LINK_STATUS_LINK_UP;
12213                 vars->link_up = 1;
12214                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12215                 led_mode = LED_MODE_OPER;
12216         }
12217         /* Update the LED according to the link state */
12218         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12219
12220         /* Update link status in the shared memory */
12221         bnx2x_update_mng(params, vars->link_status);
12222
12223         /* C. Trigger General Attention */
12224         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12225         bnx2x_notify_link_changed(bp);
12226 }
12227
12228 static void bnx2x_check_half_open_conn(struct link_params *params,
12229                                        struct link_vars *vars)
12230 {
12231         struct bnx2x *bp = params->bp;
12232         u32 lss_status = 0;
12233         u32 mac_base;
12234         /* In case link status is physically up @ 10G do */
12235         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12236                 return;
12237
12238         if (!CHIP_IS_E3(bp) &&
12239             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12240                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12241                 /* Check E1X / E2 BMAC */
12242                 u32 lss_status_reg;
12243                 u32 wb_data[2];
12244                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12245                         NIG_REG_INGRESS_BMAC0_MEM;
12246                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12247                 if (CHIP_IS_E2(bp))
12248                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12249                 else
12250                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12251
12252                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12253                 lss_status = (wb_data[0] > 0);
12254
12255                 bnx2x_analyze_link_error(params, vars, lss_status);
12256         }
12257 }
12258
12259 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12260 {
12261         struct bnx2x *bp = params->bp;
12262         if (!params) {
12263                 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12264                 return;
12265         }
12266         /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12267          RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12268           REG_RD(bp, MISC_REG_RESET_REG_2)); */
12269         bnx2x_check_half_open_conn(params, vars);
12270         if (CHIP_IS_E3(bp))
12271                 bnx2x_check_over_curr(params, vars);
12272 }
12273
12274 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12275 {
12276         u8 phy_index;
12277         struct bnx2x_phy phy;
12278         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12279               phy_index++) {
12280                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12281                                        0, &phy) != 0) {
12282                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12283                         return 0;
12284                 }
12285
12286                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12287                         return 1;
12288         }
12289         return 0;
12290 }
12291
12292 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12293                              u32 shmem_base,
12294                              u32 shmem2_base,
12295                              u8 port)
12296 {
12297         u8 phy_index, fan_failure_det_req = 0;
12298         struct bnx2x_phy phy;
12299         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12300               phy_index++) {
12301                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12302                                        port, &phy)
12303                     != 0) {
12304                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12305                         return 0;
12306                 }
12307                 fan_failure_det_req |= (phy.flags &
12308                                         FLAGS_FAN_FAILURE_DET_REQ);
12309         }
12310         return fan_failure_det_req;
12311 }
12312
12313 void bnx2x_hw_reset_phy(struct link_params *params)
12314 {
12315         u8 phy_index;
12316         struct bnx2x *bp = params->bp;
12317         bnx2x_update_mng(params, 0);
12318         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12319                        (NIG_MASK_XGXS0_LINK_STATUS |
12320                         NIG_MASK_XGXS0_LINK10G |
12321                         NIG_MASK_SERDES0_LINK_STATUS |
12322                         NIG_MASK_MI_INT));
12323
12324         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12325               phy_index++) {
12326                 if (params->phy[phy_index].hw_reset) {
12327                         params->phy[phy_index].hw_reset(
12328                                 &params->phy[phy_index],
12329                                 params);
12330                         params->phy[phy_index] = phy_null;
12331                 }
12332         }
12333 }
12334
12335 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12336                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12337                             u8 port)
12338 {
12339         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12340         u32 val;
12341         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12342         if (CHIP_IS_E3(bp)) {
12343                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12344                                               shmem_base,
12345                                               port,
12346                                               &gpio_num,
12347                                               &gpio_port) != 0)
12348                         return;
12349         } else {
12350                 struct bnx2x_phy phy;
12351                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12352                       phy_index++) {
12353                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12354                                                shmem2_base, port, &phy)
12355                             != 0) {
12356                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12357                                 return;
12358                         }
12359                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12360                                 gpio_num = MISC_REGISTERS_GPIO_3;
12361                                 gpio_port = port;
12362                                 break;
12363                         }
12364                 }
12365         }
12366
12367         if (gpio_num == 0xff)
12368                 return;
12369
12370         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12371         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12372
12373         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12374         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12375         gpio_port ^= (swap_val && swap_override);
12376
12377         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12378                 (gpio_num + (gpio_port << 2));
12379
12380         sync_offset = shmem_base +
12381                 offsetof(struct shmem_region,
12382                          dev_info.port_hw_config[port].aeu_int_mask);
12383         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12384
12385         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12386                        gpio_num, gpio_port, vars->aeu_int_mask);
12387
12388         if (port == 0)
12389                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12390         else
12391                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12392
12393         /* Open appropriate AEU for interrupts */
12394         aeu_mask = REG_RD(bp, offset);
12395         aeu_mask |= vars->aeu_int_mask;
12396         REG_WR(bp, offset, aeu_mask);
12397
12398         /* Enable the GPIO to trigger interrupt */
12399         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12400         val |= 1 << (gpio_num + (gpio_port << 2));
12401         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12402 }