drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0,
  55         MCC_STATUS_FAILED = 1,
  56         MCC_STATUS_ILLEGAL_REQUEST = 2,
  57         MCC_STATUS_ILLEGAL_FIELD = 3,
  58         MCC_STATUS_INSUFFICIENT_BUFFER = 4,
  59         MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
  60         MCC_STATUS_NOT_SUPPORTED = 66
  61 };
  62
  63 #define CQE_STATUS_COMPL_MASK           0xFFFF
  64 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  65 #define CQE_STATUS_EXTD_MASK            0xFFFF
  66 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  67
  68 struct be_mcc_compl {
  69         u32 status;             /* dword 0 */
  70         u32 tag0;               /* dword 1 */
  71         u32 tag1;               /* dword 2 */
  72         u32 flags;              /* dword 3 */
  73 };
  74
  75 /* When the async bit of mcc_compl is set, the last 4 bytes of
  76  * mcc_compl is interpreted as follows:
  77  */
  78 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  79 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  80 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT  16
  81 #define ASYNC_TRAILER_EVENT_TYPE_MASK   0xFF
  82 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  83 #define ASYNC_EVENT_CODE_GRP_5          0x5
  84 #define ASYNC_EVENT_QOS_SPEED           0x1
  85 #define ASYNC_EVENT_COS_PRIORITY        0x2
  86 #define ASYNC_EVENT_PVID_STATE          0x3
  87 struct be_async_event_trailer {
  88         u32 code;
  89 };
  90
  91 enum {
  92         LINK_DOWN       = 0x0,
  93         LINK_UP         = 0x1
  94 };
  95 #define LINK_STATUS_MASK                        0x1
  96
  97 /* When the event code of an async trailer is link-state, the mcc_compl
  98  * must be interpreted as follows
  99  */
 100 struct be_async_event_link_state {
 101         u8 physical_port;
 102         u8 port_link_status;
 103         u8 port_duplex;
 104         u8 port_speed;
 105         u8 port_fault;
 106         u8 rsvd0[7];
 107         struct be_async_event_trailer trailer;
 108 } __packed;
 109
 110 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
 111  * the mcc_compl must be interpreted as follows
 112  */
 113 struct be_async_event_grp5_qos_link_speed {
 114         u8 physical_port;
 115         u8 rsvd[5];
 116         u16 qos_link_speed;
 117         u32 event_tag;
 118         struct be_async_event_trailer trailer;
 119 } __packed;
 120
 121 /* When the event code of an async trailer is GRP5 and event type is
 122  * CoS-Priority, the mcc_compl must be interpreted as follows
 123  */
 124 struct be_async_event_grp5_cos_priority {
 125         u8 physical_port;
 126         u8 available_priority_bmap;
 127         u8 reco_default_priority;
 128         u8 valid;
 129         u8 rsvd0;
 130         u8 event_tag;
 131         struct be_async_event_trailer trailer;
 132 } __packed;
 133
 134 /* When the event code of an async trailer is GRP5 and event type is
 135  * PVID state, the mcc_compl must be interpreted as follows
 136  */
 137 struct be_async_event_grp5_pvid_state {
 138         u8 enabled;
 139         u8 rsvd0;
 140         u16 tag;
 141         u32 event_tag;
 142         u32 rsvd1;
 143         struct be_async_event_trailer trailer;
 144 } __packed;
 145
 146 struct be_mcc_mailbox {
 147         struct be_mcc_wrb wrb;
 148         struct be_mcc_compl compl;
 149 };
 150
 151 #define CMD_SUBSYSTEM_COMMON    0x1
 152 #define CMD_SUBSYSTEM_ETH       0x3
 153 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 154
 155 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 156 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 157 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 158 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 159 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 160 #define OPCODE_COMMON_READ_FLASHROM                     6
 161 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 162 #define OPCODE_COMMON_CQ_CREATE                         12
 163 #define OPCODE_COMMON_EQ_CREATE                         13
 164 #define OPCODE_COMMON_MCC_CREATE                        21
 165 #define OPCODE_COMMON_SET_QOS                           28
 166 #define OPCODE_COMMON_MCC_CREATE_EXT                    90
 167 #define OPCODE_COMMON_SEEPROM_READ                      30
 168 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES               32
 169 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 170 #define OPCODE_COMMON_GET_FW_VERSION                    35
 171 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 172 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 173 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 174 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 175 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 176 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 177 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 178 #define OPCODE_COMMON_MCC_DESTROY                       53
 179 #define OPCODE_COMMON_CQ_DESTROY                        54
 180 #define OPCODE_COMMON_EQ_DESTROY                        55
 181 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 182 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 183 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 184 #define OPCODE_COMMON_FUNCTION_RESET                    61
 185 #define OPCODE_COMMON_MANAGE_FAT                        68
 186 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 187 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 188 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 189 #define OPCODE_COMMON_GET_PHY_DETAILS                   102
 190 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP           103
 191 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES    121
 192 #define OPCODE_COMMON_WRITE_OBJECT                      172
 193
 194 #define OPCODE_ETH_RSS_CONFIG                           1
 195 #define OPCODE_ETH_ACPI_CONFIG                          2
 196 #define OPCODE_ETH_PROMISCUOUS                          3
 197 #define OPCODE_ETH_GET_STATISTICS                       4
 198 #define OPCODE_ETH_TX_CREATE                            7
 199 #define OPCODE_ETH_RX_CREATE                            8
 200 #define OPCODE_ETH_TX_DESTROY                           9
 201 #define OPCODE_ETH_RX_DESTROY                           10
 202 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 203 #define OPCODE_ETH_GET_PPORT_STATS                      18
 204
 205 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 206 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 207 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE               19
 208
 209 struct be_cmd_req_hdr {
 210         u8 opcode;              /* dword 0 */
 211         u8 subsystem;           /* dword 0 */
 212         u8 port_number;         /* dword 0 */
 213         u8 domain;              /* dword 0 */
 214         u32 timeout;            /* dword 1 */
 215         u32 request_length;     /* dword 2 */
 216         u8 version;             /* dword 3 */
 217         u8 rsvd[3];             /* dword 3 */
 218 };
 219
 220 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 221 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 222 struct be_cmd_resp_hdr {
 223         u32 info;               /* dword 0 */
 224         u32 status;             /* dword 1 */
 225         u32 response_length;    /* dword 2 */
 226         u32 actual_resp_len;    /* dword 3 */
 227 };
 228
 229 struct phys_addr {
 230         u32 lo;
 231         u32 hi;
 232 };
 233
 234 /**************************
 235  * BE Command definitions *
 236  **************************/
 237
 238 /* Pseudo amap definition in which each bit of the actual structure is defined
 239  * as a byte: used to calculate offset/shift/mask of each field */
 240 struct amap_eq_context {
 241         u8 cidx[13];            /* dword 0*/
 242         u8 rsvd0[3];            /* dword 0*/
 243         u8 epidx[13];           /* dword 0*/
 244         u8 valid;               /* dword 0*/
 245         u8 rsvd1;               /* dword 0*/
 246         u8 size;                /* dword 0*/
 247         u8 pidx[13];            /* dword 1*/
 248         u8 rsvd2[3];            /* dword 1*/
 249         u8 pd[10];              /* dword 1*/
 250         u8 count[3];            /* dword 1*/
 251         u8 solevent;            /* dword 1*/
 252         u8 stalled;             /* dword 1*/
 253         u8 armed;               /* dword 1*/
 254         u8 rsvd3[4];            /* dword 2*/
 255         u8 func[8];             /* dword 2*/
 256         u8 rsvd4;               /* dword 2*/
 257         u8 delaymult[10];       /* dword 2*/
 258         u8 rsvd5[2];            /* dword 2*/
 259         u8 phase[2];            /* dword 2*/
 260         u8 nodelay;             /* dword 2*/
 261         u8 rsvd6[4];            /* dword 2*/
 262         u8 rsvd7[32];           /* dword 3*/
 263 } __packed;
 264
 265 struct be_cmd_req_eq_create {
 266         struct be_cmd_req_hdr hdr;
 267         u16 num_pages;          /* sword */
 268         u16 rsvd0;              /* sword */
 269         u8 context[sizeof(struct amap_eq_context) / 8];
 270         struct phys_addr pages[8];
 271 } __packed;
 272
 273 struct be_cmd_resp_eq_create {
 274         struct be_cmd_resp_hdr resp_hdr;
 275         u16 eq_id;              /* sword */
 276         u16 rsvd0;              /* sword */
 277 } __packed;
 278
 279 /******************** Mac query ***************************/
 280 enum {
 281         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 282         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 283         MAC_ADDRESS_TYPE_PD = 0x2,
 284         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 285 };
 286
 287 struct mac_addr {
 288         u16 size_of_struct;
 289         u8 addr[ETH_ALEN];
 290 } __packed;
 291
 292 struct be_cmd_req_mac_query {
 293         struct be_cmd_req_hdr hdr;
 294         u8 type;
 295         u8 permanent;
 296         u16 if_id;
 297 } __packed;
 298
 299 struct be_cmd_resp_mac_query {
 300         struct be_cmd_resp_hdr hdr;
 301         struct mac_addr mac;
 302 };
 303
 304 /******************** PMac Add ***************************/
 305 struct be_cmd_req_pmac_add {
 306         struct be_cmd_req_hdr hdr;
 307         u32 if_id;
 308         u8 mac_address[ETH_ALEN];
 309         u8 rsvd0[2];
 310 } __packed;
 311
 312 struct be_cmd_resp_pmac_add {
 313         struct be_cmd_resp_hdr hdr;
 314         u32 pmac_id;
 315 };
 316
 317 /******************** PMac Del ***************************/
 318 struct be_cmd_req_pmac_del {
 319         struct be_cmd_req_hdr hdr;
 320         u32 if_id;
 321         u32 pmac_id;
 322 };
 323
 324 /******************** Create CQ ***************************/
 325 /* Pseudo amap definition in which each bit of the actual structure is defined
 326  * as a byte: used to calculate offset/shift/mask of each field */
 327 struct amap_cq_context_be {
 328         u8 cidx[11];            /* dword 0*/
 329         u8 rsvd0;               /* dword 0*/
 330         u8 coalescwm[2];        /* dword 0*/
 331         u8 nodelay;             /* dword 0*/
 332         u8 epidx[11];           /* dword 0*/
 333         u8 rsvd1;               /* dword 0*/
 334         u8 count[2];            /* dword 0*/
 335         u8 valid;               /* dword 0*/
 336         u8 solevent;            /* dword 0*/
 337         u8 eventable;           /* dword 0*/
 338         u8 pidx[11];            /* dword 1*/
 339         u8 rsvd2;               /* dword 1*/
 340         u8 pd[10];              /* dword 1*/
 341         u8 eqid[8];             /* dword 1*/
 342         u8 stalled;             /* dword 1*/
 343         u8 armed;               /* dword 1*/
 344         u8 rsvd3[4];            /* dword 2*/
 345         u8 func[8];             /* dword 2*/
 346         u8 rsvd4[20];           /* dword 2*/
 347         u8 rsvd5[32];           /* dword 3*/
 348 } __packed;
 349
 350 struct amap_cq_context_lancer {
 351         u8 rsvd0[12];           /* dword 0*/
 352         u8 coalescwm[2];        /* dword 0*/
 353         u8 nodelay;             /* dword 0*/
 354         u8 rsvd1[12];           /* dword 0*/
 355         u8 count[2];            /* dword 0*/
 356         u8 valid;               /* dword 0*/
 357         u8 rsvd2;               /* dword 0*/
 358         u8 eventable;           /* dword 0*/
 359         u8 eqid[16];            /* dword 1*/
 360         u8 rsvd3[15];           /* dword 1*/
 361         u8 armed;               /* dword 1*/
 362         u8 rsvd4[32];           /* dword 2*/
 363         u8 rsvd5[32];           /* dword 3*/
 364 } __packed;
 365
 366 struct be_cmd_req_cq_create {
 367         struct be_cmd_req_hdr hdr;
 368         u16 num_pages;
 369         u8 page_size;
 370         u8 rsvd0;
 371         u8 context[sizeof(struct amap_cq_context_be) / 8];
 372         struct phys_addr pages[8];
 373 } __packed;
 374
 375
 376 struct be_cmd_resp_cq_create {
 377         struct be_cmd_resp_hdr hdr;
 378         u16 cq_id;
 379         u16 rsvd0;
 380 } __packed;
 381
 382 struct be_cmd_req_get_fat {
 383         struct be_cmd_req_hdr hdr;
 384         u32 fat_operation;
 385         u32 read_log_offset;
 386         u32 read_log_length;
 387         u32 data_buffer_size;
 388         u32 data_buffer[1];
 389 } __packed;
 390
 391 struct be_cmd_resp_get_fat {
 392         struct be_cmd_resp_hdr hdr;
 393         u32 log_size;
 394         u32 read_log_length;
 395         u32 rsvd[2];
 396         u32 data_buffer[1];
 397 } __packed;
 398
 399
 400 /******************** Create MCCQ ***************************/
 401 /* Pseudo amap definition in which each bit of the actual structure is defined
 402  * as a byte: used to calculate offset/shift/mask of each field */
 403 struct amap_mcc_context_be {
 404         u8 con_index[14];
 405         u8 rsvd0[2];
 406         u8 ring_size[4];
 407         u8 fetch_wrb;
 408         u8 fetch_r2t;
 409         u8 cq_id[10];
 410         u8 prod_index[14];
 411         u8 fid[8];
 412         u8 pdid[9];
 413         u8 valid;
 414         u8 rsvd1[32];
 415         u8 rsvd2[32];
 416 } __packed;
 417
 418 struct amap_mcc_context_lancer {
 419         u8 async_cq_id[16];
 420         u8 ring_size[4];
 421         u8 rsvd0[12];
 422         u8 rsvd1[31];
 423         u8 valid;
 424         u8 async_cq_valid[1];
 425         u8 rsvd2[31];
 426         u8 rsvd3[32];
 427 } __packed;
 428
 429 struct be_cmd_req_mcc_create {
 430         struct be_cmd_req_hdr hdr;
 431         u16 num_pages;
 432         u16 cq_id;
 433         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 434         struct phys_addr pages[8];
 435 } __packed;
 436
 437 struct be_cmd_req_mcc_ext_create {
 438         struct be_cmd_req_hdr hdr;
 439         u16 num_pages;
 440         u16 cq_id;
 441         u32 async_event_bitmap[1];
 442         u8 context[sizeof(struct amap_mcc_context_be) / 8];
 443         struct phys_addr pages[8];
 444 } __packed;
 445
 446 struct be_cmd_resp_mcc_create {
 447         struct be_cmd_resp_hdr hdr;
 448         u16 id;
 449         u16 rsvd0;
 450 } __packed;
 451
 452 /******************** Create TxQ ***************************/
 453 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 454 #define BE_ULP1_NUM                             1
 455
 456 /* Pseudo amap definition in which each bit of the actual structure is defined
 457  * as a byte: used to calculate offset/shift/mask of each field */
 458 struct amap_tx_context {
 459         u8 if_id[16];           /* dword 0 */
 460         u8 tx_ring_size[4];     /* dword 0 */
 461         u8 rsvd1[26];           /* dword 0 */
 462         u8 pci_func_id[8];      /* dword 1 */
 463         u8 rsvd2[9];            /* dword 1 */
 464         u8 ctx_valid;           /* dword 1 */
 465         u8 cq_id_send[16];      /* dword 2 */
 466         u8 rsvd3[16];           /* dword 2 */
 467         u8 rsvd4[32];           /* dword 3 */
 468         u8 rsvd5[32];           /* dword 4 */
 469         u8 rsvd6[32];           /* dword 5 */
 470         u8 rsvd7[32];           /* dword 6 */
 471         u8 rsvd8[32];           /* dword 7 */
 472         u8 rsvd9[32];           /* dword 8 */
 473         u8 rsvd10[32];          /* dword 9 */
 474         u8 rsvd11[32];          /* dword 10 */
 475         u8 rsvd12[32];          /* dword 11 */
 476         u8 rsvd13[32];          /* dword 12 */
 477         u8 rsvd14[32];          /* dword 13 */
 478         u8 rsvd15[32];          /* dword 14 */
 479         u8 rsvd16[32];          /* dword 15 */
 480 } __packed;
 481
 482 struct be_cmd_req_eth_tx_create {
 483         struct be_cmd_req_hdr hdr;
 484         u8 num_pages;
 485         u8 ulp_num;
 486         u8 type;
 487         u8 bound_port;
 488         u8 context[sizeof(struct amap_tx_context) / 8];
 489         struct phys_addr pages[8];
 490 } __packed;
 491
 492 struct be_cmd_resp_eth_tx_create {
 493         struct be_cmd_resp_hdr hdr;
 494         u16 cid;
 495         u16 rsvd0;
 496 } __packed;
 497
 498 /******************** Create RxQ ***************************/
 499 struct be_cmd_req_eth_rx_create {
 500         struct be_cmd_req_hdr hdr;
 501         u16 cq_id;
 502         u8 frag_size;
 503         u8 num_pages;
 504         struct phys_addr pages[2];
 505         u32 interface_id;
 506         u16 max_frame_size;
 507         u16 rsvd0;
 508         u32 rss_queue;
 509 } __packed;
 510
 511 struct be_cmd_resp_eth_rx_create {
 512         struct be_cmd_resp_hdr hdr;
 513         u16 id;
 514         u8 rss_id;
 515         u8 rsvd0;
 516 } __packed;
 517
 518 /******************** Q Destroy  ***************************/
 519 /* Type of Queue to be destroyed */
 520 enum {
 521         QTYPE_EQ = 1,
 522         QTYPE_CQ,
 523         QTYPE_TXQ,
 524         QTYPE_RXQ,
 525         QTYPE_MCCQ
 526 };
 527
 528 struct be_cmd_req_q_destroy {
 529         struct be_cmd_req_hdr hdr;
 530         u16 id;
 531         u16 bypass_flush;       /* valid only for rx q destroy */
 532 } __packed;
 533
 534 /************ I/f Create (it's actually I/f Config Create)**********/
 535
 536 /* Capability flags for the i/f */
 537 enum be_if_flags {
 538         BE_IF_FLAGS_RSS = 0x4,
 539         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 540         BE_IF_FLAGS_BROADCAST = 0x10,
 541         BE_IF_FLAGS_UNTAGGED = 0x20,
 542         BE_IF_FLAGS_ULP = 0x40,
 543         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 544         BE_IF_FLAGS_VLAN = 0x100,
 545         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 546         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 547         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
 548         BE_IF_FLAGS_MULTICAST = 0x1000
 549 };
 550
 551 /* An RX interface is an object with one or more MAC addresses and
 552  * filtering capabilities. */
 553 struct be_cmd_req_if_create {
 554         struct be_cmd_req_hdr hdr;
 555         u32 version;            /* ignore currently */
 556         u32 capability_flags;
 557         u32 enable_flags;
 558         u8 mac_addr[ETH_ALEN];
 559         u8 rsvd0;
 560         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 561         u32 vlan_tag;    /* not used currently */
 562 } __packed;
 563
 564 struct be_cmd_resp_if_create {
 565         struct be_cmd_resp_hdr hdr;
 566         u32 interface_id;
 567         u32 pmac_id;
 568 };
 569
 570 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 571 struct be_cmd_req_if_destroy {
 572         struct be_cmd_req_hdr hdr;
 573         u32 interface_id;
 574 };
 575
 576 /*************** HW Stats Get **********************************/
 577 struct be_port_rxf_stats_v0 {
 578         u32 rx_bytes_lsd;       /* dword 0*/
 579         u32 rx_bytes_msd;       /* dword 1*/
 580         u32 rx_total_frames;    /* dword 2*/
 581         u32 rx_unicast_frames;  /* dword 3*/
 582         u32 rx_multicast_frames;        /* dword 4*/
 583         u32 rx_broadcast_frames;        /* dword 5*/
 584         u32 rx_crc_errors;      /* dword 6*/
 585         u32 rx_alignment_symbol_errors; /* dword 7*/
 586         u32 rx_pause_frames;    /* dword 8*/
 587         u32 rx_control_frames;  /* dword 9*/
 588         u32 rx_in_range_errors; /* dword 10*/
 589         u32 rx_out_range_errors;        /* dword 11*/
 590         u32 rx_frame_too_long;  /* dword 12*/
 591         u32 rx_address_match_errors;    /* dword 13*/
 592         u32 rx_vlan_mismatch;   /* dword 14*/
 593         u32 rx_dropped_too_small;       /* dword 15*/
 594         u32 rx_dropped_too_short;       /* dword 16*/
 595         u32 rx_dropped_header_too_small;        /* dword 17*/
 596         u32 rx_dropped_tcp_length;      /* dword 18*/
 597         u32 rx_dropped_runt;    /* dword 19*/
 598         u32 rx_64_byte_packets; /* dword 20*/
 599         u32 rx_65_127_byte_packets;     /* dword 21*/
 600         u32 rx_128_256_byte_packets;    /* dword 22*/
 601         u32 rx_256_511_byte_packets;    /* dword 23*/
 602         u32 rx_512_1023_byte_packets;   /* dword 24*/
 603         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 604         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 605         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 606         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 607         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 608         u32 rx_ip_checksum_errs;        /* dword 30*/
 609         u32 rx_tcp_checksum_errs;       /* dword 31*/
 610         u32 rx_udp_checksum_errs;       /* dword 32*/
 611         u32 rx_non_rss_packets; /* dword 33*/
 612         u32 rx_ipv4_packets;    /* dword 34*/
 613         u32 rx_ipv6_packets;    /* dword 35*/
 614         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 615         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 616         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 617         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 618         u32 rx_chute1_packets;  /* dword 40*/
 619         u32 rx_chute2_packets;  /* dword 41*/
 620         u32 rx_chute3_packets;  /* dword 42*/
 621         u32 rx_management_packets;      /* dword 43*/
 622         u32 rx_switched_unicast_packets;        /* dword 44*/
 623         u32 rx_switched_multicast_packets;      /* dword 45*/
 624         u32 rx_switched_broadcast_packets;      /* dword 46*/
 625         u32 tx_bytes_lsd;       /* dword 47*/
 626         u32 tx_bytes_msd;       /* dword 48*/
 627         u32 tx_unicastframes;   /* dword 49*/
 628         u32 tx_multicastframes; /* dword 50*/
 629         u32 tx_broadcastframes; /* dword 51*/
 630         u32 tx_pauseframes;     /* dword 52*/
 631         u32 tx_controlframes;   /* dword 53*/
 632         u32 tx_64_byte_packets; /* dword 54*/
 633         u32 tx_65_127_byte_packets;     /* dword 55*/
 634         u32 tx_128_256_byte_packets;    /* dword 56*/
 635         u32 tx_256_511_byte_packets;    /* dword 57*/
 636         u32 tx_512_1023_byte_packets;   /* dword 58*/
 637         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 638         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 639         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 640         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 641         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 642         u32 rx_fifo_overflow;   /* dword 64*/
 643         u32 rx_input_fifo_overflow;     /* dword 65*/
 644 };
 645
 646 struct be_rxf_stats_v0 {
 647         struct be_port_rxf_stats_v0 port[2];
 648         u32 rx_drops_no_pbuf;   /* dword 132*/
 649         u32 rx_drops_no_txpb;   /* dword 133*/
 650         u32 rx_drops_no_erx_descr;      /* dword 134*/
 651         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 652         u32 management_rx_port_packets; /* dword 136*/
 653         u32 management_rx_port_bytes;   /* dword 137*/
 654         u32 management_rx_port_pause_frames;    /* dword 138*/
 655         u32 management_rx_port_errors;  /* dword 139*/
 656         u32 management_tx_port_packets; /* dword 140*/
 657         u32 management_tx_port_bytes;   /* dword 141*/
 658         u32 management_tx_port_pause;   /* dword 142*/
 659         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 660         u32 rx_drops_too_many_frags;    /* dword 144*/
 661         u32 rx_drops_invalid_ring;      /* dword 145*/
 662         u32 forwarded_packets;  /* dword 146*/
 663         u32 rx_drops_mtu;       /* dword 147*/
 664         u32 rsvd0[7];
 665         u32 port0_jabber_events;
 666         u32 port1_jabber_events;
 667         u32 rsvd1[6];
 668 };
 669
 670 struct be_erx_stats_v0 {
 671         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 672         u32 rsvd[4];
 673 };
 674
 675 struct be_pmem_stats {
 676         u32 eth_red_drops;
 677         u32 rsvd[5];
 678 };
 679
 680 struct be_hw_stats_v0 {
 681         struct be_rxf_stats_v0 rxf;
 682         u32 rsvd[48];
 683         struct be_erx_stats_v0 erx;
 684         struct be_pmem_stats pmem;
 685 };
 686
 687 struct be_cmd_req_get_stats_v0 {
 688         struct be_cmd_req_hdr hdr;
 689         u8 rsvd[sizeof(struct be_hw_stats_v0)];
 690 };
 691
 692 struct be_cmd_resp_get_stats_v0 {
 693         struct be_cmd_resp_hdr hdr;
 694         struct be_hw_stats_v0 hw_stats;
 695 };
 696
 697 struct lancer_pport_stats {
 698         u32 tx_packets_lo;
 699         u32 tx_packets_hi;
 700         u32 tx_unicast_packets_lo;
 701         u32 tx_unicast_packets_hi;
 702         u32 tx_multicast_packets_lo;
 703         u32 tx_multicast_packets_hi;
 704         u32 tx_broadcast_packets_lo;
 705         u32 tx_broadcast_packets_hi;
 706         u32 tx_bytes_lo;
 707         u32 tx_bytes_hi;
 708         u32 tx_unicast_bytes_lo;
 709         u32 tx_unicast_bytes_hi;
 710         u32 tx_multicast_bytes_lo;
 711         u32 tx_multicast_bytes_hi;
 712         u32 tx_broadcast_bytes_lo;
 713         u32 tx_broadcast_bytes_hi;
 714         u32 tx_discards_lo;
 715         u32 tx_discards_hi;
 716         u32 tx_errors_lo;
 717         u32 tx_errors_hi;
 718         u32 tx_pause_frames_lo;
 719         u32 tx_pause_frames_hi;
 720         u32 tx_pause_on_frames_lo;
 721         u32 tx_pause_on_frames_hi;
 722         u32 tx_pause_off_frames_lo;
 723         u32 tx_pause_off_frames_hi;
 724         u32 tx_internal_mac_errors_lo;
 725         u32 tx_internal_mac_errors_hi;
 726         u32 tx_control_frames_lo;
 727         u32 tx_control_frames_hi;
 728         u32 tx_packets_64_bytes_lo;
 729         u32 tx_packets_64_bytes_hi;
 730         u32 tx_packets_65_to_127_bytes_lo;
 731         u32 tx_packets_65_to_127_bytes_hi;
 732         u32 tx_packets_128_to_255_bytes_lo;
 733         u32 tx_packets_128_to_255_bytes_hi;
 734         u32 tx_packets_256_to_511_bytes_lo;
 735         u32 tx_packets_256_to_511_bytes_hi;
 736         u32 tx_packets_512_to_1023_bytes_lo;
 737         u32 tx_packets_512_to_1023_bytes_hi;
 738         u32 tx_packets_1024_to_1518_bytes_lo;
 739         u32 tx_packets_1024_to_1518_bytes_hi;
 740         u32 tx_packets_1519_to_2047_bytes_lo;
 741         u32 tx_packets_1519_to_2047_bytes_hi;
 742         u32 tx_packets_2048_to_4095_bytes_lo;
 743         u32 tx_packets_2048_to_4095_bytes_hi;
 744         u32 tx_packets_4096_to_8191_bytes_lo;
 745         u32 tx_packets_4096_to_8191_bytes_hi;
 746         u32 tx_packets_8192_to_9216_bytes_lo;
 747         u32 tx_packets_8192_to_9216_bytes_hi;
 748         u32 tx_lso_packets_lo;
 749         u32 tx_lso_packets_hi;
 750         u32 rx_packets_lo;
 751         u32 rx_packets_hi;
 752         u32 rx_unicast_packets_lo;
 753         u32 rx_unicast_packets_hi;
 754         u32 rx_multicast_packets_lo;
 755         u32 rx_multicast_packets_hi;
 756         u32 rx_broadcast_packets_lo;
 757         u32 rx_broadcast_packets_hi;
 758         u32 rx_bytes_lo;
 759         u32 rx_bytes_hi;
 760         u32 rx_unicast_bytes_lo;
 761         u32 rx_unicast_bytes_hi;
 762         u32 rx_multicast_bytes_lo;
 763         u32 rx_multicast_bytes_hi;
 764         u32 rx_broadcast_bytes_lo;
 765         u32 rx_broadcast_bytes_hi;
 766         u32 rx_unknown_protos;
 767         u32 rsvd_69; /* Word 69 is reserved */
 768         u32 rx_discards_lo;
 769         u32 rx_discards_hi;
 770         u32 rx_errors_lo;
 771         u32 rx_errors_hi;
 772         u32 rx_crc_errors_lo;
 773         u32 rx_crc_errors_hi;
 774         u32 rx_alignment_errors_lo;
 775         u32 rx_alignment_errors_hi;
 776         u32 rx_symbol_errors_lo;
 777         u32 rx_symbol_errors_hi;
 778         u32 rx_pause_frames_lo;
 779         u32 rx_pause_frames_hi;
 780         u32 rx_pause_on_frames_lo;
 781         u32 rx_pause_on_frames_hi;
 782         u32 rx_pause_off_frames_lo;
 783         u32 rx_pause_off_frames_hi;
 784         u32 rx_frames_too_long_lo;
 785         u32 rx_frames_too_long_hi;
 786         u32 rx_internal_mac_errors_lo;
 787         u32 rx_internal_mac_errors_hi;
 788         u32 rx_undersize_packets;
 789         u32 rx_oversize_packets;
 790         u32 rx_fragment_packets;
 791         u32 rx_jabbers;
 792         u32 rx_control_frames_lo;
 793         u32 rx_control_frames_hi;
 794         u32 rx_control_frames_unknown_opcode_lo;
 795         u32 rx_control_frames_unknown_opcode_hi;
 796         u32 rx_in_range_errors;
 797         u32 rx_out_of_range_errors;
 798         u32 rx_address_match_errors;
 799         u32 rx_vlan_mismatch_errors;
 800         u32 rx_dropped_too_small;
 801         u32 rx_dropped_too_short;
 802         u32 rx_dropped_header_too_small;
 803         u32 rx_dropped_invalid_tcp_length;
 804         u32 rx_dropped_runt;
 805         u32 rx_ip_checksum_errors;
 806         u32 rx_tcp_checksum_errors;
 807         u32 rx_udp_checksum_errors;
 808         u32 rx_non_rss_packets;
 809         u32 rsvd_111;
 810         u32 rx_ipv4_packets_lo;
 811         u32 rx_ipv4_packets_hi;
 812         u32 rx_ipv6_packets_lo;
 813         u32 rx_ipv6_packets_hi;
 814         u32 rx_ipv4_bytes_lo;
 815         u32 rx_ipv4_bytes_hi;
 816         u32 rx_ipv6_bytes_lo;
 817         u32 rx_ipv6_bytes_hi;
 818         u32 rx_nic_packets_lo;
 819         u32 rx_nic_packets_hi;
 820         u32 rx_tcp_packets_lo;
 821         u32 rx_tcp_packets_hi;
 822         u32 rx_iscsi_packets_lo;
 823         u32 rx_iscsi_packets_hi;
 824         u32 rx_management_packets_lo;
 825         u32 rx_management_packets_hi;
 826         u32 rx_switched_unicast_packets_lo;
 827         u32 rx_switched_unicast_packets_hi;
 828         u32 rx_switched_multicast_packets_lo;
 829         u32 rx_switched_multicast_packets_hi;
 830         u32 rx_switched_broadcast_packets_lo;
 831         u32 rx_switched_broadcast_packets_hi;
 832         u32 num_forwards_lo;
 833         u32 num_forwards_hi;
 834         u32 rx_fifo_overflow;
 835         u32 rx_input_fifo_overflow;
 836         u32 rx_drops_too_many_frags_lo;
 837         u32 rx_drops_too_many_frags_hi;
 838         u32 rx_drops_invalid_queue;
 839         u32 rsvd_141;
 840         u32 rx_drops_mtu_lo;
 841         u32 rx_drops_mtu_hi;
 842         u32 rx_packets_64_bytes_lo;
 843         u32 rx_packets_64_bytes_hi;
 844         u32 rx_packets_65_to_127_bytes_lo;
 845         u32 rx_packets_65_to_127_bytes_hi;
 846         u32 rx_packets_128_to_255_bytes_lo;
 847         u32 rx_packets_128_to_255_bytes_hi;
 848         u32 rx_packets_256_to_511_bytes_lo;
 849         u32 rx_packets_256_to_511_bytes_hi;
 850         u32 rx_packets_512_to_1023_bytes_lo;
 851         u32 rx_packets_512_to_1023_bytes_hi;
 852         u32 rx_packets_1024_to_1518_bytes_lo;
 853         u32 rx_packets_1024_to_1518_bytes_hi;
 854         u32 rx_packets_1519_to_2047_bytes_lo;
 855         u32 rx_packets_1519_to_2047_bytes_hi;
 856         u32 rx_packets_2048_to_4095_bytes_lo;
 857         u32 rx_packets_2048_to_4095_bytes_hi;
 858         u32 rx_packets_4096_to_8191_bytes_lo;
 859         u32 rx_packets_4096_to_8191_bytes_hi;
 860         u32 rx_packets_8192_to_9216_bytes_lo;
 861         u32 rx_packets_8192_to_9216_bytes_hi;
 862 };
 863
 864 struct pport_stats_params {
 865         u16 pport_num;
 866         u8 rsvd;
 867         u8 reset_stats;
 868 };
 869
 870 struct lancer_cmd_req_pport_stats {
 871         struct be_cmd_req_hdr hdr;
 872         union {
 873                 struct pport_stats_params params;
 874                 u8 rsvd[sizeof(struct lancer_pport_stats)];
 875         } cmd_params;
 876 };
 877
 878 struct lancer_cmd_resp_pport_stats {
 879         struct be_cmd_resp_hdr hdr;
 880         struct lancer_pport_stats pport_stats;
 881 };
 882
 883 static inline struct lancer_pport_stats*
 884         pport_stats_from_cmd(struct be_adapter *adapter)
 885 {
 886         struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
 887         return &cmd->pport_stats;
 888 }
 889
 890 struct be_cmd_req_get_cntl_addnl_attribs {
 891         struct be_cmd_req_hdr hdr;
 892         u8 rsvd[8];
 893 };
 894
 895 struct be_cmd_resp_get_cntl_addnl_attribs {
 896         struct be_cmd_resp_hdr hdr;
 897         u16 ipl_file_number;
 898         u8 ipl_file_version;
 899         u8 rsvd0;
 900         u8 on_die_temperature; /* in degrees centigrade*/
 901         u8 rsvd1[3];
 902 };
 903
 904 struct be_cmd_req_vlan_config {
 905         struct be_cmd_req_hdr hdr;
 906         u8 interface_id;
 907         u8 promiscuous;
 908         u8 untagged;
 909         u8 num_vlan;
 910         u16 normal_vlan[64];
 911 } __packed;
 912
 913 /******************* RX FILTER ******************************/
 914 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 915 struct macaddr {
 916         u8 byte[ETH_ALEN];
 917 };
 918
 919 struct be_cmd_req_rx_filter {
 920         struct be_cmd_req_hdr hdr;
 921         u32 global_flags_mask;
 922         u32 global_flags;
 923         u32 if_flags_mask;
 924         u32 if_flags;
 925         u32 if_id;
 926         u32 mcast_num;
 927         struct macaddr mcast_mac[BE_MAX_MC];
 928 };
 929
 930 /******************** Link Status Query *******************/
 931 struct be_cmd_req_link_status {
 932         struct be_cmd_req_hdr hdr;
 933         u32 rsvd;
 934 };
 935
 936 enum {
 937         PHY_LINK_DUPLEX_NONE = 0x0,
 938         PHY_LINK_DUPLEX_HALF = 0x1,
 939         PHY_LINK_DUPLEX_FULL = 0x2
 940 };
 941
 942 enum {
 943         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 944         PHY_LINK_SPEED_10MBPS = 0x1,
 945         PHY_LINK_SPEED_100MBPS = 0x2,
 946         PHY_LINK_SPEED_1GBPS = 0x3,
 947         PHY_LINK_SPEED_10GBPS = 0x4
 948 };
 949
 950 struct be_cmd_resp_link_status {
 951         struct be_cmd_resp_hdr hdr;
 952         u8 physical_port;
 953         u8 mac_duplex;
 954         u8 mac_speed;
 955         u8 mac_fault;
 956         u8 mgmt_mac_duplex;
 957         u8 mgmt_mac_speed;
 958         u16 link_speed;
 959         u32 rsvd0;
 960 } __packed;
 961
 962 /******************** Port Identification ***************************/
 963 /*    Identifies the type of port attached to NIC     */
 964 struct be_cmd_req_port_type {
 965         struct be_cmd_req_hdr hdr;
 966         u32 page_num;
 967         u32 port;
 968 };
 969
 970 enum {
 971         TR_PAGE_A0 = 0xa0,
 972         TR_PAGE_A2 = 0xa2
 973 };
 974
 975 struct be_cmd_resp_port_type {
 976         struct be_cmd_resp_hdr hdr;
 977         u32 page_num;
 978         u32 port;
 979         struct data {
 980                 u8 identifier;
 981                 u8 identifier_ext;
 982                 u8 connector;
 983                 u8 transceiver[8];
 984                 u8 rsvd0[3];
 985                 u8 length_km;
 986                 u8 length_hm;
 987                 u8 length_om1;
 988                 u8 length_om2;
 989                 u8 length_cu;
 990                 u8 length_cu_m;
 991                 u8 vendor_name[16];
 992                 u8 rsvd;
 993                 u8 vendor_oui[3];
 994                 u8 vendor_pn[16];
 995                 u8 vendor_rev[4];
 996         } data;
 997 };
 998
 999 /******************** Get FW Version *******************/
1000 struct be_cmd_req_get_fw_version {
1001         struct be_cmd_req_hdr hdr;
1002         u8 rsvd0[FW_VER_LEN];
1003         u8 rsvd1[FW_VER_LEN];
1004 } __packed;
1005
1006 struct be_cmd_resp_get_fw_version {
1007         struct be_cmd_resp_hdr hdr;
1008         u8 firmware_version_string[FW_VER_LEN];
1009         u8 fw_on_flash_version_string[FW_VER_LEN];
1010 } __packed;
1011
1012 /******************** Set Flow Contrl *******************/
1013 struct be_cmd_req_set_flow_control {
1014         struct be_cmd_req_hdr hdr;
1015         u16 tx_flow_control;
1016         u16 rx_flow_control;
1017 } __packed;
1018
1019 /******************** Get Flow Contrl *******************/
1020 struct be_cmd_req_get_flow_control {
1021         struct be_cmd_req_hdr hdr;
1022         u32 rsvd;
1023 };
1024
1025 struct be_cmd_resp_get_flow_control {
1026         struct be_cmd_resp_hdr hdr;
1027         u16 tx_flow_control;
1028         u16 rx_flow_control;
1029 } __packed;
1030
1031 /******************** Modify EQ Delay *******************/
1032 struct be_cmd_req_modify_eq_delay {
1033         struct be_cmd_req_hdr hdr;
1034         u32 num_eq;
1035         struct {
1036                 u32 eq_id;
1037                 u32 phase;
1038                 u32 delay_multiplier;
1039         } delay[8];
1040 } __packed;
1041
1042 struct be_cmd_resp_modify_eq_delay {
1043         struct be_cmd_resp_hdr hdr;
1044         u32 rsvd0;
1045 } __packed;
1046
1047 /******************** Get FW Config *******************/
1048 #define BE_FUNCTION_CAPS_RSS                    0x2
1049 struct be_cmd_req_query_fw_cfg {
1050         struct be_cmd_req_hdr hdr;
1051         u32 rsvd[31];
1052 };
1053
1054 struct be_cmd_resp_query_fw_cfg {
1055         struct be_cmd_resp_hdr hdr;
1056         u32 be_config_number;
1057         u32 asic_revision;
1058         u32 phys_port;
1059         u32 function_mode;
1060         u32 rsvd[26];
1061         u32 function_caps;
1062 };
1063
1064 /******************** RSS Config *******************/
1065 /* RSS types */
1066 #define RSS_ENABLE_NONE                         0x0
1067 #define RSS_ENABLE_IPV4                         0x1
1068 #define RSS_ENABLE_TCP_IPV4                     0x2
1069 #define RSS_ENABLE_IPV6                         0x4
1070 #define RSS_ENABLE_TCP_IPV6                     0x8
1071
1072 struct be_cmd_req_rss_config {
1073         struct be_cmd_req_hdr hdr;
1074         u32 if_id;
1075         u16 enable_rss;
1076         u16 cpu_table_size_log2;
1077         u32 hash[10];
1078         u8 cpu_table[128];
1079         u8 flush;
1080         u8 rsvd0[3];
1081 };
1082
1083 /******************** Port Beacon ***************************/
1084
1085 #define BEACON_STATE_ENABLED            0x1
1086 #define BEACON_STATE_DISABLED           0x0
1087
1088 struct be_cmd_req_enable_disable_beacon {
1089         struct be_cmd_req_hdr hdr;
1090         u8  port_num;
1091         u8  beacon_state;
1092         u8  beacon_duration;
1093         u8  status_duration;
1094 } __packed;
1095
1096 struct be_cmd_resp_enable_disable_beacon {
1097         struct be_cmd_resp_hdr resp_hdr;
1098         u32 rsvd0;
1099 } __packed;
1100
1101 struct be_cmd_req_get_beacon_state {
1102         struct be_cmd_req_hdr hdr;
1103         u8  port_num;
1104         u8  rsvd0;
1105         u16 rsvd1;
1106 } __packed;
1107
1108 struct be_cmd_resp_get_beacon_state {
1109         struct be_cmd_resp_hdr resp_hdr;
1110         u8 beacon_state;
1111         u8 rsvd0[3];
1112 } __packed;
1113
1114 /****************** Firmware Flash ******************/
1115 struct flashrom_params {
1116         u32 op_code;
1117         u32 op_type;
1118         u32 data_buf_size;
1119         u32 offset;
1120         u8 data_buf[4];
1121 };
1122
1123 struct be_cmd_write_flashrom {
1124         struct be_cmd_req_hdr hdr;
1125         struct flashrom_params params;
1126 };
1127
1128 /**************** Lancer Firmware Flash ************/
1129 struct amap_lancer_write_obj_context {
1130         u8 write_length[24];
1131         u8 reserved1[7];
1132         u8 eof;
1133 } __packed;
1134
1135 struct lancer_cmd_req_write_object {
1136         struct be_cmd_req_hdr hdr;
1137         u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1138         u32 write_offset;
1139         u8 object_name[104];
1140         u32 descriptor_count;
1141         u32 buf_len;
1142         u32 addr_low;
1143         u32 addr_high;
1144 };
1145
1146 struct lancer_cmd_resp_write_object {
1147         u8 opcode;
1148         u8 subsystem;
1149         u8 rsvd1[2];
1150         u8 status;
1151         u8 additional_status;
1152         u8 rsvd2[2];
1153         u32 resp_len;
1154         u32 actual_resp_len;
1155         u32 actual_write_len;
1156 };
1157
1158 /************************ WOL *******************************/
1159 struct be_cmd_req_acpi_wol_magic_config{
1160         struct be_cmd_req_hdr hdr;
1161         u32 rsvd0[145];
1162         u8 magic_mac[6];
1163         u8 rsvd2[2];
1164 } __packed;
1165
1166 /********************** LoopBack test *********************/
1167 struct be_cmd_req_loopback_test {
1168         struct be_cmd_req_hdr hdr;
1169         u32 loopback_type;
1170         u32 num_pkts;
1171         u64 pattern;
1172         u32 src_port;
1173         u32 dest_port;
1174         u32 pkt_size;
1175 };
1176
1177 struct be_cmd_resp_loopback_test {
1178         struct be_cmd_resp_hdr resp_hdr;
1179         u32    status;
1180         u32    num_txfer;
1181         u32    num_rx;
1182         u32    miscomp_off;
1183         u32    ticks_compl;
1184 };
1185
1186 struct be_cmd_req_set_lmode {
1187         struct be_cmd_req_hdr hdr;
1188         u8 src_port;
1189         u8 dest_port;
1190         u8 loopback_type;
1191         u8 loopback_state;
1192 };
1193
1194 struct be_cmd_resp_set_lmode {
1195         struct be_cmd_resp_hdr resp_hdr;
1196         u8 rsvd0[4];
1197 };
1198
1199 /********************** DDR DMA test *********************/
1200 struct be_cmd_req_ddrdma_test {
1201         struct be_cmd_req_hdr hdr;
1202         u64 pattern;
1203         u32 byte_count;
1204         u32 rsvd0;
1205         u8  snd_buff[4096];
1206         u8  rsvd1[4096];
1207 };
1208
1209 struct be_cmd_resp_ddrdma_test {
1210         struct be_cmd_resp_hdr hdr;
1211         u64 pattern;
1212         u32 byte_cnt;
1213         u32 snd_err;
1214         u8  rsvd0[4096];
1215         u8  rcv_buff[4096];
1216 };
1217
1218 /*********************** SEEPROM Read ***********************/
1219
1220 #define BE_READ_SEEPROM_LEN 1024
1221 struct be_cmd_req_seeprom_read {
1222         struct be_cmd_req_hdr hdr;
1223         u8 rsvd0[BE_READ_SEEPROM_LEN];
1224 };
1225
1226 struct be_cmd_resp_seeprom_read {
1227         struct be_cmd_req_hdr hdr;
1228         u8 seeprom_data[BE_READ_SEEPROM_LEN];
1229 };
1230
1231 enum {
1232         PHY_TYPE_CX4_10GB = 0,
1233         PHY_TYPE_XFP_10GB,
1234         PHY_TYPE_SFP_1GB,
1235         PHY_TYPE_SFP_PLUS_10GB,
1236         PHY_TYPE_KR_10GB,
1237         PHY_TYPE_KX4_10GB,
1238         PHY_TYPE_BASET_10GB,
1239         PHY_TYPE_BASET_1GB,
1240         PHY_TYPE_DISABLED = 255
1241 };
1242
1243 struct be_cmd_req_get_phy_info {
1244         struct be_cmd_req_hdr hdr;
1245         u8 rsvd0[24];
1246 };
1247
1248 struct be_phy_info {
1249         u16 phy_type;
1250         u16 interface_type;
1251         u32 misc_params;
1252         u32 future_use[4];
1253 };
1254
1255 struct be_cmd_resp_get_phy_info {
1256         struct be_cmd_req_hdr hdr;
1257         struct be_phy_info phy_info;
1258 };
1259
1260 /*********************** Set QOS ***********************/
1261
1262 #define BE_QOS_BITS_NIC                         1
1263
1264 struct be_cmd_req_set_qos {
1265         struct be_cmd_req_hdr hdr;
1266         u32 valid_bits;
1267         u32 max_bps_nic;
1268         u32 rsvd[7];
1269 };
1270
1271 struct be_cmd_resp_set_qos {
1272         struct be_cmd_resp_hdr hdr;
1273         u32 rsvd;
1274 };
1275
1276 /*********************** Controller Attributes ***********************/
1277 struct be_cmd_req_cntl_attribs {
1278         struct be_cmd_req_hdr hdr;
1279 };
1280
1281 struct be_cmd_resp_cntl_attribs {
1282         struct be_cmd_resp_hdr hdr;
1283         struct mgmt_controller_attrib attribs;
1284 };
1285
1286 /*********************** Set driver function ***********************/
1287 #define CAPABILITY_SW_TIMESTAMPS        2
1288 #define CAPABILITY_BE3_NATIVE_ERX_API   4
1289
1290 struct be_cmd_req_set_func_cap {
1291         struct be_cmd_req_hdr hdr;
1292         u32 valid_cap_flags;
1293         u32 cap_flags;
1294         u8 rsvd[212];
1295 };
1296
1297 struct be_cmd_resp_set_func_cap {
1298         struct be_cmd_resp_hdr hdr;
1299         u32 valid_cap_flags;
1300         u32 cap_flags;
1301         u8 rsvd[212];
1302 };
1303
1304 /*************** HW Stats Get v1 **********************************/
1305 #define BE_TXP_SW_SZ                    48
1306 struct be_port_rxf_stats_v1 {
1307         u32 rsvd0[12];
1308         u32 rx_crc_errors;
1309         u32 rx_alignment_symbol_errors;
1310         u32 rx_pause_frames;
1311         u32 rx_priority_pause_frames;
1312         u32 rx_control_frames;
1313         u32 rx_in_range_errors;
1314         u32 rx_out_range_errors;
1315         u32 rx_frame_too_long;
1316         u32 rx_address_match_errors;
1317         u32 rx_dropped_too_small;
1318         u32 rx_dropped_too_short;
1319         u32 rx_dropped_header_too_small;
1320         u32 rx_dropped_tcp_length;
1321         u32 rx_dropped_runt;
1322         u32 rsvd1[10];
1323         u32 rx_ip_checksum_errs;
1324         u32 rx_tcp_checksum_errs;
1325         u32 rx_udp_checksum_errs;
1326         u32 rsvd2[7];
1327         u32 rx_switched_unicast_packets;
1328         u32 rx_switched_multicast_packets;
1329         u32 rx_switched_broadcast_packets;
1330         u32 rsvd3[3];
1331         u32 tx_pauseframes;
1332         u32 tx_priority_pauseframes;
1333         u32 tx_controlframes;
1334         u32 rsvd4[10];
1335         u32 rxpp_fifo_overflow_drop;
1336         u32 rx_input_fifo_overflow_drop;
1337         u32 pmem_fifo_overflow_drop;
1338         u32 jabber_events;
1339         u32 rsvd5[3];
1340 };
1341
1342
1343 struct be_rxf_stats_v1 {
1344         struct be_port_rxf_stats_v1 port[4];
1345         u32 rsvd0[2];
1346         u32 rx_drops_no_pbuf;
1347         u32 rx_drops_no_txpb;
1348         u32 rx_drops_no_erx_descr;
1349         u32 rx_drops_no_tpre_descr;
1350         u32 rsvd1[6];
1351         u32 rx_drops_too_many_frags;
1352         u32 rx_drops_invalid_ring;
1353         u32 forwarded_packets;
1354         u32 rx_drops_mtu;
1355         u32 rsvd2[14];
1356 };
1357
1358 struct be_erx_stats_v1 {
1359         u32 rx_drops_no_fragments[68];     /* dwordS 0 to 67*/
1360         u32 rsvd[4];
1361 };
1362
1363 struct be_hw_stats_v1 {
1364         struct be_rxf_stats_v1 rxf;
1365         u32 rsvd0[BE_TXP_SW_SZ];
1366         struct be_erx_stats_v1 erx;
1367         struct be_pmem_stats pmem;
1368         u32 rsvd1[3];
1369 };
1370
1371 struct be_cmd_req_get_stats_v1 {
1372         struct be_cmd_req_hdr hdr;
1373         u8 rsvd[sizeof(struct be_hw_stats_v1)];
1374 };
1375
1376 struct be_cmd_resp_get_stats_v1 {
1377         struct be_cmd_resp_hdr hdr;
1378         struct be_hw_stats_v1 hw_stats;
1379 };
1380
1381 static inline void *hw_stats_from_cmd(struct be_adapter *adapter)
1382 {
1383         if (adapter->generation == BE_GEN3) {
1384                 struct be_cmd_resp_get_stats_v1 *cmd = adapter->stats_cmd.va;
1385
1386                 return &cmd->hw_stats;
1387         } else {
1388                 struct be_cmd_resp_get_stats_v0 *cmd = adapter->stats_cmd.va;
1389
1390                 return &cmd->hw_stats;
1391         }
1392 }
1393
1394 static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter)
1395 {
1396         if (adapter->generation == BE_GEN3) {
1397                 struct be_hw_stats_v1 *hw_stats = hw_stats_from_cmd(adapter);
1398
1399                 return &hw_stats->erx;
1400         } else {
1401                 struct be_hw_stats_v0 *hw_stats = hw_stats_from_cmd(adapter);
1402
1403                 return &hw_stats->erx;
1404         }
1405 }
1406
1407 extern int be_pci_fnum_get(struct be_adapter *adapter);
1408 extern int be_cmd_POST(struct be_adapter *adapter);
1409 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1410                         u8 type, bool permanent, u32 if_handle);
1411 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1412                         u32 if_id, u32 *pmac_id, u32 domain);
1413 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
1414                         u32 pmac_id, u32 domain);
1415 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1416                         u32 en_flags, u8 *mac, bool pmac_invalid,
1417                         u32 *if_handle, u32 *pmac_id, u32 domain);
1418 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle,
1419                         u32 domain);
1420 extern int be_cmd_eq_create(struct be_adapter *adapter,
1421                         struct be_queue_info *eq, int eq_delay);
1422 extern int be_cmd_cq_create(struct be_adapter *adapter,
1423                         struct be_queue_info *cq, struct be_queue_info *eq,
1424                         bool sol_evts, bool no_delay,
1425                         int num_cqe_dma_coalesce);
1426 extern int be_cmd_mccq_create(struct be_adapter *adapter,
1427                         struct be_queue_info *mccq,
1428                         struct be_queue_info *cq);
1429 extern int be_cmd_txq_create(struct be_adapter *adapter,
1430                         struct be_queue_info *txq,
1431                         struct be_queue_info *cq);
1432 extern int be_cmd_rxq_create(struct be_adapter *adapter,
1433                         struct be_queue_info *rxq, u16 cq_id,
1434                         u16 frag_size, u16 max_frame_size, u32 if_id,
1435                         u32 rss, u8 *rss_id);
1436 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1437                         int type);
1438 extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1439                         struct be_queue_info *q);
1440 extern int be_cmd_link_status_query(struct be_adapter *adapter,
1441                         u8 *mac_speed, u16 *link_speed, u32 dom);
1442 extern int be_cmd_reset(struct be_adapter *adapter);
1443 extern int be_cmd_get_stats(struct be_adapter *adapter,
1444                         struct be_dma_mem *nonemb_cmd);
1445 extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1446                         struct be_dma_mem *nonemb_cmd);
1447 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
1448
1449 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1450 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
1451                         u16 *vtag_array, u32 num, bool untagged,
1452                         bool promiscuous);
1453 extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
1454 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
1455                         u32 tx_fc, u32 rx_fc);
1456 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
1457                         u32 *tx_fc, u32 *rx_fc);
1458 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
1459                         u32 *port_num, u32 *function_mode, u32 *function_caps);
1460 extern int be_cmd_reset_function(struct be_adapter *adapter);
1461 extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
1462                         u16 table_size);
1463 extern int be_process_mcc(struct be_adapter *adapter, int *status);
1464 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1465                         u8 port_num, u8 beacon, u8 status, u8 state);
1466 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1467                         u8 port_num, u32 *state);
1468 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1469                         struct be_dma_mem *cmd, u32 flash_oper,
1470                         u32 flash_opcode, u32 buf_size);
1471 extern int lancer_cmd_write_object(struct be_adapter *adapter,
1472                                 struct be_dma_mem *cmd,
1473                                 u32 data_size, u32 data_offset,
1474                                 const char *obj_name,
1475                                 u32 *data_written, u8 *addn_status);
1476 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1477                                 int offset);
1478 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1479                                 struct be_dma_mem *nonemb_cmd);
1480 extern int be_cmd_fw_init(struct be_adapter *adapter);
1481 extern int be_cmd_fw_clean(struct be_adapter *adapter);
1482 extern void be_async_mcc_enable(struct be_adapter *adapter);
1483 extern void be_async_mcc_disable(struct be_adapter *adapter);
1484 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1485                                 u32 loopback_type, u32 pkt_size,
1486                                 u32 num_pkts, u64 pattern);
1487 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1488                         u32 byte_cnt, struct be_dma_mem *cmd);
1489 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1490                                 struct be_dma_mem *nonemb_cmd);
1491 extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1492                                 u8 loopback_type, u8 enable);
1493 extern int be_cmd_get_phy_info(struct be_adapter *adapter,
1494                                 struct be_phy_info *phy_info);
1495 extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
1496 extern void be_detect_dump_ue(struct be_adapter *adapter);
1497 extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
1498 extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
1499 extern int be_cmd_req_native_mode(struct be_adapter *adapter);
1500 extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1501 extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
1502