2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter *adapter)
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
31 /* To check if valid bit is set, check the entire word as we don't know
32 * the endianness of the data (old entry is host endian while a new entry is
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
36 if (compl->flags != 0) {
37 compl->flags = le32_to_cpu(compl->flags);
38 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52 struct be_mcc_compl *compl)
54 u16 compl_status, extd_status;
56 /* Just swap the status to host endian; mcc tag is opaquely copied
58 be_dws_le_to_cpu(compl, 4);
60 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61 CQE_STATUS_COMPL_MASK;
62 if (compl_status == MCC_STATUS_SUCCESS) {
63 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64 struct be_cmd_resp_get_stats *resp =
65 adapter->stats.cmd.va;
66 be_dws_le_to_cpu(&resp->hw_stats,
67 sizeof(resp->hw_stats));
68 netdev_stats_update(adapter);
70 } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
73 dev_warn(&adapter->pdev->dev,
74 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75 compl->tag0, compl_status, extd_status);
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82 struct be_async_event_link_state *evt)
84 be_link_status_update(adapter,
85 evt->port_link_status == ASYNC_EVENT_LINK_UP);
88 static inline bool is_link_state_evt(u32 trailer)
90 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92 ASYNC_EVENT_CODE_LINK_STATE);
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
97 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
100 if (be_mcc_compl_is_new(compl)) {
101 queue_tail_inc(mcc_cq);
107 void be_async_mcc_enable(struct be_adapter *adapter)
109 spin_lock_bh(&adapter->mcc_cq_lock);
111 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112 adapter->mcc_obj.rearm_cq = true;
114 spin_unlock_bh(&adapter->mcc_cq_lock);
117 void be_async_mcc_disable(struct be_adapter *adapter)
119 adapter->mcc_obj.rearm_cq = false;
122 int be_process_mcc(struct be_adapter *adapter, int *status)
124 struct be_mcc_compl *compl;
126 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
128 spin_lock_bh(&adapter->mcc_cq_lock);
129 while ((compl = be_mcc_compl_get(adapter))) {
130 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
131 /* Interpret flags as an async trailer */
132 BUG_ON(!is_link_state_evt(compl->flags));
134 /* Interpret compl as a async link evt */
135 be_async_link_state_process(adapter,
136 (struct be_async_event_link_state *) compl);
137 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
138 *status = be_mcc_compl_process(adapter, compl);
139 atomic_dec(&mcc_obj->q.used);
141 be_mcc_compl_use(compl);
145 spin_unlock_bh(&adapter->mcc_cq_lock);
149 /* Wait till no more pending mcc requests are present */
150 static int be_mcc_wait_compl(struct be_adapter *adapter)
152 #define mcc_timeout 120000 /* 12s timeout */
153 int i, num, status = 0;
154 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
156 for (i = 0; i < mcc_timeout; i++) {
157 num = be_process_mcc(adapter, &status);
159 be_cq_notify(adapter, mcc_obj->cq.id,
160 mcc_obj->rearm_cq, num);
162 if (atomic_read(&mcc_obj->q.used) == 0)
166 if (i == mcc_timeout) {
167 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
173 /* Notify MCC requests and wait for completion */
174 static int be_mcc_notify_wait(struct be_adapter *adapter)
176 be_mcc_notify(adapter);
177 return be_mcc_wait_compl(adapter);
180 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
182 int cnt = 0, wait = 5;
186 ready = ioread32(db);
187 if (ready == 0xffffffff) {
188 dev_err(&adapter->pdev->dev,
189 "pci slot disconnected\n");
193 ready &= MPU_MAILBOX_DB_RDY_MASK;
198 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
212 * Insert the mailbox address into the doorbell in two steps
213 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
215 static int be_mbox_notify_wait(struct be_adapter *adapter)
219 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
220 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
221 struct be_mcc_mailbox *mbox = mbox_mem->va;
222 struct be_mcc_compl *compl = &mbox->compl;
224 /* wait for ready to be set */
225 status = be_mbox_db_ready_wait(adapter, db);
229 val |= MPU_MAILBOX_DB_HI_MASK;
230 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
234 /* wait for ready to be set */
235 status = be_mbox_db_ready_wait(adapter, db);
240 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241 val |= (u32)(mbox_mem->dma >> 4) << 2;
244 status = be_mbox_db_ready_wait(adapter, db);
248 /* A cq entry has been made now */
249 if (be_mcc_compl_is_new(compl)) {
250 status = be_mcc_compl_process(adapter, &mbox->compl);
251 be_mcc_compl_use(compl);
255 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
261 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
263 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
265 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
266 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
272 int be_cmd_POST(struct be_adapter *adapter)
275 int status, timeout = 0;
278 status = be_POST_stage_get(adapter, &stage);
280 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
283 } else if (stage != POST_STAGE_ARMFW_RDY) {
284 set_current_state(TASK_INTERRUPTIBLE);
285 schedule_timeout(2 * HZ);
290 } while (timeout < 20);
292 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
296 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
298 return wrb->payload.embedded_payload;
301 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
303 return &wrb->payload.sgl[0];
306 /* Don't touch the hdr after it's prepared */
307 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
308 bool embedded, u8 sge_cnt, u32 opcode)
311 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
313 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
314 MCC_WRB_SGE_CNT_SHIFT;
315 wrb->payload_length = payload_len;
317 be_dws_cpu_to_le(wrb, 8);
320 /* Don't touch the hdr after it's prepared */
321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
322 u8 subsystem, u8 opcode, int cmd_len)
324 req_hdr->opcode = opcode;
325 req_hdr->subsystem = subsystem;
326 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
327 req_hdr->version = 0;
330 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
331 struct be_dma_mem *mem)
333 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
334 u64 dma = (u64)mem->dma;
336 for (i = 0; i < buf_pages; i++) {
337 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
338 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
343 /* Converts interrupt delay in microseconds to multiplier value */
344 static u32 eq_delay_to_mult(u32 usec_delay)
346 #define MAX_INTR_RATE 651042
347 const u32 round = 10;
353 u32 interrupt_rate = 1000000 / usec_delay;
354 /* Max delay, corresponding to the lowest interrupt rate */
355 if (interrupt_rate == 0)
358 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
359 multiplier /= interrupt_rate;
360 /* Round the multiplier to the closest value.*/
361 multiplier = (multiplier + round/2) / round;
362 multiplier = min(multiplier, (u32)1023);
368 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
370 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
371 struct be_mcc_wrb *wrb
372 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
373 memset(wrb, 0, sizeof(*wrb));
377 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
379 struct be_queue_info *mccq = &adapter->mcc_obj.q;
380 struct be_mcc_wrb *wrb;
382 if (atomic_read(&mccq->used) >= mccq->len) {
383 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
387 wrb = queue_head_node(mccq);
388 queue_head_inc(mccq);
389 atomic_inc(&mccq->used);
390 memset(wrb, 0, sizeof(*wrb));
394 /* Tell fw we're about to start firing cmds by writing a
395 * special pattern across the wrb hdr; uses mbox
397 int be_cmd_fw_init(struct be_adapter *adapter)
402 spin_lock(&adapter->mbox_lock);
404 wrb = (u8 *)wrb_from_mbox(adapter);
414 status = be_mbox_notify_wait(adapter);
416 spin_unlock(&adapter->mbox_lock);
420 /* Tell fw we're done with firing cmds by writing a
421 * special pattern across the wrb hdr; uses mbox
423 int be_cmd_fw_clean(struct be_adapter *adapter)
428 if (adapter->eeh_err)
431 spin_lock(&adapter->mbox_lock);
433 wrb = (u8 *)wrb_from_mbox(adapter);
443 status = be_mbox_notify_wait(adapter);
445 spin_unlock(&adapter->mbox_lock);
448 int be_cmd_eq_create(struct be_adapter *adapter,
449 struct be_queue_info *eq, int eq_delay)
451 struct be_mcc_wrb *wrb;
452 struct be_cmd_req_eq_create *req;
453 struct be_dma_mem *q_mem = &eq->dma_mem;
456 spin_lock(&adapter->mbox_lock);
458 wrb = wrb_from_mbox(adapter);
459 req = embedded_payload(wrb);
461 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
463 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
464 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
466 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
468 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
469 be_pci_func(adapter));
470 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
472 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
473 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
474 __ilog2_u32(eq->len/256));
475 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
476 eq_delay_to_mult(eq_delay));
477 be_dws_cpu_to_le(req->context, sizeof(req->context));
479 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
481 status = be_mbox_notify_wait(adapter);
483 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
484 eq->id = le16_to_cpu(resp->eq_id);
488 spin_unlock(&adapter->mbox_lock);
493 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
494 u8 type, bool permanent, u32 if_handle)
496 struct be_mcc_wrb *wrb;
497 struct be_cmd_req_mac_query *req;
500 spin_lock(&adapter->mbox_lock);
502 wrb = wrb_from_mbox(adapter);
503 req = embedded_payload(wrb);
505 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
506 OPCODE_COMMON_NTWK_MAC_QUERY);
508 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
509 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
515 req->if_id = cpu_to_le16((u16) if_handle);
519 status = be_mbox_notify_wait(adapter);
521 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
522 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
525 spin_unlock(&adapter->mbox_lock);
529 /* Uses synchronous MCCQ */
530 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
531 u32 if_id, u32 *pmac_id)
533 struct be_mcc_wrb *wrb;
534 struct be_cmd_req_pmac_add *req;
537 spin_lock_bh(&adapter->mcc_lock);
539 wrb = wrb_from_mccq(adapter);
544 req = embedded_payload(wrb);
546 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
547 OPCODE_COMMON_NTWK_PMAC_ADD);
549 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
550 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
552 req->if_id = cpu_to_le32(if_id);
553 memcpy(req->mac_address, mac_addr, ETH_ALEN);
555 status = be_mcc_notify_wait(adapter);
557 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
558 *pmac_id = le32_to_cpu(resp->pmac_id);
562 spin_unlock_bh(&adapter->mcc_lock);
566 /* Uses synchronous MCCQ */
567 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
569 struct be_mcc_wrb *wrb;
570 struct be_cmd_req_pmac_del *req;
573 spin_lock_bh(&adapter->mcc_lock);
575 wrb = wrb_from_mccq(adapter);
580 req = embedded_payload(wrb);
582 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
583 OPCODE_COMMON_NTWK_PMAC_DEL);
585 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
586 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
588 req->if_id = cpu_to_le32(if_id);
589 req->pmac_id = cpu_to_le32(pmac_id);
591 status = be_mcc_notify_wait(adapter);
594 spin_unlock_bh(&adapter->mcc_lock);
599 int be_cmd_cq_create(struct be_adapter *adapter,
600 struct be_queue_info *cq, struct be_queue_info *eq,
601 bool sol_evts, bool no_delay, int coalesce_wm)
603 struct be_mcc_wrb *wrb;
604 struct be_cmd_req_cq_create *req;
605 struct be_dma_mem *q_mem = &cq->dma_mem;
609 spin_lock(&adapter->mbox_lock);
611 wrb = wrb_from_mbox(adapter);
612 req = embedded_payload(wrb);
613 ctxt = &req->context;
615 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
616 OPCODE_COMMON_CQ_CREATE);
618 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
619 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
621 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
623 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
624 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
625 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
626 __ilog2_u32(cq->len/256));
627 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
628 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
629 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
630 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
631 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
632 AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
633 be_dws_cpu_to_le(ctxt, sizeof(req->context));
635 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
637 status = be_mbox_notify_wait(adapter);
639 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
640 cq->id = le16_to_cpu(resp->cq_id);
644 spin_unlock(&adapter->mbox_lock);
649 static u32 be_encoded_q_len(int q_len)
651 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
652 if (len_encoded == 16)
657 int be_cmd_mccq_create(struct be_adapter *adapter,
658 struct be_queue_info *mccq,
659 struct be_queue_info *cq)
661 struct be_mcc_wrb *wrb;
662 struct be_cmd_req_mcc_create *req;
663 struct be_dma_mem *q_mem = &mccq->dma_mem;
667 spin_lock(&adapter->mbox_lock);
669 wrb = wrb_from_mbox(adapter);
670 req = embedded_payload(wrb);
671 ctxt = &req->context;
673 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
674 OPCODE_COMMON_MCC_CREATE);
676 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
677 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
679 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
681 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
682 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
683 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
684 be_encoded_q_len(mccq->len));
685 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
687 be_dws_cpu_to_le(ctxt, sizeof(req->context));
689 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
691 status = be_mbox_notify_wait(adapter);
693 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
694 mccq->id = le16_to_cpu(resp->id);
695 mccq->created = true;
697 spin_unlock(&adapter->mbox_lock);
702 int be_cmd_txq_create(struct be_adapter *adapter,
703 struct be_queue_info *txq,
704 struct be_queue_info *cq)
706 struct be_mcc_wrb *wrb;
707 struct be_cmd_req_eth_tx_create *req;
708 struct be_dma_mem *q_mem = &txq->dma_mem;
712 spin_lock(&adapter->mbox_lock);
714 wrb = wrb_from_mbox(adapter);
715 req = embedded_payload(wrb);
716 ctxt = &req->context;
718 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
719 OPCODE_ETH_TX_CREATE);
721 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
724 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
725 req->ulp_num = BE_ULP1_NUM;
726 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
728 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
729 be_encoded_q_len(txq->len));
730 AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
731 be_pci_func(adapter));
732 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
733 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
735 be_dws_cpu_to_le(ctxt, sizeof(req->context));
737 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
739 status = be_mbox_notify_wait(adapter);
741 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
742 txq->id = le16_to_cpu(resp->cid);
746 spin_unlock(&adapter->mbox_lock);
752 int be_cmd_rxq_create(struct be_adapter *adapter,
753 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
754 u16 max_frame_size, u32 if_id, u32 rss)
756 struct be_mcc_wrb *wrb;
757 struct be_cmd_req_eth_rx_create *req;
758 struct be_dma_mem *q_mem = &rxq->dma_mem;
761 spin_lock(&adapter->mbox_lock);
763 wrb = wrb_from_mbox(adapter);
764 req = embedded_payload(wrb);
766 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
767 OPCODE_ETH_RX_CREATE);
769 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
772 req->cq_id = cpu_to_le16(cq_id);
773 req->frag_size = fls(frag_size) - 1;
775 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
776 req->interface_id = cpu_to_le32(if_id);
777 req->max_frame_size = cpu_to_le16(max_frame_size);
778 req->rss_queue = cpu_to_le32(rss);
780 status = be_mbox_notify_wait(adapter);
782 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
783 rxq->id = le16_to_cpu(resp->id);
787 spin_unlock(&adapter->mbox_lock);
792 /* Generic destroyer function for all types of queues
795 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
798 struct be_mcc_wrb *wrb;
799 struct be_cmd_req_q_destroy *req;
800 u8 subsys = 0, opcode = 0;
803 if (adapter->eeh_err)
806 spin_lock(&adapter->mbox_lock);
808 wrb = wrb_from_mbox(adapter);
809 req = embedded_payload(wrb);
811 switch (queue_type) {
813 subsys = CMD_SUBSYSTEM_COMMON;
814 opcode = OPCODE_COMMON_EQ_DESTROY;
817 subsys = CMD_SUBSYSTEM_COMMON;
818 opcode = OPCODE_COMMON_CQ_DESTROY;
821 subsys = CMD_SUBSYSTEM_ETH;
822 opcode = OPCODE_ETH_TX_DESTROY;
825 subsys = CMD_SUBSYSTEM_ETH;
826 opcode = OPCODE_ETH_RX_DESTROY;
829 subsys = CMD_SUBSYSTEM_COMMON;
830 opcode = OPCODE_COMMON_MCC_DESTROY;
836 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
838 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
839 req->id = cpu_to_le16(q->id);
841 status = be_mbox_notify_wait(adapter);
843 spin_unlock(&adapter->mbox_lock);
848 /* Create an rx filtering policy configuration on an i/f
851 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
852 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
854 struct be_mcc_wrb *wrb;
855 struct be_cmd_req_if_create *req;
858 spin_lock(&adapter->mbox_lock);
860 wrb = wrb_from_mbox(adapter);
861 req = embedded_payload(wrb);
863 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
864 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
866 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
867 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
869 req->capability_flags = cpu_to_le32(cap_flags);
870 req->enable_flags = cpu_to_le32(en_flags);
871 req->pmac_invalid = pmac_invalid;
873 memcpy(req->mac_addr, mac, ETH_ALEN);
875 status = be_mbox_notify_wait(adapter);
877 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
878 *if_handle = le32_to_cpu(resp->interface_id);
880 *pmac_id = le32_to_cpu(resp->pmac_id);
883 spin_unlock(&adapter->mbox_lock);
888 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
890 struct be_mcc_wrb *wrb;
891 struct be_cmd_req_if_destroy *req;
894 if (adapter->eeh_err)
897 spin_lock(&adapter->mbox_lock);
899 wrb = wrb_from_mbox(adapter);
900 req = embedded_payload(wrb);
902 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
903 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
905 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
906 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
908 req->interface_id = cpu_to_le32(interface_id);
910 status = be_mbox_notify_wait(adapter);
912 spin_unlock(&adapter->mbox_lock);
917 /* Get stats is a non embedded command: the request is not embedded inside
918 * WRB but is a separate dma memory block
919 * Uses asynchronous MCC
921 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
923 struct be_mcc_wrb *wrb;
924 struct be_cmd_req_get_stats *req;
928 spin_lock_bh(&adapter->mcc_lock);
930 wrb = wrb_from_mccq(adapter);
935 req = nonemb_cmd->va;
936 sge = nonembedded_sgl(wrb);
938 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
939 OPCODE_ETH_GET_STATISTICS);
941 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
942 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
943 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
944 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
945 sge->len = cpu_to_le32(nonemb_cmd->size);
947 be_mcc_notify(adapter);
950 spin_unlock_bh(&adapter->mcc_lock);
954 /* Uses synchronous mcc */
955 int be_cmd_link_status_query(struct be_adapter *adapter,
956 bool *link_up, u8 *mac_speed, u16 *link_speed)
958 struct be_mcc_wrb *wrb;
959 struct be_cmd_req_link_status *req;
962 spin_lock_bh(&adapter->mcc_lock);
964 wrb = wrb_from_mccq(adapter);
969 req = embedded_payload(wrb);
973 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
974 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
976 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
977 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
979 status = be_mcc_notify_wait(adapter);
981 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
982 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
984 *link_speed = le16_to_cpu(resp->link_speed);
985 *mac_speed = resp->mac_speed;
990 spin_unlock_bh(&adapter->mcc_lock);
995 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
997 struct be_mcc_wrb *wrb;
998 struct be_cmd_req_get_fw_version *req;
1001 spin_lock(&adapter->mbox_lock);
1003 wrb = wrb_from_mbox(adapter);
1004 req = embedded_payload(wrb);
1006 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1007 OPCODE_COMMON_GET_FW_VERSION);
1009 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1010 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1012 status = be_mbox_notify_wait(adapter);
1014 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1015 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1018 spin_unlock(&adapter->mbox_lock);
1022 /* set the EQ delay interval of an EQ to specified value
1025 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1027 struct be_mcc_wrb *wrb;
1028 struct be_cmd_req_modify_eq_delay *req;
1031 spin_lock_bh(&adapter->mcc_lock);
1033 wrb = wrb_from_mccq(adapter);
1038 req = embedded_payload(wrb);
1040 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1041 OPCODE_COMMON_MODIFY_EQ_DELAY);
1043 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1044 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1046 req->num_eq = cpu_to_le32(1);
1047 req->delay[0].eq_id = cpu_to_le32(eq_id);
1048 req->delay[0].phase = 0;
1049 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1051 be_mcc_notify(adapter);
1054 spin_unlock_bh(&adapter->mcc_lock);
1058 /* Uses sycnhronous mcc */
1059 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1060 u32 num, bool untagged, bool promiscuous)
1062 struct be_mcc_wrb *wrb;
1063 struct be_cmd_req_vlan_config *req;
1066 spin_lock_bh(&adapter->mcc_lock);
1068 wrb = wrb_from_mccq(adapter);
1073 req = embedded_payload(wrb);
1075 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1076 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1078 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1079 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1081 req->interface_id = if_id;
1082 req->promiscuous = promiscuous;
1083 req->untagged = untagged;
1084 req->num_vlan = num;
1086 memcpy(req->normal_vlan, vtag_array,
1087 req->num_vlan * sizeof(vtag_array[0]));
1090 status = be_mcc_notify_wait(adapter);
1093 spin_unlock_bh(&adapter->mcc_lock);
1097 /* Uses MCC for this command as it may be called in BH context
1098 * Uses synchronous mcc
1100 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1102 struct be_mcc_wrb *wrb;
1103 struct be_cmd_req_promiscuous_config *req;
1106 spin_lock_bh(&adapter->mcc_lock);
1108 wrb = wrb_from_mccq(adapter);
1113 req = embedded_payload(wrb);
1115 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1117 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1118 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1121 req->port1_promiscuous = en;
1123 req->port0_promiscuous = en;
1125 status = be_mcc_notify_wait(adapter);
1128 spin_unlock_bh(&adapter->mcc_lock);
1133 * Uses MCC for this command as it may be called in BH context
1134 * (mc == NULL) => multicast promiscous
1136 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1137 struct net_device *netdev, struct be_dma_mem *mem)
1139 struct be_mcc_wrb *wrb;
1140 struct be_cmd_req_mcast_mac_config *req = mem->va;
1144 spin_lock_bh(&adapter->mcc_lock);
1146 wrb = wrb_from_mccq(adapter);
1151 sge = nonembedded_sgl(wrb);
1152 memset(req, 0, sizeof(*req));
1154 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1155 OPCODE_COMMON_NTWK_MULTICAST_SET);
1156 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1157 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1158 sge->len = cpu_to_le32(mem->size);
1160 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1161 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1163 req->interface_id = if_id;
1166 struct dev_mc_list *mc;
1168 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1171 netdev_for_each_mc_addr(mc, netdev)
1172 memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
1174 req->promiscuous = 1;
1177 status = be_mcc_notify_wait(adapter);
1180 spin_unlock_bh(&adapter->mcc_lock);
1184 /* Uses synchrounous mcc */
1185 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1187 struct be_mcc_wrb *wrb;
1188 struct be_cmd_req_set_flow_control *req;
1191 spin_lock_bh(&adapter->mcc_lock);
1193 wrb = wrb_from_mccq(adapter);
1198 req = embedded_payload(wrb);
1200 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1201 OPCODE_COMMON_SET_FLOW_CONTROL);
1203 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1204 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1206 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1207 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1209 status = be_mcc_notify_wait(adapter);
1212 spin_unlock_bh(&adapter->mcc_lock);
1217 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1219 struct be_mcc_wrb *wrb;
1220 struct be_cmd_req_get_flow_control *req;
1223 spin_lock_bh(&adapter->mcc_lock);
1225 wrb = wrb_from_mccq(adapter);
1230 req = embedded_payload(wrb);
1232 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1233 OPCODE_COMMON_GET_FLOW_CONTROL);
1235 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1236 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1238 status = be_mcc_notify_wait(adapter);
1240 struct be_cmd_resp_get_flow_control *resp =
1241 embedded_payload(wrb);
1242 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1243 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1247 spin_unlock_bh(&adapter->mcc_lock);
1252 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1254 struct be_mcc_wrb *wrb;
1255 struct be_cmd_req_query_fw_cfg *req;
1258 spin_lock(&adapter->mbox_lock);
1260 wrb = wrb_from_mbox(adapter);
1261 req = embedded_payload(wrb);
1263 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1264 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1266 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1267 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1269 status = be_mbox_notify_wait(adapter);
1271 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1272 *port_num = le32_to_cpu(resp->phys_port);
1273 *cap = le32_to_cpu(resp->function_cap);
1276 spin_unlock(&adapter->mbox_lock);
1281 int be_cmd_reset_function(struct be_adapter *adapter)
1283 struct be_mcc_wrb *wrb;
1284 struct be_cmd_req_hdr *req;
1287 spin_lock(&adapter->mbox_lock);
1289 wrb = wrb_from_mbox(adapter);
1290 req = embedded_payload(wrb);
1292 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1293 OPCODE_COMMON_FUNCTION_RESET);
1295 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1296 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1298 status = be_mbox_notify_wait(adapter);
1300 spin_unlock(&adapter->mbox_lock);
1305 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1306 u8 bcn, u8 sts, u8 state)
1308 struct be_mcc_wrb *wrb;
1309 struct be_cmd_req_enable_disable_beacon *req;
1312 spin_lock_bh(&adapter->mcc_lock);
1314 wrb = wrb_from_mccq(adapter);
1319 req = embedded_payload(wrb);
1321 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1322 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1324 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1325 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1327 req->port_num = port_num;
1328 req->beacon_state = state;
1329 req->beacon_duration = bcn;
1330 req->status_duration = sts;
1332 status = be_mcc_notify_wait(adapter);
1335 spin_unlock_bh(&adapter->mcc_lock);
1340 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1342 struct be_mcc_wrb *wrb;
1343 struct be_cmd_req_get_beacon_state *req;
1346 spin_lock_bh(&adapter->mcc_lock);
1348 wrb = wrb_from_mccq(adapter);
1353 req = embedded_payload(wrb);
1355 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1356 OPCODE_COMMON_GET_BEACON_STATE);
1358 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1359 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1361 req->port_num = port_num;
1363 status = be_mcc_notify_wait(adapter);
1365 struct be_cmd_resp_get_beacon_state *resp =
1366 embedded_payload(wrb);
1367 *state = resp->beacon_state;
1371 spin_unlock_bh(&adapter->mcc_lock);
1376 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1379 struct be_mcc_wrb *wrb;
1380 struct be_cmd_req_port_type *req;
1383 spin_lock_bh(&adapter->mcc_lock);
1385 wrb = wrb_from_mccq(adapter);
1390 req = embedded_payload(wrb);
1392 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1393 OPCODE_COMMON_READ_TRANSRECV_DATA);
1395 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1396 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1398 req->port = cpu_to_le32(port);
1399 req->page_num = cpu_to_le32(TR_PAGE_A0);
1400 status = be_mcc_notify_wait(adapter);
1402 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1403 *connector = resp->data.connector;
1407 spin_unlock_bh(&adapter->mcc_lock);
1411 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1412 u32 flash_type, u32 flash_opcode, u32 buf_size)
1414 struct be_mcc_wrb *wrb;
1415 struct be_cmd_write_flashrom *req;
1419 spin_lock_bh(&adapter->mcc_lock);
1421 wrb = wrb_from_mccq(adapter);
1427 sge = nonembedded_sgl(wrb);
1429 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1430 OPCODE_COMMON_WRITE_FLASHROM);
1432 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1433 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1434 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1435 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1436 sge->len = cpu_to_le32(cmd->size);
1438 req->params.op_type = cpu_to_le32(flash_type);
1439 req->params.op_code = cpu_to_le32(flash_opcode);
1440 req->params.data_buf_size = cpu_to_le32(buf_size);
1442 status = be_mcc_notify_wait(adapter);
1445 spin_unlock_bh(&adapter->mcc_lock);
1449 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1452 struct be_mcc_wrb *wrb;
1453 struct be_cmd_write_flashrom *req;
1456 spin_lock_bh(&adapter->mcc_lock);
1458 wrb = wrb_from_mccq(adapter);
1463 req = embedded_payload(wrb);
1465 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1466 OPCODE_COMMON_READ_FLASHROM);
1468 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1469 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1471 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1472 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1473 req->params.offset = offset;
1474 req->params.data_buf_size = 0x4;
1476 status = be_mcc_notify_wait(adapter);
1478 memcpy(flashed_crc, req->params.data_buf, 4);
1481 spin_unlock_bh(&adapter->mcc_lock);
1485 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1486 struct be_dma_mem *nonemb_cmd)
1488 struct be_mcc_wrb *wrb;
1489 struct be_cmd_req_acpi_wol_magic_config *req;
1493 spin_lock_bh(&adapter->mcc_lock);
1495 wrb = wrb_from_mccq(adapter);
1500 req = nonemb_cmd->va;
1501 sge = nonembedded_sgl(wrb);
1503 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1504 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1506 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1507 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1508 memcpy(req->magic_mac, mac, ETH_ALEN);
1510 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1511 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1512 sge->len = cpu_to_le32(nonemb_cmd->size);
1514 status = be_mcc_notify_wait(adapter);
1517 spin_unlock_bh(&adapter->mcc_lock);
1521 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1522 u8 loopback_type, u8 enable)
1524 struct be_mcc_wrb *wrb;
1525 struct be_cmd_req_set_lmode *req;
1528 spin_lock_bh(&adapter->mcc_lock);
1530 wrb = wrb_from_mccq(adapter);
1536 req = embedded_payload(wrb);
1538 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1539 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1541 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1542 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1545 req->src_port = port_num;
1546 req->dest_port = port_num;
1547 req->loopback_type = loopback_type;
1548 req->loopback_state = enable;
1550 status = be_mcc_notify_wait(adapter);
1552 spin_unlock_bh(&adapter->mcc_lock);
1556 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1557 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1559 struct be_mcc_wrb *wrb;
1560 struct be_cmd_req_loopback_test *req;
1563 spin_lock_bh(&adapter->mcc_lock);
1565 wrb = wrb_from_mccq(adapter);
1571 req = embedded_payload(wrb);
1573 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1574 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1576 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1577 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1578 req->hdr.timeout = 4;
1580 req->pattern = cpu_to_le64(pattern);
1581 req->src_port = cpu_to_le32(port_num);
1582 req->dest_port = cpu_to_le32(port_num);
1583 req->pkt_size = cpu_to_le32(pkt_size);
1584 req->num_pkts = cpu_to_le32(num_pkts);
1585 req->loopback_type = cpu_to_le32(loopback_type);
1587 status = be_mcc_notify_wait(adapter);
1589 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1590 status = le32_to_cpu(resp->status);
1594 spin_unlock_bh(&adapter->mcc_lock);
1598 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1599 u32 byte_cnt, struct be_dma_mem *cmd)
1601 struct be_mcc_wrb *wrb;
1602 struct be_cmd_req_ddrdma_test *req;
1607 spin_lock_bh(&adapter->mcc_lock);
1609 wrb = wrb_from_mccq(adapter);
1615 sge = nonembedded_sgl(wrb);
1616 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1617 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1618 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1619 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1621 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1622 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1623 sge->len = cpu_to_le32(cmd->size);
1625 req->pattern = cpu_to_le64(pattern);
1626 req->byte_count = cpu_to_le32(byte_cnt);
1627 for (i = 0; i < byte_cnt; i++) {
1628 req->snd_buff[i] = (u8)(pattern >> (j*8));
1634 status = be_mcc_notify_wait(adapter);
1637 struct be_cmd_resp_ddrdma_test *resp;
1639 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1646 spin_unlock_bh(&adapter->mcc_lock);
1650 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1651 struct be_dma_mem *nonemb_cmd)
1653 struct be_mcc_wrb *wrb;
1654 struct be_cmd_req_seeprom_read *req;
1658 spin_lock_bh(&adapter->mcc_lock);
1660 wrb = wrb_from_mccq(adapter);
1661 req = nonemb_cmd->va;
1662 sge = nonembedded_sgl(wrb);
1664 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1665 OPCODE_COMMON_SEEPROM_READ);
1667 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1668 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1670 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1671 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1672 sge->len = cpu_to_le32(nonemb_cmd->size);
1674 status = be_mcc_notify_wait(adapter);
1676 spin_unlock_bh(&adapter->mcc_lock);