drivers/mtd/spi-nor/cadence-quadspi.c

   1 /*
   2  * Driver for Cadence QSPI Controller
   3  *
   4  * Copyright Altera Corporation (C) 2012-2014. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include <linux/clk.h>
  19 #include <linux/completion.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22 #include <linux/errno.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/jiffies.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/partitions.h>
  30 #include <linux/mtd/spi-nor.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/pm_runtime.h>
  35 #include <linux/sched.h>
  36 #include <linux/spi/spi.h>
  37 #include <linux/timer.h>
  38
  39 #define CQSPI_NAME                      "cadence-qspi"
  40 #define CQSPI_MAX_CHIPSELECT            16
  41
  42 /* Quirks */
  43 #define CQSPI_NEEDS_WR_DELAY            BIT(0)
  44
  45 struct cqspi_st;
  46
  47 struct cqspi_flash_pdata {
  48         struct spi_nor  nor;
  49         struct cqspi_st *cqspi;
  50         u32             clk_rate;
  51         u32             read_delay;
  52         u32             tshsl_ns;
  53         u32             tsd2d_ns;
  54         u32             tchsh_ns;
  55         u32             tslch_ns;
  56         u8              inst_width;
  57         u8              addr_width;
  58         u8              data_width;
  59         u8              cs;
  60         bool            registered;
  61 };
  62
  63 struct cqspi_st {
  64         struct platform_device  *pdev;
  65
  66         struct clk              *clk;
  67         unsigned int            sclk;
  68
  69         void __iomem            *iobase;
  70         void __iomem            *ahb_base;
  71         struct completion       transfer_complete;
  72         struct mutex            bus_mutex;
  73
  74         int                     current_cs;
  75         int                     current_page_size;
  76         int                     current_erase_size;
  77         int                     current_addr_width;
  78         unsigned long           master_ref_clk_hz;
  79         bool                    is_decoded_cs;
  80         u32                     fifo_depth;
  81         u32                     fifo_width;
  82         bool                    rclk_en;
  83         u32                     trigger_address;
  84         u32                     wr_delay;
  85         struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
  86 };
  87
  88 /* Operation timeout value */
  89 #define CQSPI_TIMEOUT_MS                        500
  90 #define CQSPI_READ_TIMEOUT_MS                   10
  91
  92 /* Instruction type */
  93 #define CQSPI_INST_TYPE_SINGLE                  0
  94 #define CQSPI_INST_TYPE_DUAL                    1
  95 #define CQSPI_INST_TYPE_QUAD                    2
  96
  97 #define CQSPI_DUMMY_CLKS_PER_BYTE               8
  98 #define CQSPI_DUMMY_BYTES_MAX                   4
  99 #define CQSPI_DUMMY_CLKS_MAX                    31
 100
 101 #define CQSPI_STIG_DATA_LEN_MAX                 8
 102
 103 /* Register map */
 104 #define CQSPI_REG_CONFIG                        0x00
 105 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
 106 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
 107 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
 108 #define CQSPI_REG_CONFIG_DMA_MASK               BIT(15)
 109 #define CQSPI_REG_CONFIG_BAUD_LSB               19
 110 #define CQSPI_REG_CONFIG_IDLE_LSB               31
 111 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
 112 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
 113
 114 #define CQSPI_REG_RD_INSTR                      0x04
 115 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 116 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
 117 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 118 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 119 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
 120 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
 121 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
 122 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
 123 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
 124 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
 125
 126 #define CQSPI_REG_WR_INSTR                      0x08
 127 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
 128 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB        12
 129 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB        16
 130
 131 #define CQSPI_REG_DELAY                         0x0C
 132 #define CQSPI_REG_DELAY_TSLCH_LSB               0
 133 #define CQSPI_REG_DELAY_TCHSH_LSB               8
 134 #define CQSPI_REG_DELAY_TSD2D_LSB               16
 135 #define CQSPI_REG_DELAY_TSHSL_LSB               24
 136 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
 137 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
 138 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
 139 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
 140
 141 #define CQSPI_REG_READCAPTURE                   0x10
 142 #define CQSPI_REG_READCAPTURE_BYPASS_LSB        0
 143 #define CQSPI_REG_READCAPTURE_DELAY_LSB         1
 144 #define CQSPI_REG_READCAPTURE_DELAY_MASK        0xF
 145
 146 #define CQSPI_REG_SIZE                          0x14
 147 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 148 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 149 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 150 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 151 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 152 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 153
 154 #define CQSPI_REG_SRAMPARTITION                 0x18
 155 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 156
 157 #define CQSPI_REG_DMA                           0x20
 158 #define CQSPI_REG_DMA_SINGLE_LSB                0
 159 #define CQSPI_REG_DMA_BURST_LSB                 8
 160 #define CQSPI_REG_DMA_SINGLE_MASK               0xFF
 161 #define CQSPI_REG_DMA_BURST_MASK                0xFF
 162
 163 #define CQSPI_REG_REMAP                         0x24
 164 #define CQSPI_REG_MODE_BIT                      0x28
 165
 166 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 167 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 168 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 169 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 170 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 171
 172 #define CQSPI_REG_IRQSTATUS                     0x40
 173 #define CQSPI_REG_IRQMASK                       0x44
 174
 175 #define CQSPI_REG_INDIRECTRD                    0x60
 176 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 177 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 178 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 179
 180 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 181 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 182 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 183
 184 #define CQSPI_REG_CMDCTRL                       0x90
 185 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 186 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 187 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 188 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 189 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 190 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 191 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 192 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 193 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 194 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 195 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 196 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 197
 198 #define CQSPI_REG_INDIRECTWR                    0x70
 199 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 200 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 201 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 202
 203 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 204 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 205 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 206
 207 #define CQSPI_REG_CMDADDRESS                    0x94
 208 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 209 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 210 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 211 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 212
 213 /* Interrupt status bits */
 214 #define CQSPI_REG_IRQ_MODE_ERR                  BIT(0)
 215 #define CQSPI_REG_IRQ_UNDERFLOW                 BIT(1)
 216 #define CQSPI_REG_IRQ_IND_COMP                  BIT(2)
 217 #define CQSPI_REG_IRQ_IND_RD_REJECT             BIT(3)
 218 #define CQSPI_REG_IRQ_WR_PROTECTED_ERR          BIT(4)
 219 #define CQSPI_REG_IRQ_ILLEGAL_AHB_ERR           BIT(5)
 220 #define CQSPI_REG_IRQ_WATERMARK                 BIT(6)
 221 #define CQSPI_REG_IRQ_IND_SRAM_FULL             BIT(12)
 222
 223 #define CQSPI_IRQ_MASK_RD               (CQSPI_REG_IRQ_WATERMARK        | \
 224                                          CQSPI_REG_IRQ_IND_SRAM_FULL    | \
 225                                          CQSPI_REG_IRQ_IND_COMP)
 226
 227 #define CQSPI_IRQ_MASK_WR               (CQSPI_REG_IRQ_IND_COMP         | \
 228                                          CQSPI_REG_IRQ_WATERMARK        | \
 229                                          CQSPI_REG_IRQ_UNDERFLOW)
 230
 231 #define CQSPI_IRQ_STATUS_MASK           0x1FFFF
 232
 233 static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clear)
 234 {
 235         unsigned long end = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 236         u32 val;
 237
 238         while (1) {
 239                 val = readl(reg);
 240                 if (clear)
 241                         val = ~val;
 242                 val &= mask;
 243
 244                 if (val == mask)
 245                         return 0;
 246
 247                 if (time_after(jiffies, end))
 248                         return -ETIMEDOUT;
 249         }
 250 }
 251
 252 static bool cqspi_is_idle(struct cqspi_st *cqspi)
 253 {
 254         u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
 255
 256         return reg & (1 << CQSPI_REG_CONFIG_IDLE_LSB);
 257 }
 258
 259 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
 260 {
 261         u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
 262
 263         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 264         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 265 }
 266
 267 static irqreturn_t cqspi_irq_handler(int this_irq, void *dev)
 268 {
 269         struct cqspi_st *cqspi = dev;
 270         unsigned int irq_status;
 271
 272         /* Read interrupt status */
 273         irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
 274
 275         /* Clear interrupt */
 276         writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
 277
 278         irq_status &= CQSPI_IRQ_MASK_RD | CQSPI_IRQ_MASK_WR;
 279
 280         if (irq_status)
 281                 complete(&cqspi->transfer_complete);
 282
 283         return IRQ_HANDLED;
 284 }
 285
 286 static unsigned int cqspi_calc_rdreg(struct spi_nor *nor, const u8 opcode)
 287 {
 288         struct cqspi_flash_pdata *f_pdata = nor->priv;
 289         u32 rdreg = 0;
 290
 291         rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
 292         rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
 293         rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 294
 295         return rdreg;
 296 }
 297
 298 static int cqspi_wait_idle(struct cqspi_st *cqspi)
 299 {
 300         const unsigned int poll_idle_retry = 3;
 301         unsigned int count = 0;
 302         unsigned long timeout;
 303
 304         timeout = jiffies + msecs_to_jiffies(CQSPI_TIMEOUT_MS);
 305         while (1) {
 306                 /*
 307                  * Read few times in succession to ensure the controller
 308                  * is indeed idle, that is, the bit does not transition
 309                  * low again.
 310                  */
 311                 if (cqspi_is_idle(cqspi))
 312                         count++;
 313                 else
 314                         count = 0;
 315
 316                 if (count >= poll_idle_retry)
 317                         return 0;
 318
 319                 if (time_after(jiffies, timeout)) {
 320                         /* Timeout, in busy mode. */
 321                         dev_err(&cqspi->pdev->dev,
 322                                 "QSPI is still busy after %dms timeout.\n",
 323                                 CQSPI_TIMEOUT_MS);
 324                         return -ETIMEDOUT;
 325                 }
 326
 327                 cpu_relax();
 328         }
 329 }
 330
 331 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 332 {
 333         void __iomem *reg_base = cqspi->iobase;
 334         int ret;
 335
 336         /* Write the CMDCTRL without start execution. */
 337         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 338         /* Start execute */
 339         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 340         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 341
 342         /* Polling for completion. */
 343         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
 344                                  CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
 345         if (ret) {
 346                 dev_err(&cqspi->pdev->dev,
 347                         "Flash command execution timed out.\n");
 348                 return ret;
 349         }
 350
 351         /* Polling QSPI idle status. */
 352         return cqspi_wait_idle(cqspi);
 353 }
 354
 355 static int cqspi_command_read(struct spi_nor *nor,
 356                               const u8 *txbuf, const unsigned n_tx,
 357                               u8 *rxbuf, const unsigned n_rx)
 358 {
 359         struct cqspi_flash_pdata *f_pdata = nor->priv;
 360         struct cqspi_st *cqspi = f_pdata->cqspi;
 361         void __iomem *reg_base = cqspi->iobase;
 362         unsigned int rdreg;
 363         unsigned int reg;
 364         unsigned int read_len;
 365         int status;
 366
 367         if (!n_rx || n_rx > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
 368                 dev_err(nor->dev, "Invalid input argument, len %d rxbuf 0x%p\n",
 369                         n_rx, rxbuf);
 370                 return -EINVAL;
 371         }
 372
 373         reg = txbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 374
 375         rdreg = cqspi_calc_rdreg(nor, txbuf[0]);
 376         writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
 377
 378         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 379
 380         /* 0 means 1 byte. */
 381         reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 382                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 383         status = cqspi_exec_flash_cmd(cqspi, reg);
 384         if (status)
 385                 return status;
 386
 387         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 388
 389         /* Put the read value into rx_buf */
 390         read_len = (n_rx > 4) ? 4 : n_rx;
 391         memcpy(rxbuf, &reg, read_len);
 392         rxbuf += read_len;
 393
 394         if (n_rx > 4) {
 395                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 396
 397                 read_len = n_rx - read_len;
 398                 memcpy(rxbuf, &reg, read_len);
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int cqspi_command_write(struct spi_nor *nor, const u8 opcode,
 405                                const u8 *txbuf, const unsigned n_tx)
 406 {
 407         struct cqspi_flash_pdata *f_pdata = nor->priv;
 408         struct cqspi_st *cqspi = f_pdata->cqspi;
 409         void __iomem *reg_base = cqspi->iobase;
 410         unsigned int reg;
 411         unsigned int data;
 412         int ret;
 413
 414         if (n_tx > 4 || (n_tx && !txbuf)) {
 415                 dev_err(nor->dev,
 416                         "Invalid input argument, cmdlen %d txbuf 0x%p\n",
 417                         n_tx, txbuf);
 418                 return -EINVAL;
 419         }
 420
 421         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 422         if (n_tx) {
 423                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 424                 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 425                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 426                 data = 0;
 427                 memcpy(&data, txbuf, n_tx);
 428                 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
 429         }
 430
 431         ret = cqspi_exec_flash_cmd(cqspi, reg);
 432         return ret;
 433 }
 434
 435 static int cqspi_command_write_addr(struct spi_nor *nor,
 436                                     const u8 opcode, const unsigned int addr)
 437 {
 438         struct cqspi_flash_pdata *f_pdata = nor->priv;
 439         struct cqspi_st *cqspi = f_pdata->cqspi;
 440         void __iomem *reg_base = cqspi->iobase;
 441         unsigned int reg;
 442
 443         reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 444         reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 445         reg |= ((nor->addr_width - 1) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 446                 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 447
 448         writel(addr, reg_base + CQSPI_REG_CMDADDRESS);
 449
 450         return cqspi_exec_flash_cmd(cqspi, reg);
 451 }
 452
 453 static int cqspi_read_setup(struct spi_nor *nor)
 454 {
 455         struct cqspi_flash_pdata *f_pdata = nor->priv;
 456         struct cqspi_st *cqspi = f_pdata->cqspi;
 457         void __iomem *reg_base = cqspi->iobase;
 458         unsigned int dummy_clk = 0;
 459         unsigned int reg;
 460
 461         reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 462         reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
 463
 464         /* Setup dummy clock cycles */
 465         dummy_clk = nor->read_dummy;
 466         if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
 467                 dummy_clk = CQSPI_DUMMY_CLKS_MAX;
 468
 469         if (dummy_clk / 8) {
 470                 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 471                 /* Set mode bits high to ensure chip doesn't enter XIP */
 472                 writel(0xFF, reg_base + CQSPI_REG_MODE_BIT);
 473
 474                 /* Need to subtract the mode byte (8 clocks). */
 475                 if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD)
 476                         dummy_clk -= 8;
 477
 478                 if (dummy_clk)
 479                         reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 480                                << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 481         }
 482
 483         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 484
 485         /* Set address width */
 486         reg = readl(reg_base + CQSPI_REG_SIZE);
 487         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 488         reg |= (nor->addr_width - 1);
 489         writel(reg, reg_base + CQSPI_REG_SIZE);
 490         return 0;
 491 }
 492
 493 static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
 494                                        loff_t from_addr, const size_t n_rx)
 495 {
 496         struct cqspi_flash_pdata *f_pdata = nor->priv;
 497         struct cqspi_st *cqspi = f_pdata->cqspi;
 498         void __iomem *reg_base = cqspi->iobase;
 499         void __iomem *ahb_base = cqspi->ahb_base;
 500         unsigned int remaining = n_rx;
 501         unsigned int bytes_to_read = 0;
 502         int ret = 0;
 503
 504         writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
 505         writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
 506
 507         /* Clear all interrupts. */
 508         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 509
 510         writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 511
 512         reinit_completion(&cqspi->transfer_complete);
 513         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 514                reg_base + CQSPI_REG_INDIRECTRD);
 515
 516         while (remaining > 0) {
 517                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 518                                                   msecs_to_jiffies
 519                                                   (CQSPI_READ_TIMEOUT_MS));
 520
 521                 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 522
 523                 if (!ret && bytes_to_read == 0) {
 524                         dev_err(nor->dev, "Indirect read timeout, no bytes\n");
 525                         ret = -ETIMEDOUT;
 526                         goto failrd;
 527                 }
 528
 529                 while (bytes_to_read != 0) {
 530                         bytes_to_read *= cqspi->fifo_width;
 531                         bytes_to_read = bytes_to_read > remaining ?
 532                                         remaining : bytes_to_read;
 533                         ioread32_rep(ahb_base, rxbuf,
 534                                      DIV_ROUND_UP(bytes_to_read, 4));
 535                         rxbuf += bytes_to_read;
 536                         remaining -= bytes_to_read;
 537                         bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 538                 }
 539
 540                 if (remaining > 0)
 541                         reinit_completion(&cqspi->transfer_complete);
 542         }
 543
 544         /* Check indirect done status */
 545         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
 546                                  CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
 547         if (ret) {
 548                 dev_err(nor->dev,
 549                         "Indirect read completion error (%i)\n", ret);
 550                 goto failrd;
 551         }
 552
 553         /* Disable interrupt */
 554         writel(0, reg_base + CQSPI_REG_IRQMASK);
 555
 556         /* Clear indirect completion status */
 557         writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
 558
 559         return 0;
 560
 561 failrd:
 562         /* Disable interrupt */
 563         writel(0, reg_base + CQSPI_REG_IRQMASK);
 564
 565         /* Cancel the indirect read */
 566         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 567                reg_base + CQSPI_REG_INDIRECTRD);
 568         return ret;
 569 }
 570
 571 static int cqspi_write_setup(struct spi_nor *nor)
 572 {
 573         unsigned int reg;
 574         struct cqspi_flash_pdata *f_pdata = nor->priv;
 575         struct cqspi_st *cqspi = f_pdata->cqspi;
 576         void __iomem *reg_base = cqspi->iobase;
 577
 578         /* Set opcode. */
 579         reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 580         writel(reg, reg_base + CQSPI_REG_WR_INSTR);
 581         reg = cqspi_calc_rdreg(nor, nor->program_opcode);
 582         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 583
 584         reg = readl(reg_base + CQSPI_REG_SIZE);
 585         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 586         reg |= (nor->addr_width - 1);
 587         writel(reg, reg_base + CQSPI_REG_SIZE);
 588         return 0;
 589 }
 590
 591 static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
 592                                         const u8 *txbuf, const size_t n_tx)
 593 {
 594         const unsigned int page_size = nor->page_size;
 595         struct cqspi_flash_pdata *f_pdata = nor->priv;
 596         struct cqspi_st *cqspi = f_pdata->cqspi;
 597         void __iomem *reg_base = cqspi->iobase;
 598         unsigned int remaining = n_tx;
 599         unsigned int write_bytes;
 600         int ret;
 601
 602         writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
 603         writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
 604
 605         /* Clear all interrupts. */
 606         writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
 607
 608         writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
 609
 610         reinit_completion(&cqspi->transfer_complete);
 611         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 612                reg_base + CQSPI_REG_INDIRECTWR);
 613         /*
 614          * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
 615          * Controller programming sequence, couple of cycles of
 616          * QSPI_REF_CLK delay is required for the above bit to
 617          * be internally synchronized by the QSPI module. Provide 5
 618          * cycles of delay.
 619          */
 620         if (cqspi->wr_delay)
 621                 ndelay(cqspi->wr_delay);
 622
 623         while (remaining > 0) {
 624                 write_bytes = remaining > page_size ? page_size : remaining;
 625                 iowrite32_rep(cqspi->ahb_base, txbuf,
 626                               DIV_ROUND_UP(write_bytes, 4));
 627
 628                 ret = wait_for_completion_timeout(&cqspi->transfer_complete,
 629                                                   msecs_to_jiffies
 630                                                   (CQSPI_TIMEOUT_MS));
 631                 if (!ret) {
 632                         dev_err(nor->dev, "Indirect write timeout\n");
 633                         ret = -ETIMEDOUT;
 634                         goto failwr;
 635                 }
 636
 637                 txbuf += write_bytes;
 638                 remaining -= write_bytes;
 639
 640                 if (remaining > 0)
 641                         reinit_completion(&cqspi->transfer_complete);
 642         }
 643
 644         /* Check indirect done status */
 645         ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
 646                                  CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
 647         if (ret) {
 648                 dev_err(nor->dev,
 649                         "Indirect write completion error (%i)\n", ret);
 650                 goto failwr;
 651         }
 652
 653         /* Disable interrupt. */
 654         writel(0, reg_base + CQSPI_REG_IRQMASK);
 655
 656         /* Clear indirect completion status */
 657         writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
 658
 659         cqspi_wait_idle(cqspi);
 660
 661         return 0;
 662
 663 failwr:
 664         /* Disable interrupt. */
 665         writel(0, reg_base + CQSPI_REG_IRQMASK);
 666
 667         /* Cancel the indirect write */
 668         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 669                reg_base + CQSPI_REG_INDIRECTWR);
 670         return ret;
 671 }
 672
 673 static void cqspi_chipselect(struct spi_nor *nor)
 674 {
 675         struct cqspi_flash_pdata *f_pdata = nor->priv;
 676         struct cqspi_st *cqspi = f_pdata->cqspi;
 677         void __iomem *reg_base = cqspi->iobase;
 678         unsigned int chip_select = f_pdata->cs;
 679         unsigned int reg;
 680
 681         reg = readl(reg_base + CQSPI_REG_CONFIG);
 682         if (cqspi->is_decoded_cs) {
 683                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 684         } else {
 685                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 686
 687                 /* Convert CS if without decoder.
 688                  * CS0 to 4b'1110
 689                  * CS1 to 4b'1101
 690                  * CS2 to 4b'1011
 691                  * CS3 to 4b'0111
 692                  */
 693                 chip_select = 0xF & ~(1 << chip_select);
 694         }
 695
 696         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 697                  << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 698         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 699             << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 700         writel(reg, reg_base + CQSPI_REG_CONFIG);
 701 }
 702
 703 static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)
 704 {
 705         struct cqspi_flash_pdata *f_pdata = nor->priv;
 706         struct cqspi_st *cqspi = f_pdata->cqspi;
 707         void __iomem *iobase = cqspi->iobase;
 708         unsigned int reg;
 709
 710         /* configure page size and block size. */
 711         reg = readl(iobase + CQSPI_REG_SIZE);
 712         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 713         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 714         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 715         reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 716         reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);
 717         reg |= (nor->addr_width - 1);
 718         writel(reg, iobase + CQSPI_REG_SIZE);
 719
 720         /* configure the chip select */
 721         cqspi_chipselect(nor);
 722
 723         /* Store the new configuration of the controller */
 724         cqspi->current_page_size = nor->page_size;
 725         cqspi->current_erase_size = nor->mtd.erasesize;
 726         cqspi->current_addr_width = nor->addr_width;
 727 }
 728
 729 static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,
 730                                            const unsigned int ns_val)
 731 {
 732         unsigned int ticks;
 733
 734         ticks = ref_clk_hz / 1000;      /* kHz */
 735         ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
 736
 737         return ticks;
 738 }
 739
 740 static void cqspi_delay(struct spi_nor *nor)
 741 {
 742         struct cqspi_flash_pdata *f_pdata = nor->priv;
 743         struct cqspi_st *cqspi = f_pdata->cqspi;
 744         void __iomem *iobase = cqspi->iobase;
 745         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 746         unsigned int tshsl, tchsh, tslch, tsd2d;
 747         unsigned int reg;
 748         unsigned int tsclk;
 749
 750         /* calculate the number of ref ticks for one sclk tick */
 751         tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
 752
 753         tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns);
 754         /* this particular value must be at least one sclk */
 755         if (tshsl < tsclk)
 756                 tshsl = tsclk;
 757
 758         tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
 759         tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
 760         tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
 761
 762         reg = (tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 763                << CQSPI_REG_DELAY_TSHSL_LSB;
 764         reg |= (tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 765                 << CQSPI_REG_DELAY_TCHSH_LSB;
 766         reg |= (tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 767                 << CQSPI_REG_DELAY_TSLCH_LSB;
 768         reg |= (tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 769                 << CQSPI_REG_DELAY_TSD2D_LSB;
 770         writel(reg, iobase + CQSPI_REG_DELAY);
 771 }
 772
 773 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
 774 {
 775         const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
 776         void __iomem *reg_base = cqspi->iobase;
 777         u32 reg, div;
 778
 779         /* Recalculate the baudrate divisor based on QSPI specification. */
 780         div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
 781
 782         reg = readl(reg_base + CQSPI_REG_CONFIG);
 783         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 784         reg |= (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 785         writel(reg, reg_base + CQSPI_REG_CONFIG);
 786 }
 787
 788 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
 789                                    const bool bypass,
 790                                    const unsigned int delay)
 791 {
 792         void __iomem *reg_base = cqspi->iobase;
 793         unsigned int reg;
 794
 795         reg = readl(reg_base + CQSPI_REG_READCAPTURE);
 796
 797         if (bypass)
 798                 reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 799         else
 800                 reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);
 801
 802         reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK
 803                  << CQSPI_REG_READCAPTURE_DELAY_LSB);
 804
 805         reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK)
 806                 << CQSPI_REG_READCAPTURE_DELAY_LSB;
 807
 808         writel(reg, reg_base + CQSPI_REG_READCAPTURE);
 809 }
 810
 811 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
 812 {
 813         void __iomem *reg_base = cqspi->iobase;
 814         unsigned int reg;
 815
 816         reg = readl(reg_base + CQSPI_REG_CONFIG);
 817
 818         if (enable)
 819                 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 820         else
 821                 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 822
 823         writel(reg, reg_base + CQSPI_REG_CONFIG);
 824 }
 825
 826 static void cqspi_configure(struct spi_nor *nor)
 827 {
 828         struct cqspi_flash_pdata *f_pdata = nor->priv;
 829         struct cqspi_st *cqspi = f_pdata->cqspi;
 830         const unsigned int sclk = f_pdata->clk_rate;
 831         int switch_cs = (cqspi->current_cs != f_pdata->cs);
 832         int switch_ck = (cqspi->sclk != sclk);
 833
 834         if ((cqspi->current_page_size != nor->page_size) ||
 835             (cqspi->current_erase_size != nor->mtd.erasesize) ||
 836             (cqspi->current_addr_width != nor->addr_width))
 837                 switch_cs = 1;
 838
 839         if (switch_cs || switch_ck)
 840                 cqspi_controller_enable(cqspi, 0);
 841
 842         /* Switch chip select. */
 843         if (switch_cs) {
 844                 cqspi->current_cs = f_pdata->cs;
 845                 cqspi_configure_cs_and_sizes(nor);
 846         }
 847
 848         /* Setup baudrate divisor and delays */
 849         if (switch_ck) {
 850                 cqspi->sclk = sclk;
 851                 cqspi_config_baudrate_div(cqspi);
 852                 cqspi_delay(nor);
 853                 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
 854                                        f_pdata->read_delay);
 855         }
 856
 857         if (switch_cs || switch_ck)
 858                 cqspi_controller_enable(cqspi, 1);
 859 }
 860
 861 static int cqspi_set_protocol(struct spi_nor *nor, const int read)
 862 {
 863         struct cqspi_flash_pdata *f_pdata = nor->priv;
 864
 865         f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
 866         f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
 867         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 868
 869         if (read) {
 870                 switch (nor->read_proto) {
 871                 case SNOR_PROTO_1_1_1:
 872                         f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
 873                         break;
 874                 case SNOR_PROTO_1_1_2:
 875                         f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
 876                         break;
 877                 case SNOR_PROTO_1_1_4:
 878                         f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
 879                         break;
 880                 default:
 881                         return -EINVAL;
 882                 }
 883         }
 884
 885         cqspi_configure(nor);
 886
 887         return 0;
 888 }
 889
 890 static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
 891                            size_t len, const u_char *buf)
 892 {
 893         int ret;
 894
 895         ret = cqspi_set_protocol(nor, 0);
 896         if (ret)
 897                 return ret;
 898
 899         ret = cqspi_write_setup(nor);
 900         if (ret)
 901                 return ret;
 902
 903         ret = cqspi_indirect_write_execute(nor, to, buf, len);
 904         if (ret)
 905                 return ret;
 906
 907         return len;
 908 }
 909
 910 static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
 911                           size_t len, u_char *buf)
 912 {
 913         int ret;
 914
 915         ret = cqspi_set_protocol(nor, 1);
 916         if (ret)
 917                 return ret;
 918
 919         ret = cqspi_read_setup(nor);
 920         if (ret)
 921                 return ret;
 922
 923         ret = cqspi_indirect_read_execute(nor, buf, from, len);
 924         if (ret)
 925                 return ret;
 926
 927         return len;
 928 }
 929
 930 static int cqspi_erase(struct spi_nor *nor, loff_t offs)
 931 {
 932         int ret;
 933
 934         ret = cqspi_set_protocol(nor, 0);
 935         if (ret)
 936                 return ret;
 937
 938         /* Send write enable, then erase commands. */
 939         ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 940         if (ret)
 941                 return ret;
 942
 943         /* Set up command buffer. */
 944         ret = cqspi_command_write_addr(nor, nor->erase_opcode, offs);
 945         if (ret)
 946                 return ret;
 947
 948         return 0;
 949 }
 950
 951 static int cqspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
 952 {
 953         struct cqspi_flash_pdata *f_pdata = nor->priv;
 954         struct cqspi_st *cqspi = f_pdata->cqspi;
 955
 956         mutex_lock(&cqspi->bus_mutex);
 957
 958         return 0;
 959 }
 960
 961 static void cqspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
 962 {
 963         struct cqspi_flash_pdata *f_pdata = nor->priv;
 964         struct cqspi_st *cqspi = f_pdata->cqspi;
 965
 966         mutex_unlock(&cqspi->bus_mutex);
 967 }
 968
 969 static int cqspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 970 {
 971         int ret;
 972
 973         ret = cqspi_set_protocol(nor, 0);
 974         if (!ret)
 975                 ret = cqspi_command_read(nor, &opcode, 1, buf, len);
 976
 977         return ret;
 978 }
 979
 980 static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 981 {
 982         int ret;
 983
 984         ret = cqspi_set_protocol(nor, 0);
 985         if (!ret)
 986                 ret = cqspi_command_write(nor, opcode, buf, len);
 987
 988         return ret;
 989 }
 990
 991 static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
 992                                     struct cqspi_flash_pdata *f_pdata,
 993                                     struct device_node *np)
 994 {
 995         if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) {
 996                 dev_err(&pdev->dev, "couldn't determine read-delay\n");
 997                 return -ENXIO;
 998         }
 999
1000         if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) {
1001                 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n");
1002                 return -ENXIO;
1003         }
1004
1005         if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) {
1006                 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n");
1007                 return -ENXIO;
1008         }
1009
1010         if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) {
1011                 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n");
1012                 return -ENXIO;
1013         }
1014
1015         if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) {
1016                 dev_err(&pdev->dev, "couldn't determine tslch-ns\n");
1017                 return -ENXIO;
1018         }
1019
1020         if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) {
1021                 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n");
1022                 return -ENXIO;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static int cqspi_of_get_pdata(struct platform_device *pdev)
1029 {
1030         struct device_node *np = pdev->dev.of_node;
1031         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1032
1033         cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1034
1035         if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1036                 dev_err(&pdev->dev, "couldn't determine fifo-depth\n");
1037                 return -ENXIO;
1038         }
1039
1040         if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1041                 dev_err(&pdev->dev, "couldn't determine fifo-width\n");
1042                 return -ENXIO;
1043         }
1044
1045         if (of_property_read_u32(np, "cdns,trigger-address",
1046                                  &cqspi->trigger_address)) {
1047                 dev_err(&pdev->dev, "couldn't determine trigger-address\n");
1048                 return -ENXIO;
1049         }
1050
1051         cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1052
1053         return 0;
1054 }
1055
1056 static void cqspi_controller_init(struct cqspi_st *cqspi)
1057 {
1058         cqspi_controller_enable(cqspi, 0);
1059
1060         /* Configure the remap address register, no remap */
1061         writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1062
1063         /* Disable all interrupts. */
1064         writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1065
1066         /* Configure the SRAM split to 1:1 . */
1067         writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1068
1069         /* Load indirect trigger address. */
1070         writel(cqspi->trigger_address,
1071                cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1072
1073         /* Program read watermark -- 1/2 of the FIFO. */
1074         writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1075                cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1076         /* Program write watermark -- 1/8 of the FIFO. */
1077         writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1078                cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1079
1080         cqspi_controller_enable(cqspi, 1);
1081 }
1082
1083 static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
1084 {
1085         const struct spi_nor_hwcaps hwcaps = {
1086                 .mask = SNOR_HWCAPS_READ |
1087                         SNOR_HWCAPS_READ_FAST |
1088                         SNOR_HWCAPS_READ_1_1_2 |
1089                         SNOR_HWCAPS_READ_1_1_4 |
1090                         SNOR_HWCAPS_PP,
1091         };
1092         struct platform_device *pdev = cqspi->pdev;
1093         struct device *dev = &pdev->dev;
1094         struct cqspi_flash_pdata *f_pdata;
1095         struct spi_nor *nor;
1096         struct mtd_info *mtd;
1097         unsigned int cs;
1098         int i, ret;
1099
1100         /* Get flash device data */
1101         for_each_available_child_of_node(dev->of_node, np) {
1102                 ret = of_property_read_u32(np, "reg", &cs);
1103                 if (ret) {
1104                         dev_err(dev, "Couldn't determine chip select.\n");
1105                         goto err;
1106                 }
1107
1108                 if (cs >= CQSPI_MAX_CHIPSELECT) {
1109                         ret = -EINVAL;
1110                         dev_err(dev, "Chip select %d out of range.\n", cs);
1111                         goto err;
1112                 }
1113
1114                 f_pdata = &cqspi->f_pdata[cs];
1115                 f_pdata->cqspi = cqspi;
1116                 f_pdata->cs = cs;
1117
1118                 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1119                 if (ret)
1120                         goto err;
1121
1122                 nor = &f_pdata->nor;
1123                 mtd = &nor->mtd;
1124
1125                 mtd->priv = nor;
1126
1127                 nor->dev = dev;
1128                 spi_nor_set_flash_node(nor, np);
1129                 nor->priv = f_pdata;
1130
1131                 nor->read_reg = cqspi_read_reg;
1132                 nor->write_reg = cqspi_write_reg;
1133                 nor->read = cqspi_read;
1134                 nor->write = cqspi_write;
1135                 nor->erase = cqspi_erase;
1136                 nor->prepare = cqspi_prep;
1137                 nor->unprepare = cqspi_unprep;
1138
1139                 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d",
1140                                            dev_name(dev), cs);
1141                 if (!mtd->name) {
1142                         ret = -ENOMEM;
1143                         goto err;
1144                 }
1145
1146                 ret = spi_nor_scan(nor, NULL, &hwcaps);
1147                 if (ret)
1148                         goto err;
1149
1150                 ret = mtd_device_register(mtd, NULL, 0);
1151                 if (ret)
1152                         goto err;
1153
1154                 f_pdata->registered = true;
1155         }
1156
1157         return 0;
1158
1159 err:
1160         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1161                 if (cqspi->f_pdata[i].registered)
1162                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1163         return ret;
1164 }
1165
1166 static int cqspi_probe(struct platform_device *pdev)
1167 {
1168         struct device_node *np = pdev->dev.of_node;
1169         struct device *dev = &pdev->dev;
1170         struct cqspi_st *cqspi;
1171         struct resource *res;
1172         struct resource *res_ahb;
1173         unsigned long data;
1174         int ret;
1175         int irq;
1176
1177         cqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);
1178         if (!cqspi)
1179                 return -ENOMEM;
1180
1181         mutex_init(&cqspi->bus_mutex);
1182         cqspi->pdev = pdev;
1183         platform_set_drvdata(pdev, cqspi);
1184
1185         /* Obtain configuration from OF. */
1186         ret = cqspi_of_get_pdata(pdev);
1187         if (ret) {
1188                 dev_err(dev, "Cannot get mandatory OF data.\n");
1189                 return -ENODEV;
1190         }
1191
1192         /* Obtain QSPI clock. */
1193         cqspi->clk = devm_clk_get(dev, NULL);
1194         if (IS_ERR(cqspi->clk)) {
1195                 dev_err(dev, "Cannot claim QSPI clock.\n");
1196                 return PTR_ERR(cqspi->clk);
1197         }
1198
1199         /* Obtain and remap controller address. */
1200         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201         cqspi->iobase = devm_ioremap_resource(dev, res);
1202         if (IS_ERR(cqspi->iobase)) {
1203                 dev_err(dev, "Cannot remap controller address.\n");
1204                 return PTR_ERR(cqspi->iobase);
1205         }
1206
1207         /* Obtain and remap AHB address. */
1208         res_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1209         cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);
1210         if (IS_ERR(cqspi->ahb_base)) {
1211                 dev_err(dev, "Cannot remap AHB address.\n");
1212                 return PTR_ERR(cqspi->ahb_base);
1213         }
1214
1215         init_completion(&cqspi->transfer_complete);
1216
1217         /* Obtain IRQ line. */
1218         irq = platform_get_irq(pdev, 0);
1219         if (irq < 0) {
1220                 dev_err(dev, "Cannot obtain IRQ.\n");
1221                 return -ENXIO;
1222         }
1223
1224         pm_runtime_enable(dev);
1225         ret = pm_runtime_get_sync(dev);
1226         if (ret < 0) {
1227                 pm_runtime_put_noidle(dev);
1228                 return ret;
1229         }
1230
1231         ret = clk_prepare_enable(cqspi->clk);
1232         if (ret) {
1233                 dev_err(dev, "Cannot enable QSPI clock.\n");
1234                 goto probe_clk_failed;
1235         }
1236
1237         cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1238         data  = (unsigned long)of_device_get_match_data(dev);
1239         if (data & CQSPI_NEEDS_WR_DELAY)
1240                 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
1241                                                    cqspi->master_ref_clk_hz);
1242
1243         ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1244                                pdev->name, cqspi);
1245         if (ret) {
1246                 dev_err(dev, "Cannot request IRQ.\n");
1247                 goto probe_irq_failed;
1248         }
1249
1250         cqspi_wait_idle(cqspi);
1251         cqspi_controller_init(cqspi);
1252         cqspi->current_cs = -1;
1253         cqspi->sclk = 0;
1254
1255         ret = cqspi_setup_flash(cqspi, np);
1256         if (ret) {
1257                 dev_err(dev, "Cadence QSPI NOR probe failed %d\n", ret);
1258                 goto probe_setup_failed;
1259         }
1260
1261         return ret;
1262 probe_setup_failed:
1263         cqspi_controller_enable(cqspi, 0);
1264 probe_irq_failed:
1265         clk_disable_unprepare(cqspi->clk);
1266 probe_clk_failed:
1267         pm_runtime_put_sync(dev);
1268         pm_runtime_disable(dev);
1269         return ret;
1270 }
1271
1272 static int cqspi_remove(struct platform_device *pdev)
1273 {
1274         struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1275         int i;
1276
1277         for (i = 0; i < CQSPI_MAX_CHIPSELECT; i++)
1278                 if (cqspi->f_pdata[i].registered)
1279                         mtd_device_unregister(&cqspi->f_pdata[i].nor.mtd);
1280
1281         cqspi_controller_enable(cqspi, 0);
1282
1283         clk_disable_unprepare(cqspi->clk);
1284
1285         pm_runtime_put_sync(&pdev->dev);
1286         pm_runtime_disable(&pdev->dev);
1287
1288         return 0;
1289 }
1290
1291 #ifdef CONFIG_PM_SLEEP
1292 static int cqspi_suspend(struct device *dev)
1293 {
1294         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1295
1296         cqspi_controller_enable(cqspi, 0);
1297         return 0;
1298 }
1299
1300 static int cqspi_resume(struct device *dev)
1301 {
1302         struct cqspi_st *cqspi = dev_get_drvdata(dev);
1303
1304         cqspi_controller_enable(cqspi, 1);
1305         return 0;
1306 }
1307
1308 static const struct dev_pm_ops cqspi__dev_pm_ops = {
1309         .suspend = cqspi_suspend,
1310         .resume = cqspi_resume,
1311 };
1312
1313 #define CQSPI_DEV_PM_OPS        (&cqspi__dev_pm_ops)
1314 #else
1315 #define CQSPI_DEV_PM_OPS        NULL
1316 #endif
1317
1318 static const struct of_device_id cqspi_dt_ids[] = {
1319         {
1320                 .compatible = "cdns,qspi-nor",
1321                 .data = (void *)0,
1322         },
1323         {
1324                 .compatible = "ti,k2g-qspi",
1325                 .data = (void *)CQSPI_NEEDS_WR_DELAY,
1326         },
1327         { /* end of table */ }
1328 };
1329
1330 MODULE_DEVICE_TABLE(of, cqspi_dt_ids);
1331
1332 static struct platform_driver cqspi_platform_driver = {
1333         .probe = cqspi_probe,
1334         .remove = cqspi_remove,
1335         .driver = {
1336                 .name = CQSPI_NAME,
1337                 .pm = CQSPI_DEV_PM_OPS,
1338                 .of_match_table = cqspi_dt_ids,
1339         },
1340 };
1341
1342 module_platform_driver(cqspi_platform_driver);
1343
1344 MODULE_DESCRIPTION("Cadence QSPI Controller Driver");
1345 MODULE_LICENSE("GPL v2");
1346 MODULE_ALIAS("platform:" CQSPI_NAME);
1347 MODULE_AUTHOR("Ley Foon Tan <lftan@altera.com>");
1348 MODULE_AUTHOR("Graham Moore <grmoore@opensource.altera.com>");