drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright © 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/mtd.h>
  29 #include <linux/mtd/onenand.h>
  30 #include <linux/mtd/partitions.h>
  31 #include <linux/of_device.h>
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/delay.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/io.h>
  39 #include <linux/slab.h>
  40 #include <linux/gpio/consumer.h>
  41
  42 #include <asm/mach/flash.h>
  43
  44 #define DRIVER_NAME "omap2-onenand"
  45
  46 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  47
  48 struct omap2_onenand {
  49         struct platform_device *pdev;
  50         int gpmc_cs;
  51         unsigned long phys_base;
  52         struct gpio_desc *int_gpiod;
  53         struct mtd_info mtd;
  54         struct onenand_chip onenand;
  55         struct completion irq_done;
  56         struct completion dma_done;
  57         struct dma_chan *dma_chan;
  58 };
  59
  60 static void omap2_onenand_dma_complete_func(void *completion)
  61 {
  62         complete(completion);
  63 }
  64
  65 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  66 {
  67         struct omap2_onenand *c = dev_id;
  68
  69         complete(&c->irq_done);
  70
  71         return IRQ_HANDLED;
  72 }
  73
  74 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  75 {
  76         return readw(c->onenand.base + reg);
  77 }
  78
  79 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  80                              int reg)
  81 {
  82         writew(value, c->onenand.base + reg);
  83 }
  84
  85 static int omap2_onenand_set_cfg(struct omap2_onenand *c,
  86                                  bool sr, bool sw,
  87                                  int latency, int burst_len)
  88 {
  89         unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
  90
  91         reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
  92
  93         switch (burst_len) {
  94         case 0:         /* continuous */
  95                 break;
  96         case 4:
  97                 reg |= ONENAND_SYS_CFG1_BL_4;
  98                 break;
  99         case 8:
 100                 reg |= ONENAND_SYS_CFG1_BL_8;
 101                 break;
 102         case 16:
 103                 reg |= ONENAND_SYS_CFG1_BL_16;
 104                 break;
 105         case 32:
 106                 reg |= ONENAND_SYS_CFG1_BL_32;
 107                 break;
 108         default:
 109                 return -EINVAL;
 110         }
 111
 112         if (latency > 5)
 113                 reg |= ONENAND_SYS_CFG1_HF;
 114         if (latency > 7)
 115                 reg |= ONENAND_SYS_CFG1_VHF;
 116         if (sr)
 117                 reg |= ONENAND_SYS_CFG1_SYNC_READ;
 118         if (sw)
 119                 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
 120
 121         write_reg(c, reg, ONENAND_REG_SYS_CFG1);
 122
 123         return 0;
 124 }
 125
 126 static int omap2_onenand_get_freq(int ver)
 127 {
 128         switch ((ver >> 4) & 0xf) {
 129         case 0:
 130                 return 40;
 131         case 1:
 132                 return 54;
 133         case 2:
 134                 return 66;
 135         case 3:
 136                 return 83;
 137         case 4:
 138                 return 104;
 139         }
 140
 141         return -EINVAL;
 142 }
 143
 144 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
 145 {
 146         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
 147                msg, state, ctrl, intr);
 148 }
 149
 150 static void wait_warn(char *msg, int state, unsigned int ctrl,
 151                       unsigned int intr)
 152 {
 153         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 154                "intr 0x%04x\n", msg, state, ctrl, intr);
 155 }
 156
 157 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 158 {
 159         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 160         struct onenand_chip *this = mtd->priv;
 161         unsigned int intr = 0;
 162         unsigned int ctrl, ctrl_mask;
 163         unsigned long timeout;
 164         u32 syscfg;
 165
 166         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 167             state == FL_VERIFYING_ERASE) {
 168                 int i = 21;
 169                 unsigned int intr_flags = ONENAND_INT_MASTER;
 170
 171                 switch (state) {
 172                 case FL_RESETING:
 173                         intr_flags |= ONENAND_INT_RESET;
 174                         break;
 175                 case FL_PREPARING_ERASE:
 176                         intr_flags |= ONENAND_INT_ERASE;
 177                         break;
 178                 case FL_VERIFYING_ERASE:
 179                         i = 101;
 180                         break;
 181                 }
 182
 183                 while (--i) {
 184                         udelay(1);
 185                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 186                         if (intr & ONENAND_INT_MASTER)
 187                                 break;
 188                 }
 189                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 190                 if (ctrl & ONENAND_CTRL_ERROR) {
 191                         wait_err("controller error", state, ctrl, intr);
 192                         return -EIO;
 193                 }
 194                 if ((intr & intr_flags) == intr_flags)
 195                         return 0;
 196                 /* Continue in wait for interrupt branch */
 197         }
 198
 199         if (state != FL_READING) {
 200                 int result;
 201
 202                 /* Turn interrupts on */
 203                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 204                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 205                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 206                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 207                         /* Add a delay to let GPIO settle */
 208                         syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 209                 }
 210
 211                 reinit_completion(&c->irq_done);
 212                 result = gpiod_get_value(c->int_gpiod);
 213                 if (result < 0) {
 214                         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 215                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 216                         wait_err("gpio error", state, ctrl, intr);
 217                         return result;
 218                 } else if (result == 0) {
 219                         int retry_cnt = 0;
 220 retry:
 221                         if (!wait_for_completion_io_timeout(&c->irq_done,
 222                                                 msecs_to_jiffies(20))) {
 223                                 /* Timeout after 20ms */
 224                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 225                                 if (ctrl & ONENAND_CTRL_ONGO &&
 226                                     !this->ongoing) {
 227                                         /*
 228                                          * The operation seems to be still going
 229                                          * so give it some more time.
 230                                          */
 231                                         retry_cnt += 1;
 232                                         if (retry_cnt < 3)
 233                                                 goto retry;
 234                                         intr = read_reg(c,
 235                                                         ONENAND_REG_INTERRUPT);
 236                                         wait_err("timeout", state, ctrl, intr);
 237                                         return -EIO;
 238                                 }
 239                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 240                                 if ((intr & ONENAND_INT_MASTER) == 0)
 241                                         wait_warn("timeout", state, ctrl, intr);
 242                         }
 243                 }
 244         } else {
 245                 int retry_cnt = 0;
 246
 247                 /* Turn interrupts off */
 248                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 249                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 250                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 251
 252                 timeout = jiffies + msecs_to_jiffies(20);
 253                 while (1) {
 254                         if (time_before(jiffies, timeout)) {
 255                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 256                                 if (intr & ONENAND_INT_MASTER)
 257                                         break;
 258                         } else {
 259                                 /* Timeout after 20ms */
 260                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 261                                 if (ctrl & ONENAND_CTRL_ONGO) {
 262                                         /*
 263                                          * The operation seems to be still going
 264                                          * so give it some more time.
 265                                          */
 266                                         retry_cnt += 1;
 267                                         if (retry_cnt < 3) {
 268                                                 timeout = jiffies +
 269                                                           msecs_to_jiffies(20);
 270                                                 continue;
 271                                         }
 272                                 }
 273                                 break;
 274                         }
 275                 }
 276         }
 277
 278         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 279         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 280
 281         if (intr & ONENAND_INT_READ) {
 282                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 283
 284                 if (ecc) {
 285                         unsigned int addr1, addr8;
 286
 287                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 288                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 289                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 290                                 printk(KERN_ERR "onenand_wait: ECC error = "
 291                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 292                                        ecc, addr1, addr8);
 293                                 mtd->ecc_stats.failed++;
 294                                 return -EBADMSG;
 295                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 296                                 printk(KERN_NOTICE "onenand_wait: correctable "
 297                                        "ECC error = 0x%04x, addr1 %#x, "
 298                                        "addr8 %#x\n", ecc, addr1, addr8);
 299                                 mtd->ecc_stats.corrected++;
 300                         }
 301                 }
 302         } else if (state == FL_READING) {
 303                 wait_err("timeout", state, ctrl, intr);
 304                 return -EIO;
 305         }
 306
 307         if (ctrl & ONENAND_CTRL_ERROR) {
 308                 wait_err("controller error", state, ctrl, intr);
 309                 if (ctrl & ONENAND_CTRL_LOCK)
 310                         printk(KERN_ERR "onenand_wait: "
 311                                         "Device is write protected!!!\n");
 312                 return -EIO;
 313         }
 314
 315         ctrl_mask = 0xFE9F;
 316         if (this->ongoing)
 317                 ctrl_mask &= ~0x8000;
 318
 319         if (ctrl & ctrl_mask)
 320                 wait_warn("unexpected controller status", state, ctrl, intr);
 321
 322         return 0;
 323 }
 324
 325 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 326 {
 327         struct onenand_chip *this = mtd->priv;
 328
 329         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 330                 if (area == ONENAND_DATARAM)
 331                         return this->writesize;
 332                 if (area == ONENAND_SPARERAM)
 333                         return mtd->oobsize;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static inline int omap2_onenand_dma_transfer(struct omap2_onenand *c,
 340                                              dma_addr_t src, dma_addr_t dst,
 341                                              size_t count)
 342 {
 343         struct dma_async_tx_descriptor *tx;
 344         dma_cookie_t cookie;
 345
 346         tx = dmaengine_prep_dma_memcpy(c->dma_chan, dst, src, count, 0);
 347         if (!tx) {
 348                 dev_err(&c->pdev->dev, "Failed to prepare DMA memcpy\n");
 349                 return -EIO;
 350         }
 351
 352         reinit_completion(&c->dma_done);
 353
 354         tx->callback = omap2_onenand_dma_complete_func;
 355         tx->callback_param = &c->dma_done;
 356
 357         cookie = tx->tx_submit(tx);
 358         if (dma_submit_error(cookie)) {
 359                 dev_err(&c->pdev->dev, "Failed to do DMA tx_submit\n");
 360                 return -EIO;
 361         }
 362
 363         dma_async_issue_pending(c->dma_chan);
 364
 365         if (!wait_for_completion_io_timeout(&c->dma_done,
 366                                             msecs_to_jiffies(20))) {
 367                 dmaengine_terminate_sync(c->dma_chan);
 368                 return -ETIMEDOUT;
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 375                                         unsigned char *buffer, int offset,
 376                                         size_t count)
 377 {
 378         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 379         struct onenand_chip *this = mtd->priv;
 380         dma_addr_t dma_src, dma_dst;
 381         int bram_offset;
 382         void *buf = (void *)buffer;
 383         size_t xtra;
 384         int ret;
 385
 386         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 387         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 388                 goto out_copy;
 389
 390         /* panic_write() may be in an interrupt context */
 391         if (in_interrupt() || oops_in_progress)
 392                 goto out_copy;
 393
 394         if (buf >= high_memory) {
 395                 struct page *p1;
 396
 397                 if (((size_t)buf & PAGE_MASK) !=
 398                     ((size_t)(buf + count - 1) & PAGE_MASK))
 399                         goto out_copy;
 400                 p1 = vmalloc_to_page(buf);
 401                 if (!p1)
 402                         goto out_copy;
 403                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 404         }
 405
 406         xtra = count & 3;
 407         if (xtra) {
 408                 count -= xtra;
 409                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 410         }
 411
 412         dma_src = c->phys_base + bram_offset;
 413         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 414         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 415                 dev_err(&c->pdev->dev,
 416                         "Couldn't DMA map a %d byte buffer\n",
 417                         count);
 418                 goto out_copy;
 419         }
 420
 421         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 422         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 423
 424         if (ret) {
 425                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 426                 goto out_copy;
 427         }
 428
 429         return 0;
 430
 431 out_copy:
 432         memcpy(buf, this->base + bram_offset, count);
 433         return 0;
 434 }
 435
 436 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 437                                          const unsigned char *buffer,
 438                                          int offset, size_t count)
 439 {
 440         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 441         struct onenand_chip *this = mtd->priv;
 442         dma_addr_t dma_src, dma_dst;
 443         int bram_offset;
 444         void *buf = (void *)buffer;
 445         int ret;
 446
 447         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 448         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 449                 goto out_copy;
 450
 451         /* panic_write() may be in an interrupt context */
 452         if (in_interrupt() || oops_in_progress)
 453                 goto out_copy;
 454
 455         if (buf >= high_memory) {
 456                 struct page *p1;
 457
 458                 if (((size_t)buf & PAGE_MASK) !=
 459                     ((size_t)(buf + count - 1) & PAGE_MASK))
 460                         goto out_copy;
 461                 p1 = vmalloc_to_page(buf);
 462                 if (!p1)
 463                         goto out_copy;
 464                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 465         }
 466
 467         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 468         dma_dst = c->phys_base + bram_offset;
 469         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 470                 dev_err(&c->pdev->dev,
 471                         "Couldn't DMA map a %d byte buffer\n",
 472                         count);
 473                 return -1;
 474         }
 475
 476         ret = omap2_onenand_dma_transfer(c, dma_src, dma_dst, count);
 477         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 478
 479         if (ret) {
 480                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 481                 goto out_copy;
 482         }
 483
 484         return 0;
 485
 486 out_copy:
 487         memcpy(this->base + bram_offset, buf, count);
 488         return 0;
 489 }
 490
 491 static void omap2_onenand_shutdown(struct platform_device *pdev)
 492 {
 493         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 494
 495         /* With certain content in the buffer RAM, the OMAP boot ROM code
 496          * can recognize the flash chip incorrectly. Zero it out before
 497          * soft reset.
 498          */
 499         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 500 }
 501
 502 static int omap2_onenand_probe(struct platform_device *pdev)
 503 {
 504         u32 val;
 505         dma_cap_mask_t mask;
 506         int freq, latency, r;
 507         struct resource *res;
 508         struct omap2_onenand *c;
 509         struct gpmc_onenand_info info;
 510         struct device *dev = &pdev->dev;
 511         struct device_node *np = dev->of_node;
 512
 513         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 514         if (!res) {
 515                 dev_err(dev, "error getting memory resource\n");
 516                 return -EINVAL;
 517         }
 518
 519         r = of_property_read_u32(np, "reg", &val);
 520         if (r) {
 521                 dev_err(dev, "reg not found in DT\n");
 522                 return r;
 523         }
 524
 525         c = devm_kzalloc(dev, sizeof(struct omap2_onenand), GFP_KERNEL);
 526         if (!c)
 527                 return -ENOMEM;
 528
 529         init_completion(&c->irq_done);
 530         init_completion(&c->dma_done);
 531         c->gpmc_cs = val;
 532         c->phys_base = res->start;
 533
 534         c->onenand.base = devm_ioremap_resource(dev, res);
 535         if (IS_ERR(c->onenand.base)) {
 536                 dev_err(dev, "Cannot reserve memory region at 0x%08x, size: 0x%x\n",
 537                         res->start, resource_size(res));
 538                 return PTR_ERR(c->onenand.base);
 539         }
 540
 541         c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN);
 542         if (IS_ERR(c->int_gpiod)) {
 543                 r = PTR_ERR(c->int_gpiod);
 544                 /* Just try again if this happens */
 545                 if (r != -EPROBE_DEFER)
 546                         dev_err(dev, "error getting gpio: %d\n", r);
 547                 return r;
 548         }
 549
 550         if (c->int_gpiod) {
 551                 r = devm_request_irq(dev, gpiod_to_irq(c->int_gpiod),
 552                                      omap2_onenand_interrupt,
 553                                      IRQF_TRIGGER_RISING, "onenand", c);
 554                 if (r)
 555                         return r;
 556
 557                 c->onenand.wait = omap2_onenand_wait;
 558         }
 559
 560         dma_cap_zero(mask);
 561         dma_cap_set(DMA_MEMCPY, mask);
 562
 563         c->dma_chan = dma_request_channel(mask, NULL, NULL);
 564         if (c->dma_chan) {
 565                 c->onenand.read_bufferram = omap2_onenand_read_bufferram;
 566                 c->onenand.write_bufferram = omap2_onenand_write_bufferram;
 567         }
 568
 569         c->pdev = pdev;
 570         c->mtd.priv = &c->onenand;
 571         c->mtd.dev.parent = dev;
 572         mtd_set_of_node(&c->mtd, dev->of_node);
 573
 574         dev_info(dev, "initializing on CS%d (0x%08lx), va %p, %s mode\n",
 575                  c->gpmc_cs, c->phys_base, c->onenand.base,
 576                  c->dma_chan ? "DMA" : "PIO");
 577
 578         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 579                 goto err_release_dma;
 580
 581         freq = omap2_onenand_get_freq(c->onenand.version_id);
 582         if (freq > 0) {
 583                 switch (freq) {
 584                 case 104:
 585                         latency = 7;
 586                         break;
 587                 case 83:
 588                         latency = 6;
 589                         break;
 590                 case 66:
 591                         latency = 5;
 592                         break;
 593                 case 56:
 594                         latency = 4;
 595                         break;
 596                 default:        /* 40 MHz or lower */
 597                         latency = 3;
 598                         break;
 599                 }
 600
 601                 r = gpmc_omap_onenand_set_timings(dev, c->gpmc_cs,
 602                                                   freq, latency, &info);
 603                 if (r)
 604                         goto err_release_onenand;
 605
 606                 r = omap2_onenand_set_cfg(c, info.sync_read, info.sync_write,
 607                                           latency, info.burst_len);
 608                 if (r)
 609                         goto err_release_onenand;
 610
 611                 if (info.sync_read || info.sync_write)
 612                         dev_info(dev, "optimized timings for %d MHz\n", freq);
 613         }
 614
 615         r = mtd_device_register(&c->mtd, NULL, 0);
 616         if (r)
 617                 goto err_release_onenand;
 618
 619         platform_set_drvdata(pdev, c);
 620
 621         return 0;
 622
 623 err_release_onenand:
 624         onenand_release(&c->mtd);
 625 err_release_dma:
 626         if (c->dma_chan)
 627                 dma_release_channel(c->dma_chan);
 628
 629         return r;
 630 }
 631
 632 static int omap2_onenand_remove(struct platform_device *pdev)
 633 {
 634         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 635
 636         onenand_release(&c->mtd);
 637         if (c->dma_chan)
 638                 dma_release_channel(c->dma_chan);
 639         omap2_onenand_shutdown(pdev);
 640
 641         return 0;
 642 }
 643
 644 static const struct of_device_id omap2_onenand_id_table[] = {
 645         { .compatible = "ti,omap2-onenand", },
 646         {},
 647 };
 648 MODULE_DEVICE_TABLE(of, omap2_onenand_id_table);
 649
 650 static struct platform_driver omap2_onenand_driver = {
 651         .probe          = omap2_onenand_probe,
 652         .remove         = omap2_onenand_remove,
 653         .shutdown       = omap2_onenand_shutdown,
 654         .driver         = {
 655                 .name   = DRIVER_NAME,
 656                 .of_match_table = omap2_onenand_id_table,
 657         },
 658 };
 659
 660 module_platform_driver(omap2_onenand_driver);
 661
 662 MODULE_ALIAS("platform:" DRIVER_NAME);
 663 MODULE_LICENSE("GPL");
 664 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 665 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");