drivers/mtd/nand/raw/davinci_nand.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * davinci_nand.c - NAND Flash Driver for DaVinci family chips
   4  *
   5  * Copyright © 2006 Texas Instruments.
   6  *
   7  * Port to 2.6.23 Copyright © 2008 by:
   8  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
   9  *   Troy Kisky <troy.kisky@boundarydevices.com>
  10  *   Dirk Behme <Dirk.Behme@gmail.com>
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/mtd/rawnand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/slab.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of.h>
  23
  24 #include <linux/platform_data/mtd-davinci.h>
  25 #include <linux/platform_data/mtd-davinci-aemif.h>
  26
  27 /*
  28  * This is a device driver for the NAND flash controller found on the
  29  * various DaVinci family chips.  It handles up to four SoC chipselects,
  30  * and some flavors of secondary chipselect (e.g. based on A12) as used
  31  * with multichip packages.
  32  *
  33  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
  34  * available on chips like the DM355 and OMAP-L137 and needed with the
  35  * more error-prone MLC NAND chips.
  36  *
  37  * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
  38  * outputs in a "wire-AND" configuration, with no per-chip signals.
  39  */
  40 struct davinci_nand_info {
  41         struct nand_chip        chip;
  42
  43         struct platform_device  *pdev;
  44
  45         bool                    is_readmode;
  46
  47         void __iomem            *base;
  48         void __iomem            *vaddr;
  49
  50         void __iomem            *current_cs;
  51
  52         uint32_t                mask_chipsel;
  53         uint32_t                mask_ale;
  54         uint32_t                mask_cle;
  55
  56         uint32_t                core_chipsel;
  57
  58         struct davinci_aemif_timing     *timing;
  59 };
  60
  61 static DEFINE_SPINLOCK(davinci_nand_lock);
  62 static bool ecc4_busy;
  63
  64 static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
  65 {
  66         return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
  67 }
  68
  69 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
  70                 int offset)
  71 {
  72         return __raw_readl(info->base + offset);
  73 }
  74
  75 static inline void davinci_nand_writel(struct davinci_nand_info *info,
  76                 int offset, unsigned long value)
  77 {
  78         __raw_writel(value, info->base + offset);
  79 }
  80
  81 /*----------------------------------------------------------------------*/
  82
  83 /*
  84  * Access to hardware control lines:  ALE, CLE, secondary chipselect.
  85  */
  86
  87 static void nand_davinci_hwcontrol(struct nand_chip *nand, int cmd,
  88                                    unsigned int ctrl)
  89 {
  90         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
  91         void __iomem                    *addr = info->current_cs;
  92
  93         /* Did the control lines change? */
  94         if (ctrl & NAND_CTRL_CHANGE) {
  95                 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
  96                         addr += info->mask_cle;
  97                 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
  98                         addr += info->mask_ale;
  99
 100                 nand->legacy.IO_ADDR_W = addr;
 101         }
 102
 103         if (cmd != NAND_CMD_NONE)
 104                 iowrite8(cmd, nand->legacy.IO_ADDR_W);
 105 }
 106
 107 static void nand_davinci_select_chip(struct nand_chip *nand, int chip)
 108 {
 109         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(nand));
 110
 111         info->current_cs = info->vaddr;
 112
 113         /* maybe kick in a second chipselect */
 114         if (chip > 0)
 115                 info->current_cs += info->mask_chipsel;
 116
 117         info->chip.legacy.IO_ADDR_W = info->current_cs;
 118         info->chip.legacy.IO_ADDR_R = info->chip.legacy.IO_ADDR_W;
 119 }
 120
 121 /*----------------------------------------------------------------------*/
 122
 123 /*
 124  * 1-bit hardware ECC ... context maintained for each core chipselect
 125  */
 126
 127 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
 128 {
 129         struct davinci_nand_info *info = to_davinci_nand(mtd);
 130
 131         return davinci_nand_readl(info, NANDF1ECC_OFFSET
 132                         + 4 * info->core_chipsel);
 133 }
 134
 135 static void nand_davinci_hwctl_1bit(struct nand_chip *chip, int mode)
 136 {
 137         struct davinci_nand_info *info;
 138         uint32_t nandcfr;
 139         unsigned long flags;
 140
 141         info = to_davinci_nand(nand_to_mtd(chip));
 142
 143         /* Reset ECC hardware */
 144         nand_davinci_readecc_1bit(nand_to_mtd(chip));
 145
 146         spin_lock_irqsave(&davinci_nand_lock, flags);
 147
 148         /* Restart ECC hardware */
 149         nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
 150         nandcfr |= BIT(8 + info->core_chipsel);
 151         davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
 152
 153         spin_unlock_irqrestore(&davinci_nand_lock, flags);
 154 }
 155
 156 /*
 157  * Read hardware ECC value and pack into three bytes
 158  */
 159 static int nand_davinci_calculate_1bit(struct nand_chip *chip,
 160                                        const u_char *dat, u_char *ecc_code)
 161 {
 162         unsigned int ecc_val = nand_davinci_readecc_1bit(nand_to_mtd(chip));
 163         unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
 164
 165         /* invert so that erased block ecc is correct */
 166         ecc24 = ~ecc24;
 167         ecc_code[0] = (u_char)(ecc24);
 168         ecc_code[1] = (u_char)(ecc24 >> 8);
 169         ecc_code[2] = (u_char)(ecc24 >> 16);
 170
 171         return 0;
 172 }
 173
 174 static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
 175                                      u_char *read_ecc, u_char *calc_ecc)
 176 {
 177         uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
 178                                           (read_ecc[2] << 16);
 179         uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
 180                                           (calc_ecc[2] << 16);
 181         uint32_t diff = eccCalc ^ eccNand;
 182
 183         if (diff) {
 184                 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
 185                         /* Correctable error */
 186                         if ((diff >> (12 + 3)) < chip->ecc.size) {
 187                                 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
 188                                 return 1;
 189                         } else {
 190                                 return -EBADMSG;
 191                         }
 192                 } else if (!(diff & (diff - 1))) {
 193                         /* Single bit ECC error in the ECC itself,
 194                          * nothing to fix */
 195                         return 1;
 196                 } else {
 197                         /* Uncorrectable error */
 198                         return -EBADMSG;
 199                 }
 200
 201         }
 202         return 0;
 203 }
 204
 205 /*----------------------------------------------------------------------*/
 206
 207 /*
 208  * 4-bit hardware ECC ... context maintained over entire AEMIF
 209  *
 210  * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
 211  * since that forces use of a problematic "infix OOB" layout.
 212  * Among other things, it trashes manufacturer bad block markers.
 213  * Also, and specific to this hardware, it ECC-protects the "prepad"
 214  * in the OOB ... while having ECC protection for parts of OOB would
 215  * seem useful, the current MTD stack sometimes wants to update the
 216  * OOB without recomputing ECC.
 217  */
 218
 219 static void nand_davinci_hwctl_4bit(struct nand_chip *chip, int mode)
 220 {
 221         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 222         unsigned long flags;
 223         u32 val;
 224
 225         /* Reset ECC hardware */
 226         davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
 227
 228         spin_lock_irqsave(&davinci_nand_lock, flags);
 229
 230         /* Start 4-bit ECC calculation for read/write */
 231         val = davinci_nand_readl(info, NANDFCR_OFFSET);
 232         val &= ~(0x03 << 4);
 233         val |= (info->core_chipsel << 4) | BIT(12);
 234         davinci_nand_writel(info, NANDFCR_OFFSET, val);
 235
 236         info->is_readmode = (mode == NAND_ECC_READ);
 237
 238         spin_unlock_irqrestore(&davinci_nand_lock, flags);
 239 }
 240
 241 /* Read raw ECC code after writing to NAND. */
 242 static void
 243 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
 244 {
 245         const u32 mask = 0x03ff03ff;
 246
 247         code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
 248         code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
 249         code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
 250         code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
 251 }
 252
 253 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
 254 static int nand_davinci_calculate_4bit(struct nand_chip *chip,
 255                                        const u_char *dat, u_char *ecc_code)
 256 {
 257         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 258         u32 raw_ecc[4], *p;
 259         unsigned i;
 260
 261         /* After a read, terminate ECC calculation by a dummy read
 262          * of some 4-bit ECC register.  ECC covers everything that
 263          * was read; correct() just uses the hardware state, so
 264          * ecc_code is not needed.
 265          */
 266         if (info->is_readmode) {
 267                 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
 268                 return 0;
 269         }
 270
 271         /* Pack eight raw 10-bit ecc values into ten bytes, making
 272          * two passes which each convert four values (in upper and
 273          * lower halves of two 32-bit words) into five bytes.  The
 274          * ROM boot loader uses this same packing scheme.
 275          */
 276         nand_davinci_readecc_4bit(info, raw_ecc);
 277         for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
 278                 *ecc_code++ =   p[0]        & 0xff;
 279                 *ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 280                 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 281                 *ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 282                 *ecc_code++ =  (p[1] >> 18) & 0xff;
 283         }
 284
 285         return 0;
 286 }
 287
 288 /* Correct up to 4 bits in data we just read, using state left in the
 289  * hardware plus the ecc_code computed when it was first written.
 290  */
 291 static int nand_davinci_correct_4bit(struct nand_chip *chip, u_char *data,
 292                                      u_char *ecc_code, u_char *null)
 293 {
 294         int i;
 295         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 296         unsigned short ecc10[8];
 297         unsigned short *ecc16;
 298         u32 syndrome[4];
 299         u32 ecc_state;
 300         unsigned num_errors, corrected;
 301         unsigned long timeo;
 302
 303         /* Unpack ten bytes into eight 10 bit values.  We know we're
 304          * little-endian, and use type punning for less shifting/masking.
 305          */
 306         if (WARN_ON(0x01 & (uintptr_t)ecc_code))
 307                 return -EINVAL;
 308         ecc16 = (unsigned short *)ecc_code;
 309
 310         ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
 311         ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
 312         ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
 313         ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
 314         ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
 315         ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
 316         ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
 317         ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;
 318
 319         /* Tell ECC controller about the expected ECC codes. */
 320         for (i = 7; i >= 0; i--)
 321                 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
 322
 323         /* Allow time for syndrome calculation ... then read it.
 324          * A syndrome of all zeroes 0 means no detected errors.
 325          */
 326         davinci_nand_readl(info, NANDFSR_OFFSET);
 327         nand_davinci_readecc_4bit(info, syndrome);
 328         if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
 329                 return 0;
 330
 331         /*
 332          * Clear any previous address calculation by doing a dummy read of an
 333          * error address register.
 334          */
 335         davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
 336
 337         /* Start address calculation, and wait for it to complete.
 338          * We _could_ start reading more data while this is working,
 339          * to speed up the overall page read.
 340          */
 341         davinci_nand_writel(info, NANDFCR_OFFSET,
 342                         davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
 343
 344         /*
 345          * ECC_STATE field reads 0x3 (Error correction complete) immediately
 346          * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
 347          * begin trying to poll for the state, you may fall right out of your
 348          * loop without any of the correction calculations having taken place.
 349          * The recommendation from the hardware team is to initially delay as
 350          * long as ECC_STATE reads less than 4. After that, ECC HW has entered
 351          * correction state.
 352          */
 353         timeo = jiffies + usecs_to_jiffies(100);
 354         do {
 355                 ecc_state = (davinci_nand_readl(info,
 356                                 NANDFSR_OFFSET) >> 8) & 0x0f;
 357                 cpu_relax();
 358         } while ((ecc_state < 4) && time_before(jiffies, timeo));
 359
 360         for (;;) {
 361                 u32     fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
 362
 363                 switch ((fsr >> 8) & 0x0f) {
 364                 case 0:         /* no error, should not happen */
 365                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
 366                         return 0;
 367                 case 1:         /* five or more errors detected */
 368                         davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
 369                         return -EBADMSG;
 370                 case 2:         /* error addresses computed */
 371                 case 3:
 372                         num_errors = 1 + ((fsr >> 16) & 0x03);
 373                         goto correct;
 374                 default:        /* still working on it */
 375                         cpu_relax();
 376                         continue;
 377                 }
 378         }
 379
 380 correct:
 381         /* correct each error */
 382         for (i = 0, corrected = 0; i < num_errors; i++) {
 383                 int error_address, error_value;
 384
 385                 if (i > 1) {
 386                         error_address = davinci_nand_readl(info,
 387                                                 NAND_ERR_ADD2_OFFSET);
 388                         error_value = davinci_nand_readl(info,
 389                                                 NAND_ERR_ERRVAL2_OFFSET);
 390                 } else {
 391                         error_address = davinci_nand_readl(info,
 392                                                 NAND_ERR_ADD1_OFFSET);
 393                         error_value = davinci_nand_readl(info,
 394                                                 NAND_ERR_ERRVAL1_OFFSET);
 395                 }
 396
 397                 if (i & 1) {
 398                         error_address >>= 16;
 399                         error_value >>= 16;
 400                 }
 401                 error_address &= 0x3ff;
 402                 error_address = (512 + 7) - error_address;
 403
 404                 if (error_address < 512) {
 405                         data[error_address] ^= error_value;
 406                         corrected++;
 407                 }
 408         }
 409
 410         return corrected;
 411 }
 412
 413 /*----------------------------------------------------------------------*/
 414
 415 /*
 416  * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
 417  * how these chips are normally wired.  This translates to both 8 and 16
 418  * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
 419  *
 420  * For now we assume that configuration, or any other one which ignores
 421  * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
 422  * and have that transparently morphed into multiple NAND operations.
 423  */
 424 static void nand_davinci_read_buf(struct nand_chip *chip, uint8_t *buf,
 425                                   int len)
 426 {
 427         if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
 428                 ioread32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
 429         else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
 430                 ioread16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
 431         else
 432                 ioread8_rep(chip->legacy.IO_ADDR_R, buf, len);
 433 }
 434
 435 static void nand_davinci_write_buf(struct nand_chip *chip, const uint8_t *buf,
 436                                    int len)
 437 {
 438         if ((0x03 & ((uintptr_t)buf)) == 0 && (0x03 & len) == 0)
 439                 iowrite32_rep(chip->legacy.IO_ADDR_R, buf, len >> 2);
 440         else if ((0x01 & ((uintptr_t)buf)) == 0 && (0x01 & len) == 0)
 441                 iowrite16_rep(chip->legacy.IO_ADDR_R, buf, len >> 1);
 442         else
 443                 iowrite8_rep(chip->legacy.IO_ADDR_R, buf, len);
 444 }
 445
 446 /*
 447  * Check hardware register for wait status. Returns 1 if device is ready,
 448  * 0 if it is still busy.
 449  */
 450 static int nand_davinci_dev_ready(struct nand_chip *chip)
 451 {
 452         struct davinci_nand_info *info = to_davinci_nand(nand_to_mtd(chip));
 453
 454         return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
 455 }
 456
 457 /*----------------------------------------------------------------------*/
 458
 459 /* An ECC layout for using 4-bit ECC with small-page flash, storing
 460  * ten ECC bytes plus the manufacturer's bad block marker byte, and
 461  * and not overlapping the default BBT markers.
 462  */
 463 static int hwecc4_ooblayout_small_ecc(struct mtd_info *mtd, int section,
 464                                       struct mtd_oob_region *oobregion)
 465 {
 466         if (section > 2)
 467                 return -ERANGE;
 468
 469         if (!section) {
 470                 oobregion->offset = 0;
 471                 oobregion->length = 5;
 472         } else if (section == 1) {
 473                 oobregion->offset = 6;
 474                 oobregion->length = 2;
 475         } else {
 476                 oobregion->offset = 13;
 477                 oobregion->length = 3;
 478         }
 479
 480         return 0;
 481 }
 482
 483 static int hwecc4_ooblayout_small_free(struct mtd_info *mtd, int section,
 484                                        struct mtd_oob_region *oobregion)
 485 {
 486         if (section > 1)
 487                 return -ERANGE;
 488
 489         if (!section) {
 490                 oobregion->offset = 8;
 491                 oobregion->length = 5;
 492         } else {
 493                 oobregion->offset = 16;
 494                 oobregion->length = mtd->oobsize - 16;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops = {
 501         .ecc = hwecc4_ooblayout_small_ecc,
 502         .free = hwecc4_ooblayout_small_free,
 503 };
 504
 505 #if defined(CONFIG_OF)
 506 static const struct of_device_id davinci_nand_of_match[] = {
 507         {.compatible = "ti,davinci-nand", },
 508         {.compatible = "ti,keystone-nand", },
 509         {},
 510 };
 511 MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
 512
 513 static struct davinci_nand_pdata
 514         *nand_davinci_get_pdata(struct platform_device *pdev)
 515 {
 516         if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
 517                 struct davinci_nand_pdata *pdata;
 518                 const char *mode;
 519                 u32 prop;
 520
 521                 pdata =  devm_kzalloc(&pdev->dev,
 522                                 sizeof(struct davinci_nand_pdata),
 523                                 GFP_KERNEL);
 524                 pdev->dev.platform_data = pdata;
 525                 if (!pdata)
 526                         return ERR_PTR(-ENOMEM);
 527                 if (!of_property_read_u32(pdev->dev.of_node,
 528                         "ti,davinci-chipselect", &prop))
 529                         pdata->core_chipsel = prop;
 530                 else
 531                         return ERR_PTR(-EINVAL);
 532
 533                 if (!of_property_read_u32(pdev->dev.of_node,
 534                         "ti,davinci-mask-ale", &prop))
 535                         pdata->mask_ale = prop;
 536                 if (!of_property_read_u32(pdev->dev.of_node,
 537                         "ti,davinci-mask-cle", &prop))
 538                         pdata->mask_cle = prop;
 539                 if (!of_property_read_u32(pdev->dev.of_node,
 540                         "ti,davinci-mask-chipsel", &prop))
 541                         pdata->mask_chipsel = prop;
 542                 if (!of_property_read_string(pdev->dev.of_node,
 543                         "ti,davinci-ecc-mode", &mode)) {
 544                         if (!strncmp("none", mode, 4))
 545                                 pdata->ecc_mode = NAND_ECC_NONE;
 546                         if (!strncmp("soft", mode, 4))
 547                                 pdata->ecc_mode = NAND_ECC_SOFT;
 548                         if (!strncmp("hw", mode, 2))
 549                                 pdata->ecc_mode = NAND_ECC_HW;
 550                 }
 551                 if (!of_property_read_u32(pdev->dev.of_node,
 552                         "ti,davinci-ecc-bits", &prop))
 553                         pdata->ecc_bits = prop;
 554
 555                 if (!of_property_read_u32(pdev->dev.of_node,
 556                         "ti,davinci-nand-buswidth", &prop) && prop == 16)
 557                         pdata->options |= NAND_BUSWIDTH_16;
 558
 559                 if (of_property_read_bool(pdev->dev.of_node,
 560                         "ti,davinci-nand-use-bbt"))
 561                         pdata->bbt_options = NAND_BBT_USE_FLASH;
 562
 563                 /*
 564                  * Since kernel v4.8, this driver has been fixed to enable
 565                  * use of 4-bit hardware ECC with subpages and verified on
 566                  * TI's keystone EVMs (K2L, K2HK and K2E).
 567                  * However, in the interest of not breaking systems using
 568                  * existing UBI partitions, sub-page writes are not being
 569                  * (re)enabled. If you want to use subpage writes on Keystone
 570                  * platforms (i.e. do not have any existing UBI partitions),
 571                  * then use "ti,davinci-nand" as the compatible in your
 572                  * device-tree file.
 573                  */
 574                 if (of_device_is_compatible(pdev->dev.of_node,
 575                                             "ti,keystone-nand")) {
 576                         pdata->options |= NAND_NO_SUBPAGE_WRITE;
 577                 }
 578         }
 579
 580         return dev_get_platdata(&pdev->dev);
 581 }
 582 #else
 583 static struct davinci_nand_pdata
 584         *nand_davinci_get_pdata(struct platform_device *pdev)
 585 {
 586         return dev_get_platdata(&pdev->dev);
 587 }
 588 #endif
 589
 590 static int davinci_nand_attach_chip(struct nand_chip *chip)
 591 {
 592         struct mtd_info *mtd = nand_to_mtd(chip);
 593         struct davinci_nand_info *info = to_davinci_nand(mtd);
 594         struct davinci_nand_pdata *pdata = nand_davinci_get_pdata(info->pdev);
 595         int ret = 0;
 596
 597         if (IS_ERR(pdata))
 598                 return PTR_ERR(pdata);
 599
 600         switch (info->chip.ecc.mode) {
 601         case NAND_ECC_NONE:
 602                 pdata->ecc_bits = 0;
 603                 break;
 604         case NAND_ECC_SOFT:
 605                 pdata->ecc_bits = 0;
 606                 /*
 607                  * This driver expects Hamming based ECC when ecc_mode is set
 608                  * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
 609                  * avoid adding an extra ->ecc_algo field to
 610                  * davinci_nand_pdata.
 611                  */
 612                 info->chip.ecc.algo = NAND_ECC_HAMMING;
 613                 break;
 614         case NAND_ECC_HW:
 615                 if (pdata->ecc_bits == 4) {
 616                         /*
 617                          * No sanity checks:  CPUs must support this,
 618                          * and the chips may not use NAND_BUSWIDTH_16.
 619                          */
 620
 621                         /* No sharing 4-bit hardware between chipselects yet */
 622                         spin_lock_irq(&davinci_nand_lock);
 623                         if (ecc4_busy)
 624                                 ret = -EBUSY;
 625                         else
 626                                 ecc4_busy = true;
 627                         spin_unlock_irq(&davinci_nand_lock);
 628
 629                         if (ret == -EBUSY)
 630                                 return ret;
 631
 632                         info->chip.ecc.calculate = nand_davinci_calculate_4bit;
 633                         info->chip.ecc.correct = nand_davinci_correct_4bit;
 634                         info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
 635                         info->chip.ecc.bytes = 10;
 636                         info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
 637                         info->chip.ecc.algo = NAND_ECC_BCH;
 638                 } else {
 639                         /* 1bit ecc hamming */
 640                         info->chip.ecc.calculate = nand_davinci_calculate_1bit;
 641                         info->chip.ecc.correct = nand_davinci_correct_1bit;
 642                         info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
 643                         info->chip.ecc.bytes = 3;
 644                         info->chip.ecc.algo = NAND_ECC_HAMMING;
 645                 }
 646                 info->chip.ecc.size = 512;
 647                 info->chip.ecc.strength = pdata->ecc_bits;
 648                 break;
 649         default:
 650                 return -EINVAL;
 651         }
 652
 653         /*
 654          * Update ECC layout if needed ... for 1-bit HW ECC, the default
 655          * is OK, but it allocates 6 bytes when only 3 are needed (for
 656          * each 512 bytes).  For the 4-bit HW ECC, that default is not
 657          * usable:  10 bytes are needed, not 6.
 658          */
 659         if (pdata->ecc_bits == 4) {
 660                 int chunks = mtd->writesize / 512;
 661
 662                 if (!chunks || mtd->oobsize < 16) {
 663                         dev_dbg(&info->pdev->dev, "too small\n");
 664                         return -EINVAL;
 665                 }
 666
 667                 /* For small page chips, preserve the manufacturer's
 668                  * badblock marking data ... and make sure a flash BBT
 669                  * table marker fits in the free bytes.
 670                  */
 671                 if (chunks == 1) {
 672                         mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
 673                 } else if (chunks == 4 || chunks == 8) {
 674                         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
 675                         info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
 676                 } else {
 677                         return -EIO;
 678                 }
 679         }
 680
 681         return ret;
 682 }
 683
 684 static const struct nand_controller_ops davinci_nand_controller_ops = {
 685         .attach_chip = davinci_nand_attach_chip,
 686 };
 687
 688 static int nand_davinci_probe(struct platform_device *pdev)
 689 {
 690         struct davinci_nand_pdata       *pdata;
 691         struct davinci_nand_info        *info;
 692         struct resource                 *res1;
 693         struct resource                 *res2;
 694         void __iomem                    *vaddr;
 695         void __iomem                    *base;
 696         int                             ret;
 697         uint32_t                        val;
 698         struct mtd_info                 *mtd;
 699
 700         pdata = nand_davinci_get_pdata(pdev);
 701         if (IS_ERR(pdata))
 702                 return PTR_ERR(pdata);
 703
 704         /* insist on board-specific configuration */
 705         if (!pdata)
 706                 return -ENODEV;
 707
 708         /* which external chipselect will we be managing? */
 709         if (pdata->core_chipsel < 0 || pdata->core_chipsel > 3)
 710                 return -ENODEV;
 711
 712         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 713         if (!info)
 714                 return -ENOMEM;
 715
 716         platform_set_drvdata(pdev, info);
 717
 718         res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 719         res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 720         if (!res1 || !res2) {
 721                 dev_err(&pdev->dev, "resource missing\n");
 722                 return -EINVAL;
 723         }
 724
 725         vaddr = devm_ioremap_resource(&pdev->dev, res1);
 726         if (IS_ERR(vaddr))
 727                 return PTR_ERR(vaddr);
 728
 729         /*
 730          * This registers range is used to setup NAND settings. In case with
 731          * TI AEMIF driver, the same memory address range is requested already
 732          * by AEMIF, so we cannot request it twice, just ioremap.
 733          * The AEMIF and NAND drivers not use the same registers in this range.
 734          */
 735         base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
 736         if (!base) {
 737                 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
 738                 return -EADDRNOTAVAIL;
 739         }
 740
 741         info->pdev              = pdev;
 742         info->base              = base;
 743         info->vaddr             = vaddr;
 744
 745         mtd                     = nand_to_mtd(&info->chip);
 746         mtd->dev.parent         = &pdev->dev;
 747         nand_set_flash_node(&info->chip, pdev->dev.of_node);
 748
 749         info->chip.legacy.IO_ADDR_R     = vaddr;
 750         info->chip.legacy.IO_ADDR_W     = vaddr;
 751         info->chip.legacy.chip_delay    = 0;
 752         info->chip.legacy.select_chip   = nand_davinci_select_chip;
 753
 754         /* options such as NAND_BBT_USE_FLASH */
 755         info->chip.bbt_options  = pdata->bbt_options;
 756         /* options such as 16-bit widths */
 757         info->chip.options      = pdata->options;
 758         info->chip.bbt_td       = pdata->bbt_td;
 759         info->chip.bbt_md       = pdata->bbt_md;
 760         info->timing            = pdata->timing;
 761
 762         info->current_cs        = info->vaddr;
 763         info->core_chipsel      = pdata->core_chipsel;
 764         info->mask_chipsel      = pdata->mask_chipsel;
 765
 766         /* use nandboot-capable ALE/CLE masks by default */
 767         info->mask_ale          = pdata->mask_ale ? : MASK_ALE;
 768         info->mask_cle          = pdata->mask_cle ? : MASK_CLE;
 769
 770         /* Set address of hardware control function */
 771         info->chip.legacy.cmd_ctrl      = nand_davinci_hwcontrol;
 772         info->chip.legacy.dev_ready     = nand_davinci_dev_ready;
 773
 774         /* Speed up buffer I/O */
 775         info->chip.legacy.read_buf     = nand_davinci_read_buf;
 776         info->chip.legacy.write_buf    = nand_davinci_write_buf;
 777
 778         /* Use board-specific ECC config */
 779         info->chip.ecc.mode     = pdata->ecc_mode;
 780
 781         spin_lock_irq(&davinci_nand_lock);
 782
 783         /* put CSxNAND into NAND mode */
 784         val = davinci_nand_readl(info, NANDFCR_OFFSET);
 785         val |= BIT(info->core_chipsel);
 786         davinci_nand_writel(info, NANDFCR_OFFSET, val);
 787
 788         spin_unlock_irq(&davinci_nand_lock);
 789
 790         /* Scan to find existence of the device(s) */
 791         info->chip.legacy.dummy_controller.ops = &davinci_nand_controller_ops;
 792         ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
 793         if (ret < 0) {
 794                 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
 795                 return ret;
 796         }
 797
 798         if (pdata->parts)
 799                 ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
 800         else
 801                 ret = mtd_device_register(mtd, NULL, 0);
 802         if (ret < 0)
 803                 goto err_cleanup_nand;
 804
 805         val = davinci_nand_readl(info, NRCSR_OFFSET);
 806         dev_info(&pdev->dev, "controller rev. %d.%d\n",
 807                (val >> 8) & 0xff, val & 0xff);
 808
 809         return 0;
 810
 811 err_cleanup_nand:
 812         nand_cleanup(&info->chip);
 813
 814         return ret;
 815 }
 816
 817 static int nand_davinci_remove(struct platform_device *pdev)
 818 {
 819         struct davinci_nand_info *info = platform_get_drvdata(pdev);
 820
 821         spin_lock_irq(&davinci_nand_lock);
 822         if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
 823                 ecc4_busy = false;
 824         spin_unlock_irq(&davinci_nand_lock);
 825
 826         nand_release(&info->chip);
 827
 828         return 0;
 829 }
 830
 831 static struct platform_driver nand_davinci_driver = {
 832         .probe          = nand_davinci_probe,
 833         .remove         = nand_davinci_remove,
 834         .driver         = {
 835                 .name   = "davinci_nand",
 836                 .of_match_table = of_match_ptr(davinci_nand_of_match),
 837         },
 838 };
 839 MODULE_ALIAS("platform:davinci_nand");
 840
 841 module_platform_driver(nand_davinci_driver);
 842
 843 MODULE_LICENSE("GPL");
 844 MODULE_AUTHOR("Texas Instruments");
 845 MODULE_DESCRIPTION("Davinci NAND flash driver");
 846