2 * NAND flash simulator.
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
6 * Copyright (C) 2004 Nokia Corporation
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/vmalloc.h>
31 #include <linux/math64.h>
32 #include <linux/slab.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mtd/mtd.h>
36 #include <linux/mtd/nand.h>
37 #include <linux/mtd/nand_bch.h>
38 #include <linux/mtd/partitions.h>
39 #include <linux/delay.h>
40 #include <linux/list.h>
41 #include <linux/random.h>
42 #include <linux/sched.h>
44 #include <linux/pagemap.h>
45 #include <linux/seq_file.h>
46 #include <linux/debugfs.h>
48 /* Default simulator parameters values */
49 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
50 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
51 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
52 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
53 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
54 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
55 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
56 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
59 #ifndef CONFIG_NANDSIM_ACCESS_DELAY
60 #define CONFIG_NANDSIM_ACCESS_DELAY 25
62 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
63 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200
65 #ifndef CONFIG_NANDSIM_ERASE_DELAY
66 #define CONFIG_NANDSIM_ERASE_DELAY 2
68 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
69 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40
71 #ifndef CONFIG_NANDSIM_INPUT_CYCLE
72 #define CONFIG_NANDSIM_INPUT_CYCLE 50
74 #ifndef CONFIG_NANDSIM_BUS_WIDTH
75 #define CONFIG_NANDSIM_BUS_WIDTH 8
77 #ifndef CONFIG_NANDSIM_DO_DELAYS
78 #define CONFIG_NANDSIM_DO_DELAYS 0
80 #ifndef CONFIG_NANDSIM_LOG
81 #define CONFIG_NANDSIM_LOG 0
83 #ifndef CONFIG_NANDSIM_DBG
84 #define CONFIG_NANDSIM_DBG 0
86 #ifndef CONFIG_NANDSIM_MAX_PARTS
87 #define CONFIG_NANDSIM_MAX_PARTS 32
90 static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
91 static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
92 static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
93 static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
94 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
95 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
96 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
97 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
98 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
99 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
100 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
101 static uint log = CONFIG_NANDSIM_LOG;
102 static uint dbg = CONFIG_NANDSIM_DBG;
103 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
104 static unsigned int parts_num;
105 static char *badblocks = NULL;
106 static char *weakblocks = NULL;
107 static char *weakpages = NULL;
108 static unsigned int bitflips = 0;
109 static char *gravepages = NULL;
110 static unsigned int overridesize = 0;
111 static char *cache_file = NULL;
112 static unsigned int bbt;
113 static unsigned int bch;
115 module_param(first_id_byte, uint, 0400);
116 module_param(second_id_byte, uint, 0400);
117 module_param(third_id_byte, uint, 0400);
118 module_param(fourth_id_byte, uint, 0400);
119 module_param(access_delay, uint, 0400);
120 module_param(programm_delay, uint, 0400);
121 module_param(erase_delay, uint, 0400);
122 module_param(output_cycle, uint, 0400);
123 module_param(input_cycle, uint, 0400);
124 module_param(bus_width, uint, 0400);
125 module_param(do_delays, uint, 0400);
126 module_param(log, uint, 0400);
127 module_param(dbg, uint, 0400);
128 module_param_array(parts, ulong, &parts_num, 0400);
129 module_param(badblocks, charp, 0400);
130 module_param(weakblocks, charp, 0400);
131 module_param(weakpages, charp, 0400);
132 module_param(bitflips, uint, 0400);
133 module_param(gravepages, charp, 0400);
134 module_param(overridesize, uint, 0400);
135 module_param(cache_file, charp, 0400);
136 module_param(bbt, uint, 0400);
137 module_param(bch, uint, 0400);
139 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
140 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
141 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
142 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
143 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
144 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
145 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
146 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
147 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
148 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
149 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
150 MODULE_PARM_DESC(log, "Perform logging if not zero");
151 MODULE_PARM_DESC(dbg, "Output debug information if not zero");
152 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
153 /* Page and erase block positions for the following parameters are independent of any partitions */
154 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
155 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
156 " separated by commas e.g. 113:2 means eb 113"
157 " can be erased only twice before failing");
158 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
159 " separated by commas e.g. 1401:2 means page 1401"
160 " can be written only twice before failing");
161 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
162 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
163 " separated by commas e.g. 1401:2 means page 1401"
164 " can be read only twice before failing");
165 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
166 "The size is specified in erase blocks and as the exponent of a power of two"
167 " e.g. 5 means a size of 32 erase blocks");
168 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
169 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
170 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
171 "be correctable in 512-byte blocks");
173 /* The largest possible page size */
174 #define NS_LARGEST_PAGE_SIZE 4096
176 /* The prefix for simulator output */
177 #define NS_OUTPUT_PREFIX "[nandsim]"
179 /* Simulator's output macros (logging, debugging, warning, error) */
180 #define NS_LOG(args...) \
181 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
182 #define NS_DBG(args...) \
183 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
184 #define NS_WARN(args...) \
185 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
186 #define NS_ERR(args...) \
187 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
188 #define NS_INFO(args...) \
189 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
191 /* Busy-wait delay macros (microseconds, milliseconds) */
192 #define NS_UDELAY(us) \
193 do { if (do_delays) udelay(us); } while(0)
194 #define NS_MDELAY(us) \
195 do { if (do_delays) mdelay(us); } while(0)
197 /* Is the nandsim structure initialized ? */
198 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
200 /* Good operation completion status */
201 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
203 /* Operation failed completion status */
204 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
206 /* Calculate the page offset in flash RAM image by (row, column) address */
207 #define NS_RAW_OFFSET(ns) \
208 (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column)
210 /* Calculate the OOB offset in flash RAM image by (row, column) address */
211 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
213 /* After a command is input, the simulator goes to one of the following states */
214 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
215 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
216 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
217 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
218 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */
219 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
220 #define STATE_CMD_STATUS 0x00000007 /* read status */
221 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
222 #define STATE_CMD_READID 0x0000000A /* read ID */
223 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
224 #define STATE_CMD_RESET 0x0000000C /* reset */
225 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */
226 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
227 #define STATE_CMD_MASK 0x0000000F /* command states mask */
229 /* After an address is input, the simulator goes to one of these states */
230 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
231 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
232 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
233 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
234 #define STATE_ADDR_MASK 0x00000070 /* address states mask */
236 /* During data input/output the simulator is in these states */
237 #define STATE_DATAIN 0x00000100 /* waiting for data input */
238 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
240 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */
241 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
242 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
243 #define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
244 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
246 /* Previous operation is done, ready to accept new requests */
247 #define STATE_READY 0x00000000
249 /* This state is used to mark that the next state isn't known yet */
250 #define STATE_UNKNOWN 0x10000000
252 /* Simulator's actions bit masks */
253 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
254 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
255 #define ACTION_SECERASE 0x00300000 /* erase sector */
256 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
257 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */
258 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
259 #define ACTION_MASK 0x00700000 /* action mask */
261 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
262 #define NS_OPER_STATES 6 /* Maximum number of states in operation */
264 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
265 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */
266 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
267 #define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
268 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
269 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
270 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
271 #define OPT_SMALLPAGE (OPT_PAGE512) /* 512-byte page chips */
273 /* Remove action bits from state */
274 #define NS_STATE(x) ((x) & ~ACTION_MASK)
277 * Maximum previous states which need to be saved. Currently saving is
278 * only needed for page program operation with preceded read command
279 * (which is only valid for 512-byte pages).
281 #define NS_MAX_PREVSTATES 1
283 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */
284 #define NS_MAX_HELD_PAGES 16
286 struct nandsim_debug_info {
287 struct dentry *dfs_root;
288 struct dentry *dfs_wear_report;
292 * A union to represent flash memory contents and flash buffer.
295 u_char *byte; /* for byte access */
296 uint16_t *word; /* for 16-bit word access */
300 * The structure which describes all the internal simulator data.
303 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
304 unsigned int nbparts;
306 uint busw; /* flash chip bus width (8 or 16) */
307 u_char ids[4]; /* chip's ID bytes */
308 uint32_t options; /* chip's characteristic bits */
309 uint32_t state; /* current chip state */
310 uint32_t nxstate; /* next expected state */
312 uint32_t *op; /* current operation, NULL operations isn't known yet */
313 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
314 uint16_t npstates; /* number of previous states saved */
315 uint16_t stateidx; /* current state index */
317 /* The simulated NAND flash pages array */
320 /* Slab allocator for nand pages */
321 struct kmem_cache *nand_pages_slab;
323 /* Internal buffer of page + OOB size bytes */
326 /* NAND flash "geometry" */
328 uint64_t totsz; /* total flash size, bytes */
329 uint32_t secsz; /* flash sector (erase block) size, bytes */
330 uint pgsz; /* NAND flash page size, bytes */
331 uint oobsz; /* page OOB area size, bytes */
332 uint64_t totszoob; /* total flash size including OOB, bytes */
333 uint pgszoob; /* page size including OOB , bytes*/
334 uint secszoob; /* sector size including OOB, bytes */
335 uint pgnum; /* total number of pages */
336 uint pgsec; /* number of pages per sector */
337 uint secshift; /* bits number in sector size */
338 uint pgshift; /* bits number in page size */
339 uint oobshift; /* bits number in OOB size */
340 uint pgaddrbytes; /* bytes per page address */
341 uint secaddrbytes; /* bytes per sector address */
342 uint idbytes; /* the number ID bytes that this chip outputs */
345 /* NAND flash internal registers */
347 unsigned command; /* the command register */
348 u_char status; /* the status register */
349 uint row; /* the page number */
350 uint column; /* the offset within page */
351 uint count; /* internal counter */
352 uint num; /* number of bytes which must be processed */
353 uint off; /* fixed page offset */
356 /* NAND flash lines state */
358 int ce; /* chip Enable */
359 int cle; /* command Latch Enable */
360 int ale; /* address Latch Enable */
361 int wp; /* write Protect */
364 /* Fields needed when using a cache file */
365 struct file *cfile; /* Open file */
366 unsigned long *pages_written; /* Which pages have been written */
368 struct page *held_pages[NS_MAX_HELD_PAGES];
371 struct nandsim_debug_info dbg;
375 * Operations array. To perform any operation the simulator must pass
376 * through the correspondent states chain.
378 static struct nandsim_operations {
379 uint32_t reqopts; /* options which are required to perform the operation */
380 uint32_t states[NS_OPER_STATES]; /* operation's states */
381 } ops[NS_OPER_NUM] = {
382 /* Read page + OOB from the beginning */
383 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
384 STATE_DATAOUT, STATE_READY}},
385 /* Read page + OOB from the second half */
386 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
387 STATE_DATAOUT, STATE_READY}},
389 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
390 STATE_DATAOUT, STATE_READY}},
391 /* Program page starting from the beginning */
392 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
393 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
394 /* Program page starting from the beginning */
395 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
396 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
397 /* Program page starting from the second half */
398 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
399 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
401 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
402 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
404 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
406 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
408 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
409 /* Large page devices read page */
410 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
411 STATE_DATAOUT, STATE_READY}},
412 /* Large page devices random page read */
413 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
414 STATE_DATAOUT, STATE_READY}},
418 struct list_head list;
419 unsigned int erase_block_no;
420 unsigned int max_erases;
421 unsigned int erases_done;
424 static LIST_HEAD(weak_blocks);
427 struct list_head list;
428 unsigned int page_no;
429 unsigned int max_writes;
430 unsigned int writes_done;
433 static LIST_HEAD(weak_pages);
436 struct list_head list;
437 unsigned int page_no;
438 unsigned int max_reads;
439 unsigned int reads_done;
442 static LIST_HEAD(grave_pages);
444 static unsigned long *erase_block_wear = NULL;
445 static unsigned int wear_eb_count = 0;
446 static unsigned long total_wear = 0;
448 /* MTD structure for NAND controller */
449 static struct mtd_info *nsmtd;
451 static int nandsim_debugfs_show(struct seq_file *m, void *private)
453 unsigned long wmin = -1, wmax = 0, avg;
454 unsigned long deciles[10], decile_max[10], tot = 0;
457 /* Calc wear stats */
458 for (i = 0; i < wear_eb_count; ++i) {
459 unsigned long wear = erase_block_wear[i];
467 for (i = 0; i < 9; ++i) {
469 decile_max[i] = (wmax * (i + 1) + 5) / 10;
472 decile_max[9] = wmax;
473 for (i = 0; i < wear_eb_count; ++i) {
475 unsigned long wear = erase_block_wear[i];
476 for (d = 0; d < 10; ++d)
477 if (wear <= decile_max[d]) {
482 avg = tot / wear_eb_count;
484 /* Output wear report */
485 seq_printf(m, "Total numbers of erases: %lu\n", tot);
486 seq_printf(m, "Number of erase blocks: %u\n", wear_eb_count);
487 seq_printf(m, "Average number of erases: %lu\n", avg);
488 seq_printf(m, "Maximum number of erases: %lu\n", wmax);
489 seq_printf(m, "Minimum number of erases: %lu\n", wmin);
490 for (i = 0; i < 10; ++i) {
491 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
492 if (from > decile_max[i])
494 seq_printf(m, "Number of ebs with erase counts from %lu to %lu : %lu\n",
503 static int nandsim_debugfs_open(struct inode *inode, struct file *file)
505 return single_open(file, nandsim_debugfs_show, inode->i_private);
508 static const struct file_operations dfs_fops = {
509 .open = nandsim_debugfs_open,
512 .release = single_release,
516 * nandsim_debugfs_create - initialize debugfs
517 * @dev: nandsim device description object
519 * This function creates all debugfs files for UBI device @ubi. Returns zero in
520 * case of success and a negative error code in case of failure.
522 static int nandsim_debugfs_create(struct nandsim *dev)
524 struct nandsim_debug_info *dbg = &dev->dbg;
528 if (!IS_ENABLED(CONFIG_DEBUG_FS))
531 dent = debugfs_create_dir("nandsim", NULL);
532 if (IS_ERR_OR_NULL(dent)) {
533 int err = dent ? -ENODEV : PTR_ERR(dent);
535 NS_ERR("cannot create \"nandsim\" debugfs directory, err %d\n",
539 dbg->dfs_root = dent;
541 dent = debugfs_create_file("wear_report", S_IRUSR,
542 dbg->dfs_root, dev, &dfs_fops);
543 if (IS_ERR_OR_NULL(dent))
545 dbg->dfs_wear_report = dent;
550 debugfs_remove_recursive(dbg->dfs_root);
551 err = dent ? PTR_ERR(dent) : -ENODEV;
556 * nandsim_debugfs_remove - destroy all debugfs files
558 static void nandsim_debugfs_remove(struct nandsim *ns)
560 if (IS_ENABLED(CONFIG_DEBUG_FS))
561 debugfs_remove_recursive(ns->dbg.dfs_root);
565 * Allocate array of page pointers, create slab allocation for an array
566 * and initialize the array by NULL pointers.
568 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
570 static int alloc_device(struct nandsim *ns)
576 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
578 return PTR_ERR(cfile);
579 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
580 NS_ERR("alloc_device: cache file not readable\n");
584 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
585 NS_ERR("alloc_device: cache file not writeable\n");
589 ns->pages_written = vzalloc(BITS_TO_LONGS(ns->geom.pgnum) *
590 sizeof(unsigned long));
591 if (!ns->pages_written) {
592 NS_ERR("alloc_device: unable to allocate pages written array\n");
596 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
598 NS_ERR("alloc_device: unable to allocate file buf\n");
606 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
608 NS_ERR("alloc_device: unable to allocate page array\n");
611 for (i = 0; i < ns->geom.pgnum; i++) {
612 ns->pages[i].byte = NULL;
614 ns->nand_pages_slab = kmem_cache_create("nandsim",
615 ns->geom.pgszoob, 0, 0, NULL);
616 if (!ns->nand_pages_slab) {
617 NS_ERR("cache_create: unable to create kmem_cache\n");
624 vfree(ns->pages_written);
626 filp_close(cfile, NULL);
631 * Free any allocated pages, and free the array of page pointers.
633 static void free_device(struct nandsim *ns)
639 vfree(ns->pages_written);
640 filp_close(ns->cfile, NULL);
645 for (i = 0; i < ns->geom.pgnum; i++) {
646 if (ns->pages[i].byte)
647 kmem_cache_free(ns->nand_pages_slab,
650 kmem_cache_destroy(ns->nand_pages_slab);
655 static char *get_partition_name(int i)
657 return kasprintf(GFP_KERNEL, "NAND simulator partition %d", i);
661 * Initialize the nandsim structure.
663 * RETURNS: 0 if success, -ERRNO if failure.
665 static int init_nandsim(struct mtd_info *mtd)
667 struct nand_chip *chip = mtd->priv;
668 struct nandsim *ns = chip->priv;
671 uint64_t next_offset;
673 if (NS_IS_INITIALIZED(ns)) {
674 NS_ERR("init_nandsim: nandsim is already initialized\n");
678 /* Force mtd to not do delays */
679 chip->chip_delay = 0;
681 /* Initialize the NAND flash parameters */
682 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
683 ns->geom.totsz = mtd->size;
684 ns->geom.pgsz = mtd->writesize;
685 ns->geom.oobsz = mtd->oobsize;
686 ns->geom.secsz = mtd->erasesize;
687 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
688 ns->geom.pgnum = div_u64(ns->geom.totsz, ns->geom.pgsz);
689 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
690 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
691 ns->geom.pgshift = chip->page_shift;
692 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
693 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
694 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
697 if (ns->geom.pgsz == 512) {
698 ns->options |= OPT_PAGE512;
700 ns->options |= OPT_PAGE512_8BIT;
701 } else if (ns->geom.pgsz == 2048) {
702 ns->options |= OPT_PAGE2048;
703 } else if (ns->geom.pgsz == 4096) {
704 ns->options |= OPT_PAGE4096;
706 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
710 if (ns->options & OPT_SMALLPAGE) {
711 if (ns->geom.totsz <= (32 << 20)) {
712 ns->geom.pgaddrbytes = 3;
713 ns->geom.secaddrbytes = 2;
715 ns->geom.pgaddrbytes = 4;
716 ns->geom.secaddrbytes = 3;
719 if (ns->geom.totsz <= (128 << 20)) {
720 ns->geom.pgaddrbytes = 4;
721 ns->geom.secaddrbytes = 2;
723 ns->geom.pgaddrbytes = 5;
724 ns->geom.secaddrbytes = 3;
728 /* Fill the partition_info structure */
729 if (parts_num > ARRAY_SIZE(ns->partitions)) {
730 NS_ERR("too many partitions.\n");
734 remains = ns->geom.totsz;
736 for (i = 0; i < parts_num; ++i) {
737 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
739 if (!part_sz || part_sz > remains) {
740 NS_ERR("bad partition size.\n");
744 ns->partitions[i].name = get_partition_name(i);
745 ns->partitions[i].offset = next_offset;
746 ns->partitions[i].size = part_sz;
747 next_offset += ns->partitions[i].size;
748 remains -= ns->partitions[i].size;
750 ns->nbparts = parts_num;
752 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
753 NS_ERR("too many partitions.\n");
757 ns->partitions[i].name = get_partition_name(i);
758 ns->partitions[i].offset = next_offset;
759 ns->partitions[i].size = remains;
763 /* Detect how many ID bytes the NAND chip outputs */
764 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
765 if (second_id_byte != nand_flash_ids[i].dev_id)
770 NS_WARN("16-bit flashes support wasn't tested\n");
772 printk("flash size: %llu MiB\n",
773 (unsigned long long)ns->geom.totsz >> 20);
774 printk("page size: %u bytes\n", ns->geom.pgsz);
775 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
776 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
777 printk("pages number: %u\n", ns->geom.pgnum);
778 printk("pages per sector: %u\n", ns->geom.pgsec);
779 printk("bus width: %u\n", ns->busw);
780 printk("bits in sector size: %u\n", ns->geom.secshift);
781 printk("bits in page size: %u\n", ns->geom.pgshift);
782 printk("bits in OOB size: %u\n", ns->geom.oobshift);
783 printk("flash size with OOB: %llu KiB\n",
784 (unsigned long long)ns->geom.totszoob >> 10);
785 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
786 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
787 printk("options: %#x\n", ns->options);
789 if ((ret = alloc_device(ns)) != 0)
792 /* Allocate / initialize the internal buffer */
793 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
795 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
800 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
811 * Free the nandsim structure.
813 static void free_nandsim(struct nandsim *ns)
821 static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
825 unsigned int erase_block_no;
832 zero_ok = (*w == '0' ? 1 : 0);
833 erase_block_no = simple_strtoul(w, &w, 0);
834 if (!zero_ok && !erase_block_no) {
835 NS_ERR("invalid badblocks.\n");
838 offset = erase_block_no * ns->geom.secsz;
839 if (mtd_block_markbad(mtd, offset)) {
840 NS_ERR("invalid badblocks.\n");
849 static int parse_weakblocks(void)
853 unsigned int erase_block_no;
854 unsigned int max_erases;
855 struct weak_block *wb;
861 zero_ok = (*w == '0' ? 1 : 0);
862 erase_block_no = simple_strtoul(w, &w, 0);
863 if (!zero_ok && !erase_block_no) {
864 NS_ERR("invalid weakblocks.\n");
870 max_erases = simple_strtoul(w, &w, 0);
874 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
876 NS_ERR("unable to allocate memory.\n");
879 wb->erase_block_no = erase_block_no;
880 wb->max_erases = max_erases;
881 list_add(&wb->list, &weak_blocks);
886 static int erase_error(unsigned int erase_block_no)
888 struct weak_block *wb;
890 list_for_each_entry(wb, &weak_blocks, list)
891 if (wb->erase_block_no == erase_block_no) {
892 if (wb->erases_done >= wb->max_erases)
894 wb->erases_done += 1;
900 static int parse_weakpages(void)
904 unsigned int page_no;
905 unsigned int max_writes;
906 struct weak_page *wp;
912 zero_ok = (*w == '0' ? 1 : 0);
913 page_no = simple_strtoul(w, &w, 0);
914 if (!zero_ok && !page_no) {
915 NS_ERR("invalid weakpagess.\n");
921 max_writes = simple_strtoul(w, &w, 0);
925 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
927 NS_ERR("unable to allocate memory.\n");
930 wp->page_no = page_no;
931 wp->max_writes = max_writes;
932 list_add(&wp->list, &weak_pages);
937 static int write_error(unsigned int page_no)
939 struct weak_page *wp;
941 list_for_each_entry(wp, &weak_pages, list)
942 if (wp->page_no == page_no) {
943 if (wp->writes_done >= wp->max_writes)
945 wp->writes_done += 1;
951 static int parse_gravepages(void)
955 unsigned int page_no;
956 unsigned int max_reads;
957 struct grave_page *gp;
963 zero_ok = (*g == '0' ? 1 : 0);
964 page_no = simple_strtoul(g, &g, 0);
965 if (!zero_ok && !page_no) {
966 NS_ERR("invalid gravepagess.\n");
972 max_reads = simple_strtoul(g, &g, 0);
976 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
978 NS_ERR("unable to allocate memory.\n");
981 gp->page_no = page_no;
982 gp->max_reads = max_reads;
983 list_add(&gp->list, &grave_pages);
988 static int read_error(unsigned int page_no)
990 struct grave_page *gp;
992 list_for_each_entry(gp, &grave_pages, list)
993 if (gp->page_no == page_no) {
994 if (gp->reads_done >= gp->max_reads)
1002 static void free_lists(void)
1004 struct list_head *pos, *n;
1005 list_for_each_safe(pos, n, &weak_blocks) {
1007 kfree(list_entry(pos, struct weak_block, list));
1009 list_for_each_safe(pos, n, &weak_pages) {
1011 kfree(list_entry(pos, struct weak_page, list));
1013 list_for_each_safe(pos, n, &grave_pages) {
1015 kfree(list_entry(pos, struct grave_page, list));
1017 kfree(erase_block_wear);
1020 static int setup_wear_reporting(struct mtd_info *mtd)
1024 wear_eb_count = div_u64(mtd->size, mtd->erasesize);
1025 mem = wear_eb_count * sizeof(unsigned long);
1026 if (mem / sizeof(unsigned long) != wear_eb_count) {
1027 NS_ERR("Too many erase blocks for wear reporting\n");
1030 erase_block_wear = kzalloc(mem, GFP_KERNEL);
1031 if (!erase_block_wear) {
1032 NS_ERR("Too many erase blocks for wear reporting\n");
1038 static void update_wear(unsigned int erase_block_no)
1040 if (!erase_block_wear)
1044 * TODO: Notify this through a debugfs entry,
1045 * instead of showing an error message.
1047 if (total_wear == 0)
1048 NS_ERR("Erase counter total overflow\n");
1049 erase_block_wear[erase_block_no] += 1;
1050 if (erase_block_wear[erase_block_no] == 0)
1051 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
1055 * Returns the string representation of 'state' state.
1057 static char *get_state_name(uint32_t state)
1059 switch (NS_STATE(state)) {
1060 case STATE_CMD_READ0:
1061 return "STATE_CMD_READ0";
1062 case STATE_CMD_READ1:
1063 return "STATE_CMD_READ1";
1064 case STATE_CMD_PAGEPROG:
1065 return "STATE_CMD_PAGEPROG";
1066 case STATE_CMD_READOOB:
1067 return "STATE_CMD_READOOB";
1068 case STATE_CMD_READSTART:
1069 return "STATE_CMD_READSTART";
1070 case STATE_CMD_ERASE1:
1071 return "STATE_CMD_ERASE1";
1072 case STATE_CMD_STATUS:
1073 return "STATE_CMD_STATUS";
1074 case STATE_CMD_SEQIN:
1075 return "STATE_CMD_SEQIN";
1076 case STATE_CMD_READID:
1077 return "STATE_CMD_READID";
1078 case STATE_CMD_ERASE2:
1079 return "STATE_CMD_ERASE2";
1080 case STATE_CMD_RESET:
1081 return "STATE_CMD_RESET";
1082 case STATE_CMD_RNDOUT:
1083 return "STATE_CMD_RNDOUT";
1084 case STATE_CMD_RNDOUTSTART:
1085 return "STATE_CMD_RNDOUTSTART";
1086 case STATE_ADDR_PAGE:
1087 return "STATE_ADDR_PAGE";
1088 case STATE_ADDR_SEC:
1089 return "STATE_ADDR_SEC";
1090 case STATE_ADDR_ZERO:
1091 return "STATE_ADDR_ZERO";
1092 case STATE_ADDR_COLUMN:
1093 return "STATE_ADDR_COLUMN";
1095 return "STATE_DATAIN";
1097 return "STATE_DATAOUT";
1098 case STATE_DATAOUT_ID:
1099 return "STATE_DATAOUT_ID";
1100 case STATE_DATAOUT_STATUS:
1101 return "STATE_DATAOUT_STATUS";
1102 case STATE_DATAOUT_STATUS_M:
1103 return "STATE_DATAOUT_STATUS_M";
1105 return "STATE_READY";
1107 return "STATE_UNKNOWN";
1110 NS_ERR("get_state_name: unknown state, BUG\n");
1115 * Check if command is valid.
1117 * RETURNS: 1 if wrong command, 0 if right.
1119 static int check_command(int cmd)
1123 case NAND_CMD_READ0:
1124 case NAND_CMD_READ1:
1125 case NAND_CMD_READSTART:
1126 case NAND_CMD_PAGEPROG:
1127 case NAND_CMD_READOOB:
1128 case NAND_CMD_ERASE1:
1129 case NAND_CMD_STATUS:
1130 case NAND_CMD_SEQIN:
1131 case NAND_CMD_READID:
1132 case NAND_CMD_ERASE2:
1133 case NAND_CMD_RESET:
1134 case NAND_CMD_RNDOUT:
1135 case NAND_CMD_RNDOUTSTART:
1144 * Returns state after command is accepted by command number.
1146 static uint32_t get_state_by_command(unsigned command)
1149 case NAND_CMD_READ0:
1150 return STATE_CMD_READ0;
1151 case NAND_CMD_READ1:
1152 return STATE_CMD_READ1;
1153 case NAND_CMD_PAGEPROG:
1154 return STATE_CMD_PAGEPROG;
1155 case NAND_CMD_READSTART:
1156 return STATE_CMD_READSTART;
1157 case NAND_CMD_READOOB:
1158 return STATE_CMD_READOOB;
1159 case NAND_CMD_ERASE1:
1160 return STATE_CMD_ERASE1;
1161 case NAND_CMD_STATUS:
1162 return STATE_CMD_STATUS;
1163 case NAND_CMD_SEQIN:
1164 return STATE_CMD_SEQIN;
1165 case NAND_CMD_READID:
1166 return STATE_CMD_READID;
1167 case NAND_CMD_ERASE2:
1168 return STATE_CMD_ERASE2;
1169 case NAND_CMD_RESET:
1170 return STATE_CMD_RESET;
1171 case NAND_CMD_RNDOUT:
1172 return STATE_CMD_RNDOUT;
1173 case NAND_CMD_RNDOUTSTART:
1174 return STATE_CMD_RNDOUTSTART;
1177 NS_ERR("get_state_by_command: unknown command, BUG\n");
1182 * Move an address byte to the correspondent internal register.
1184 static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1186 uint byte = (uint)bt;
1188 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1189 ns->regs.column |= (byte << 8 * ns->regs.count);
1191 ns->regs.row |= (byte << 8 * (ns->regs.count -
1192 ns->geom.pgaddrbytes +
1193 ns->geom.secaddrbytes));
1200 * Switch to STATE_READY state.
1202 static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1204 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1206 ns->state = STATE_READY;
1207 ns->nxstate = STATE_UNKNOWN;
1215 ns->regs.column = 0;
1216 ns->regs.status = status;
1220 * If the operation isn't known yet, try to find it in the global array
1221 * of supported operations.
1223 * Operation can be unknown because of the following.
1224 * 1. New command was accepted and this is the first call to find the
1225 * correspondent states chain. In this case ns->npstates = 0;
1226 * 2. There are several operations which begin with the same command(s)
1227 * (for example program from the second half and read from the
1228 * second half operations both begin with the READ1 command). In this
1229 * case the ns->pstates[] array contains previous states.
1231 * Thus, the function tries to find operation containing the following
1232 * states (if the 'flag' parameter is 0):
1233 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1235 * If (one and only one) matching operation is found, it is accepted (
1236 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1239 * If there are several matches, the current state is pushed to the
1242 * The operation can be unknown only while commands are input to the chip.
1243 * As soon as address command is accepted, the operation must be known.
1244 * In such situation the function is called with 'flag' != 0, and the
1245 * operation is searched using the following pattern:
1246 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1248 * It is supposed that this pattern must either match one operation or
1249 * none. There can't be ambiguity in that case.
1251 * If no matches found, the function does the following:
1252 * 1. if there are saved states present, try to ignore them and search
1253 * again only using the last command. If nothing was found, switch
1254 * to the STATE_READY state.
1255 * 2. if there are no saved states, switch to the STATE_READY state.
1257 * RETURNS: -2 - no matched operations found.
1258 * -1 - several matches.
1259 * 0 - operation is found.
1261 static int find_operation(struct nandsim *ns, uint32_t flag)
1266 for (i = 0; i < NS_OPER_NUM; i++) {
1270 if (!(ns->options & ops[i].reqopts))
1271 /* Ignore operations we can't perform */
1275 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1278 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1282 for (j = 0; j < ns->npstates; j++)
1283 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1284 && (ns->options & ops[idx].reqopts)) {
1295 if (opsfound == 1) {
1297 ns->op = &ops[idx].states[0];
1300 * In this case the find_operation function was
1301 * called when address has just began input. But it isn't
1302 * yet fully input and the current state must
1303 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1304 * state must be the next state (ns->nxstate).
1306 ns->stateidx = ns->npstates - 1;
1308 ns->stateidx = ns->npstates;
1311 ns->state = ns->op[ns->stateidx];
1312 ns->nxstate = ns->op[ns->stateidx + 1];
1313 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1314 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1318 if (opsfound == 0) {
1319 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1320 if (ns->npstates != 0) {
1321 NS_DBG("find_operation: no operation found, try again with state %s\n",
1322 get_state_name(ns->state));
1324 return find_operation(ns, 0);
1327 NS_DBG("find_operation: no operations found\n");
1328 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1333 /* This shouldn't happen */
1334 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1338 NS_DBG("find_operation: there is still ambiguity\n");
1340 ns->pstates[ns->npstates++] = ns->state;
1345 static void put_pages(struct nandsim *ns)
1349 for (i = 0; i < ns->held_cnt; i++)
1350 page_cache_release(ns->held_pages[i]);
1353 /* Get page cache pages in advance to provide NOFS memory allocation */
1354 static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1356 pgoff_t index, start_index, end_index;
1358 struct address_space *mapping = file->f_mapping;
1360 start_index = pos >> PAGE_CACHE_SHIFT;
1361 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1362 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1365 for (index = start_index; index <= end_index; index++) {
1366 page = find_get_page(mapping, index);
1368 page = find_or_create_page(mapping, index, GFP_NOFS);
1370 write_inode_now(mapping->host, 1);
1371 page = find_or_create_page(mapping, index, GFP_NOFS);
1379 ns->held_pages[ns->held_cnt++] = page;
1384 static int set_memalloc(void)
1386 if (current->flags & PF_MEMALLOC)
1388 current->flags |= PF_MEMALLOC;
1392 static void clear_memalloc(int memalloc)
1395 current->flags &= ~PF_MEMALLOC;
1398 static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos)
1403 err = get_pages(ns, file, count, pos);
1406 memalloc = set_memalloc();
1407 tx = kernel_read(file, pos, buf, count);
1408 clear_memalloc(memalloc);
1413 static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t pos)
1418 err = get_pages(ns, file, count, pos);
1421 memalloc = set_memalloc();
1422 tx = kernel_write(file, buf, count, pos);
1423 clear_memalloc(memalloc);
1429 * Returns a pointer to the current page.
1431 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1433 return &(ns->pages[ns->regs.row]);
1437 * Retuns a pointer to the current byte, within the current page.
1439 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1441 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1444 int do_read_error(struct nandsim *ns, int num)
1446 unsigned int page_no = ns->regs.row;
1448 if (read_error(page_no)) {
1449 prandom_bytes(ns->buf.byte, num);
1450 NS_WARN("simulating read error in page %u\n", page_no);
1456 void do_bit_flips(struct nandsim *ns, int num)
1458 if (bitflips && prandom_u32() < (1 << 22)) {
1461 flips = (prandom_u32() % (int) bitflips) + 1;
1463 int pos = prandom_u32() % (num * 8);
1464 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1465 NS_WARN("read_page: flipping bit %d in page %d "
1466 "reading from %d ecc: corrected=%u failed=%u\n",
1467 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1468 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1474 * Fill the NAND buffer with data read from the specified page.
1476 static void read_page(struct nandsim *ns, int num)
1478 union ns_mem *mypage;
1481 if (!test_bit(ns->regs.row, ns->pages_written)) {
1482 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1483 memset(ns->buf.byte, 0xFF, num);
1488 NS_DBG("read_page: page %d written, reading from %d\n",
1489 ns->regs.row, ns->regs.column + ns->regs.off);
1490 if (do_read_error(ns, num))
1492 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1493 tx = read_file(ns, ns->cfile, ns->buf.byte, num, pos);
1495 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1498 do_bit_flips(ns, num);
1503 mypage = NS_GET_PAGE(ns);
1504 if (mypage->byte == NULL) {
1505 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1506 memset(ns->buf.byte, 0xFF, num);
1508 NS_DBG("read_page: page %d allocated, reading from %d\n",
1509 ns->regs.row, ns->regs.column + ns->regs.off);
1510 if (do_read_error(ns, num))
1512 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1513 do_bit_flips(ns, num);
1518 * Erase all pages in the specified sector.
1520 static void erase_sector(struct nandsim *ns)
1522 union ns_mem *mypage;
1526 for (i = 0; i < ns->geom.pgsec; i++)
1527 if (__test_and_clear_bit(ns->regs.row + i,
1528 ns->pages_written)) {
1529 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1534 mypage = NS_GET_PAGE(ns);
1535 for (i = 0; i < ns->geom.pgsec; i++) {
1536 if (mypage->byte != NULL) {
1537 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1538 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1539 mypage->byte = NULL;
1546 * Program the specified page with the contents from the NAND buffer.
1548 static int prog_page(struct nandsim *ns, int num)
1551 union ns_mem *mypage;
1559 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1560 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1561 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1562 if (!test_bit(ns->regs.row, ns->pages_written)) {
1564 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1567 tx = read_file(ns, ns->cfile, pg_off, num, off);
1569 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1573 for (i = 0; i < num; i++)
1574 pg_off[i] &= ns->buf.byte[i];
1576 loff_t pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1577 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, pos);
1578 if (tx != ns->geom.pgszoob) {
1579 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1582 __set_bit(ns->regs.row, ns->pages_written);
1584 tx = write_file(ns, ns->cfile, pg_off, num, off);
1586 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1593 mypage = NS_GET_PAGE(ns);
1594 if (mypage->byte == NULL) {
1595 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1597 * We allocate memory with GFP_NOFS because a flash FS may
1598 * utilize this. If it is holding an FS lock, then gets here,
1599 * then kernel memory alloc runs writeback which goes to the FS
1600 * again and deadlocks. This was seen in practice.
1602 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1603 if (mypage->byte == NULL) {
1604 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1607 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1610 pg_off = NS_PAGE_BYTE_OFF(ns);
1611 for (i = 0; i < num; i++)
1612 pg_off[i] &= ns->buf.byte[i];
1618 * If state has any action bit, perform this action.
1620 * RETURNS: 0 if success, -1 if error.
1622 static int do_state_action(struct nandsim *ns, uint32_t action)
1625 int busdiv = ns->busw == 8 ? 1 : 2;
1626 unsigned int erase_block_no, page_no;
1628 action &= ACTION_MASK;
1630 /* Check that page address input is correct */
1631 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1632 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1640 * Copy page data to the internal buffer.
1643 /* Column shouldn't be very large */
1644 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1645 NS_ERR("do_state_action: column number is too large\n");
1648 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1651 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1652 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1654 if (ns->regs.off == 0)
1655 NS_LOG("read page %d\n", ns->regs.row);
1656 else if (ns->regs.off < ns->geom.pgsz)
1657 NS_LOG("read page %d (second half)\n", ns->regs.row);
1659 NS_LOG("read OOB of page %d\n", ns->regs.row);
1661 NS_UDELAY(access_delay);
1662 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1666 case ACTION_SECERASE:
1672 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1676 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1677 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1678 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1682 ns->regs.row = (ns->regs.row <<
1683 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1684 ns->regs.column = 0;
1686 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1688 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1689 ns->regs.row, NS_RAW_OFFSET(ns));
1690 NS_LOG("erase sector %u\n", erase_block_no);
1694 NS_MDELAY(erase_delay);
1696 if (erase_block_wear)
1697 update_wear(erase_block_no);
1699 if (erase_error(erase_block_no)) {
1700 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1706 case ACTION_PRGPAGE:
1708 * Program page - move internal buffer data to the page.
1712 NS_WARN("do_state_action: device is write-protected, programm\n");
1716 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1717 if (num != ns->regs.count) {
1718 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1719 ns->regs.count, num);
1723 if (prog_page(ns, num) == -1)
1726 page_no = ns->regs.row;
1728 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1729 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1730 NS_LOG("programm page %d\n", ns->regs.row);
1732 NS_UDELAY(programm_delay);
1733 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1735 if (write_error(page_no)) {
1736 NS_WARN("simulating write failure in page %u\n", page_no);
1742 case ACTION_ZEROOFF:
1743 NS_DBG("do_state_action: set internal offset to 0\n");
1747 case ACTION_HALFOFF:
1748 if (!(ns->options & OPT_PAGE512_8BIT)) {
1749 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1750 "byte page size 8x chips\n");
1753 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1754 ns->regs.off = ns->geom.pgsz/2;
1758 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1759 ns->regs.off = ns->geom.pgsz;
1763 NS_DBG("do_state_action: BUG! unknown action\n");
1770 * Switch simulator's state.
1772 static void switch_state(struct nandsim *ns)
1776 * The current operation have already been identified.
1777 * Just follow the states chain.
1781 ns->state = ns->nxstate;
1782 ns->nxstate = ns->op[ns->stateidx + 1];
1784 NS_DBG("switch_state: operation is known, switch to the next state, "
1785 "state: %s, nxstate: %s\n",
1786 get_state_name(ns->state), get_state_name(ns->nxstate));
1788 /* See, whether we need to do some action */
1789 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1790 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1796 * We don't yet know which operation we perform.
1797 * Try to identify it.
1801 * The only event causing the switch_state function to
1802 * be called with yet unknown operation is new command.
1804 ns->state = get_state_by_command(ns->regs.command);
1806 NS_DBG("switch_state: operation is unknown, try to find it\n");
1808 if (find_operation(ns, 0) != 0)
1811 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1812 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1817 /* For 16x devices column means the page offset in words */
1818 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1819 NS_DBG("switch_state: double the column number for 16x device\n");
1820 ns->regs.column <<= 1;
1823 if (NS_STATE(ns->nxstate) == STATE_READY) {
1825 * The current state is the last. Return to STATE_READY
1828 u_char status = NS_STATUS_OK(ns);
1830 /* In case of data states, see if all bytes were input/output */
1831 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1832 && ns->regs.count != ns->regs.num) {
1833 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1834 ns->regs.num - ns->regs.count);
1835 status = NS_STATUS_FAILED(ns);
1838 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1840 switch_to_ready_state(ns, status);
1843 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1845 * If the next state is data input/output, switch to it now
1848 ns->state = ns->nxstate;
1849 ns->nxstate = ns->op[++ns->stateidx + 1];
1850 ns->regs.num = ns->regs.count = 0;
1852 NS_DBG("switch_state: the next state is data I/O, switch, "
1853 "state: %s, nxstate: %s\n",
1854 get_state_name(ns->state), get_state_name(ns->nxstate));
1857 * Set the internal register to the count of bytes which
1858 * are expected to be input or output
1860 switch (NS_STATE(ns->state)) {
1863 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1866 case STATE_DATAOUT_ID:
1867 ns->regs.num = ns->geom.idbytes;
1870 case STATE_DATAOUT_STATUS:
1871 case STATE_DATAOUT_STATUS_M:
1872 ns->regs.count = ns->regs.num = 0;
1876 NS_ERR("switch_state: BUG! unknown data state\n");
1879 } else if (ns->nxstate & STATE_ADDR_MASK) {
1881 * If the next state is address input, set the internal
1882 * register to the number of expected address bytes
1887 switch (NS_STATE(ns->nxstate)) {
1888 case STATE_ADDR_PAGE:
1889 ns->regs.num = ns->geom.pgaddrbytes;
1892 case STATE_ADDR_SEC:
1893 ns->regs.num = ns->geom.secaddrbytes;
1896 case STATE_ADDR_ZERO:
1900 case STATE_ADDR_COLUMN:
1901 /* Column address is always 2 bytes */
1902 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1906 NS_ERR("switch_state: BUG! unknown address state\n");
1910 * Just reset internal counters.
1918 static u_char ns_nand_read_byte(struct mtd_info *mtd)
1920 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1923 /* Sanity and correctness checks */
1924 if (!ns->lines.ce) {
1925 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1928 if (ns->lines.ale || ns->lines.cle) {
1929 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1932 if (!(ns->state & STATE_DATAOUT_MASK)) {
1933 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1934 "return %#x\n", get_state_name(ns->state), (uint)outb);
1938 /* Status register may be read as many times as it is wanted */
1939 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1940 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1941 return ns->regs.status;
1944 /* Check if there is any data in the internal buffer which may be read */
1945 if (ns->regs.count == ns->regs.num) {
1946 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1950 switch (NS_STATE(ns->state)) {
1952 if (ns->busw == 8) {
1953 outb = ns->buf.byte[ns->regs.count];
1954 ns->regs.count += 1;
1956 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1957 ns->regs.count += 2;
1960 case STATE_DATAOUT_ID:
1961 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1962 outb = ns->ids[ns->regs.count];
1963 ns->regs.count += 1;
1969 if (ns->regs.count == ns->regs.num) {
1970 NS_DBG("read_byte: all bytes were read\n");
1972 if (NS_STATE(ns->nxstate) == STATE_READY)
1979 static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1981 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1983 /* Sanity and correctness checks */
1984 if (!ns->lines.ce) {
1985 NS_ERR("write_byte: chip is disabled, ignore write\n");
1988 if (ns->lines.ale && ns->lines.cle) {
1989 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1993 if (ns->lines.cle == 1) {
1995 * The byte written is a command.
1998 if (byte == NAND_CMD_RESET) {
1999 NS_LOG("reset chip\n");
2000 switch_to_ready_state(ns, NS_STATUS_OK(ns));
2004 /* Check that the command byte is correct */
2005 if (check_command(byte)) {
2006 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
2010 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
2011 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
2012 || NS_STATE(ns->state) == STATE_DATAOUT) {
2013 int row = ns->regs.row;
2016 if (byte == NAND_CMD_RNDOUT)
2020 /* Check if chip is expecting command */
2021 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
2022 /* Do not warn if only 2 id bytes are read */
2023 if (!(ns->regs.command == NAND_CMD_READID &&
2024 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
2026 * We are in situation when something else (not command)
2027 * was expected but command was input. In this case ignore
2028 * previous command(s)/state(s) and accept the last one.
2030 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
2031 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
2033 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2036 NS_DBG("command byte corresponding to %s state accepted\n",
2037 get_state_name(get_state_by_command(byte)));
2038 ns->regs.command = byte;
2041 } else if (ns->lines.ale == 1) {
2043 * The byte written is an address.
2046 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2048 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2050 if (find_operation(ns, 1) < 0)
2053 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2054 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2059 switch (NS_STATE(ns->nxstate)) {
2060 case STATE_ADDR_PAGE:
2061 ns->regs.num = ns->geom.pgaddrbytes;
2063 case STATE_ADDR_SEC:
2064 ns->regs.num = ns->geom.secaddrbytes;
2066 case STATE_ADDR_ZERO:
2074 /* Check that chip is expecting address */
2075 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2076 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2077 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2078 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2082 /* Check if this is expected byte */
2083 if (ns->regs.count == ns->regs.num) {
2084 NS_ERR("write_byte: no more address bytes expected\n");
2085 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2089 accept_addr_byte(ns, byte);
2091 ns->regs.count += 1;
2093 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2094 (uint)byte, ns->regs.count, ns->regs.num);
2096 if (ns->regs.count == ns->regs.num) {
2097 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2103 * The byte written is an input data.
2106 /* Check that chip is expecting data input */
2107 if (!(ns->state & STATE_DATAIN_MASK)) {
2108 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2109 "switch to %s\n", (uint)byte,
2110 get_state_name(ns->state), get_state_name(STATE_READY));
2111 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2115 /* Check if this is expected byte */
2116 if (ns->regs.count == ns->regs.num) {
2117 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2122 if (ns->busw == 8) {
2123 ns->buf.byte[ns->regs.count] = byte;
2124 ns->regs.count += 1;
2126 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2127 ns->regs.count += 2;
2134 static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2136 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2138 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2139 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2140 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2142 if (cmd != NAND_CMD_NONE)
2143 ns_nand_write_byte(mtd, cmd);
2146 static int ns_device_ready(struct mtd_info *mtd)
2148 NS_DBG("device_ready\n");
2152 static uint16_t ns_nand_read_word(struct mtd_info *mtd)
2154 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2156 NS_DBG("read_word\n");
2158 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2161 static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2163 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2165 /* Check that chip is expecting data input */
2166 if (!(ns->state & STATE_DATAIN_MASK)) {
2167 NS_ERR("write_buf: data input isn't expected, state is %s, "
2168 "switch to STATE_READY\n", get_state_name(ns->state));
2169 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2173 /* Check if these are expected bytes */
2174 if (ns->regs.count + len > ns->regs.num) {
2175 NS_ERR("write_buf: too many input bytes\n");
2176 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2180 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2181 ns->regs.count += len;
2183 if (ns->regs.count == ns->regs.num) {
2184 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2188 static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2190 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2192 /* Sanity and correctness checks */
2193 if (!ns->lines.ce) {
2194 NS_ERR("read_buf: chip is disabled\n");
2197 if (ns->lines.ale || ns->lines.cle) {
2198 NS_ERR("read_buf: ALE or CLE pin is high\n");
2201 if (!(ns->state & STATE_DATAOUT_MASK)) {
2202 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2203 get_state_name(ns->state));
2207 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2210 for (i = 0; i < len; i++)
2211 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2216 /* Check if these are expected bytes */
2217 if (ns->regs.count + len > ns->regs.num) {
2218 NS_ERR("read_buf: too many bytes to read\n");
2219 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2223 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2224 ns->regs.count += len;
2226 if (ns->regs.count == ns->regs.num) {
2227 if (NS_STATE(ns->nxstate) == STATE_READY)
2235 * Module initialization function
2237 static int __init ns_init_module(void)
2239 struct nand_chip *chip;
2240 struct nandsim *nand;
2241 int retval = -ENOMEM, i;
2243 if (bus_width != 8 && bus_width != 16) {
2244 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2248 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
2249 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
2250 + sizeof(struct nandsim), GFP_KERNEL);
2252 NS_ERR("unable to allocate core structures.\n");
2255 chip = (struct nand_chip *)(nsmtd + 1);
2256 nsmtd->priv = (void *)chip;
2257 nand = (struct nandsim *)(chip + 1);
2258 chip->priv = (void *)nand;
2261 * Register simulator's callbacks.
2263 chip->cmd_ctrl = ns_hwcontrol;
2264 chip->read_byte = ns_nand_read_byte;
2265 chip->dev_ready = ns_device_ready;
2266 chip->write_buf = ns_nand_write_buf;
2267 chip->read_buf = ns_nand_read_buf;
2268 chip->read_word = ns_nand_read_word;
2269 chip->ecc.mode = NAND_ECC_SOFT;
2270 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2271 /* and 'badblocks' parameters to work */
2272 chip->options |= NAND_SKIP_BBTSCAN;
2276 chip->bbt_options |= NAND_BBT_NO_OOB;
2278 chip->bbt_options |= NAND_BBT_USE_FLASH;
2282 NS_ERR("bbt has to be 0..2\n");
2287 * Perform minimum nandsim structure initialization to handle
2288 * the initial ID read command correctly
2290 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2291 nand->geom.idbytes = 4;
2293 nand->geom.idbytes = 2;
2294 nand->regs.status = NS_STATUS_OK(nand);
2295 nand->nxstate = STATE_UNKNOWN;
2296 nand->options |= OPT_PAGE512; /* temporary value */
2297 nand->ids[0] = first_id_byte;
2298 nand->ids[1] = second_id_byte;
2299 nand->ids[2] = third_id_byte;
2300 nand->ids[3] = fourth_id_byte;
2301 if (bus_width == 16) {
2303 chip->options |= NAND_BUSWIDTH_16;
2306 nsmtd->owner = THIS_MODULE;
2308 if ((retval = parse_weakblocks()) != 0)
2311 if ((retval = parse_weakpages()) != 0)
2314 if ((retval = parse_gravepages()) != 0)
2317 retval = nand_scan_ident(nsmtd, 1, NULL);
2319 NS_ERR("cannot scan NAND Simulator device\n");
2326 unsigned int eccsteps, eccbytes;
2327 if (!mtd_nand_has_bch()) {
2328 NS_ERR("BCH ECC support is disabled\n");
2332 /* use 512-byte ecc blocks */
2333 eccsteps = nsmtd->writesize/512;
2334 eccbytes = (bch*13+7)/8;
2335 /* do not bother supporting small page devices */
2336 if ((nsmtd->oobsize < 64) || !eccsteps) {
2337 NS_ERR("bch not available on small page devices\n");
2341 if ((eccbytes*eccsteps+2) > nsmtd->oobsize) {
2342 NS_ERR("invalid bch value %u\n", bch);
2346 chip->ecc.mode = NAND_ECC_SOFT_BCH;
2347 chip->ecc.size = 512;
2348 chip->ecc.bytes = eccbytes;
2349 NS_INFO("using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2352 retval = nand_scan_tail(nsmtd);
2354 NS_ERR("can't register NAND Simulator\n");
2361 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2362 if (new_size >> overridesize != nsmtd->erasesize) {
2363 NS_ERR("overridesize is too big\n");
2367 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2368 nsmtd->size = new_size;
2369 chip->chipsize = new_size;
2370 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2371 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2374 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2377 if ((retval = nandsim_debugfs_create(nand)) != 0)
2380 if ((retval = init_nandsim(nsmtd)) != 0)
2383 if ((retval = nand_default_bbt(nsmtd)) != 0)
2386 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2389 /* Register NAND partitions */
2390 retval = mtd_device_register(nsmtd, &nand->partitions[0],
2399 nand_release(nsmtd);
2400 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2401 kfree(nand->partitions[i].name);
2409 module_init(ns_init_module);
2412 * Module clean-up function
2414 static void __exit ns_cleanup_module(void)
2416 struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv;
2419 nandsim_debugfs_remove(ns);
2420 free_nandsim(ns); /* Free nandsim private resources */
2421 nand_release(nsmtd); /* Unregister driver */
2422 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2423 kfree(ns->partitions[i].name);
2424 kfree(nsmtd); /* Free other structures */
2428 module_exit(ns_cleanup_module);
2430 MODULE_LICENSE ("GPL");
2431 MODULE_AUTHOR ("Artem B. Bityuckiy");
2432 MODULE_DESCRIPTION ("The NAND flash simulator");