3 * This is the generic MTD driver for NAND flash devices. It should be
4 * capable of working with almost all NAND chips currently available.
6 * Additional technical information is available on
7 * http://www.linux-mtd.infradead.org/doc/nand.html
9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
13 * David Woodhouse for adding multichip support
15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
22 * BBT table is not serialized, has to be fixed
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <linux/err.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
39 #include <linux/types.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/nand_ecc.h>
43 #include <linux/mtd/nand_bch.h>
44 #include <linux/interrupt.h>
45 #include <linux/bitops.h>
47 #include <linux/mtd/partitions.h>
50 static int nand_get_device(struct mtd_info *mtd, int new_state);
52 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
53 struct mtd_oob_ops *ops);
55 /* Define default oob placement schemes for large and small page devices */
56 static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
57 struct mtd_oob_region *oobregion)
59 struct nand_chip *chip = mtd_to_nand(mtd);
60 struct nand_ecc_ctrl *ecc = &chip->ecc;
66 oobregion->offset = 0;
67 oobregion->length = 4;
69 oobregion->offset = 6;
70 oobregion->length = ecc->total - 4;
76 static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section,
77 struct mtd_oob_region *oobregion)
82 if (mtd->oobsize == 16) {
86 oobregion->length = 8;
87 oobregion->offset = 8;
89 oobregion->length = 2;
91 oobregion->offset = 3;
93 oobregion->offset = 6;
99 const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = {
100 .ecc = nand_ooblayout_ecc_sp,
101 .free = nand_ooblayout_free_sp,
103 EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops);
105 static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section,
106 struct mtd_oob_region *oobregion)
108 struct nand_chip *chip = mtd_to_nand(mtd);
109 struct nand_ecc_ctrl *ecc = &chip->ecc;
114 oobregion->length = ecc->total;
115 oobregion->offset = mtd->oobsize - oobregion->length;
120 static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section,
121 struct mtd_oob_region *oobregion)
123 struct nand_chip *chip = mtd_to_nand(mtd);
124 struct nand_ecc_ctrl *ecc = &chip->ecc;
129 oobregion->length = mtd->oobsize - ecc->total - 2;
130 oobregion->offset = 2;
135 const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
136 .ecc = nand_ooblayout_ecc_lp,
137 .free = nand_ooblayout_free_lp,
139 EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops);
141 static int check_offs_len(struct mtd_info *mtd,
142 loff_t ofs, uint64_t len)
144 struct nand_chip *chip = mtd_to_nand(mtd);
147 /* Start address must align on block boundary */
148 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
149 pr_debug("%s: unaligned address\n", __func__);
153 /* Length must align on block boundary */
154 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
155 pr_debug("%s: length not block aligned\n", __func__);
163 * nand_release_device - [GENERIC] release chip
164 * @mtd: MTD device structure
166 * Release chip lock and wake up anyone waiting on the device.
168 static void nand_release_device(struct mtd_info *mtd)
170 struct nand_chip *chip = mtd_to_nand(mtd);
172 /* Release the controller and the chip */
173 spin_lock(&chip->controller->lock);
174 chip->controller->active = NULL;
175 chip->state = FL_READY;
176 wake_up(&chip->controller->wq);
177 spin_unlock(&chip->controller->lock);
181 * nand_read_byte - [DEFAULT] read one byte from the chip
182 * @mtd: MTD device structure
184 * Default read function for 8bit buswidth
186 static uint8_t nand_read_byte(struct mtd_info *mtd)
188 struct nand_chip *chip = mtd_to_nand(mtd);
189 return readb(chip->IO_ADDR_R);
193 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
194 * @mtd: MTD device structure
196 * Default read function for 16bit buswidth with endianness conversion.
199 static uint8_t nand_read_byte16(struct mtd_info *mtd)
201 struct nand_chip *chip = mtd_to_nand(mtd);
202 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
206 * nand_read_word - [DEFAULT] read one word from the chip
207 * @mtd: MTD device structure
209 * Default read function for 16bit buswidth without endianness conversion.
211 static u16 nand_read_word(struct mtd_info *mtd)
213 struct nand_chip *chip = mtd_to_nand(mtd);
214 return readw(chip->IO_ADDR_R);
218 * nand_select_chip - [DEFAULT] control CE line
219 * @mtd: MTD device structure
220 * @chipnr: chipnumber to select, -1 for deselect
222 * Default select function for 1 chip devices.
224 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
226 struct nand_chip *chip = mtd_to_nand(mtd);
230 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
241 * nand_write_byte - [DEFAULT] write single byte to chip
242 * @mtd: MTD device structure
243 * @byte: value to write
245 * Default function to write a byte to I/O[7:0]
247 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
249 struct nand_chip *chip = mtd_to_nand(mtd);
251 chip->write_buf(mtd, &byte, 1);
255 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
256 * @mtd: MTD device structure
257 * @byte: value to write
259 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
261 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
263 struct nand_chip *chip = mtd_to_nand(mtd);
264 uint16_t word = byte;
267 * It's not entirely clear what should happen to I/O[15:8] when writing
268 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
270 * When the host supports a 16-bit bus width, only data is
271 * transferred at the 16-bit width. All address and command line
272 * transfers shall use only the lower 8-bits of the data bus. During
273 * command transfers, the host may place any value on the upper
274 * 8-bits of the data bus. During address transfers, the host shall
275 * set the upper 8-bits of the data bus to 00h.
277 * One user of the write_byte callback is nand_onfi_set_features. The
278 * four parameters are specified to be written to I/O[7:0], but this is
279 * neither an address nor a command transfer. Let's assume a 0 on the
280 * upper I/O lines is OK.
282 chip->write_buf(mtd, (uint8_t *)&word, 2);
286 * nand_write_buf - [DEFAULT] write buffer to chip
287 * @mtd: MTD device structure
289 * @len: number of bytes to write
291 * Default write function for 8bit buswidth.
293 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
295 struct nand_chip *chip = mtd_to_nand(mtd);
297 iowrite8_rep(chip->IO_ADDR_W, buf, len);
301 * nand_read_buf - [DEFAULT] read chip data into buffer
302 * @mtd: MTD device structure
303 * @buf: buffer to store date
304 * @len: number of bytes to read
306 * Default read function for 8bit buswidth.
308 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
310 struct nand_chip *chip = mtd_to_nand(mtd);
312 ioread8_rep(chip->IO_ADDR_R, buf, len);
316 * nand_write_buf16 - [DEFAULT] write buffer to chip
317 * @mtd: MTD device structure
319 * @len: number of bytes to write
321 * Default write function for 16bit buswidth.
323 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
325 struct nand_chip *chip = mtd_to_nand(mtd);
326 u16 *p = (u16 *) buf;
328 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
332 * nand_read_buf16 - [DEFAULT] read chip data into buffer
333 * @mtd: MTD device structure
334 * @buf: buffer to store date
335 * @len: number of bytes to read
337 * Default read function for 16bit buswidth.
339 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
341 struct nand_chip *chip = mtd_to_nand(mtd);
342 u16 *p = (u16 *) buf;
344 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
348 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
349 * @mtd: MTD device structure
350 * @ofs: offset from device start
352 * Check, if the block is bad.
354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
356 int page, res = 0, i = 0;
357 struct nand_chip *chip = mtd_to_nand(mtd);
360 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
361 ofs += mtd->erasesize - mtd->writesize;
363 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
366 if (chip->options & NAND_BUSWIDTH_16) {
367 chip->cmdfunc(mtd, NAND_CMD_READOOB,
368 chip->badblockpos & 0xFE, page);
369 bad = cpu_to_le16(chip->read_word(mtd));
370 if (chip->badblockpos & 0x1)
375 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
377 bad = chip->read_byte(mtd);
380 if (likely(chip->badblockbits == 8))
383 res = hweight8(bad) < chip->badblockbits;
384 ofs += mtd->writesize;
385 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
387 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
393 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
397 * This is the default implementation, which can be overridden by a hardware
398 * specific driver. It provides the details for writing a bad block marker to a
401 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
403 struct nand_chip *chip = mtd_to_nand(mtd);
404 struct mtd_oob_ops ops;
405 uint8_t buf[2] = { 0, 0 };
406 int ret = 0, res, i = 0;
408 memset(&ops, 0, sizeof(ops));
410 ops.ooboffs = chip->badblockpos;
411 if (chip->options & NAND_BUSWIDTH_16) {
412 ops.ooboffs &= ~0x01;
413 ops.len = ops.ooblen = 2;
415 ops.len = ops.ooblen = 1;
417 ops.mode = MTD_OPS_PLACE_OOB;
419 /* Write to first/last page(s) if necessary */
420 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
421 ofs += mtd->erasesize - mtd->writesize;
423 res = nand_do_write_oob(mtd, ofs, &ops);
428 ofs += mtd->writesize;
429 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
435 * nand_block_markbad_lowlevel - mark a block bad
436 * @mtd: MTD device structure
437 * @ofs: offset from device start
439 * This function performs the generic NAND bad block marking steps (i.e., bad
440 * block table(s) and/or marker(s)). We only allow the hardware driver to
441 * specify how to write bad block markers to OOB (chip->block_markbad).
443 * We try operations in the following order:
444 * (1) erase the affected block, to allow OOB marker to be written cleanly
445 * (2) write bad block marker to OOB area of affected block (unless flag
446 * NAND_BBT_NO_OOB_BBM is present)
448 * Note that we retain the first error encountered in (2) or (3), finish the
449 * procedures, and dump the error in the end.
451 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
453 struct nand_chip *chip = mtd_to_nand(mtd);
456 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
457 struct erase_info einfo;
459 /* Attempt erase before marking OOB */
460 memset(&einfo, 0, sizeof(einfo));
463 einfo.len = 1ULL << chip->phys_erase_shift;
464 nand_erase_nand(mtd, &einfo, 0);
466 /* Write bad block marker to OOB */
467 nand_get_device(mtd, FL_WRITING);
468 ret = chip->block_markbad(mtd, ofs);
469 nand_release_device(mtd);
472 /* Mark block bad in BBT */
474 res = nand_markbad_bbt(mtd, ofs);
480 mtd->ecc_stats.badblocks++;
486 * nand_check_wp - [GENERIC] check if the chip is write protected
487 * @mtd: MTD device structure
489 * Check, if the device is write protected. The function expects, that the
490 * device is already selected.
492 static int nand_check_wp(struct mtd_info *mtd)
494 struct nand_chip *chip = mtd_to_nand(mtd);
496 /* Broken xD cards report WP despite being writable */
497 if (chip->options & NAND_BROKEN_XD)
500 /* Check the WP bit */
501 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
502 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
506 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
507 * @mtd: MTD device structure
508 * @ofs: offset from device start
510 * Check if the block is marked as reserved.
512 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
514 struct nand_chip *chip = mtd_to_nand(mtd);
518 /* Return info from the table */
519 return nand_isreserved_bbt(mtd, ofs);
523 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
524 * @mtd: MTD device structure
525 * @ofs: offset from device start
526 * @allowbbt: 1, if its allowed to access the bbt area
528 * Check, if the block is bad. Either by reading the bad block table or
529 * calling of the scan function.
531 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
533 struct nand_chip *chip = mtd_to_nand(mtd);
536 return chip->block_bad(mtd, ofs);
538 /* Return info from the table */
539 return nand_isbad_bbt(mtd, ofs, allowbbt);
543 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
544 * @mtd: MTD device structure
547 * Helper function for nand_wait_ready used when needing to wait in interrupt
550 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
552 struct nand_chip *chip = mtd_to_nand(mtd);
555 /* Wait for the device to get ready */
556 for (i = 0; i < timeo; i++) {
557 if (chip->dev_ready(mtd))
559 touch_softlockup_watchdog();
565 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
566 * @mtd: MTD device structure
568 * Wait for the ready pin after a command, and warn if a timeout occurs.
570 void nand_wait_ready(struct mtd_info *mtd)
572 struct nand_chip *chip = mtd_to_nand(mtd);
573 unsigned long timeo = 400;
575 if (in_interrupt() || oops_in_progress)
576 return panic_nand_wait_ready(mtd, timeo);
578 /* Wait until command is processed or timeout occurs */
579 timeo = jiffies + msecs_to_jiffies(timeo);
581 if (chip->dev_ready(mtd))
584 } while (time_before(jiffies, timeo));
586 if (!chip->dev_ready(mtd))
587 pr_warn_ratelimited("timeout while waiting for chip to become ready\n");
589 EXPORT_SYMBOL_GPL(nand_wait_ready);
592 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
593 * @mtd: MTD device structure
594 * @timeo: Timeout in ms
596 * Wait for status ready (i.e. command done) or timeout.
598 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
600 register struct nand_chip *chip = mtd_to_nand(mtd);
602 timeo = jiffies + msecs_to_jiffies(timeo);
604 if ((chip->read_byte(mtd) & NAND_STATUS_READY))
606 touch_softlockup_watchdog();
607 } while (time_before(jiffies, timeo));
611 * nand_command - [DEFAULT] Send command to NAND device
612 * @mtd: MTD device structure
613 * @command: the command to be sent
614 * @column: the column address for this command, -1 if none
615 * @page_addr: the page address for this command, -1 if none
617 * Send command to NAND device. This function is used for small page devices
618 * (512 Bytes per page).
620 static void nand_command(struct mtd_info *mtd, unsigned int command,
621 int column, int page_addr)
623 register struct nand_chip *chip = mtd_to_nand(mtd);
624 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
626 /* Write out the command to the device */
627 if (command == NAND_CMD_SEQIN) {
630 if (column >= mtd->writesize) {
632 column -= mtd->writesize;
633 readcmd = NAND_CMD_READOOB;
634 } else if (column < 256) {
635 /* First 256 bytes --> READ0 */
636 readcmd = NAND_CMD_READ0;
639 readcmd = NAND_CMD_READ1;
641 chip->cmd_ctrl(mtd, readcmd, ctrl);
642 ctrl &= ~NAND_CTRL_CHANGE;
644 chip->cmd_ctrl(mtd, command, ctrl);
646 /* Address cycle, when necessary */
647 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
648 /* Serially input address */
650 /* Adjust columns for 16 bit buswidth */
651 if (chip->options & NAND_BUSWIDTH_16 &&
652 !nand_opcode_8bits(command))
654 chip->cmd_ctrl(mtd, column, ctrl);
655 ctrl &= ~NAND_CTRL_CHANGE;
657 if (page_addr != -1) {
658 chip->cmd_ctrl(mtd, page_addr, ctrl);
659 ctrl &= ~NAND_CTRL_CHANGE;
660 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
661 /* One more address cycle for devices > 32MiB */
662 if (chip->chipsize > (32 << 20))
663 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
665 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
668 * Program and erase have their own busy handlers status and sequential
673 case NAND_CMD_PAGEPROG:
674 case NAND_CMD_ERASE1:
675 case NAND_CMD_ERASE2:
677 case NAND_CMD_STATUS:
683 udelay(chip->chip_delay);
684 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
685 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
687 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
688 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
689 nand_wait_status_ready(mtd, 250);
692 /* This applies to read commands */
695 * If we don't have access to the busy pin, we apply the given
698 if (!chip->dev_ready) {
699 udelay(chip->chip_delay);
704 * Apply this short delay always to ensure that we do wait tWB in
705 * any case on any machine.
709 nand_wait_ready(mtd);
713 * nand_command_lp - [DEFAULT] Send command to NAND large page device
714 * @mtd: MTD device structure
715 * @command: the command to be sent
716 * @column: the column address for this command, -1 if none
717 * @page_addr: the page address for this command, -1 if none
719 * Send command to NAND device. This is the version for the new large page
720 * devices. We don't have the separate regions as we have in the small page
721 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
723 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
724 int column, int page_addr)
726 register struct nand_chip *chip = mtd_to_nand(mtd);
728 /* Emulate NAND_CMD_READOOB */
729 if (command == NAND_CMD_READOOB) {
730 column += mtd->writesize;
731 command = NAND_CMD_READ0;
734 /* Command latch cycle */
735 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
737 if (column != -1 || page_addr != -1) {
738 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
740 /* Serially input address */
742 /* Adjust columns for 16 bit buswidth */
743 if (chip->options & NAND_BUSWIDTH_16 &&
744 !nand_opcode_8bits(command))
746 chip->cmd_ctrl(mtd, column, ctrl);
747 ctrl &= ~NAND_CTRL_CHANGE;
749 /* Only output a single addr cycle for 8bits opcodes. */
750 if (!nand_opcode_8bits(command))
751 chip->cmd_ctrl(mtd, column >> 8, ctrl);
753 if (page_addr != -1) {
754 chip->cmd_ctrl(mtd, page_addr, ctrl);
755 chip->cmd_ctrl(mtd, page_addr >> 8,
756 NAND_NCE | NAND_ALE);
757 /* One more address cycle for devices > 128MiB */
758 if (chip->chipsize > (128 << 20))
759 chip->cmd_ctrl(mtd, page_addr >> 16,
760 NAND_NCE | NAND_ALE);
763 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
766 * Program and erase have their own busy handlers status, sequential
767 * in and status need no delay.
771 case NAND_CMD_CACHEDPROG:
772 case NAND_CMD_PAGEPROG:
773 case NAND_CMD_ERASE1:
774 case NAND_CMD_ERASE2:
777 case NAND_CMD_STATUS:
783 udelay(chip->chip_delay);
784 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
785 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
786 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
787 NAND_NCE | NAND_CTRL_CHANGE);
788 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
789 nand_wait_status_ready(mtd, 250);
792 case NAND_CMD_RNDOUT:
793 /* No ready / busy check necessary */
794 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
795 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
796 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
797 NAND_NCE | NAND_CTRL_CHANGE);
801 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
802 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
803 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
804 NAND_NCE | NAND_CTRL_CHANGE);
806 /* This applies to read commands */
809 * If we don't have access to the busy pin, we apply the given
812 if (!chip->dev_ready) {
813 udelay(chip->chip_delay);
819 * Apply this short delay always to ensure that we do wait tWB in
820 * any case on any machine.
824 nand_wait_ready(mtd);
828 * panic_nand_get_device - [GENERIC] Get chip for selected access
829 * @chip: the nand chip descriptor
830 * @mtd: MTD device structure
831 * @new_state: the state which is requested
833 * Used when in panic, no locks are taken.
835 static void panic_nand_get_device(struct nand_chip *chip,
836 struct mtd_info *mtd, int new_state)
838 /* Hardware controller shared among independent devices */
839 chip->controller->active = chip;
840 chip->state = new_state;
844 * nand_get_device - [GENERIC] Get chip for selected access
845 * @mtd: MTD device structure
846 * @new_state: the state which is requested
848 * Get the device and lock it for exclusive access
851 nand_get_device(struct mtd_info *mtd, int new_state)
853 struct nand_chip *chip = mtd_to_nand(mtd);
854 spinlock_t *lock = &chip->controller->lock;
855 wait_queue_head_t *wq = &chip->controller->wq;
856 DECLARE_WAITQUEUE(wait, current);
860 /* Hardware controller shared among independent devices */
861 if (!chip->controller->active)
862 chip->controller->active = chip;
864 if (chip->controller->active == chip && chip->state == FL_READY) {
865 chip->state = new_state;
869 if (new_state == FL_PM_SUSPENDED) {
870 if (chip->controller->active->state == FL_PM_SUSPENDED) {
871 chip->state = FL_PM_SUSPENDED;
876 set_current_state(TASK_UNINTERRUPTIBLE);
877 add_wait_queue(wq, &wait);
880 remove_wait_queue(wq, &wait);
885 * panic_nand_wait - [GENERIC] wait until the command is done
886 * @mtd: MTD device structure
887 * @chip: NAND chip structure
890 * Wait for command done. This is a helper function for nand_wait used when
891 * we are in interrupt context. May happen when in panic and trying to write
892 * an oops through mtdoops.
894 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
898 for (i = 0; i < timeo; i++) {
899 if (chip->dev_ready) {
900 if (chip->dev_ready(mtd))
903 if (chip->read_byte(mtd) & NAND_STATUS_READY)
911 * nand_wait - [DEFAULT] wait until the command is done
912 * @mtd: MTD device structure
913 * @chip: NAND chip structure
915 * Wait for command done. This applies to erase and program only.
917 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
921 unsigned long timeo = 400;
924 * Apply this short delay always to ensure that we do wait tWB in any
925 * case on any machine.
929 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
931 if (in_interrupt() || oops_in_progress)
932 panic_nand_wait(mtd, chip, timeo);
934 timeo = jiffies + msecs_to_jiffies(timeo);
936 if (chip->dev_ready) {
937 if (chip->dev_ready(mtd))
940 if (chip->read_byte(mtd) & NAND_STATUS_READY)
944 } while (time_before(jiffies, timeo));
947 status = (int)chip->read_byte(mtd);
948 /* This can happen if in case of timeout or buggy dev_ready */
949 WARN_ON(!(status & NAND_STATUS_READY));
954 * nand_reset_data_interface - Reset data interface and timings
955 * @chip: The NAND chip
957 * Reset the Data interface and timings to ONFI mode 0.
959 * Returns 0 for success or negative error code otherwise.
961 static int nand_reset_data_interface(struct nand_chip *chip)
963 struct mtd_info *mtd = nand_to_mtd(chip);
964 const struct nand_data_interface *conf;
967 if (!chip->setup_data_interface)
971 * The ONFI specification says:
973 * To transition from NV-DDR or NV-DDR2 to the SDR data
974 * interface, the host shall use the Reset (FFh) command
975 * using SDR timing mode 0. A device in any timing mode is
976 * required to recognize Reset (FFh) command issued in SDR
980 * Configure the data interface in SDR mode and set the
981 * timings to timing mode 0.
984 conf = nand_get_default_data_interface();
985 ret = chip->setup_data_interface(mtd, conf, false);
987 pr_err("Failed to configure data interface to SDR timing mode 0\n");
993 * nand_setup_data_interface - Setup the best data interface and timings
994 * @chip: The NAND chip
996 * Find and configure the best data interface and NAND timings supported by
997 * the chip and the driver.
998 * First tries to retrieve supported timing modes from ONFI information,
999 * and if the NAND chip does not support ONFI, relies on the
1000 * ->onfi_timing_mode_default specified in the nand_ids table.
1002 * Returns 0 for success or negative error code otherwise.
1004 static int nand_setup_data_interface(struct nand_chip *chip)
1006 struct mtd_info *mtd = nand_to_mtd(chip);
1009 if (!chip->setup_data_interface || !chip->data_interface)
1013 * Ensure the timing mode has been changed on the chip side
1014 * before changing timings on the controller side.
1016 if (chip->onfi_version) {
1017 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
1018 chip->onfi_timing_mode_default,
1021 ret = chip->onfi_set_features(mtd, chip,
1022 ONFI_FEATURE_ADDR_TIMING_MODE,
1028 ret = chip->setup_data_interface(mtd, chip->data_interface, false);
1034 * nand_init_data_interface - find the best data interface and timings
1035 * @chip: The NAND chip
1037 * Find the best data interface and NAND timings supported by the chip
1039 * First tries to retrieve supported timing modes from ONFI information,
1040 * and if the NAND chip does not support ONFI, relies on the
1041 * ->onfi_timing_mode_default specified in the nand_ids table. After this
1042 * function nand_chip->data_interface is initialized with the best timing mode
1045 * Returns 0 for success or negative error code otherwise.
1047 static int nand_init_data_interface(struct nand_chip *chip)
1049 struct mtd_info *mtd = nand_to_mtd(chip);
1050 int modes, mode, ret;
1052 if (!chip->setup_data_interface)
1056 * First try to identify the best timings from ONFI parameters and
1057 * if the NAND does not support ONFI, fallback to the default ONFI
1060 modes = onfi_get_async_timing_mode(chip);
1061 if (modes == ONFI_TIMING_MODE_UNKNOWN) {
1062 if (!chip->onfi_timing_mode_default)
1065 modes = GENMASK(chip->onfi_timing_mode_default, 0);
1068 chip->data_interface = kzalloc(sizeof(*chip->data_interface),
1070 if (!chip->data_interface)
1073 for (mode = fls(modes) - 1; mode >= 0; mode--) {
1074 ret = onfi_init_data_interface(chip, chip->data_interface,
1075 NAND_SDR_IFACE, mode);
1079 ret = chip->setup_data_interface(mtd, chip->data_interface,
1082 chip->onfi_timing_mode_default = mode;
1090 static void nand_release_data_interface(struct nand_chip *chip)
1092 kfree(chip->data_interface);
1096 * nand_reset - Reset and initialize a NAND device
1097 * @chip: The NAND chip
1098 * @chipnr: Internal die id
1100 * Returns 0 for success or negative error code otherwise
1102 int nand_reset(struct nand_chip *chip, int chipnr)
1104 struct mtd_info *mtd = nand_to_mtd(chip);
1107 ret = nand_reset_data_interface(chip);
1112 * The CS line has to be released before we can apply the new NAND
1113 * interface settings, hence this weird ->select_chip() dance.
1115 chip->select_chip(mtd, chipnr);
1116 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1117 chip->select_chip(mtd, -1);
1119 chip->select_chip(mtd, chipnr);
1120 ret = nand_setup_data_interface(chip);
1121 chip->select_chip(mtd, -1);
1129 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1131 * @ofs: offset to start unlock from
1132 * @len: length to unlock
1133 * @invert: when = 0, unlock the range of blocks within the lower and
1134 * upper boundary address
1135 * when = 1, unlock the range of blocks outside the boundaries
1136 * of the lower and upper boundary address
1138 * Returs unlock status.
1140 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1141 uint64_t len, int invert)
1145 struct nand_chip *chip = mtd_to_nand(mtd);
1147 /* Submit address of first page to unlock */
1148 page = ofs >> chip->page_shift;
1149 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1151 /* Submit address of last page to unlock */
1152 page = (ofs + len) >> chip->page_shift;
1153 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1154 (page | invert) & chip->pagemask);
1156 /* Call wait ready function */
1157 status = chip->waitfunc(mtd, chip);
1158 /* See if device thinks it succeeded */
1159 if (status & NAND_STATUS_FAIL) {
1160 pr_debug("%s: error status = 0x%08x\n",
1169 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1171 * @ofs: offset to start unlock from
1172 * @len: length to unlock
1174 * Returns unlock status.
1176 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1180 struct nand_chip *chip = mtd_to_nand(mtd);
1182 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1183 __func__, (unsigned long long)ofs, len);
1185 if (check_offs_len(mtd, ofs, len))
1188 /* Align to last block address if size addresses end of the device */
1189 if (ofs + len == mtd->size)
1190 len -= mtd->erasesize;
1192 nand_get_device(mtd, FL_UNLOCKING);
1194 /* Shift to get chip number */
1195 chipnr = ofs >> chip->chip_shift;
1199 * If we want to check the WP through READ STATUS and check the bit 7
1200 * we must reset the chip
1201 * some operation can also clear the bit 7 of status register
1202 * eg. erase/program a locked block
1204 nand_reset(chip, chipnr);
1206 chip->select_chip(mtd, chipnr);
1208 /* Check, if it is write protected */
1209 if (nand_check_wp(mtd)) {
1210 pr_debug("%s: device is write protected!\n",
1216 ret = __nand_unlock(mtd, ofs, len, 0);
1219 chip->select_chip(mtd, -1);
1220 nand_release_device(mtd);
1224 EXPORT_SYMBOL(nand_unlock);
1227 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1229 * @ofs: offset to start unlock from
1230 * @len: length to unlock
1232 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1233 * have this feature, but it allows only to lock all blocks, not for specified
1234 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1237 * Returns lock status.
1239 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1242 int chipnr, status, page;
1243 struct nand_chip *chip = mtd_to_nand(mtd);
1245 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1246 __func__, (unsigned long long)ofs, len);
1248 if (check_offs_len(mtd, ofs, len))
1251 nand_get_device(mtd, FL_LOCKING);
1253 /* Shift to get chip number */
1254 chipnr = ofs >> chip->chip_shift;
1258 * If we want to check the WP through READ STATUS and check the bit 7
1259 * we must reset the chip
1260 * some operation can also clear the bit 7 of status register
1261 * eg. erase/program a locked block
1263 nand_reset(chip, chipnr);
1265 chip->select_chip(mtd, chipnr);
1267 /* Check, if it is write protected */
1268 if (nand_check_wp(mtd)) {
1269 pr_debug("%s: device is write protected!\n",
1271 status = MTD_ERASE_FAILED;
1276 /* Submit address of first page to lock */
1277 page = ofs >> chip->page_shift;
1278 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1280 /* Call wait ready function */
1281 status = chip->waitfunc(mtd, chip);
1282 /* See if device thinks it succeeded */
1283 if (status & NAND_STATUS_FAIL) {
1284 pr_debug("%s: error status = 0x%08x\n",
1290 ret = __nand_unlock(mtd, ofs, len, 0x1);
1293 chip->select_chip(mtd, -1);
1294 nand_release_device(mtd);
1298 EXPORT_SYMBOL(nand_lock);
1301 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
1302 * @buf: buffer to test
1303 * @len: buffer length
1304 * @bitflips_threshold: maximum number of bitflips
1306 * Check if a buffer contains only 0xff, which means the underlying region
1307 * has been erased and is ready to be programmed.
1308 * The bitflips_threshold specify the maximum number of bitflips before
1309 * considering the region is not erased.
1310 * Note: The logic of this function has been extracted from the memweight
1311 * implementation, except that nand_check_erased_buf function exit before
1312 * testing the whole buffer if the number of bitflips exceed the
1313 * bitflips_threshold value.
1315 * Returns a positive number of bitflips less than or equal to
1316 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1319 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
1321 const unsigned char *bitmap = buf;
1325 for (; len && ((uintptr_t)bitmap) % sizeof(long);
1327 weight = hweight8(*bitmap);
1328 bitflips += BITS_PER_BYTE - weight;
1329 if (unlikely(bitflips > bitflips_threshold))
1333 for (; len >= sizeof(long);
1334 len -= sizeof(long), bitmap += sizeof(long)) {
1335 weight = hweight_long(*((unsigned long *)bitmap));
1336 bitflips += BITS_PER_LONG - weight;
1337 if (unlikely(bitflips > bitflips_threshold))
1341 for (; len > 0; len--, bitmap++) {
1342 weight = hweight8(*bitmap);
1343 bitflips += BITS_PER_BYTE - weight;
1344 if (unlikely(bitflips > bitflips_threshold))
1352 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
1354 * @data: data buffer to test
1355 * @datalen: data length
1357 * @ecclen: ECC length
1358 * @extraoob: extra OOB buffer
1359 * @extraooblen: extra OOB length
1360 * @bitflips_threshold: maximum number of bitflips
1362 * Check if a data buffer and its associated ECC and OOB data contains only
1363 * 0xff pattern, which means the underlying region has been erased and is
1364 * ready to be programmed.
1365 * The bitflips_threshold specify the maximum number of bitflips before
1366 * considering the region as not erased.
1369 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
1370 * different from the NAND page size. When fixing bitflips, ECC engines will
1371 * report the number of errors per chunk, and the NAND core infrastructure
1372 * expect you to return the maximum number of bitflips for the whole page.
1373 * This is why you should always use this function on a single chunk and
1374 * not on the whole page. After checking each chunk you should update your
1375 * max_bitflips value accordingly.
1376 * 2/ When checking for bitflips in erased pages you should not only check
1377 * the payload data but also their associated ECC data, because a user might
1378 * have programmed almost all bits to 1 but a few. In this case, we
1379 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
1381 * 3/ The extraoob argument is optional, and should be used if some of your OOB
1382 * data are protected by the ECC engine.
1383 * It could also be used if you support subpages and want to attach some
1384 * extra OOB data to an ECC chunk.
1386 * Returns a positive number of bitflips less than or equal to
1387 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
1388 * threshold. In case of success, the passed buffers are filled with 0xff.
1390 int nand_check_erased_ecc_chunk(void *data, int datalen,
1391 void *ecc, int ecclen,
1392 void *extraoob, int extraooblen,
1393 int bitflips_threshold)
1395 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
1397 data_bitflips = nand_check_erased_buf(data, datalen,
1398 bitflips_threshold);
1399 if (data_bitflips < 0)
1400 return data_bitflips;
1402 bitflips_threshold -= data_bitflips;
1404 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
1405 if (ecc_bitflips < 0)
1406 return ecc_bitflips;
1408 bitflips_threshold -= ecc_bitflips;
1410 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
1411 bitflips_threshold);
1412 if (extraoob_bitflips < 0)
1413 return extraoob_bitflips;
1416 memset(data, 0xff, datalen);
1419 memset(ecc, 0xff, ecclen);
1421 if (extraoob_bitflips)
1422 memset(extraoob, 0xff, extraooblen);
1424 return data_bitflips + ecc_bitflips + extraoob_bitflips;
1426 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
1429 * nand_read_page_raw - [INTERN] read raw page data without ecc
1430 * @mtd: mtd info structure
1431 * @chip: nand chip info structure
1432 * @buf: buffer to store read data
1433 * @oob_required: caller requires OOB data read to chip->oob_poi
1434 * @page: page number to read
1436 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1438 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1439 uint8_t *buf, int oob_required, int page)
1441 chip->read_buf(mtd, buf, mtd->writesize);
1443 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1448 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1449 * @mtd: mtd info structure
1450 * @chip: nand chip info structure
1451 * @buf: buffer to store read data
1452 * @oob_required: caller requires OOB data read to chip->oob_poi
1453 * @page: page number to read
1455 * We need a special oob layout and handling even when OOB isn't used.
1457 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1458 struct nand_chip *chip, uint8_t *buf,
1459 int oob_required, int page)
1461 int eccsize = chip->ecc.size;
1462 int eccbytes = chip->ecc.bytes;
1463 uint8_t *oob = chip->oob_poi;
1466 for (steps = chip->ecc.steps; steps > 0; steps--) {
1467 chip->read_buf(mtd, buf, eccsize);
1470 if (chip->ecc.prepad) {
1471 chip->read_buf(mtd, oob, chip->ecc.prepad);
1472 oob += chip->ecc.prepad;
1475 chip->read_buf(mtd, oob, eccbytes);
1478 if (chip->ecc.postpad) {
1479 chip->read_buf(mtd, oob, chip->ecc.postpad);
1480 oob += chip->ecc.postpad;
1484 size = mtd->oobsize - (oob - chip->oob_poi);
1486 chip->read_buf(mtd, oob, size);
1492 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1493 * @mtd: mtd info structure
1494 * @chip: nand chip info structure
1495 * @buf: buffer to store read data
1496 * @oob_required: caller requires OOB data read to chip->oob_poi
1497 * @page: page number to read
1499 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1500 uint8_t *buf, int oob_required, int page)
1502 int i, eccsize = chip->ecc.size, ret;
1503 int eccbytes = chip->ecc.bytes;
1504 int eccsteps = chip->ecc.steps;
1506 uint8_t *ecc_calc = chip->buffers->ecccalc;
1507 uint8_t *ecc_code = chip->buffers->ecccode;
1508 unsigned int max_bitflips = 0;
1510 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1512 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1513 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1515 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1520 eccsteps = chip->ecc.steps;
1523 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1526 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1528 mtd->ecc_stats.failed++;
1530 mtd->ecc_stats.corrected += stat;
1531 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1534 return max_bitflips;
1538 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1539 * @mtd: mtd info structure
1540 * @chip: nand chip info structure
1541 * @data_offs: offset of requested data within the page
1542 * @readlen: data length
1543 * @bufpoi: buffer to store read data
1544 * @page: page number to read
1546 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1547 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1550 int start_step, end_step, num_steps, ret;
1552 int data_col_addr, i, gaps = 0;
1553 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1554 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1555 int index, section = 0;
1556 unsigned int max_bitflips = 0;
1557 struct mtd_oob_region oobregion = { };
1559 /* Column address within the page aligned to ECC size (256bytes) */
1560 start_step = data_offs / chip->ecc.size;
1561 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1562 num_steps = end_step - start_step + 1;
1563 index = start_step * chip->ecc.bytes;
1565 /* Data size aligned to ECC ecc.size */
1566 datafrag_len = num_steps * chip->ecc.size;
1567 eccfrag_len = num_steps * chip->ecc.bytes;
1569 data_col_addr = start_step * chip->ecc.size;
1570 /* If we read not a page aligned data */
1571 if (data_col_addr != 0)
1572 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1574 p = bufpoi + data_col_addr;
1575 chip->read_buf(mtd, p, datafrag_len);
1578 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1579 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1582 * The performance is faster if we position offsets according to
1583 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1585 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion);
1589 if (oobregion.length < eccfrag_len)
1593 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1594 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1597 * Send the command to read the particular ECC bytes take care
1598 * about buswidth alignment in read_buf.
1600 aligned_pos = oobregion.offset & ~(busw - 1);
1601 aligned_len = eccfrag_len;
1602 if (oobregion.offset & (busw - 1))
1604 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
1608 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1609 mtd->writesize + aligned_pos, -1);
1610 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1613 ret = mtd_ooblayout_get_eccbytes(mtd, chip->buffers->ecccode,
1614 chip->oob_poi, index, eccfrag_len);
1618 p = bufpoi + data_col_addr;
1619 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1622 stat = chip->ecc.correct(mtd, p,
1623 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1624 if (stat == -EBADMSG &&
1625 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1626 /* check for empty pages with bitflips */
1627 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1628 &chip->buffers->ecccode[i],
1631 chip->ecc.strength);
1635 mtd->ecc_stats.failed++;
1637 mtd->ecc_stats.corrected += stat;
1638 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1641 return max_bitflips;
1645 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1646 * @mtd: mtd info structure
1647 * @chip: nand chip info structure
1648 * @buf: buffer to store read data
1649 * @oob_required: caller requires OOB data read to chip->oob_poi
1650 * @page: page number to read
1652 * Not for syndrome calculating ECC controllers which need a special oob layout.
1654 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1655 uint8_t *buf, int oob_required, int page)
1657 int i, eccsize = chip->ecc.size, ret;
1658 int eccbytes = chip->ecc.bytes;
1659 int eccsteps = chip->ecc.steps;
1661 uint8_t *ecc_calc = chip->buffers->ecccalc;
1662 uint8_t *ecc_code = chip->buffers->ecccode;
1663 unsigned int max_bitflips = 0;
1665 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1666 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1667 chip->read_buf(mtd, p, eccsize);
1668 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1670 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1672 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1677 eccsteps = chip->ecc.steps;
1680 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1683 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1684 if (stat == -EBADMSG &&
1685 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1686 /* check for empty pages with bitflips */
1687 stat = nand_check_erased_ecc_chunk(p, eccsize,
1688 &ecc_code[i], eccbytes,
1690 chip->ecc.strength);
1694 mtd->ecc_stats.failed++;
1696 mtd->ecc_stats.corrected += stat;
1697 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1700 return max_bitflips;
1704 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1705 * @mtd: mtd info structure
1706 * @chip: nand chip info structure
1707 * @buf: buffer to store read data
1708 * @oob_required: caller requires OOB data read to chip->oob_poi
1709 * @page: page number to read
1711 * Hardware ECC for large page chips, require OOB to be read first. For this
1712 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1713 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1714 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1715 * the data area, by overwriting the NAND manufacturer bad block markings.
1717 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1718 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1720 int i, eccsize = chip->ecc.size, ret;
1721 int eccbytes = chip->ecc.bytes;
1722 int eccsteps = chip->ecc.steps;
1724 uint8_t *ecc_code = chip->buffers->ecccode;
1725 uint8_t *ecc_calc = chip->buffers->ecccalc;
1726 unsigned int max_bitflips = 0;
1728 /* Read the OOB area first */
1729 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1730 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1731 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1733 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
1738 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1741 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1742 chip->read_buf(mtd, p, eccsize);
1743 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1745 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1746 if (stat == -EBADMSG &&
1747 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1748 /* check for empty pages with bitflips */
1749 stat = nand_check_erased_ecc_chunk(p, eccsize,
1750 &ecc_code[i], eccbytes,
1752 chip->ecc.strength);
1756 mtd->ecc_stats.failed++;
1758 mtd->ecc_stats.corrected += stat;
1759 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1762 return max_bitflips;
1766 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1767 * @mtd: mtd info structure
1768 * @chip: nand chip info structure
1769 * @buf: buffer to store read data
1770 * @oob_required: caller requires OOB data read to chip->oob_poi
1771 * @page: page number to read
1773 * The hw generator calculates the error syndrome automatically. Therefore we
1774 * need a special oob layout and handling.
1776 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1777 uint8_t *buf, int oob_required, int page)
1779 int i, eccsize = chip->ecc.size;
1780 int eccbytes = chip->ecc.bytes;
1781 int eccsteps = chip->ecc.steps;
1782 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
1784 uint8_t *oob = chip->oob_poi;
1785 unsigned int max_bitflips = 0;
1787 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1790 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1791 chip->read_buf(mtd, p, eccsize);
1793 if (chip->ecc.prepad) {
1794 chip->read_buf(mtd, oob, chip->ecc.prepad);
1795 oob += chip->ecc.prepad;
1798 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1799 chip->read_buf(mtd, oob, eccbytes);
1800 stat = chip->ecc.correct(mtd, p, oob, NULL);
1804 if (chip->ecc.postpad) {
1805 chip->read_buf(mtd, oob, chip->ecc.postpad);
1806 oob += chip->ecc.postpad;
1809 if (stat == -EBADMSG &&
1810 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
1811 /* check for empty pages with bitflips */
1812 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
1816 chip->ecc.strength);
1820 mtd->ecc_stats.failed++;
1822 mtd->ecc_stats.corrected += stat;
1823 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1827 /* Calculate remaining oob bytes */
1828 i = mtd->oobsize - (oob - chip->oob_poi);
1830 chip->read_buf(mtd, oob, i);
1832 return max_bitflips;
1836 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1837 * @mtd: mtd info structure
1838 * @oob: oob destination address
1839 * @ops: oob ops structure
1840 * @len: size of oob to transfer
1842 static uint8_t *nand_transfer_oob(struct mtd_info *mtd, uint8_t *oob,
1843 struct mtd_oob_ops *ops, size_t len)
1845 struct nand_chip *chip = mtd_to_nand(mtd);
1848 switch (ops->mode) {
1850 case MTD_OPS_PLACE_OOB:
1852 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1855 case MTD_OPS_AUTO_OOB:
1856 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
1868 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1869 * @mtd: MTD device structure
1870 * @retry_mode: the retry mode to use
1872 * Some vendors supply a special command to shift the Vt threshold, to be used
1873 * when there are too many bitflips in a page (i.e., ECC error). After setting
1874 * a new threshold, the host should retry reading the page.
1876 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1878 struct nand_chip *chip = mtd_to_nand(mtd);
1880 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1882 if (retry_mode >= chip->read_retries)
1885 if (!chip->setup_read_retry)
1888 return chip->setup_read_retry(mtd, retry_mode);
1892 * nand_do_read_ops - [INTERN] Read data with ECC
1893 * @mtd: MTD device structure
1894 * @from: offset to read from
1895 * @ops: oob ops structure
1897 * Internal function. Called with chip held.
1899 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1900 struct mtd_oob_ops *ops)
1902 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1903 struct nand_chip *chip = mtd_to_nand(mtd);
1905 uint32_t readlen = ops->len;
1906 uint32_t oobreadlen = ops->ooblen;
1907 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
1909 uint8_t *bufpoi, *oob, *buf;
1911 unsigned int max_bitflips = 0;
1913 bool ecc_fail = false;
1915 chipnr = (int)(from >> chip->chip_shift);
1916 chip->select_chip(mtd, chipnr);
1918 realpage = (int)(from >> chip->page_shift);
1919 page = realpage & chip->pagemask;
1921 col = (int)(from & (mtd->writesize - 1));
1925 oob_required = oob ? 1 : 0;
1928 unsigned int ecc_failures = mtd->ecc_stats.failed;
1930 bytes = min(mtd->writesize - col, readlen);
1931 aligned = (bytes == mtd->writesize);
1935 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
1936 use_bufpoi = !virt_addr_valid(buf);
1940 /* Is the current page in the buffer? */
1941 if (realpage != chip->pagebuf || oob) {
1942 bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
1944 if (use_bufpoi && aligned)
1945 pr_debug("%s: using read bounce buffer for buf@%p\n",
1949 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1952 * Now read the page into the buffer. Absent an error,
1953 * the read methods return max bitflips per ecc step.
1955 if (unlikely(ops->mode == MTD_OPS_RAW))
1956 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1959 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1961 ret = chip->ecc.read_subpage(mtd, chip,
1965 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1966 oob_required, page);
1969 /* Invalidate page cache */
1974 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1976 /* Transfer not aligned data */
1978 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1979 !(mtd->ecc_stats.failed - ecc_failures) &&
1980 (ops->mode != MTD_OPS_RAW)) {
1981 chip->pagebuf = realpage;
1982 chip->pagebuf_bitflips = ret;
1984 /* Invalidate page cache */
1987 memcpy(buf, chip->buffers->databuf + col, bytes);
1990 if (unlikely(oob)) {
1991 int toread = min(oobreadlen, max_oobsize);
1994 oob = nand_transfer_oob(mtd,
1996 oobreadlen -= toread;
2000 if (chip->options & NAND_NEED_READRDY) {
2001 /* Apply delay or wait for ready/busy pin */
2002 if (!chip->dev_ready)
2003 udelay(chip->chip_delay);
2005 nand_wait_ready(mtd);
2008 if (mtd->ecc_stats.failed - ecc_failures) {
2009 if (retry_mode + 1 < chip->read_retries) {
2011 ret = nand_setup_read_retry(mtd,
2016 /* Reset failures; retry */
2017 mtd->ecc_stats.failed = ecc_failures;
2020 /* No more retry modes; real failure */
2027 memcpy(buf, chip->buffers->databuf + col, bytes);
2029 max_bitflips = max_t(unsigned int, max_bitflips,
2030 chip->pagebuf_bitflips);
2035 /* Reset to retry mode 0 */
2037 ret = nand_setup_read_retry(mtd, 0);
2046 /* For subsequent reads align to page boundary */
2048 /* Increment page address */
2051 page = realpage & chip->pagemask;
2052 /* Check, if we cross a chip boundary */
2055 chip->select_chip(mtd, -1);
2056 chip->select_chip(mtd, chipnr);
2059 chip->select_chip(mtd, -1);
2061 ops->retlen = ops->len - (size_t) readlen;
2063 ops->oobretlen = ops->ooblen - oobreadlen;
2071 return max_bitflips;
2075 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
2076 * @mtd: MTD device structure
2077 * @from: offset to read from
2078 * @len: number of bytes to read
2079 * @retlen: pointer to variable to store the number of read bytes
2080 * @buf: the databuffer to put data
2082 * Get hold of the chip and call nand_do_read.
2084 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
2085 size_t *retlen, uint8_t *buf)
2087 struct mtd_oob_ops ops;
2090 nand_get_device(mtd, FL_READING);
2091 memset(&ops, 0, sizeof(ops));
2094 ops.mode = MTD_OPS_PLACE_OOB;
2095 ret = nand_do_read_ops(mtd, from, &ops);
2096 *retlen = ops.retlen;
2097 nand_release_device(mtd);
2102 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
2103 * @mtd: mtd info structure
2104 * @chip: nand chip info structure
2105 * @page: page number to read
2107 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
2109 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
2110 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
2113 EXPORT_SYMBOL(nand_read_oob_std);
2116 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
2118 * @mtd: mtd info structure
2119 * @chip: nand chip info structure
2120 * @page: page number to read
2122 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2125 int length = mtd->oobsize;
2126 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2127 int eccsize = chip->ecc.size;
2128 uint8_t *bufpoi = chip->oob_poi;
2129 int i, toread, sndrnd = 0, pos;
2131 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
2132 for (i = 0; i < chip->ecc.steps; i++) {
2134 pos = eccsize + i * (eccsize + chunk);
2135 if (mtd->writesize > 512)
2136 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
2138 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
2141 toread = min_t(int, length, chunk);
2142 chip->read_buf(mtd, bufpoi, toread);
2147 chip->read_buf(mtd, bufpoi, length);
2151 EXPORT_SYMBOL(nand_read_oob_syndrome);
2154 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
2155 * @mtd: mtd info structure
2156 * @chip: nand chip info structure
2157 * @page: page number to write
2159 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page)
2162 const uint8_t *buf = chip->oob_poi;
2163 int length = mtd->oobsize;
2165 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
2166 chip->write_buf(mtd, buf, length);
2167 /* Send command to program the OOB data */
2168 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2170 status = chip->waitfunc(mtd, chip);
2172 return status & NAND_STATUS_FAIL ? -EIO : 0;
2174 EXPORT_SYMBOL(nand_write_oob_std);
2177 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
2178 * with syndrome - only for large page flash
2179 * @mtd: mtd info structure
2180 * @chip: nand chip info structure
2181 * @page: page number to write
2183 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
2186 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
2187 int eccsize = chip->ecc.size, length = mtd->oobsize;
2188 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
2189 const uint8_t *bufpoi = chip->oob_poi;
2192 * data-ecc-data-ecc ... ecc-oob
2194 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
2196 if (!chip->ecc.prepad && !chip->ecc.postpad) {
2197 pos = steps * (eccsize + chunk);
2202 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
2203 for (i = 0; i < steps; i++) {
2205 if (mtd->writesize <= 512) {
2206 uint32_t fill = 0xFFFFFFFF;
2210 int num = min_t(int, len, 4);
2211 chip->write_buf(mtd, (uint8_t *)&fill,
2216 pos = eccsize + i * (eccsize + chunk);
2217 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
2221 len = min_t(int, length, chunk);
2222 chip->write_buf(mtd, bufpoi, len);
2227 chip->write_buf(mtd, bufpoi, length);
2229 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2230 status = chip->waitfunc(mtd, chip);
2232 return status & NAND_STATUS_FAIL ? -EIO : 0;
2234 EXPORT_SYMBOL(nand_write_oob_syndrome);
2237 * nand_do_read_oob - [INTERN] NAND read out-of-band
2238 * @mtd: MTD device structure
2239 * @from: offset to read from
2240 * @ops: oob operations description structure
2242 * NAND read out-of-band data from the spare area.
2244 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2245 struct mtd_oob_ops *ops)
2247 int page, realpage, chipnr;
2248 struct nand_chip *chip = mtd_to_nand(mtd);
2249 struct mtd_ecc_stats stats;
2250 int readlen = ops->ooblen;
2252 uint8_t *buf = ops->oobbuf;
2255 pr_debug("%s: from = 0x%08Lx, len = %i\n",
2256 __func__, (unsigned long long)from, readlen);
2258 stats = mtd->ecc_stats;
2260 len = mtd_oobavail(mtd, ops);
2262 if (unlikely(ops->ooboffs >= len)) {
2263 pr_debug("%s: attempt to start read outside oob\n",
2268 /* Do not allow reads past end of device */
2269 if (unlikely(from >= mtd->size ||
2270 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2271 (from >> chip->page_shift)) * len)) {
2272 pr_debug("%s: attempt to read beyond end of device\n",
2277 chipnr = (int)(from >> chip->chip_shift);
2278 chip->select_chip(mtd, chipnr);
2280 /* Shift to get page */
2281 realpage = (int)(from >> chip->page_shift);
2282 page = realpage & chip->pagemask;
2285 if (ops->mode == MTD_OPS_RAW)
2286 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2288 ret = chip->ecc.read_oob(mtd, chip, page);
2293 len = min(len, readlen);
2294 buf = nand_transfer_oob(mtd, buf, ops, len);
2296 if (chip->options & NAND_NEED_READRDY) {
2297 /* Apply delay or wait for ready/busy pin */
2298 if (!chip->dev_ready)
2299 udelay(chip->chip_delay);
2301 nand_wait_ready(mtd);
2308 /* Increment page address */
2311 page = realpage & chip->pagemask;
2312 /* Check, if we cross a chip boundary */
2315 chip->select_chip(mtd, -1);
2316 chip->select_chip(mtd, chipnr);
2319 chip->select_chip(mtd, -1);
2321 ops->oobretlen = ops->ooblen - readlen;
2326 if (mtd->ecc_stats.failed - stats.failed)
2329 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2333 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2334 * @mtd: MTD device structure
2335 * @from: offset to read from
2336 * @ops: oob operation description structure
2338 * NAND read data and/or out-of-band data.
2340 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2341 struct mtd_oob_ops *ops)
2347 /* Do not allow reads past end of device */
2348 if (ops->datbuf && (from + ops->len) > mtd->size) {
2349 pr_debug("%s: attempt to read beyond end of device\n",
2354 if (ops->mode != MTD_OPS_PLACE_OOB &&
2355 ops->mode != MTD_OPS_AUTO_OOB &&
2356 ops->mode != MTD_OPS_RAW)
2359 nand_get_device(mtd, FL_READING);
2362 ret = nand_do_read_oob(mtd, from, ops);
2364 ret = nand_do_read_ops(mtd, from, ops);
2366 nand_release_device(mtd);
2372 * nand_write_page_raw - [INTERN] raw page write function
2373 * @mtd: mtd info structure
2374 * @chip: nand chip info structure
2376 * @oob_required: must write chip->oob_poi to OOB
2377 * @page: page number to write
2379 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2381 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2382 const uint8_t *buf, int oob_required, int page)
2384 chip->write_buf(mtd, buf, mtd->writesize);
2386 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2392 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2393 * @mtd: mtd info structure
2394 * @chip: nand chip info structure
2396 * @oob_required: must write chip->oob_poi to OOB
2397 * @page: page number to write
2399 * We need a special oob layout and handling even when ECC isn't checked.
2401 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2402 struct nand_chip *chip,
2403 const uint8_t *buf, int oob_required,
2406 int eccsize = chip->ecc.size;
2407 int eccbytes = chip->ecc.bytes;
2408 uint8_t *oob = chip->oob_poi;
2411 for (steps = chip->ecc.steps; steps > 0; steps--) {
2412 chip->write_buf(mtd, buf, eccsize);
2415 if (chip->ecc.prepad) {
2416 chip->write_buf(mtd, oob, chip->ecc.prepad);
2417 oob += chip->ecc.prepad;
2420 chip->write_buf(mtd, oob, eccbytes);
2423 if (chip->ecc.postpad) {
2424 chip->write_buf(mtd, oob, chip->ecc.postpad);
2425 oob += chip->ecc.postpad;
2429 size = mtd->oobsize - (oob - chip->oob_poi);
2431 chip->write_buf(mtd, oob, size);
2436 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2437 * @mtd: mtd info structure
2438 * @chip: nand chip info structure
2440 * @oob_required: must write chip->oob_poi to OOB
2441 * @page: page number to write
2443 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2444 const uint8_t *buf, int oob_required,
2447 int i, eccsize = chip->ecc.size, ret;
2448 int eccbytes = chip->ecc.bytes;
2449 int eccsteps = chip->ecc.steps;
2450 uint8_t *ecc_calc = chip->buffers->ecccalc;
2451 const uint8_t *p = buf;
2453 /* Software ECC calculation */
2454 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2455 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2457 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2462 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
2466 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2467 * @mtd: mtd info structure
2468 * @chip: nand chip info structure
2470 * @oob_required: must write chip->oob_poi to OOB
2471 * @page: page number to write
2473 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2474 const uint8_t *buf, int oob_required,
2477 int i, eccsize = chip->ecc.size, ret;
2478 int eccbytes = chip->ecc.bytes;
2479 int eccsteps = chip->ecc.steps;
2480 uint8_t *ecc_calc = chip->buffers->ecccalc;
2481 const uint8_t *p = buf;
2483 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2484 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2485 chip->write_buf(mtd, p, eccsize);
2486 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2489 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2494 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2501 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
2502 * @mtd: mtd info structure
2503 * @chip: nand chip info structure
2504 * @offset: column address of subpage within the page
2505 * @data_len: data length
2507 * @oob_required: must write chip->oob_poi to OOB
2508 * @page: page number to write
2510 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2511 struct nand_chip *chip, uint32_t offset,
2512 uint32_t data_len, const uint8_t *buf,
2513 int oob_required, int page)
2515 uint8_t *oob_buf = chip->oob_poi;
2516 uint8_t *ecc_calc = chip->buffers->ecccalc;
2517 int ecc_size = chip->ecc.size;
2518 int ecc_bytes = chip->ecc.bytes;
2519 int ecc_steps = chip->ecc.steps;
2520 uint32_t start_step = offset / ecc_size;
2521 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2522 int oob_bytes = mtd->oobsize / ecc_steps;
2525 for (step = 0; step < ecc_steps; step++) {
2526 /* configure controller for WRITE access */
2527 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2529 /* write data (untouched subpages already masked by 0xFF) */
2530 chip->write_buf(mtd, buf, ecc_size);
2532 /* mask ECC of un-touched subpages by padding 0xFF */
2533 if ((step < start_step) || (step > end_step))
2534 memset(ecc_calc, 0xff, ecc_bytes);
2536 chip->ecc.calculate(mtd, buf, ecc_calc);
2538 /* mask OOB of un-touched subpages by padding 0xFF */
2539 /* if oob_required, preserve OOB metadata of written subpage */
2540 if (!oob_required || (step < start_step) || (step > end_step))
2541 memset(oob_buf, 0xff, oob_bytes);
2544 ecc_calc += ecc_bytes;
2545 oob_buf += oob_bytes;
2548 /* copy calculated ECC for whole page to chip->buffer->oob */
2549 /* this include masked-value(0xFF) for unwritten subpages */
2550 ecc_calc = chip->buffers->ecccalc;
2551 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
2556 /* write OOB buffer to NAND device */
2557 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2564 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2565 * @mtd: mtd info structure
2566 * @chip: nand chip info structure
2568 * @oob_required: must write chip->oob_poi to OOB
2569 * @page: page number to write
2571 * The hw generator calculates the error syndrome automatically. Therefore we
2572 * need a special oob layout and handling.
2574 static int nand_write_page_syndrome(struct mtd_info *mtd,
2575 struct nand_chip *chip,
2576 const uint8_t *buf, int oob_required,
2579 int i, eccsize = chip->ecc.size;
2580 int eccbytes = chip->ecc.bytes;
2581 int eccsteps = chip->ecc.steps;
2582 const uint8_t *p = buf;
2583 uint8_t *oob = chip->oob_poi;
2585 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2587 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2588 chip->write_buf(mtd, p, eccsize);
2590 if (chip->ecc.prepad) {
2591 chip->write_buf(mtd, oob, chip->ecc.prepad);
2592 oob += chip->ecc.prepad;
2595 chip->ecc.calculate(mtd, p, oob);
2596 chip->write_buf(mtd, oob, eccbytes);
2599 if (chip->ecc.postpad) {
2600 chip->write_buf(mtd, oob, chip->ecc.postpad);
2601 oob += chip->ecc.postpad;
2605 /* Calculate remaining oob bytes */
2606 i = mtd->oobsize - (oob - chip->oob_poi);
2608 chip->write_buf(mtd, oob, i);
2614 * nand_write_page - [REPLACEABLE] write one page
2615 * @mtd: MTD device structure
2616 * @chip: NAND chip descriptor
2617 * @offset: address offset within the page
2618 * @data_len: length of actual data to be written
2619 * @buf: the data to write
2620 * @oob_required: must write chip->oob_poi to OOB
2621 * @page: page number to write
2622 * @cached: cached programming
2623 * @raw: use _raw version of write_page
2625 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2626 uint32_t offset, int data_len, const uint8_t *buf,
2627 int oob_required, int page, int cached, int raw)
2629 int status, subpage;
2631 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2632 chip->ecc.write_subpage)
2633 subpage = offset || (data_len < mtd->writesize);
2637 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2640 status = chip->ecc.write_page_raw(mtd, chip, buf,
2641 oob_required, page);
2643 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2644 buf, oob_required, page);
2646 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2653 * Cached progamming disabled for now. Not sure if it's worth the
2654 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2658 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2660 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2661 status = chip->waitfunc(mtd, chip);
2663 * See if operation failed and additional status checks are
2666 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2667 status = chip->errstat(mtd, chip, FL_WRITING, status,
2670 if (status & NAND_STATUS_FAIL)
2673 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2674 status = chip->waitfunc(mtd, chip);
2681 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2682 * @mtd: MTD device structure
2683 * @oob: oob data buffer
2684 * @len: oob data write length
2685 * @ops: oob ops structure
2687 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2688 struct mtd_oob_ops *ops)
2690 struct nand_chip *chip = mtd_to_nand(mtd);
2694 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2695 * data from a previous OOB read.
2697 memset(chip->oob_poi, 0xff, mtd->oobsize);
2699 switch (ops->mode) {
2701 case MTD_OPS_PLACE_OOB:
2703 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2706 case MTD_OPS_AUTO_OOB:
2707 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
2718 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2721 * nand_do_write_ops - [INTERN] NAND write with ECC
2722 * @mtd: MTD device structure
2723 * @to: offset to write to
2724 * @ops: oob operations description structure
2726 * NAND write with ECC.
2728 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2729 struct mtd_oob_ops *ops)
2731 int chipnr, realpage, page, blockmask, column;
2732 struct nand_chip *chip = mtd_to_nand(mtd);
2733 uint32_t writelen = ops->len;
2735 uint32_t oobwritelen = ops->ooblen;
2736 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
2738 uint8_t *oob = ops->oobbuf;
2739 uint8_t *buf = ops->datbuf;
2741 int oob_required = oob ? 1 : 0;
2747 /* Reject writes, which are not page aligned */
2748 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2749 pr_notice("%s: attempt to write non page aligned data\n",
2754 column = to & (mtd->writesize - 1);
2756 chipnr = (int)(to >> chip->chip_shift);
2757 chip->select_chip(mtd, chipnr);
2759 /* Check, if it is write protected */
2760 if (nand_check_wp(mtd)) {
2765 realpage = (int)(to >> chip->page_shift);
2766 page = realpage & chip->pagemask;
2767 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2769 /* Invalidate the page cache, when we write to the cached page */
2770 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
2771 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
2774 /* Don't allow multipage oob writes with offset */
2775 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2781 int bytes = mtd->writesize;
2782 int cached = writelen > bytes && page != blockmask;
2783 uint8_t *wbuf = buf;
2785 int part_pagewr = (column || writelen < mtd->writesize);
2789 else if (chip->options & NAND_USE_BOUNCE_BUFFER)
2790 use_bufpoi = !virt_addr_valid(buf);
2794 /* Partial page write?, or need to use bounce buffer */
2796 pr_debug("%s: using write bounce buffer for buf@%p\n",
2800 bytes = min_t(int, bytes - column, writelen);
2802 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2803 memcpy(&chip->buffers->databuf[column], buf, bytes);
2804 wbuf = chip->buffers->databuf;
2807 if (unlikely(oob)) {
2808 size_t len = min(oobwritelen, oobmaxlen);
2809 oob = nand_fill_oob(mtd, oob, len, ops);
2812 /* We still need to erase leftover OOB data */
2813 memset(chip->oob_poi, 0xff, mtd->oobsize);
2815 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2816 oob_required, page, cached,
2817 (ops->mode == MTD_OPS_RAW));
2829 page = realpage & chip->pagemask;
2830 /* Check, if we cross a chip boundary */
2833 chip->select_chip(mtd, -1);
2834 chip->select_chip(mtd, chipnr);
2838 ops->retlen = ops->len - writelen;
2840 ops->oobretlen = ops->ooblen;
2843 chip->select_chip(mtd, -1);
2848 * panic_nand_write - [MTD Interface] NAND write with ECC
2849 * @mtd: MTD device structure
2850 * @to: offset to write to
2851 * @len: number of bytes to write
2852 * @retlen: pointer to variable to store the number of written bytes
2853 * @buf: the data to write
2855 * NAND write with ECC. Used when performing writes in interrupt context, this
2856 * may for example be called by mtdoops when writing an oops while in panic.
2858 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2859 size_t *retlen, const uint8_t *buf)
2861 struct nand_chip *chip = mtd_to_nand(mtd);
2862 struct mtd_oob_ops ops;
2865 /* Wait for the device to get ready */
2866 panic_nand_wait(mtd, chip, 400);
2868 /* Grab the device */
2869 panic_nand_get_device(chip, mtd, FL_WRITING);
2871 memset(&ops, 0, sizeof(ops));
2873 ops.datbuf = (uint8_t *)buf;
2874 ops.mode = MTD_OPS_PLACE_OOB;
2876 ret = nand_do_write_ops(mtd, to, &ops);
2878 *retlen = ops.retlen;
2883 * nand_write - [MTD Interface] NAND write with ECC
2884 * @mtd: MTD device structure
2885 * @to: offset to write to
2886 * @len: number of bytes to write
2887 * @retlen: pointer to variable to store the number of written bytes
2888 * @buf: the data to write
2890 * NAND write with ECC.
2892 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2893 size_t *retlen, const uint8_t *buf)
2895 struct mtd_oob_ops ops;
2898 nand_get_device(mtd, FL_WRITING);
2899 memset(&ops, 0, sizeof(ops));
2901 ops.datbuf = (uint8_t *)buf;
2902 ops.mode = MTD_OPS_PLACE_OOB;
2903 ret = nand_do_write_ops(mtd, to, &ops);
2904 *retlen = ops.retlen;
2905 nand_release_device(mtd);
2910 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2911 * @mtd: MTD device structure
2912 * @to: offset to write to
2913 * @ops: oob operation description structure
2915 * NAND write out-of-band.
2917 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2918 struct mtd_oob_ops *ops)
2920 int chipnr, page, status, len;
2921 struct nand_chip *chip = mtd_to_nand(mtd);
2923 pr_debug("%s: to = 0x%08x, len = %i\n",
2924 __func__, (unsigned int)to, (int)ops->ooblen);
2926 len = mtd_oobavail(mtd, ops);
2928 /* Do not allow write past end of page */
2929 if ((ops->ooboffs + ops->ooblen) > len) {
2930 pr_debug("%s: attempt to write past end of page\n",
2935 if (unlikely(ops->ooboffs >= len)) {
2936 pr_debug("%s: attempt to start write outside oob\n",
2941 /* Do not allow write past end of device */
2942 if (unlikely(to >= mtd->size ||
2943 ops->ooboffs + ops->ooblen >
2944 ((mtd->size >> chip->page_shift) -
2945 (to >> chip->page_shift)) * len)) {
2946 pr_debug("%s: attempt to write beyond end of device\n",
2951 chipnr = (int)(to >> chip->chip_shift);
2954 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2955 * of my DiskOnChip 2000 test units) will clear the whole data page too
2956 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2957 * it in the doc2000 driver in August 1999. dwmw2.
2959 nand_reset(chip, chipnr);
2961 chip->select_chip(mtd, chipnr);
2963 /* Shift to get page */
2964 page = (int)(to >> chip->page_shift);
2966 /* Check, if it is write protected */
2967 if (nand_check_wp(mtd)) {
2968 chip->select_chip(mtd, -1);
2972 /* Invalidate the page cache, if we write to the cached page */
2973 if (page == chip->pagebuf)
2976 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2978 if (ops->mode == MTD_OPS_RAW)
2979 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2981 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2983 chip->select_chip(mtd, -1);
2988 ops->oobretlen = ops->ooblen;
2994 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2995 * @mtd: MTD device structure
2996 * @to: offset to write to
2997 * @ops: oob operation description structure
2999 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
3000 struct mtd_oob_ops *ops)
3002 int ret = -ENOTSUPP;
3006 /* Do not allow writes past end of device */
3007 if (ops->datbuf && (to + ops->len) > mtd->size) {
3008 pr_debug("%s: attempt to write beyond end of device\n",
3013 nand_get_device(mtd, FL_WRITING);
3015 switch (ops->mode) {
3016 case MTD_OPS_PLACE_OOB:
3017 case MTD_OPS_AUTO_OOB:
3026 ret = nand_do_write_oob(mtd, to, ops);
3028 ret = nand_do_write_ops(mtd, to, ops);
3031 nand_release_device(mtd);
3036 * single_erase - [GENERIC] NAND standard block erase command function
3037 * @mtd: MTD device structure
3038 * @page: the page address of the block which will be erased
3040 * Standard erase command for NAND chips. Returns NAND status.
3042 static int single_erase(struct mtd_info *mtd, int page)
3044 struct nand_chip *chip = mtd_to_nand(mtd);
3045 /* Send commands to erase a block */
3046 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
3047 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
3049 return chip->waitfunc(mtd, chip);
3053 * nand_erase - [MTD Interface] erase block(s)
3054 * @mtd: MTD device structure
3055 * @instr: erase instruction
3057 * Erase one ore more blocks.
3059 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
3061 return nand_erase_nand(mtd, instr, 0);
3065 * nand_erase_nand - [INTERN] erase block(s)
3066 * @mtd: MTD device structure
3067 * @instr: erase instruction
3068 * @allowbbt: allow erasing the bbt area
3070 * Erase one ore more blocks.
3072 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
3075 int page, status, pages_per_block, ret, chipnr;
3076 struct nand_chip *chip = mtd_to_nand(mtd);
3079 pr_debug("%s: start = 0x%012llx, len = %llu\n",
3080 __func__, (unsigned long long)instr->addr,
3081 (unsigned long long)instr->len);
3083 if (check_offs_len(mtd, instr->addr, instr->len))
3086 /* Grab the lock and see if the device is available */
3087 nand_get_device(mtd, FL_ERASING);
3089 /* Shift to get first page */
3090 page = (int)(instr->addr >> chip->page_shift);
3091 chipnr = (int)(instr->addr >> chip->chip_shift);
3093 /* Calculate pages in each block */
3094 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3096 /* Select the NAND device */
3097 chip->select_chip(mtd, chipnr);
3099 /* Check, if it is write protected */
3100 if (nand_check_wp(mtd)) {
3101 pr_debug("%s: device is write protected!\n",
3103 instr->state = MTD_ERASE_FAILED;
3107 /* Loop through the pages */
3110 instr->state = MTD_ERASING;
3113 /* Check if we have a bad block, we do not erase bad blocks! */
3114 if (nand_block_checkbad(mtd, ((loff_t) page) <<
3115 chip->page_shift, allowbbt)) {
3116 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
3118 instr->state = MTD_ERASE_FAILED;
3123 * Invalidate the page cache, if we erase the block which
3124 * contains the current cached page.
3126 if (page <= chip->pagebuf && chip->pagebuf <
3127 (page + pages_per_block))
3130 status = chip->erase(mtd, page & chip->pagemask);
3133 * See if operation failed and additional status checks are
3136 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
3137 status = chip->errstat(mtd, chip, FL_ERASING,
3140 /* See if block erase succeeded */
3141 if (status & NAND_STATUS_FAIL) {
3142 pr_debug("%s: failed erase, page 0x%08x\n",
3144 instr->state = MTD_ERASE_FAILED;
3146 ((loff_t)page << chip->page_shift);
3150 /* Increment page address and decrement length */
3151 len -= (1ULL << chip->phys_erase_shift);
3152 page += pages_per_block;
3154 /* Check, if we cross a chip boundary */
3155 if (len && !(page & chip->pagemask)) {
3157 chip->select_chip(mtd, -1);
3158 chip->select_chip(mtd, chipnr);
3161 instr->state = MTD_ERASE_DONE;
3165 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
3167 /* Deselect and wake up anyone waiting on the device */
3168 chip->select_chip(mtd, -1);
3169 nand_release_device(mtd);
3171 /* Do call back function */
3173 mtd_erase_callback(instr);
3175 /* Return more or less happy */
3180 * nand_sync - [MTD Interface] sync
3181 * @mtd: MTD device structure
3183 * Sync is actually a wait for chip ready function.
3185 static void nand_sync(struct mtd_info *mtd)
3187 pr_debug("%s: called\n", __func__);
3189 /* Grab the lock and see if the device is available */
3190 nand_get_device(mtd, FL_SYNCING);
3191 /* Release it and go back */
3192 nand_release_device(mtd);
3196 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
3197 * @mtd: MTD device structure
3198 * @offs: offset relative to mtd start
3200 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
3202 struct nand_chip *chip = mtd_to_nand(mtd);
3203 int chipnr = (int)(offs >> chip->chip_shift);
3206 /* Select the NAND device */
3207 nand_get_device(mtd, FL_READING);
3208 chip->select_chip(mtd, chipnr);
3210 ret = nand_block_checkbad(mtd, offs, 0);
3212 chip->select_chip(mtd, -1);
3213 nand_release_device(mtd);
3219 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3220 * @mtd: MTD device structure
3221 * @ofs: offset relative to mtd start
3223 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3227 ret = nand_block_isbad(mtd, ofs);
3229 /* If it was bad already, return success and do nothing */
3235 return nand_block_markbad_lowlevel(mtd, ofs);
3239 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3240 * @mtd: MTD device structure
3241 * @chip: nand chip info structure
3242 * @addr: feature address.
3243 * @subfeature_param: the subfeature parameters, a four bytes array.
3245 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3246 int addr, uint8_t *subfeature_param)
3251 if (!chip->onfi_version ||
3252 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3253 & ONFI_OPT_CMD_SET_GET_FEATURES))
3256 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3257 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3258 chip->write_byte(mtd, subfeature_param[i]);
3260 status = chip->waitfunc(mtd, chip);
3261 if (status & NAND_STATUS_FAIL)
3267 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3268 * @mtd: MTD device structure
3269 * @chip: nand chip info structure
3270 * @addr: feature address.
3271 * @subfeature_param: the subfeature parameters, a four bytes array.
3273 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3274 int addr, uint8_t *subfeature_param)
3278 if (!chip->onfi_version ||
3279 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3280 & ONFI_OPT_CMD_SET_GET_FEATURES))
3283 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3284 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3285 *subfeature_param++ = chip->read_byte(mtd);
3290 * nand_suspend - [MTD Interface] Suspend the NAND flash
3291 * @mtd: MTD device structure
3293 static int nand_suspend(struct mtd_info *mtd)
3295 return nand_get_device(mtd, FL_PM_SUSPENDED);
3299 * nand_resume - [MTD Interface] Resume the NAND flash
3300 * @mtd: MTD device structure
3302 static void nand_resume(struct mtd_info *mtd)
3304 struct nand_chip *chip = mtd_to_nand(mtd);
3306 if (chip->state == FL_PM_SUSPENDED)
3307 nand_release_device(mtd);
3309 pr_err("%s called for a chip which is not in suspended state\n",
3314 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
3315 * prevent further operations
3316 * @mtd: MTD device structure
3318 static void nand_shutdown(struct mtd_info *mtd)
3320 nand_get_device(mtd, FL_PM_SUSPENDED);
3323 /* Set default functions */
3324 static void nand_set_defaults(struct nand_chip *chip, int busw)
3326 /* check for proper chip_delay setup, set 20us if not */
3327 if (!chip->chip_delay)
3328 chip->chip_delay = 20;
3330 /* check, if a user supplied command function given */
3331 if (chip->cmdfunc == NULL)
3332 chip->cmdfunc = nand_command;
3334 /* check, if a user supplied wait function given */
3335 if (chip->waitfunc == NULL)
3336 chip->waitfunc = nand_wait;
3338 if (!chip->select_chip)
3339 chip->select_chip = nand_select_chip;
3341 /* set for ONFI nand */
3342 if (!chip->onfi_set_features)
3343 chip->onfi_set_features = nand_onfi_set_features;
3344 if (!chip->onfi_get_features)
3345 chip->onfi_get_features = nand_onfi_get_features;
3347 /* If called twice, pointers that depend on busw may need to be reset */
3348 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3349 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3350 if (!chip->read_word)
3351 chip->read_word = nand_read_word;
3352 if (!chip->block_bad)
3353 chip->block_bad = nand_block_bad;
3354 if (!chip->block_markbad)
3355 chip->block_markbad = nand_default_block_markbad;
3356 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3357 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3358 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3359 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3360 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3361 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3362 if (!chip->scan_bbt)
3363 chip->scan_bbt = nand_default_bbt;
3365 if (!chip->controller) {
3366 chip->controller = &chip->hwcontrol;
3367 nand_hw_control_init(chip->controller);
3372 /* Sanitize ONFI strings so we can safely print them */
3373 static void sanitize_string(uint8_t *s, size_t len)
3377 /* Null terminate */
3380 /* Remove non printable chars */
3381 for (i = 0; i < len - 1; i++) {
3382 if (s[i] < ' ' || s[i] > 127)
3386 /* Remove trailing spaces */
3390 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3395 for (i = 0; i < 8; i++)
3396 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3402 /* Parse the Extended Parameter Page. */
3403 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3404 struct nand_chip *chip, struct nand_onfi_params *p)
3406 struct onfi_ext_param_page *ep;
3407 struct onfi_ext_section *s;
3408 struct onfi_ext_ecc_info *ecc;
3414 len = le16_to_cpu(p->ext_param_page_length) * 16;
3415 ep = kmalloc(len, GFP_KERNEL);
3419 /* Send our own NAND_CMD_PARAM. */
3420 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3422 /* Use the Change Read Column command to skip the ONFI param pages. */
3423 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3424 sizeof(*p) * p->num_of_param_pages , -1);
3426 /* Read out the Extended Parameter Page. */
3427 chip->read_buf(mtd, (uint8_t *)ep, len);
3428 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3429 != le16_to_cpu(ep->crc))) {
3430 pr_debug("fail in the CRC.\n");
3435 * Check the signature.
3436 * Do not strictly follow the ONFI spec, maybe changed in future.
3438 if (strncmp(ep->sig, "EPPS", 4)) {
3439 pr_debug("The signature is invalid.\n");
3443 /* find the ECC section. */
3444 cursor = (uint8_t *)(ep + 1);
3445 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3446 s = ep->sections + i;
3447 if (s->type == ONFI_SECTION_TYPE_2)
3449 cursor += s->length * 16;
3451 if (i == ONFI_EXT_SECTION_MAX) {
3452 pr_debug("We can not find the ECC section.\n");
3456 /* get the info we want. */
3457 ecc = (struct onfi_ext_ecc_info *)cursor;
3459 if (!ecc->codeword_size) {
3460 pr_debug("Invalid codeword size\n");
3464 chip->ecc_strength_ds = ecc->ecc_bits;
3465 chip->ecc_step_ds = 1 << ecc->codeword_size;
3473 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3475 struct nand_chip *chip = mtd_to_nand(mtd);
3476 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3478 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3483 * Configure chip properties from Micron vendor-specific ONFI table
3485 static void nand_onfi_detect_micron(struct nand_chip *chip,
3486 struct nand_onfi_params *p)
3488 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3490 if (le16_to_cpu(p->vendor_revision) < 1)
3493 chip->read_retries = micron->read_retry_options;
3494 chip->setup_read_retry = nand_setup_read_retry_micron;
3498 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3500 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3503 struct nand_onfi_params *p = &chip->onfi_params;
3507 /* Try ONFI for unknown chip or LP */
3508 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3509 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3510 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3513 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3514 for (i = 0; i < 3; i++) {
3515 for (j = 0; j < sizeof(*p); j++)
3516 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3517 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3518 le16_to_cpu(p->crc)) {
3524 pr_err("Could not find valid ONFI parameter page; aborting\n");
3529 val = le16_to_cpu(p->revision);
3531 chip->onfi_version = 23;
3532 else if (val & (1 << 4))
3533 chip->onfi_version = 22;
3534 else if (val & (1 << 3))
3535 chip->onfi_version = 21;
3536 else if (val & (1 << 2))
3537 chip->onfi_version = 20;
3538 else if (val & (1 << 1))
3539 chip->onfi_version = 10;
3541 if (!chip->onfi_version) {
3542 pr_info("unsupported ONFI version: %d\n", val);
3546 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3547 sanitize_string(p->model, sizeof(p->model));
3549 mtd->name = p->model;
3551 mtd->writesize = le32_to_cpu(p->byte_per_page);
3554 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3555 * (don't ask me who thought of this...). MTD assumes that these
3556 * dimensions will be power-of-2, so just truncate the remaining area.
3558 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3559 mtd->erasesize *= mtd->writesize;
3561 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3563 /* See erasesize comment */
3564 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3565 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3566 chip->bits_per_cell = p->bits_per_cell;
3568 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3569 *busw = NAND_BUSWIDTH_16;
3573 if (p->ecc_bits != 0xff) {
3574 chip->ecc_strength_ds = p->ecc_bits;
3575 chip->ecc_step_ds = 512;
3576 } else if (chip->onfi_version >= 21 &&
3577 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3580 * The nand_flash_detect_ext_param_page() uses the
3581 * Change Read Column command which maybe not supported
3582 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3583 * now. We do not replace user supplied command function.
3585 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3586 chip->cmdfunc = nand_command_lp;
3588 /* The Extended Parameter Page is supported since ONFI 2.1. */
3589 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3590 pr_warn("Failed to detect ONFI extended param page\n");
3592 pr_warn("Could not retrieve ONFI ECC requirements\n");
3595 if (p->jedec_id == NAND_MFR_MICRON)
3596 nand_onfi_detect_micron(chip, p);
3602 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3604 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3607 struct nand_jedec_params *p = &chip->jedec_params;
3608 struct jedec_ecc_info *ecc;
3612 /* Try JEDEC for unknown chip or LP */
3613 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3614 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3615 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3616 chip->read_byte(mtd) != 'C')
3619 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3620 for (i = 0; i < 3; i++) {
3621 for (j = 0; j < sizeof(*p); j++)
3622 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3624 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3625 le16_to_cpu(p->crc))
3630 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3635 val = le16_to_cpu(p->revision);
3637 chip->jedec_version = 10;
3638 else if (val & (1 << 1))
3639 chip->jedec_version = 1; /* vendor specific version */
3641 if (!chip->jedec_version) {
3642 pr_info("unsupported JEDEC version: %d\n", val);
3646 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3647 sanitize_string(p->model, sizeof(p->model));
3649 mtd->name = p->model;
3651 mtd->writesize = le32_to_cpu(p->byte_per_page);
3653 /* Please reference to the comment for nand_flash_detect_onfi. */
3654 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3655 mtd->erasesize *= mtd->writesize;
3657 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3659 /* Please reference to the comment for nand_flash_detect_onfi. */
3660 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3661 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3662 chip->bits_per_cell = p->bits_per_cell;
3664 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3665 *busw = NAND_BUSWIDTH_16;
3670 ecc = &p->ecc_info[0];
3672 if (ecc->codeword_size >= 9) {
3673 chip->ecc_strength_ds = ecc->ecc_bits;
3674 chip->ecc_step_ds = 1 << ecc->codeword_size;
3676 pr_warn("Invalid codeword size\n");
3683 * nand_id_has_period - Check if an ID string has a given wraparound period
3684 * @id_data: the ID string
3685 * @arrlen: the length of the @id_data array
3686 * @period: the period of repitition
3688 * Check if an ID string is repeated within a given sequence of bytes at
3689 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3690 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3691 * if the repetition has a period of @period; otherwise, returns zero.
3693 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3696 for (i = 0; i < period; i++)
3697 for (j = i + period; j < arrlen; j += period)
3698 if (id_data[i] != id_data[j])
3704 * nand_id_len - Get the length of an ID string returned by CMD_READID
3705 * @id_data: the ID string
3706 * @arrlen: the length of the @id_data array
3708 * Returns the length of the ID string, according to known wraparound/trailing
3709 * zero patterns. If no pattern exists, returns the length of the array.
3711 static int nand_id_len(u8 *id_data, int arrlen)
3713 int last_nonzero, period;
3715 /* Find last non-zero byte */
3716 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3717 if (id_data[last_nonzero])
3721 if (last_nonzero < 0)
3724 /* Calculate wraparound period */
3725 for (period = 1; period < arrlen; period++)
3726 if (nand_id_has_period(id_data, arrlen, period))
3729 /* There's a repeated pattern */
3730 if (period < arrlen)
3733 /* There are trailing zeros */
3734 if (last_nonzero < arrlen - 1)
3735 return last_nonzero + 1;
3737 /* No pattern detected */
3741 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3742 static int nand_get_bits_per_cell(u8 cellinfo)
3746 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3747 bits >>= NAND_CI_CELLTYPE_SHIFT;
3752 * Many new NAND share similar device ID codes, which represent the size of the
3753 * chip. The rest of the parameters must be decoded according to generic or
3754 * manufacturer-specific "extended ID" decoding patterns.
3756 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3757 u8 id_data[8], int *busw)
3760 /* The 3rd id byte holds MLC / multichip data */
3761 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3762 /* The 4th id byte is the important one */
3765 id_len = nand_id_len(id_data, 8);
3768 * Field definitions are in the following datasheets:
3769 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3770 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3771 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3773 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3774 * ID to decide what to do.
3776 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3777 !nand_is_slc(chip) && id_data[5] != 0x00) {
3779 mtd->writesize = 2048 << (extid & 0x03);
3782 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3802 default: /* Other cases are "reserved" (unknown) */
3803 mtd->oobsize = 1024;
3807 /* Calc blocksize */
3808 mtd->erasesize = (128 * 1024) <<
3809 (((extid >> 1) & 0x04) | (extid & 0x03));
3811 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3812 !nand_is_slc(chip)) {
3816 mtd->writesize = 2048 << (extid & 0x03);
3819 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3843 /* Calc blocksize */
3844 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3846 mtd->erasesize = (128 * 1024) << tmp;
3847 else if (tmp == 0x03)
3848 mtd->erasesize = 768 * 1024;
3850 mtd->erasesize = (64 * 1024) << tmp;
3854 mtd->writesize = 1024 << (extid & 0x03);
3857 mtd->oobsize = (8 << (extid & 0x01)) *
3858 (mtd->writesize >> 9);
3860 /* Calc blocksize. Blocksize is multiples of 64KiB */
3861 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3863 /* Get buswidth information */
3864 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3867 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3868 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3870 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3872 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3874 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3875 nand_is_slc(chip) &&
3876 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3877 !(id_data[4] & 0x80) /* !BENAND */) {
3878 mtd->oobsize = 32 * mtd->writesize >> 9;
3885 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3886 * decodes a matching ID table entry and assigns the MTD size parameters for
3889 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3890 struct nand_flash_dev *type, u8 id_data[8],
3893 int maf_id = id_data[0];
3895 mtd->erasesize = type->erasesize;
3896 mtd->writesize = type->pagesize;
3897 mtd->oobsize = mtd->writesize / 32;
3898 *busw = type->options & NAND_BUSWIDTH_16;
3900 /* All legacy ID NAND are small-page, SLC */
3901 chip->bits_per_cell = 1;
3904 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3905 * some Spansion chips have erasesize that conflicts with size
3906 * listed in nand_ids table.
3907 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3909 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3910 && id_data[6] == 0x00 && id_data[7] == 0x00
3911 && mtd->writesize == 512) {
3912 mtd->erasesize = 128 * 1024;
3913 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3918 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3919 * heuristic patterns using various detected parameters (e.g., manufacturer,
3920 * page size, cell-type information).
3922 static void nand_decode_bbm_options(struct mtd_info *mtd,
3923 struct nand_chip *chip, u8 id_data[8])
3925 int maf_id = id_data[0];
3927 /* Set the bad block position */
3928 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3929 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3931 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3934 * Bad block marker is stored in the last page of each block on Samsung
3935 * and Hynix MLC devices; stored in first two pages of each block on
3936 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3937 * AMD/Spansion, and Macronix. All others scan only the first page.
3939 if (!nand_is_slc(chip) &&
3940 (maf_id == NAND_MFR_SAMSUNG ||
3941 maf_id == NAND_MFR_HYNIX))
3942 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3943 else if ((nand_is_slc(chip) &&
3944 (maf_id == NAND_MFR_SAMSUNG ||
3945 maf_id == NAND_MFR_HYNIX ||
3946 maf_id == NAND_MFR_TOSHIBA ||
3947 maf_id == NAND_MFR_AMD ||
3948 maf_id == NAND_MFR_MACRONIX)) ||
3949 (mtd->writesize == 2048 &&
3950 maf_id == NAND_MFR_MICRON))
3951 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3954 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3956 return type->id_len;
3959 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3960 struct nand_flash_dev *type, u8 *id_data, int *busw)
3962 if (!strncmp(type->id, id_data, type->id_len)) {
3963 mtd->writesize = type->pagesize;
3964 mtd->erasesize = type->erasesize;
3965 mtd->oobsize = type->oobsize;
3967 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3968 chip->chipsize = (uint64_t)type->chipsize << 20;
3969 chip->options |= type->options;
3970 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3971 chip->ecc_step_ds = NAND_ECC_STEP(type);
3972 chip->onfi_timing_mode_default =
3973 type->onfi_timing_mode_default;
3975 *busw = type->options & NAND_BUSWIDTH_16;
3978 mtd->name = type->name;
3986 * Get the flash and manufacturer id and lookup if the type is supported.
3988 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3989 struct nand_chip *chip,
3990 int *maf_id, int *dev_id,
3991 struct nand_flash_dev *type)
3998 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4001 nand_reset(chip, 0);
4003 /* Select the device */
4004 chip->select_chip(mtd, 0);
4006 /* Send the command for reading device ID */
4007 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4009 /* Read manufacturer and device IDs */
4010 *maf_id = chip->read_byte(mtd);
4011 *dev_id = chip->read_byte(mtd);
4014 * Try again to make sure, as some systems the bus-hold or other
4015 * interface concerns can cause random data which looks like a
4016 * possibly credible NAND flash to appear. If the two results do
4017 * not match, ignore the device completely.
4020 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4022 /* Read entire ID string */
4023 for (i = 0; i < 8; i++)
4024 id_data[i] = chip->read_byte(mtd);
4026 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
4027 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4028 *maf_id, *dev_id, id_data[0], id_data[1]);
4029 return ERR_PTR(-ENODEV);
4033 type = nand_flash_ids;
4035 for (; type->name != NULL; type++) {
4036 if (is_full_id_nand(type)) {
4037 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
4039 } else if (*dev_id == type->dev_id) {
4044 chip->onfi_version = 0;
4045 if (!type->name || !type->pagesize) {
4046 /* Check if the chip is ONFI compliant */
4047 if (nand_flash_detect_onfi(mtd, chip, &busw))
4050 /* Check if the chip is JEDEC compliant */
4051 if (nand_flash_detect_jedec(mtd, chip, &busw))
4056 return ERR_PTR(-ENODEV);
4059 mtd->name = type->name;
4061 chip->chipsize = (uint64_t)type->chipsize << 20;
4063 if (!type->pagesize) {
4064 /* Decode parameters from extended ID */
4065 nand_decode_ext_id(mtd, chip, id_data, &busw);
4067 nand_decode_id(mtd, chip, type, id_data, &busw);
4069 /* Get chip options */
4070 chip->options |= type->options;
4073 * Check if chip is not a Samsung device. Do not clear the
4074 * options for chips which do not have an extended id.
4076 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
4077 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4080 /* Try to identify manufacturer */
4081 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
4082 if (nand_manuf_ids[maf_idx].id == *maf_id)
4086 if (chip->options & NAND_BUSWIDTH_AUTO) {
4087 WARN_ON(chip->options & NAND_BUSWIDTH_16);
4088 chip->options |= busw;
4089 nand_set_defaults(chip, busw);
4090 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4092 * Check, if buswidth is correct. Hardware drivers should set
4095 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4097 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
4098 pr_warn("bus width %d instead %d bit\n",
4099 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
4101 return ERR_PTR(-EINVAL);
4104 nand_decode_bbm_options(mtd, chip, id_data);
4106 /* Calculate the address shift from the page size */
4107 chip->page_shift = ffs(mtd->writesize) - 1;
4108 /* Convert chipsize to number of pages per chip -1 */
4109 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
4111 chip->bbt_erase_shift = chip->phys_erase_shift =
4112 ffs(mtd->erasesize) - 1;
4113 if (chip->chipsize & 0xffffffff)
4114 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
4116 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
4117 chip->chip_shift += 32 - 1;
4120 chip->badblockbits = 8;
4121 chip->erase = single_erase;
4123 /* Do not replace user supplied command function! */
4124 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
4125 chip->cmdfunc = nand_command_lp;
4127 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4130 if (chip->onfi_version)
4131 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4132 chip->onfi_params.model);
4133 else if (chip->jedec_version)
4134 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4135 chip->jedec_params.model);
4137 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
4140 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4141 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4142 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4146 static const char * const nand_ecc_modes[] = {
4147 [NAND_ECC_NONE] = "none",
4148 [NAND_ECC_SOFT] = "soft",
4149 [NAND_ECC_HW] = "hw",
4150 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
4151 [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
4154 static int of_get_nand_ecc_mode(struct device_node *np)
4159 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4163 for (i = 0; i < ARRAY_SIZE(nand_ecc_modes); i++)
4164 if (!strcasecmp(pm, nand_ecc_modes[i]))
4168 * For backward compatibility we support few obsoleted values that don't
4169 * have their mappings into nand_ecc_modes_t anymore (they were merged
4170 * with other enums).
4172 if (!strcasecmp(pm, "soft_bch"))
4173 return NAND_ECC_SOFT;
4178 static const char * const nand_ecc_algos[] = {
4179 [NAND_ECC_HAMMING] = "hamming",
4180 [NAND_ECC_BCH] = "bch",
4183 static int of_get_nand_ecc_algo(struct device_node *np)
4188 err = of_property_read_string(np, "nand-ecc-algo", &pm);
4190 for (i = NAND_ECC_HAMMING; i < ARRAY_SIZE(nand_ecc_algos); i++)
4191 if (!strcasecmp(pm, nand_ecc_algos[i]))
4197 * For backward compatibility we also read "nand-ecc-mode" checking
4198 * for some obsoleted values that were specifying ECC algorithm.
4200 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4204 if (!strcasecmp(pm, "soft"))
4205 return NAND_ECC_HAMMING;
4206 else if (!strcasecmp(pm, "soft_bch"))
4207 return NAND_ECC_BCH;
4212 static int of_get_nand_ecc_step_size(struct device_node *np)
4217 ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
4218 return ret ? ret : val;
4221 static int of_get_nand_ecc_strength(struct device_node *np)
4226 ret = of_property_read_u32(np, "nand-ecc-strength", &val);
4227 return ret ? ret : val;
4230 static int of_get_nand_bus_width(struct device_node *np)
4234 if (of_property_read_u32(np, "nand-bus-width", &val))
4246 static bool of_get_nand_on_flash_bbt(struct device_node *np)
4248 return of_property_read_bool(np, "nand-on-flash-bbt");
4251 static int nand_dt_init(struct nand_chip *chip)
4253 struct device_node *dn = nand_get_flash_node(chip);
4254 int ecc_mode, ecc_algo, ecc_strength, ecc_step;
4259 if (of_get_nand_bus_width(dn) == 16)
4260 chip->options |= NAND_BUSWIDTH_16;
4262 if (of_get_nand_on_flash_bbt(dn))
4263 chip->bbt_options |= NAND_BBT_USE_FLASH;
4265 ecc_mode = of_get_nand_ecc_mode(dn);
4266 ecc_algo = of_get_nand_ecc_algo(dn);
4267 ecc_strength = of_get_nand_ecc_strength(dn);
4268 ecc_step = of_get_nand_ecc_step_size(dn);
4270 if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
4271 (!(ecc_step >= 0) && ecc_strength >= 0)) {
4272 pr_err("must set both strength and step size in DT\n");
4277 chip->ecc.mode = ecc_mode;
4280 chip->ecc.algo = ecc_algo;
4282 if (ecc_strength >= 0)
4283 chip->ecc.strength = ecc_strength;
4286 chip->ecc.size = ecc_step;
4288 if (of_property_read_bool(dn, "nand-ecc-maximize"))
4289 chip->ecc.options |= NAND_ECC_MAXIMIZE;
4295 * nand_scan_ident - [NAND Interface] Scan for the NAND device
4296 * @mtd: MTD device structure
4297 * @maxchips: number of chips to scan for
4298 * @table: alternative NAND ID table
4300 * This is the first phase of the normal nand_scan() function. It reads the
4301 * flash ID and sets up MTD fields accordingly.
4304 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
4305 struct nand_flash_dev *table)
4307 int i, nand_maf_id, nand_dev_id;
4308 struct nand_chip *chip = mtd_to_nand(mtd);
4309 struct nand_flash_dev *type;
4312 ret = nand_dt_init(chip);
4316 if (!mtd->name && mtd->dev.parent)
4317 mtd->name = dev_name(mtd->dev.parent);
4319 if ((!chip->cmdfunc || !chip->select_chip) && !chip->cmd_ctrl) {
4321 * Default functions assigned for chip_select() and
4322 * cmdfunc() both expect cmd_ctrl() to be populated,
4323 * so we need to check that that's the case
4325 pr_err("chip.cmd_ctrl() callback is not provided");
4328 /* Set the default functions */
4329 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
4331 /* Read the flash type */
4332 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
4333 &nand_dev_id, table);
4336 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
4337 pr_warn("No NAND device found\n");
4338 chip->select_chip(mtd, -1);
4339 return PTR_ERR(type);
4342 /* Initialize the ->data_interface field. */
4343 ret = nand_init_data_interface(chip);
4348 * Setup the data interface correctly on the chip and controller side.
4349 * This explicit call to nand_setup_data_interface() is only required
4350 * for the first die, because nand_reset() has been called before
4351 * ->data_interface and ->default_onfi_timing_mode were set.
4352 * For the other dies, nand_reset() will automatically switch to the
4355 ret = nand_setup_data_interface(chip);
4359 chip->select_chip(mtd, -1);
4361 /* Check for a chip array */
4362 for (i = 1; i < maxchips; i++) {
4363 /* See comment in nand_get_flash_type for reset */
4364 nand_reset(chip, i);
4366 chip->select_chip(mtd, i);
4367 /* Send the command for reading device ID */
4368 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4369 /* Read manufacturer and device IDs */
4370 if (nand_maf_id != chip->read_byte(mtd) ||
4371 nand_dev_id != chip->read_byte(mtd)) {
4372 chip->select_chip(mtd, -1);
4375 chip->select_chip(mtd, -1);
4378 pr_info("%d chips detected\n", i);
4380 /* Store the number of chips and calc total size for mtd */
4382 mtd->size = i * chip->chipsize;
4386 EXPORT_SYMBOL(nand_scan_ident);
4388 static int nand_set_ecc_soft_ops(struct mtd_info *mtd)
4390 struct nand_chip *chip = mtd_to_nand(mtd);
4391 struct nand_ecc_ctrl *ecc = &chip->ecc;
4393 if (WARN_ON(ecc->mode != NAND_ECC_SOFT))
4396 switch (ecc->algo) {
4397 case NAND_ECC_HAMMING:
4398 ecc->calculate = nand_calculate_ecc;
4399 ecc->correct = nand_correct_data;
4400 ecc->read_page = nand_read_page_swecc;
4401 ecc->read_subpage = nand_read_subpage;
4402 ecc->write_page = nand_write_page_swecc;
4403 ecc->read_page_raw = nand_read_page_raw;
4404 ecc->write_page_raw = nand_write_page_raw;
4405 ecc->read_oob = nand_read_oob_std;
4406 ecc->write_oob = nand_write_oob_std;
4413 if (!mtd_nand_has_bch()) {
4414 WARN(1, "CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4417 ecc->calculate = nand_bch_calculate_ecc;
4418 ecc->correct = nand_bch_correct_data;
4419 ecc->read_page = nand_read_page_swecc;
4420 ecc->read_subpage = nand_read_subpage;
4421 ecc->write_page = nand_write_page_swecc;
4422 ecc->read_page_raw = nand_read_page_raw;
4423 ecc->write_page_raw = nand_write_page_raw;
4424 ecc->read_oob = nand_read_oob_std;
4425 ecc->write_oob = nand_write_oob_std;
4428 * Board driver should supply ecc.size and ecc.strength
4429 * values to select how many bits are correctable.
4430 * Otherwise, default to 4 bits for large page devices.
4432 if (!ecc->size && (mtd->oobsize >= 64)) {
4438 * if no ecc placement scheme was provided pickup the default
4441 if (!mtd->ooblayout) {
4442 /* handle large page devices only */
4443 if (mtd->oobsize < 64) {
4444 WARN(1, "OOB layout is required when using software BCH on small pages\n");
4448 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
4453 * We can only maximize ECC config when the default layout is
4454 * used, otherwise we don't know how many bytes can really be
4457 if (mtd->ooblayout == &nand_ooblayout_lp_ops &&
4458 ecc->options & NAND_ECC_MAXIMIZE) {
4461 /* Always prefer 1k blocks over 512bytes ones */
4463 steps = mtd->writesize / ecc->size;
4465 /* Reserve 2 bytes for the BBM */
4466 bytes = (mtd->oobsize - 2) / steps;
4467 ecc->strength = bytes * 8 / fls(8 * ecc->size);
4470 /* See nand_bch_init() for details. */
4472 ecc->priv = nand_bch_init(mtd);
4474 WARN(1, "BCH ECC initialization failed!\n");
4479 WARN(1, "Unsupported ECC algorithm!\n");
4485 * Check if the chip configuration meet the datasheet requirements.
4487 * If our configuration corrects A bits per B bytes and the minimum
4488 * required correction level is X bits per Y bytes, then we must ensure
4489 * both of the following are true:
4491 * (1) A / B >= X / Y
4494 * Requirement (1) ensures we can correct for the required bitflip density.
4495 * Requirement (2) ensures we can correct even when all bitflips are clumped
4496 * in the same sector.
4498 static bool nand_ecc_strength_good(struct mtd_info *mtd)
4500 struct nand_chip *chip = mtd_to_nand(mtd);
4501 struct nand_ecc_ctrl *ecc = &chip->ecc;
4504 if (ecc->size == 0 || chip->ecc_step_ds == 0)
4505 /* Not enough information */
4509 * We get the number of corrected bits per page to compare
4510 * the correction density.
4512 corr = (mtd->writesize * ecc->strength) / ecc->size;
4513 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
4515 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
4519 * nand_scan_tail - [NAND Interface] Scan for the NAND device
4520 * @mtd: MTD device structure
4522 * This is the second phase of the normal nand_scan() function. It fills out
4523 * all the uninitialized function pointers with the defaults and scans for a
4524 * bad block table if appropriate.
4526 int nand_scan_tail(struct mtd_info *mtd)
4528 struct nand_chip *chip = mtd_to_nand(mtd);
4529 struct nand_ecc_ctrl *ecc = &chip->ecc;
4530 struct nand_buffers *nbuf;
4533 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4534 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4535 !(chip->bbt_options & NAND_BBT_USE_FLASH)))
4538 if (!(chip->options & NAND_OWN_BUFFERS)) {
4539 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4540 + mtd->oobsize * 3, GFP_KERNEL);
4543 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4544 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4545 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4547 chip->buffers = nbuf;
4553 /* Set the internal oob buffer location, just after the page data */
4554 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4557 * If no default placement scheme is given, select an appropriate one.
4559 if (!mtd->ooblayout &&
4560 !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
4561 switch (mtd->oobsize) {
4564 mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops);
4568 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
4571 WARN(1, "No oob scheme defined for oobsize %d\n",
4578 if (!chip->write_page)
4579 chip->write_page = nand_write_page;
4582 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4583 * selected and we have 256 byte pagesize fallback to software ECC
4586 switch (ecc->mode) {
4587 case NAND_ECC_HW_OOB_FIRST:
4588 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4589 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4590 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4594 if (!ecc->read_page)
4595 ecc->read_page = nand_read_page_hwecc_oob_first;
4598 /* Use standard hwecc read page function? */
4599 if (!ecc->read_page)
4600 ecc->read_page = nand_read_page_hwecc;
4601 if (!ecc->write_page)
4602 ecc->write_page = nand_write_page_hwecc;
4603 if (!ecc->read_page_raw)
4604 ecc->read_page_raw = nand_read_page_raw;
4605 if (!ecc->write_page_raw)
4606 ecc->write_page_raw = nand_write_page_raw;
4608 ecc->read_oob = nand_read_oob_std;
4609 if (!ecc->write_oob)
4610 ecc->write_oob = nand_write_oob_std;
4611 if (!ecc->read_subpage)
4612 ecc->read_subpage = nand_read_subpage;
4613 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
4614 ecc->write_subpage = nand_write_subpage_hwecc;
4616 case NAND_ECC_HW_SYNDROME:
4617 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4619 ecc->read_page == nand_read_page_hwecc ||
4621 ecc->write_page == nand_write_page_hwecc)) {
4622 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
4626 /* Use standard syndrome read/write page function? */
4627 if (!ecc->read_page)
4628 ecc->read_page = nand_read_page_syndrome;
4629 if (!ecc->write_page)
4630 ecc->write_page = nand_write_page_syndrome;
4631 if (!ecc->read_page_raw)
4632 ecc->read_page_raw = nand_read_page_raw_syndrome;
4633 if (!ecc->write_page_raw)
4634 ecc->write_page_raw = nand_write_page_raw_syndrome;
4636 ecc->read_oob = nand_read_oob_syndrome;
4637 if (!ecc->write_oob)
4638 ecc->write_oob = nand_write_oob_syndrome;
4640 if (mtd->writesize >= ecc->size) {
4641 if (!ecc->strength) {
4642 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
4648 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4649 ecc->size, mtd->writesize);
4650 ecc->mode = NAND_ECC_SOFT;
4651 ecc->algo = NAND_ECC_HAMMING;
4654 ret = nand_set_ecc_soft_ops(mtd);
4662 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
4663 ecc->read_page = nand_read_page_raw;
4664 ecc->write_page = nand_write_page_raw;
4665 ecc->read_oob = nand_read_oob_std;
4666 ecc->read_page_raw = nand_read_page_raw;
4667 ecc->write_page_raw = nand_write_page_raw;
4668 ecc->write_oob = nand_write_oob_std;
4669 ecc->size = mtd->writesize;
4675 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode);
4680 /* For many systems, the standard OOB write also works for raw */
4681 if (!ecc->read_oob_raw)
4682 ecc->read_oob_raw = ecc->read_oob;
4683 if (!ecc->write_oob_raw)
4684 ecc->write_oob_raw = ecc->write_oob;
4686 /* propagate ecc info to mtd_info */
4687 mtd->ecc_strength = ecc->strength;
4688 mtd->ecc_step_size = ecc->size;
4691 * Set the number of read / write steps for one page depending on ECC
4694 ecc->steps = mtd->writesize / ecc->size;
4695 if (ecc->steps * ecc->size != mtd->writesize) {
4696 WARN(1, "Invalid ECC parameters\n");
4700 ecc->total = ecc->steps * ecc->bytes;
4703 * The number of bytes available for a client to place data into
4704 * the out of band area.
4706 ret = mtd_ooblayout_count_freebytes(mtd);
4710 mtd->oobavail = ret;
4712 /* ECC sanity check: warn if it's too weak */
4713 if (!nand_ecc_strength_good(mtd))
4714 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
4717 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4718 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4719 switch (ecc->steps) {
4721 mtd->subpage_sft = 1;
4726 mtd->subpage_sft = 2;
4730 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4732 /* Initialize state */
4733 chip->state = FL_READY;
4735 /* Invalidate the pagebuffer reference */
4738 /* Large page NAND with SOFT_ECC should support subpage reads */
4739 switch (ecc->mode) {
4741 if (chip->page_shift > 9)
4742 chip->options |= NAND_SUBPAGE_READ;
4749 /* Fill in remaining MTD driver data */
4750 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4751 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4753 mtd->_erase = nand_erase;
4755 mtd->_unpoint = NULL;
4756 mtd->_read = nand_read;
4757 mtd->_write = nand_write;
4758 mtd->_panic_write = panic_nand_write;
4759 mtd->_read_oob = nand_read_oob;
4760 mtd->_write_oob = nand_write_oob;
4761 mtd->_sync = nand_sync;
4763 mtd->_unlock = NULL;
4764 mtd->_suspend = nand_suspend;
4765 mtd->_resume = nand_resume;
4766 mtd->_reboot = nand_shutdown;
4767 mtd->_block_isreserved = nand_block_isreserved;
4768 mtd->_block_isbad = nand_block_isbad;
4769 mtd->_block_markbad = nand_block_markbad;
4770 mtd->writebufsize = mtd->writesize;
4773 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4774 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4777 if (!mtd->bitflip_threshold)
4778 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
4780 /* Check, if we should skip the bad block table scan */
4781 if (chip->options & NAND_SKIP_BBTSCAN)
4784 /* Build bad block table */
4785 return chip->scan_bbt(mtd);
4787 if (!(chip->options & NAND_OWN_BUFFERS))
4788 kfree(chip->buffers);
4791 EXPORT_SYMBOL(nand_scan_tail);
4794 * is_module_text_address() isn't exported, and it's mostly a pointless
4795 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4796 * to call us from in-kernel code if the core NAND support is modular.
4799 #define caller_is_module() (1)
4801 #define caller_is_module() \
4802 is_module_text_address((unsigned long)__builtin_return_address(0))
4806 * nand_scan - [NAND Interface] Scan for the NAND device
4807 * @mtd: MTD device structure
4808 * @maxchips: number of chips to scan for
4810 * This fills out all the uninitialized function pointers with the defaults.
4811 * The flash ID is read and the mtd/chip structures are filled with the
4812 * appropriate values.
4814 int nand_scan(struct mtd_info *mtd, int maxchips)
4818 ret = nand_scan_ident(mtd, maxchips, NULL);
4820 ret = nand_scan_tail(mtd);
4823 EXPORT_SYMBOL(nand_scan);
4826 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
4827 * @chip: NAND chip object
4829 void nand_cleanup(struct nand_chip *chip)
4831 if (chip->ecc.mode == NAND_ECC_SOFT &&
4832 chip->ecc.algo == NAND_ECC_BCH)
4833 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4835 nand_release_data_interface(chip);
4837 /* Free bad block table memory */
4839 if (!(chip->options & NAND_OWN_BUFFERS))
4840 kfree(chip->buffers);
4842 /* Free bad block descriptor memory */
4843 if (chip->badblock_pattern && chip->badblock_pattern->options
4844 & NAND_BBT_DYNAMICSTRUCT)
4845 kfree(chip->badblock_pattern);
4847 EXPORT_SYMBOL_GPL(nand_cleanup);
4850 * nand_release - [NAND Interface] Unregister the MTD device and free resources
4851 * held by the NAND device
4852 * @mtd: MTD device structure
4854 void nand_release(struct mtd_info *mtd)
4856 mtd_device_unregister(mtd);
4857 nand_cleanup(mtd_to_nand(mtd));
4859 EXPORT_SYMBOL_GPL(nand_release);
4861 MODULE_LICENSE("GPL");
4862 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4863 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4864 MODULE_DESCRIPTION("Generic NAND flash driver code");