drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 static int check_offs_len(struct mtd_info *mtd,
 112                                         loff_t ofs, uint64_t len)
 113 {
 114         struct nand_chip *chip = mtd->priv;
 115         int ret = 0;
 116
 117         /* Start address must align on block boundary */
 118         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 119                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 120                 ret = -EINVAL;
 121         }
 122
 123         /* Length must align on block boundary */
 124         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 125                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 126                                         __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Do not allow past end of device */
 131         if (ofs + len > mtd->size) {
 132                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd:        MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152
 153         /* Release the controller and the chip */
 154         spin_lock(&chip->controller->lock);
 155         chip->controller->active = NULL;
 156         chip->state = FL_READY;
 157         wake_up(&chip->controller->wq);
 158         spin_unlock(&chip->controller->lock);
 159 }
 160
 161 /**
 162  * nand_read_byte - [DEFAULT] read one byte from the chip
 163  * @mtd:        MTD device structure
 164  *
 165  * Default read function for 8bit buswith
 166  */
 167 static uint8_t nand_read_byte(struct mtd_info *mtd)
 168 {
 169         struct nand_chip *chip = mtd->priv;
 170         return readb(chip->IO_ADDR_R);
 171 }
 172
 173 /**
 174  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 175  * @mtd:        MTD device structure
 176  *
 177  * Default read function for 16bit buswith with
 178  * endianess conversion
 179  */
 180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 184 }
 185
 186 /**
 187  * nand_read_word - [DEFAULT] read one word from the chip
 188  * @mtd:        MTD device structure
 189  *
 190  * Default read function for 16bit buswith without
 191  * endianess conversion
 192  */
 193 static u16 nand_read_word(struct mtd_info *mtd)
 194 {
 195         struct nand_chip *chip = mtd->priv;
 196         return readw(chip->IO_ADDR_R);
 197 }
 198
 199 /**
 200  * nand_select_chip - [DEFAULT] control CE line
 201  * @mtd:        MTD device structure
 202  * @chipnr:     chipnumber to select, -1 for deselect
 203  *
 204  * Default select function for 1 chip devices.
 205  */
 206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 207 {
 208         struct nand_chip *chip = mtd->priv;
 209
 210         switch (chipnr) {
 211         case -1:
 212                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 213                 break;
 214         case 0:
 215                 break;
 216
 217         default:
 218                 BUG();
 219         }
 220 }
 221
 222 /**
 223  * nand_write_buf - [DEFAULT] write buffer to chip
 224  * @mtd:        MTD device structure
 225  * @buf:        data buffer
 226  * @len:        number of bytes to write
 227  *
 228  * Default write function for 8bit buswith
 229  */
 230 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 231 {
 232         int i;
 233         struct nand_chip *chip = mtd->priv;
 234
 235         for (i = 0; i < len; i++)
 236                 writeb(buf[i], chip->IO_ADDR_W);
 237 }
 238
 239 /**
 240  * nand_read_buf - [DEFAULT] read chip data into buffer
 241  * @mtd:        MTD device structure
 242  * @buf:        buffer to store date
 243  * @len:        number of bytes to read
 244  *
 245  * Default read function for 8bit buswith
 246  */
 247 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 248 {
 249         int i;
 250         struct nand_chip *chip = mtd->priv;
 251
 252         for (i = 0; i < len; i++)
 253                 buf[i] = readb(chip->IO_ADDR_R);
 254 }
 255
 256 /**
 257  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 258  * @mtd:        MTD device structure
 259  * @buf:        buffer containing the data to compare
 260  * @len:        number of bytes to compare
 261  *
 262  * Default verify function for 8bit buswith
 263  */
 264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 265 {
 266         int i;
 267         struct nand_chip *chip = mtd->priv;
 268
 269         for (i = 0; i < len; i++)
 270                 if (buf[i] != readb(chip->IO_ADDR_R))
 271                         return -EFAULT;
 272         return 0;
 273 }
 274
 275 /**
 276  * nand_write_buf16 - [DEFAULT] write buffer to chip
 277  * @mtd:        MTD device structure
 278  * @buf:        data buffer
 279  * @len:        number of bytes to write
 280  *
 281  * Default write function for 16bit buswith
 282  */
 283 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 284 {
 285         int i;
 286         struct nand_chip *chip = mtd->priv;
 287         u16 *p = (u16 *) buf;
 288         len >>= 1;
 289
 290         for (i = 0; i < len; i++)
 291                 writew(p[i], chip->IO_ADDR_W);
 292
 293 }
 294
 295 /**
 296  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 297  * @mtd:        MTD device structure
 298  * @buf:        buffer to store date
 299  * @len:        number of bytes to read
 300  *
 301  * Default read function for 16bit buswith
 302  */
 303 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 304 {
 305         int i;
 306         struct nand_chip *chip = mtd->priv;
 307         u16 *p = (u16 *) buf;
 308         len >>= 1;
 309
 310         for (i = 0; i < len; i++)
 311                 p[i] = readw(chip->IO_ADDR_R);
 312 }
 313
 314 /**
 315  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 316  * @mtd:        MTD device structure
 317  * @buf:        buffer containing the data to compare
 318  * @len:        number of bytes to compare
 319  *
 320  * Default verify function for 16bit buswith
 321  */
 322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 323 {
 324         int i;
 325         struct nand_chip *chip = mtd->priv;
 326         u16 *p = (u16 *) buf;
 327         len >>= 1;
 328
 329         for (i = 0; i < len; i++)
 330                 if (p[i] != readw(chip->IO_ADDR_R))
 331                         return -EFAULT;
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 338  * @mtd:        MTD device structure
 339  * @ofs:        offset from device start
 340  * @getchip:    0, if the chip is already selected
 341  *
 342  * Check, if the block is bad.
 343  */
 344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 345 {
 346         int page, chipnr, res = 0;
 347         struct nand_chip *chip = mtd->priv;
 348         u16 bad;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 if ((bad & 0xFF) != 0xff)
 368                         res = 1;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 if (chip->read_byte(mtd) != 0xff)
 372                         res = 1;
 373         }
 374
 375         if (getchip)
 376                 nand_release_device(mtd);
 377
 378         return res;
 379 }
 380
 381 /**
 382  * nand_default_block_markbad - [DEFAULT] mark a block bad
 383  * @mtd:        MTD device structure
 384  * @ofs:        offset from device start
 385  *
 386  * This is the default implementation, which can be overridden by
 387  * a hardware specific driver.
 388 */
 389 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 390 {
 391         struct nand_chip *chip = mtd->priv;
 392         uint8_t buf[2] = { 0, 0 };
 393         int block, ret;
 394
 395         /* Get block number */
 396         block = (int)(ofs >> chip->bbt_erase_shift);
 397         if (chip->bbt)
 398                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 399
 400         /* Do we have a flash based bad block table ? */
 401         if (chip->options & NAND_USE_FLASH_BBT)
 402                 ret = nand_update_bbt(mtd, ofs);
 403         else {
 404                 /* We write two bytes, so we dont have to mess with 16 bit
 405                  * access
 406                  */
 407                 nand_get_device(chip, mtd, FL_WRITING);
 408                 ofs += mtd->oobsize;
 409                 chip->ops.len = chip->ops.ooblen = 2;
 410                 chip->ops.datbuf = NULL;
 411                 chip->ops.oobbuf = buf;
 412                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 413
 414                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 415                 nand_release_device(mtd);
 416         }
 417         if (!ret)
 418                 mtd->ecc_stats.badblocks++;
 419
 420         return ret;
 421 }
 422
 423 /**
 424  * nand_check_wp - [GENERIC] check if the chip is write protected
 425  * @mtd:        MTD device structure
 426  * Check, if the device is write protected
 427  *
 428  * The function expects, that the device is already selected
 429  */
 430 static int nand_check_wp(struct mtd_info *mtd)
 431 {
 432         struct nand_chip *chip = mtd->priv;
 433         /* Check the WP bit */
 434         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 435         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 436 }
 437
 438 /**
 439  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 440  * @mtd:        MTD device structure
 441  * @ofs:        offset from device start
 442  * @getchip:    0, if the chip is already selected
 443  * @allowbbt:   1, if its allowed to access the bbt area
 444  *
 445  * Check, if the block is bad. Either by reading the bad block table or
 446  * calling of the scan function.
 447  */
 448 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 449                                int allowbbt)
 450 {
 451         struct nand_chip *chip = mtd->priv;
 452
 453         if (!chip->bbt)
 454                 return chip->block_bad(mtd, ofs, getchip);
 455
 456         /* Return info from the table */
 457         return nand_isbad_bbt(mtd, ofs, allowbbt);
 458 }
 459
 460 /**
 461  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 462  * @mtd:        MTD device structure
 463  * @timeo:      Timeout
 464  *
 465  * Helper function for nand_wait_ready used when needing to wait in interrupt
 466  * context.
 467  */
 468 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 469 {
 470         struct nand_chip *chip = mtd->priv;
 471         int i;
 472
 473         /* Wait for the device to get ready */
 474         for (i = 0; i < timeo; i++) {
 475                 if (chip->dev_ready(mtd))
 476                         break;
 477                 touch_softlockup_watchdog();
 478                 mdelay(1);
 479         }
 480 }
 481
 482 /*
 483  * Wait for the ready pin, after a command
 484  * The timeout is catched later.
 485  */
 486 void nand_wait_ready(struct mtd_info *mtd)
 487 {
 488         struct nand_chip *chip = mtd->priv;
 489         unsigned long timeo = jiffies + 2;
 490
 491         /* 400ms timeout */
 492         if (in_interrupt() || oops_in_progress)
 493                 return panic_nand_wait_ready(mtd, 400);
 494
 495         led_trigger_event(nand_led_trigger, LED_FULL);
 496         /* wait until command is processed or timeout occures */
 497         do {
 498                 if (chip->dev_ready(mtd))
 499                         break;
 500                 touch_softlockup_watchdog();
 501         } while (time_before(jiffies, timeo));
 502         led_trigger_event(nand_led_trigger, LED_OFF);
 503 }
 504 EXPORT_SYMBOL_GPL(nand_wait_ready);
 505
 506 /**
 507  * nand_command - [DEFAULT] Send command to NAND device
 508  * @mtd:        MTD device structure
 509  * @command:    the command to be sent
 510  * @column:     the column address for this command, -1 if none
 511  * @page_addr:  the page address for this command, -1 if none
 512  *
 513  * Send command to NAND device. This function is used for small page
 514  * devices (256/512 Bytes per page)
 515  */
 516 static void nand_command(struct mtd_info *mtd, unsigned int command,
 517                          int column, int page_addr)
 518 {
 519         register struct nand_chip *chip = mtd->priv;
 520         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 521
 522         /*
 523          * Write out the command to the device.
 524          */
 525         if (command == NAND_CMD_SEQIN) {
 526                 int readcmd;
 527
 528                 if (column >= mtd->writesize) {
 529                         /* OOB area */
 530                         column -= mtd->writesize;
 531                         readcmd = NAND_CMD_READOOB;
 532                 } else if (column < 256) {
 533                         /* First 256 bytes --> READ0 */
 534                         readcmd = NAND_CMD_READ0;
 535                 } else {
 536                         column -= 256;
 537                         readcmd = NAND_CMD_READ1;
 538                 }
 539                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 540                 ctrl &= ~NAND_CTRL_CHANGE;
 541         }
 542         chip->cmd_ctrl(mtd, command, ctrl);
 543
 544         /*
 545          * Address cycle, when necessary
 546          */
 547         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 548         /* Serially input address */
 549         if (column != -1) {
 550                 /* Adjust columns for 16 bit buswidth */
 551                 if (chip->options & NAND_BUSWIDTH_16)
 552                         column >>= 1;
 553                 chip->cmd_ctrl(mtd, column, ctrl);
 554                 ctrl &= ~NAND_CTRL_CHANGE;
 555         }
 556         if (page_addr != -1) {
 557                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 560                 /* One more address cycle for devices > 32MiB */
 561                 if (chip->chipsize > (32 << 20))
 562                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 563         }
 564         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 565
 566         /*
 567          * program and erase have their own busy handlers
 568          * status and sequential in needs no delay
 569          */
 570         switch (command) {
 571
 572         case NAND_CMD_PAGEPROG:
 573         case NAND_CMD_ERASE1:
 574         case NAND_CMD_ERASE2:
 575         case NAND_CMD_SEQIN:
 576         case NAND_CMD_STATUS:
 577                 return;
 578
 579         case NAND_CMD_RESET:
 580                 if (chip->dev_ready)
 581                         break;
 582                 udelay(chip->chip_delay);
 583                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 584                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 585                 chip->cmd_ctrl(mtd,
 586                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 588                 return;
 589
 590                 /* This applies to read commands */
 591         default:
 592                 /*
 593                  * If we don't have access to the busy pin, we apply the given
 594                  * command delay
 595                  */
 596                 if (!chip->dev_ready) {
 597                         udelay(chip->chip_delay);
 598                         return;
 599                 }
 600         }
 601         /* Apply this short delay always to ensure that we do wait tWB in
 602          * any case on any machine. */
 603         ndelay(100);
 604
 605         nand_wait_ready(mtd);
 606 }
 607
 608 /**
 609  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 610  * @mtd:        MTD device structure
 611  * @command:    the command to be sent
 612  * @column:     the column address for this command, -1 if none
 613  * @page_addr:  the page address for this command, -1 if none
 614  *
 615  * Send command to NAND device. This is the version for the new large page
 616  * devices We dont have the separate regions as we have in the small page
 617  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 618  */
 619 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 620                             int column, int page_addr)
 621 {
 622         register struct nand_chip *chip = mtd->priv;
 623
 624         /* Emulate NAND_CMD_READOOB */
 625         if (command == NAND_CMD_READOOB) {
 626                 column += mtd->writesize;
 627                 command = NAND_CMD_READ0;
 628         }
 629
 630         /* Command latch cycle */
 631         chip->cmd_ctrl(mtd, command & 0xff,
 632                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 633
 634         if (column != -1 || page_addr != -1) {
 635                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 636
 637                 /* Serially input address */
 638                 if (column != -1) {
 639                         /* Adjust columns for 16 bit buswidth */
 640                         if (chip->options & NAND_BUSWIDTH_16)
 641                                 column >>= 1;
 642                         chip->cmd_ctrl(mtd, column, ctrl);
 643                         ctrl &= ~NAND_CTRL_CHANGE;
 644                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 645                 }
 646                 if (page_addr != -1) {
 647                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 648                         chip->cmd_ctrl(mtd, page_addr >> 8,
 649                                        NAND_NCE | NAND_ALE);
 650                         /* One more address cycle for devices > 128MiB */
 651                         if (chip->chipsize > (128 << 20))
 652                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 653                                                NAND_NCE | NAND_ALE);
 654                 }
 655         }
 656         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 657
 658         /*
 659          * program and erase have their own busy handlers
 660          * status, sequential in, and deplete1 need no delay
 661          */
 662         switch (command) {
 663
 664         case NAND_CMD_CACHEDPROG:
 665         case NAND_CMD_PAGEPROG:
 666         case NAND_CMD_ERASE1:
 667         case NAND_CMD_ERASE2:
 668         case NAND_CMD_SEQIN:
 669         case NAND_CMD_RNDIN:
 670         case NAND_CMD_STATUS:
 671         case NAND_CMD_DEPLETE1:
 672                 return;
 673
 674                 /*
 675                  * read error status commands require only a short delay
 676                  */
 677         case NAND_CMD_STATUS_ERROR:
 678         case NAND_CMD_STATUS_ERROR0:
 679         case NAND_CMD_STATUS_ERROR1:
 680         case NAND_CMD_STATUS_ERROR2:
 681         case NAND_CMD_STATUS_ERROR3:
 682                 udelay(chip->chip_delay);
 683                 return;
 684
 685         case NAND_CMD_RESET:
 686                 if (chip->dev_ready)
 687                         break;
 688                 udelay(chip->chip_delay);
 689                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 690                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 691                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 692                                NAND_NCE | NAND_CTRL_CHANGE);
 693                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 694                 return;
 695
 696         case NAND_CMD_RNDOUT:
 697                 /* No ready / busy check necessary */
 698                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 699                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 700                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 701                                NAND_NCE | NAND_CTRL_CHANGE);
 702                 return;
 703
 704         case NAND_CMD_READ0:
 705                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 706                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 707                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 708                                NAND_NCE | NAND_CTRL_CHANGE);
 709
 710                 /* This applies to read commands */
 711         default:
 712                 /*
 713                  * If we don't have access to the busy pin, we apply the given
 714                  * command delay
 715                  */
 716                 if (!chip->dev_ready) {
 717                         udelay(chip->chip_delay);
 718                         return;
 719                 }
 720         }
 721
 722         /* Apply this short delay always to ensure that we do wait tWB in
 723          * any case on any machine. */
 724         ndelay(100);
 725
 726         nand_wait_ready(mtd);
 727 }
 728
 729 /**
 730  * panic_nand_get_device - [GENERIC] Get chip for selected access
 731  * @chip:       the nand chip descriptor
 732  * @mtd:        MTD device structure
 733  * @new_state:  the state which is requested
 734  *
 735  * Used when in panic, no locks are taken.
 736  */
 737 static void panic_nand_get_device(struct nand_chip *chip,
 738                       struct mtd_info *mtd, int new_state)
 739 {
 740         /* Hardware controller shared among independend devices */
 741         chip->controller->active = chip;
 742         chip->state = new_state;
 743 }
 744
 745 /**
 746  * nand_get_device - [GENERIC] Get chip for selected access
 747  * @chip:       the nand chip descriptor
 748  * @mtd:        MTD device structure
 749  * @new_state:  the state which is requested
 750  *
 751  * Get the device and lock it for exclusive access
 752  */
 753 static int
 754 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 755 {
 756         spinlock_t *lock = &chip->controller->lock;
 757         wait_queue_head_t *wq = &chip->controller->wq;
 758         DECLARE_WAITQUEUE(wait, current);
 759  retry:
 760         spin_lock(lock);
 761
 762         /* Hardware controller shared among independent devices */
 763         if (!chip->controller->active)
 764                 chip->controller->active = chip;
 765
 766         if (chip->controller->active == chip && chip->state == FL_READY) {
 767                 chip->state = new_state;
 768                 spin_unlock(lock);
 769                 return 0;
 770         }
 771         if (new_state == FL_PM_SUSPENDED) {
 772                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 773                         chip->state = FL_PM_SUSPENDED;
 774                         spin_unlock(lock);
 775                         return 0;
 776                 } else {
 777                         spin_unlock(lock);
 778                         return -EAGAIN;
 779                 }
 780         }
 781         set_current_state(TASK_UNINTERRUPTIBLE);
 782         add_wait_queue(wq, &wait);
 783         spin_unlock(lock);
 784         schedule();
 785         remove_wait_queue(wq, &wait);
 786         goto retry;
 787 }
 788
 789 /**
 790  * panic_nand_wait - [GENERIC]  wait until the command is done
 791  * @mtd:        MTD device structure
 792  * @chip:       NAND chip structure
 793  * @timeo:      Timeout
 794  *
 795  * Wait for command done. This is a helper function for nand_wait used when
 796  * we are in interrupt context. May happen when in panic and trying to write
 797  * an oops trough mtdoops.
 798  */
 799 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 800                             unsigned long timeo)
 801 {
 802         int i;
 803         for (i = 0; i < timeo; i++) {
 804                 if (chip->dev_ready) {
 805                         if (chip->dev_ready(mtd))
 806                                 break;
 807                 } else {
 808                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 809                                 break;
 810                 }
 811                 mdelay(1);
 812         }
 813 }
 814
 815 /**
 816  * nand_wait - [DEFAULT]  wait until the command is done
 817  * @mtd:        MTD device structure
 818  * @chip:       NAND chip structure
 819  *
 820  * Wait for command done. This applies to erase and program only
 821  * Erase can take up to 400ms and program up to 20ms according to
 822  * general NAND and SmartMedia specs
 823  */
 824 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 825 {
 826
 827         unsigned long timeo = jiffies;
 828         int status, state = chip->state;
 829
 830         if (state == FL_ERASING)
 831                 timeo += (HZ * 400) / 1000;
 832         else
 833                 timeo += (HZ * 20) / 1000;
 834
 835         led_trigger_event(nand_led_trigger, LED_FULL);
 836
 837         /* Apply this short delay always to ensure that we do wait tWB in
 838          * any case on any machine. */
 839         ndelay(100);
 840
 841         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 842                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 843         else
 844                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 845
 846         if (in_interrupt() || oops_in_progress)
 847                 panic_nand_wait(mtd, chip, timeo);
 848         else {
 849                 while (time_before(jiffies, timeo)) {
 850                         if (chip->dev_ready) {
 851                                 if (chip->dev_ready(mtd))
 852                                         break;
 853                         } else {
 854                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 855                                         break;
 856                         }
 857                         cond_resched();
 858                 }
 859         }
 860         led_trigger_event(nand_led_trigger, LED_OFF);
 861
 862         status = (int)chip->read_byte(mtd);
 863         return status;
 864 }
 865
 866 /**
 867  * __nand_unlock - [REPLACABLE] unlocks specified locked blockes
 868  *
 869  * @param mtd - mtd info
 870  * @param ofs - offset to start unlock from
 871  * @param len - length to unlock
 872  * @invert -  when = 0, unlock the range of blocks within the lower and
 873  *                      upper boundary address
 874  *            whne = 1, unlock the range of blocks outside the boundaries
 875  *                      of the lower and upper boundary address
 876  *
 877  * @return - unlock status
 878  */
 879 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 880                                         uint64_t len, int invert)
 881 {
 882         int ret = 0;
 883         int status, page;
 884         struct nand_chip *chip = mtd->priv;
 885
 886         /* Submit address of first page to unlock */
 887         page = ofs >> chip->page_shift;
 888         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 889
 890         /* Submit address of last page to unlock */
 891         page = (ofs + len) >> chip->page_shift;
 892         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 893                                 (page | invert) & chip->pagemask);
 894
 895         /* Call wait ready function */
 896         status = chip->waitfunc(mtd, chip);
 897         udelay(1000);
 898         /* See if device thinks it succeeded */
 899         if (status & 0x01) {
 900                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 901                                         __func__, status);
 902                 ret = -EIO;
 903         }
 904
 905         return ret;
 906 }
 907
 908 /**
 909  * nand_unlock - [REPLACABLE] unlocks specified locked blockes
 910  *
 911  * @param mtd - mtd info
 912  * @param ofs - offset to start unlock from
 913  * @param len - length to unlock
 914  *
 915  * @return - unlock status
 916  */
 917 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 918 {
 919         int ret = 0;
 920         int chipnr;
 921         struct nand_chip *chip = mtd->priv;
 922
 923         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 924                         __func__, (unsigned long long)ofs, len);
 925
 926         if (check_offs_len(mtd, ofs, len))
 927                 ret = -EINVAL;
 928
 929         /* Align to last block address if size addresses end of the device */
 930         if (ofs + len == mtd->size)
 931                 len -= mtd->erasesize;
 932
 933         nand_get_device(chip, mtd, FL_UNLOCKING);
 934
 935         /* Shift to get chip number */
 936         chipnr = ofs >> chip->chip_shift;
 937
 938         chip->select_chip(mtd, chipnr);
 939
 940         /* Check, if it is write protected */
 941         if (nand_check_wp(mtd)) {
 942                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 943                                         __func__);
 944                 ret = -EIO;
 945                 goto out;
 946         }
 947
 948         ret = __nand_unlock(mtd, ofs, len, 0);
 949
 950 out:
 951         /* de-select the NAND device */
 952         chip->select_chip(mtd, -1);
 953
 954         nand_release_device(mtd);
 955
 956         return ret;
 957 }
 958
 959 /**
 960  * nand_lock - [REPLACABLE] locks all blockes present in the device
 961  *
 962  * @param mtd - mtd info
 963  * @param ofs - offset to start unlock from
 964  * @param len - length to unlock
 965  *
 966  * @return - lock status
 967  *
 968  * This feature is not support in many NAND parts. 'Micron' NAND parts
 969  * do have this feature, but it allows only to lock all blocks not for
 970  * specified range for block.
 971  *
 972  * Implementing 'lock' feature by making use of 'unlock', for now.
 973  */
 974 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 975 {
 976         int ret = 0;
 977         int chipnr, status, page;
 978         struct nand_chip *chip = mtd->priv;
 979
 980         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 981                         __func__, (unsigned long long)ofs, len);
 982
 983         if (check_offs_len(mtd, ofs, len))
 984                 ret = -EINVAL;
 985
 986         nand_get_device(chip, mtd, FL_LOCKING);
 987
 988         /* Shift to get chip number */
 989         chipnr = ofs >> chip->chip_shift;
 990
 991         chip->select_chip(mtd, chipnr);
 992
 993         /* Check, if it is write protected */
 994         if (nand_check_wp(mtd)) {
 995                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 996                                         __func__);
 997                 status = MTD_ERASE_FAILED;
 998                 ret = -EIO;
 999                 goto out;
1000         }
1001
1002         /* Submit address of first page to lock */
1003         page = ofs >> chip->page_shift;
1004         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1005
1006         /* Call wait ready function */
1007         status = chip->waitfunc(mtd, chip);
1008         udelay(1000);
1009         /* See if device thinks it succeeded */
1010         if (status & 0x01) {
1011                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1012                                         __func__, status);
1013                 ret = -EIO;
1014                 goto out;
1015         }
1016
1017         ret = __nand_unlock(mtd, ofs, len, 0x1);
1018
1019 out:
1020         /* de-select the NAND device */
1021         chip->select_chip(mtd, -1);
1022
1023         nand_release_device(mtd);
1024
1025         return ret;
1026 }
1027
1028 /**
1029  * nand_read_page_raw - [Intern] read raw page data without ecc
1030  * @mtd:        mtd info structure
1031  * @chip:       nand chip info structure
1032  * @buf:        buffer to store read data
1033  * @page:       page number to read
1034  *
1035  * Not for syndrome calculating ecc controllers, which use a special oob layout
1036  */
1037 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1038                               uint8_t *buf, int page)
1039 {
1040         chip->read_buf(mtd, buf, mtd->writesize);
1041         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1042         return 0;
1043 }
1044
1045 /**
1046  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1047  * @mtd:        mtd info structure
1048  * @chip:       nand chip info structure
1049  * @buf:        buffer to store read data
1050  * @page:       page number to read
1051  *
1052  * We need a special oob layout and handling even when OOB isn't used.
1053  */
1054 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1055                               uint8_t *buf, int page)
1056 {
1057         int eccsize = chip->ecc.size;
1058         int eccbytes = chip->ecc.bytes;
1059         uint8_t *oob = chip->oob_poi;
1060         int steps, size;
1061
1062         for (steps = chip->ecc.steps; steps > 0; steps--) {
1063                 chip->read_buf(mtd, buf, eccsize);
1064                 buf += eccsize;
1065
1066                 if (chip->ecc.prepad) {
1067                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1068                         oob += chip->ecc.prepad;
1069                 }
1070
1071                 chip->read_buf(mtd, oob, eccbytes);
1072                 oob += eccbytes;
1073
1074                 if (chip->ecc.postpad) {
1075                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1076                         oob += chip->ecc.postpad;
1077                 }
1078         }
1079
1080         size = mtd->oobsize - (oob - chip->oob_poi);
1081         if (size)
1082                 chip->read_buf(mtd, oob, size);
1083
1084         return 0;
1085 }
1086
1087 /**
1088  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1089  * @mtd:        mtd info structure
1090  * @chip:       nand chip info structure
1091  * @buf:        buffer to store read data
1092  * @page:       page number to read
1093  */
1094 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1095                                 uint8_t *buf, int page)
1096 {
1097         int i, eccsize = chip->ecc.size;
1098         int eccbytes = chip->ecc.bytes;
1099         int eccsteps = chip->ecc.steps;
1100         uint8_t *p = buf;
1101         uint8_t *ecc_calc = chip->buffers->ecccalc;
1102         uint8_t *ecc_code = chip->buffers->ecccode;
1103         uint32_t *eccpos = chip->ecc.layout->eccpos;
1104
1105         chip->ecc.read_page_raw(mtd, chip, buf, page);
1106
1107         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1108                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1109
1110         for (i = 0; i < chip->ecc.total; i++)
1111                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1112
1113         eccsteps = chip->ecc.steps;
1114         p = buf;
1115
1116         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1117                 int stat;
1118
1119                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1120                 if (stat < 0)
1121                         mtd->ecc_stats.failed++;
1122                 else
1123                         mtd->ecc_stats.corrected += stat;
1124         }
1125         return 0;
1126 }
1127
1128 /**
1129  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1130  * @mtd:        mtd info structure
1131  * @chip:       nand chip info structure
1132  * @data_offs:  offset of requested data within the page
1133  * @readlen:    data length
1134  * @bufpoi:     buffer to store read data
1135  */
1136 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1137 {
1138         int start_step, end_step, num_steps;
1139         uint32_t *eccpos = chip->ecc.layout->eccpos;
1140         uint8_t *p;
1141         int data_col_addr, i, gaps = 0;
1142         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1143         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1144
1145         /* Column address wihin the page aligned to ECC size (256bytes). */
1146         start_step = data_offs / chip->ecc.size;
1147         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1148         num_steps = end_step - start_step + 1;
1149
1150         /* Data size aligned to ECC ecc.size*/
1151         datafrag_len = num_steps * chip->ecc.size;
1152         eccfrag_len = num_steps * chip->ecc.bytes;
1153
1154         data_col_addr = start_step * chip->ecc.size;
1155         /* If we read not a page aligned data */
1156         if (data_col_addr != 0)
1157                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1158
1159         p = bufpoi + data_col_addr;
1160         chip->read_buf(mtd, p, datafrag_len);
1161
1162         /* Calculate  ECC */
1163         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1164                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1165
1166         /* The performance is faster if to position offsets
1167            according to ecc.pos. Let make sure here that
1168            there are no gaps in ecc positions */
1169         for (i = 0; i < eccfrag_len - 1; i++) {
1170                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1171                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1172                         gaps = 1;
1173                         break;
1174                 }
1175         }
1176         if (gaps) {
1177                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1178                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1179         } else {
1180                 /* send the command to read the particular ecc bytes */
1181                 /* take care about buswidth alignment in read_buf */
1182                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1183                 aligned_len = eccfrag_len;
1184                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1185                         aligned_len++;
1186                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1187                         aligned_len++;
1188
1189                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1190                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1191         }
1192
1193         for (i = 0; i < eccfrag_len; i++)
1194                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1195
1196         p = bufpoi + data_col_addr;
1197         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1198                 int stat;
1199
1200                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1201                 if (stat == -1)
1202                         mtd->ecc_stats.failed++;
1203                 else
1204                         mtd->ecc_stats.corrected += stat;
1205         }
1206         return 0;
1207 }
1208
1209 /**
1210  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1211  * @mtd:        mtd info structure
1212  * @chip:       nand chip info structure
1213  * @buf:        buffer to store read data
1214  * @page:       page number to read
1215  *
1216  * Not for syndrome calculating ecc controllers which need a special oob layout
1217  */
1218 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1219                                 uint8_t *buf, int page)
1220 {
1221         int i, eccsize = chip->ecc.size;
1222         int eccbytes = chip->ecc.bytes;
1223         int eccsteps = chip->ecc.steps;
1224         uint8_t *p = buf;
1225         uint8_t *ecc_calc = chip->buffers->ecccalc;
1226         uint8_t *ecc_code = chip->buffers->ecccode;
1227         uint32_t *eccpos = chip->ecc.layout->eccpos;
1228
1229         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1230                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1231                 chip->read_buf(mtd, p, eccsize);
1232                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1233         }
1234         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1235
1236         for (i = 0; i < chip->ecc.total; i++)
1237                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1238
1239         eccsteps = chip->ecc.steps;
1240         p = buf;
1241
1242         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1243                 int stat;
1244
1245                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1246                 if (stat < 0)
1247                         mtd->ecc_stats.failed++;
1248                 else
1249                         mtd->ecc_stats.corrected += stat;
1250         }
1251         return 0;
1252 }
1253
1254 /**
1255  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1256  * @mtd:        mtd info structure
1257  * @chip:       nand chip info structure
1258  * @buf:        buffer to store read data
1259  * @page:       page number to read
1260  *
1261  * Hardware ECC for large page chips, require OOB to be read first.
1262  * For this ECC mode, the write_page method is re-used from ECC_HW.
1263  * These methods read/write ECC from the OOB area, unlike the
1264  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1265  * "infix ECC" scheme and reads/writes ECC from the data area, by
1266  * overwriting the NAND manufacturer bad block markings.
1267  */
1268 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1269         struct nand_chip *chip, uint8_t *buf, int page)
1270 {
1271         int i, eccsize = chip->ecc.size;
1272         int eccbytes = chip->ecc.bytes;
1273         int eccsteps = chip->ecc.steps;
1274         uint8_t *p = buf;
1275         uint8_t *ecc_code = chip->buffers->ecccode;
1276         uint32_t *eccpos = chip->ecc.layout->eccpos;
1277         uint8_t *ecc_calc = chip->buffers->ecccalc;
1278
1279         /* Read the OOB area first */
1280         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1281         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1282         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1283
1284         for (i = 0; i < chip->ecc.total; i++)
1285                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1286
1287         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1288                 int stat;
1289
1290                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1291                 chip->read_buf(mtd, p, eccsize);
1292                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1293
1294                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1295                 if (stat < 0)
1296                         mtd->ecc_stats.failed++;
1297                 else
1298                         mtd->ecc_stats.corrected += stat;
1299         }
1300         return 0;
1301 }
1302
1303 /**
1304  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1305  * @mtd:        mtd info structure
1306  * @chip:       nand chip info structure
1307  * @buf:        buffer to store read data
1308  * @page:       page number to read
1309  *
1310  * The hw generator calculates the error syndrome automatically. Therefor
1311  * we need a special oob layout and handling.
1312  */
1313 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1314                                    uint8_t *buf, int page)
1315 {
1316         int i, eccsize = chip->ecc.size;
1317         int eccbytes = chip->ecc.bytes;
1318         int eccsteps = chip->ecc.steps;
1319         uint8_t *p = buf;
1320         uint8_t *oob = chip->oob_poi;
1321
1322         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1323                 int stat;
1324
1325                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1326                 chip->read_buf(mtd, p, eccsize);
1327
1328                 if (chip->ecc.prepad) {
1329                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1330                         oob += chip->ecc.prepad;
1331                 }
1332
1333                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1334                 chip->read_buf(mtd, oob, eccbytes);
1335                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1336
1337                 if (stat < 0)
1338                         mtd->ecc_stats.failed++;
1339                 else
1340                         mtd->ecc_stats.corrected += stat;
1341
1342                 oob += eccbytes;
1343
1344                 if (chip->ecc.postpad) {
1345                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1346                         oob += chip->ecc.postpad;
1347                 }
1348         }
1349
1350         /* Calculate remaining oob bytes */
1351         i = mtd->oobsize - (oob - chip->oob_poi);
1352         if (i)
1353                 chip->read_buf(mtd, oob, i);
1354
1355         return 0;
1356 }
1357
1358 /**
1359  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1360  * @chip:       nand chip structure
1361  * @oob:        oob destination address
1362  * @ops:        oob ops structure
1363  * @len:        size of oob to transfer
1364  */
1365 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1366                                   struct mtd_oob_ops *ops, size_t len)
1367 {
1368         switch(ops->mode) {
1369
1370         case MTD_OOB_PLACE:
1371         case MTD_OOB_RAW:
1372                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1373                 return oob + len;
1374
1375         case MTD_OOB_AUTO: {
1376                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1377                 uint32_t boffs = 0, roffs = ops->ooboffs;
1378                 size_t bytes = 0;
1379
1380                 for(; free->length && len; free++, len -= bytes) {
1381                         /* Read request not from offset 0 ? */
1382                         if (unlikely(roffs)) {
1383                                 if (roffs >= free->length) {
1384                                         roffs -= free->length;
1385                                         continue;
1386                                 }
1387                                 boffs = free->offset + roffs;
1388                                 bytes = min_t(size_t, len,
1389                                               (free->length - roffs));
1390                                 roffs = 0;
1391                         } else {
1392                                 bytes = min_t(size_t, len, free->length);
1393                                 boffs = free->offset;
1394                         }
1395                         memcpy(oob, chip->oob_poi + boffs, bytes);
1396                         oob += bytes;
1397                 }
1398                 return oob;
1399         }
1400         default:
1401                 BUG();
1402         }
1403         return NULL;
1404 }
1405
1406 /**
1407  * nand_do_read_ops - [Internal] Read data with ECC
1408  *
1409  * @mtd:        MTD device structure
1410  * @from:       offset to read from
1411  * @ops:        oob ops structure
1412  *
1413  * Internal function. Called with chip held.
1414  */
1415 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1416                             struct mtd_oob_ops *ops)
1417 {
1418         int chipnr, page, realpage, col, bytes, aligned;
1419         struct nand_chip *chip = mtd->priv;
1420         struct mtd_ecc_stats stats;
1421         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1422         int sndcmd = 1;
1423         int ret = 0;
1424         uint32_t readlen = ops->len;
1425         uint32_t oobreadlen = ops->ooblen;
1426         uint8_t *bufpoi, *oob, *buf;
1427
1428         stats = mtd->ecc_stats;
1429
1430         chipnr = (int)(from >> chip->chip_shift);
1431         chip->select_chip(mtd, chipnr);
1432
1433         realpage = (int)(from >> chip->page_shift);
1434         page = realpage & chip->pagemask;
1435
1436         col = (int)(from & (mtd->writesize - 1));
1437
1438         buf = ops->datbuf;
1439         oob = ops->oobbuf;
1440
1441         while(1) {
1442                 bytes = min(mtd->writesize - col, readlen);
1443                 aligned = (bytes == mtd->writesize);
1444
1445                 /* Is the current page in the buffer ? */
1446                 if (realpage != chip->pagebuf || oob) {
1447                         bufpoi = aligned ? buf : chip->buffers->databuf;
1448
1449                         if (likely(sndcmd)) {
1450                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1451                                 sndcmd = 0;
1452                         }
1453
1454                         /* Now read the page into the buffer */
1455                         if (unlikely(ops->mode == MTD_OOB_RAW))
1456                                 ret = chip->ecc.read_page_raw(mtd, chip,
1457                                                               bufpoi, page);
1458                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1459                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1460                         else
1461                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1462                                                           page);
1463                         if (ret < 0)
1464                                 break;
1465
1466                         /* Transfer not aligned data */
1467                         if (!aligned) {
1468                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1469                                         chip->pagebuf = realpage;
1470                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1471                         }
1472
1473                         buf += bytes;
1474
1475                         if (unlikely(oob)) {
1476                                 /* Raw mode does data:oob:data:oob */
1477                                 if (ops->mode != MTD_OOB_RAW) {
1478                                         int toread = min(oobreadlen,
1479                                                 chip->ecc.layout->oobavail);
1480                                         if (toread) {
1481                                                 oob = nand_transfer_oob(chip,
1482                                                         oob, ops, toread);
1483                                                 oobreadlen -= toread;
1484                                         }
1485                                 } else
1486                                         buf = nand_transfer_oob(chip,
1487                                                 buf, ops, mtd->oobsize);
1488                         }
1489
1490                         if (!(chip->options & NAND_NO_READRDY)) {
1491                                 /*
1492                                  * Apply delay or wait for ready/busy pin. Do
1493                                  * this before the AUTOINCR check, so no
1494                                  * problems arise if a chip which does auto
1495                                  * increment is marked as NOAUTOINCR by the
1496                                  * board driver.
1497                                  */
1498                                 if (!chip->dev_ready)
1499                                         udelay(chip->chip_delay);
1500                                 else
1501                                         nand_wait_ready(mtd);
1502                         }
1503                 } else {
1504                         memcpy(buf, chip->buffers->databuf + col, bytes);
1505                         buf += bytes;
1506                 }
1507
1508                 readlen -= bytes;
1509
1510                 if (!readlen)
1511                         break;
1512
1513                 /* For subsequent reads align to page boundary. */
1514                 col = 0;
1515                 /* Increment page address */
1516                 realpage++;
1517
1518                 page = realpage & chip->pagemask;
1519                 /* Check, if we cross a chip boundary */
1520                 if (!page) {
1521                         chipnr++;
1522                         chip->select_chip(mtd, -1);
1523                         chip->select_chip(mtd, chipnr);
1524                 }
1525
1526                 /* Check, if the chip supports auto page increment
1527                  * or if we have hit a block boundary.
1528                  */
1529                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1530                         sndcmd = 1;
1531         }
1532
1533         ops->retlen = ops->len - (size_t) readlen;
1534         if (oob)
1535                 ops->oobretlen = ops->ooblen - oobreadlen;
1536
1537         if (ret)
1538                 return ret;
1539
1540         if (mtd->ecc_stats.failed - stats.failed)
1541                 return -EBADMSG;
1542
1543         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1544 }
1545
1546 /**
1547  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1548  * @mtd:        MTD device structure
1549  * @from:       offset to read from
1550  * @len:        number of bytes to read
1551  * @retlen:     pointer to variable to store the number of read bytes
1552  * @buf:        the databuffer to put data
1553  *
1554  * Get hold of the chip and call nand_do_read
1555  */
1556 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1557                      size_t *retlen, uint8_t *buf)
1558 {
1559         struct nand_chip *chip = mtd->priv;
1560         int ret;
1561
1562         /* Do not allow reads past end of device */
1563         if ((from + len) > mtd->size)
1564                 return -EINVAL;
1565         if (!len)
1566                 return 0;
1567
1568         nand_get_device(chip, mtd, FL_READING);
1569
1570         chip->ops.len = len;
1571         chip->ops.datbuf = buf;
1572         chip->ops.oobbuf = NULL;
1573
1574         ret = nand_do_read_ops(mtd, from, &chip->ops);
1575
1576         *retlen = chip->ops.retlen;
1577
1578         nand_release_device(mtd);
1579
1580         return ret;
1581 }
1582
1583 /**
1584  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1585  * @mtd:        mtd info structure
1586  * @chip:       nand chip info structure
1587  * @page:       page number to read
1588  * @sndcmd:     flag whether to issue read command or not
1589  */
1590 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1591                              int page, int sndcmd)
1592 {
1593         if (sndcmd) {
1594                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1595                 sndcmd = 0;
1596         }
1597         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1598         return sndcmd;
1599 }
1600
1601 /**
1602  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1603  *                          with syndromes
1604  * @mtd:        mtd info structure
1605  * @chip:       nand chip info structure
1606  * @page:       page number to read
1607  * @sndcmd:     flag whether to issue read command or not
1608  */
1609 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1610                                   int page, int sndcmd)
1611 {
1612         uint8_t *buf = chip->oob_poi;
1613         int length = mtd->oobsize;
1614         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1615         int eccsize = chip->ecc.size;
1616         uint8_t *bufpoi = buf;
1617         int i, toread, sndrnd = 0, pos;
1618
1619         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1620         for (i = 0; i < chip->ecc.steps; i++) {
1621                 if (sndrnd) {
1622                         pos = eccsize + i * (eccsize + chunk);
1623                         if (mtd->writesize > 512)
1624                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1625                         else
1626                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1627                 } else
1628                         sndrnd = 1;
1629                 toread = min_t(int, length, chunk);
1630                 chip->read_buf(mtd, bufpoi, toread);
1631                 bufpoi += toread;
1632                 length -= toread;
1633         }
1634         if (length > 0)
1635                 chip->read_buf(mtd, bufpoi, length);
1636
1637         return 1;
1638 }
1639
1640 /**
1641  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1642  * @mtd:        mtd info structure
1643  * @chip:       nand chip info structure
1644  * @page:       page number to write
1645  */
1646 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1647                               int page)
1648 {
1649         int status = 0;
1650         const uint8_t *buf = chip->oob_poi;
1651         int length = mtd->oobsize;
1652
1653         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1654         chip->write_buf(mtd, buf, length);
1655         /* Send command to program the OOB data */
1656         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1657
1658         status = chip->waitfunc(mtd, chip);
1659
1660         return status & NAND_STATUS_FAIL ? -EIO : 0;
1661 }
1662
1663 /**
1664  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1665  *                           with syndrome - only for large page flash !
1666  * @mtd:        mtd info structure
1667  * @chip:       nand chip info structure
1668  * @page:       page number to write
1669  */
1670 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1671                                    struct nand_chip *chip, int page)
1672 {
1673         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1674         int eccsize = chip->ecc.size, length = mtd->oobsize;
1675         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1676         const uint8_t *bufpoi = chip->oob_poi;
1677
1678         /*
1679          * data-ecc-data-ecc ... ecc-oob
1680          * or
1681          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1682          */
1683         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1684                 pos = steps * (eccsize + chunk);
1685                 steps = 0;
1686         } else
1687                 pos = eccsize;
1688
1689         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1690         for (i = 0; i < steps; i++) {
1691                 if (sndcmd) {
1692                         if (mtd->writesize <= 512) {
1693                                 uint32_t fill = 0xFFFFFFFF;
1694
1695                                 len = eccsize;
1696                                 while (len > 0) {
1697                                         int num = min_t(int, len, 4);
1698                                         chip->write_buf(mtd, (uint8_t *)&fill,
1699                                                         num);
1700                                         len -= num;
1701                                 }
1702                         } else {
1703                                 pos = eccsize + i * (eccsize + chunk);
1704                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1705                         }
1706                 } else
1707                         sndcmd = 1;
1708                 len = min_t(int, length, chunk);
1709                 chip->write_buf(mtd, bufpoi, len);
1710                 bufpoi += len;
1711                 length -= len;
1712         }
1713         if (length > 0)
1714                 chip->write_buf(mtd, bufpoi, length);
1715
1716         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1717         status = chip->waitfunc(mtd, chip);
1718
1719         return status & NAND_STATUS_FAIL ? -EIO : 0;
1720 }
1721
1722 /**
1723  * nand_do_read_oob - [Intern] NAND read out-of-band
1724  * @mtd:        MTD device structure
1725  * @from:       offset to read from
1726  * @ops:        oob operations description structure
1727  *
1728  * NAND read out-of-band data from the spare area
1729  */
1730 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1731                             struct mtd_oob_ops *ops)
1732 {
1733         int page, realpage, chipnr, sndcmd = 1;
1734         struct nand_chip *chip = mtd->priv;
1735         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1736         int readlen = ops->ooblen;
1737         int len;
1738         uint8_t *buf = ops->oobbuf;
1739
1740         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1741                         __func__, (unsigned long long)from, readlen);
1742
1743         if (ops->mode == MTD_OOB_AUTO)
1744                 len = chip->ecc.layout->oobavail;
1745         else
1746                 len = mtd->oobsize;
1747
1748         if (unlikely(ops->ooboffs >= len)) {
1749                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1750                                         "outside oob\n", __func__);
1751                 return -EINVAL;
1752         }
1753
1754         /* Do not allow reads past end of device */
1755         if (unlikely(from >= mtd->size ||
1756                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1757                                         (from >> chip->page_shift)) * len)) {
1758                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1759                                         "of device\n", __func__);
1760                 return -EINVAL;
1761         }
1762
1763         chipnr = (int)(from >> chip->chip_shift);
1764         chip->select_chip(mtd, chipnr);
1765
1766         /* Shift to get page */
1767         realpage = (int)(from >> chip->page_shift);
1768         page = realpage & chip->pagemask;
1769
1770         while(1) {
1771                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1772
1773                 len = min(len, readlen);
1774                 buf = nand_transfer_oob(chip, buf, ops, len);
1775
1776                 if (!(chip->options & NAND_NO_READRDY)) {
1777                         /*
1778                          * Apply delay or wait for ready/busy pin. Do this
1779                          * before the AUTOINCR check, so no problems arise if a
1780                          * chip which does auto increment is marked as
1781                          * NOAUTOINCR by the board driver.
1782                          */
1783                         if (!chip->dev_ready)
1784                                 udelay(chip->chip_delay);
1785                         else
1786                                 nand_wait_ready(mtd);
1787                 }
1788
1789                 readlen -= len;
1790                 if (!readlen)
1791                         break;
1792
1793                 /* Increment page address */
1794                 realpage++;
1795
1796                 page = realpage & chip->pagemask;
1797                 /* Check, if we cross a chip boundary */
1798                 if (!page) {
1799                         chipnr++;
1800                         chip->select_chip(mtd, -1);
1801                         chip->select_chip(mtd, chipnr);
1802                 }
1803
1804                 /* Check, if the chip supports auto page increment
1805                  * or if we have hit a block boundary.
1806                  */
1807                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1808                         sndcmd = 1;
1809         }
1810
1811         ops->oobretlen = ops->ooblen;
1812         return 0;
1813 }
1814
1815 /**
1816  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1817  * @mtd:        MTD device structure
1818  * @from:       offset to read from
1819  * @ops:        oob operation description structure
1820  *
1821  * NAND read data and/or out-of-band data
1822  */
1823 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1824                          struct mtd_oob_ops *ops)
1825 {
1826         struct nand_chip *chip = mtd->priv;
1827         int ret = -ENOTSUPP;
1828
1829         ops->retlen = 0;
1830
1831         /* Do not allow reads past end of device */
1832         if (ops->datbuf && (from + ops->len) > mtd->size) {
1833                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1834                                 "beyond end of device\n", __func__);
1835                 return -EINVAL;
1836         }
1837
1838         nand_get_device(chip, mtd, FL_READING);
1839
1840         switch(ops->mode) {
1841         case MTD_OOB_PLACE:
1842         case MTD_OOB_AUTO:
1843         case MTD_OOB_RAW:
1844                 break;
1845
1846         default:
1847                 goto out;
1848         }
1849
1850         if (!ops->datbuf)
1851                 ret = nand_do_read_oob(mtd, from, ops);
1852         else
1853                 ret = nand_do_read_ops(mtd, from, ops);
1854
1855  out:
1856         nand_release_device(mtd);
1857         return ret;
1858 }
1859
1860
1861 /**
1862  * nand_write_page_raw - [Intern] raw page write function
1863  * @mtd:        mtd info structure
1864  * @chip:       nand chip info structure
1865  * @buf:        data buffer
1866  *
1867  * Not for syndrome calculating ecc controllers, which use a special oob layout
1868  */
1869 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1870                                 const uint8_t *buf)
1871 {
1872         chip->write_buf(mtd, buf, mtd->writesize);
1873         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1874 }
1875
1876 /**
1877  * nand_write_page_raw_syndrome - [Intern] raw page write function
1878  * @mtd:        mtd info structure
1879  * @chip:       nand chip info structure
1880  * @buf:        data buffer
1881  *
1882  * We need a special oob layout and handling even when ECC isn't checked.
1883  */
1884 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1885                                 const uint8_t *buf)
1886 {
1887         int eccsize = chip->ecc.size;
1888         int eccbytes = chip->ecc.bytes;
1889         uint8_t *oob = chip->oob_poi;
1890         int steps, size;
1891
1892         for (steps = chip->ecc.steps; steps > 0; steps--) {
1893                 chip->write_buf(mtd, buf, eccsize);
1894                 buf += eccsize;
1895
1896                 if (chip->ecc.prepad) {
1897                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1898                         oob += chip->ecc.prepad;
1899                 }
1900
1901                 chip->read_buf(mtd, oob, eccbytes);
1902                 oob += eccbytes;
1903
1904                 if (chip->ecc.postpad) {
1905                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1906                         oob += chip->ecc.postpad;
1907                 }
1908         }
1909
1910         size = mtd->oobsize - (oob - chip->oob_poi);
1911         if (size)
1912                 chip->write_buf(mtd, oob, size);
1913 }
1914 /**
1915  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1916  * @mtd:        mtd info structure
1917  * @chip:       nand chip info structure
1918  * @buf:        data buffer
1919  */
1920 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1921                                   const uint8_t *buf)
1922 {
1923         int i, eccsize = chip->ecc.size;
1924         int eccbytes = chip->ecc.bytes;
1925         int eccsteps = chip->ecc.steps;
1926         uint8_t *ecc_calc = chip->buffers->ecccalc;
1927         const uint8_t *p = buf;
1928         uint32_t *eccpos = chip->ecc.layout->eccpos;
1929
1930         /* Software ecc calculation */
1931         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1932                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1933
1934         for (i = 0; i < chip->ecc.total; i++)
1935                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1936
1937         chip->ecc.write_page_raw(mtd, chip, buf);
1938 }
1939
1940 /**
1941  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1942  * @mtd:        mtd info structure
1943  * @chip:       nand chip info structure
1944  * @buf:        data buffer
1945  */
1946 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1947                                   const uint8_t *buf)
1948 {
1949         int i, eccsize = chip->ecc.size;
1950         int eccbytes = chip->ecc.bytes;
1951         int eccsteps = chip->ecc.steps;
1952         uint8_t *ecc_calc = chip->buffers->ecccalc;
1953         const uint8_t *p = buf;
1954         uint32_t *eccpos = chip->ecc.layout->eccpos;
1955
1956         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1957                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1958                 chip->write_buf(mtd, p, eccsize);
1959                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1960         }
1961
1962         for (i = 0; i < chip->ecc.total; i++)
1963                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1964
1965         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1966 }
1967
1968 /**
1969  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1970  * @mtd:        mtd info structure
1971  * @chip:       nand chip info structure
1972  * @buf:        data buffer
1973  *
1974  * The hw generator calculates the error syndrome automatically. Therefor
1975  * we need a special oob layout and handling.
1976  */
1977 static void nand_write_page_syndrome(struct mtd_info *mtd,
1978                                     struct nand_chip *chip, const uint8_t *buf)
1979 {
1980         int i, eccsize = chip->ecc.size;
1981         int eccbytes = chip->ecc.bytes;
1982         int eccsteps = chip->ecc.steps;
1983         const uint8_t *p = buf;
1984         uint8_t *oob = chip->oob_poi;
1985
1986         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1987
1988                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1989                 chip->write_buf(mtd, p, eccsize);
1990
1991                 if (chip->ecc.prepad) {
1992                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1993                         oob += chip->ecc.prepad;
1994                 }
1995
1996                 chip->ecc.calculate(mtd, p, oob);
1997                 chip->write_buf(mtd, oob, eccbytes);
1998                 oob += eccbytes;
1999
2000                 if (chip->ecc.postpad) {
2001                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2002                         oob += chip->ecc.postpad;
2003                 }
2004         }
2005
2006         /* Calculate remaining oob bytes */
2007         i = mtd->oobsize - (oob - chip->oob_poi);
2008         if (i)
2009                 chip->write_buf(mtd, oob, i);
2010 }
2011
2012 /**
2013  * nand_write_page - [REPLACEABLE] write one page
2014  * @mtd:        MTD device structure
2015  * @chip:       NAND chip descriptor
2016  * @buf:        the data to write
2017  * @page:       page number to write
2018  * @cached:     cached programming
2019  * @raw:        use _raw version of write_page
2020  */
2021 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2022                            const uint8_t *buf, int page, int cached, int raw)
2023 {
2024         int status;
2025
2026         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2027
2028         if (unlikely(raw))
2029                 chip->ecc.write_page_raw(mtd, chip, buf);
2030         else
2031                 chip->ecc.write_page(mtd, chip, buf);
2032
2033         /*
2034          * Cached progamming disabled for now, Not sure if its worth the
2035          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2036          */
2037         cached = 0;
2038
2039         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2040
2041                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2042                 status = chip->waitfunc(mtd, chip);
2043                 /*
2044                  * See if operation failed and additional status checks are
2045                  * available
2046                  */
2047                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2048                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2049                                                page);
2050
2051                 if (status & NAND_STATUS_FAIL)
2052                         return -EIO;
2053         } else {
2054                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2055                 status = chip->waitfunc(mtd, chip);
2056         }
2057
2058 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2059         /* Send command to read back the data */
2060         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2061
2062         if (chip->verify_buf(mtd, buf, mtd->writesize))
2063                 return -EIO;
2064 #endif
2065         return 0;
2066 }
2067
2068 /**
2069  * nand_fill_oob - [Internal] Transfer client buffer to oob
2070  * @chip:       nand chip structure
2071  * @oob:        oob data buffer
2072  * @ops:        oob ops structure
2073  */
2074 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
2075                                   struct mtd_oob_ops *ops)
2076 {
2077         size_t len = ops->ooblen;
2078
2079         switch(ops->mode) {
2080
2081         case MTD_OOB_PLACE:
2082         case MTD_OOB_RAW:
2083                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2084                 return oob + len;
2085
2086         case MTD_OOB_AUTO: {
2087                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2088                 uint32_t boffs = 0, woffs = ops->ooboffs;
2089                 size_t bytes = 0;
2090
2091                 for(; free->length && len; free++, len -= bytes) {
2092                         /* Write request not from offset 0 ? */
2093                         if (unlikely(woffs)) {
2094                                 if (woffs >= free->length) {
2095                                         woffs -= free->length;
2096                                         continue;
2097                                 }
2098                                 boffs = free->offset + woffs;
2099                                 bytes = min_t(size_t, len,
2100                                               (free->length - woffs));
2101                                 woffs = 0;
2102                         } else {
2103                                 bytes = min_t(size_t, len, free->length);
2104                                 boffs = free->offset;
2105                         }
2106                         memcpy(chip->oob_poi + boffs, oob, bytes);
2107                         oob += bytes;
2108                 }
2109                 return oob;
2110         }
2111         default:
2112                 BUG();
2113         }
2114         return NULL;
2115 }
2116
2117 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
2118
2119 /**
2120  * nand_do_write_ops - [Internal] NAND write with ECC
2121  * @mtd:        MTD device structure
2122  * @to:         offset to write to
2123  * @ops:        oob operations description structure
2124  *
2125  * NAND write with ECC
2126  */
2127 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2128                              struct mtd_oob_ops *ops)
2129 {
2130         int chipnr, realpage, page, blockmask, column;
2131         struct nand_chip *chip = mtd->priv;
2132         uint32_t writelen = ops->len;
2133         uint8_t *oob = ops->oobbuf;
2134         uint8_t *buf = ops->datbuf;
2135         int ret, subpage;
2136
2137         ops->retlen = 0;
2138         if (!writelen)
2139                 return 0;
2140
2141         /* reject writes, which are not page aligned */
2142         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2143                 printk(KERN_NOTICE "%s: Attempt to write not "
2144                                 "page aligned data\n", __func__);
2145                 return -EINVAL;
2146         }
2147
2148         column = to & (mtd->writesize - 1);
2149         subpage = column || (writelen & (mtd->writesize - 1));
2150
2151         if (subpage && oob)
2152                 return -EINVAL;
2153
2154         chipnr = (int)(to >> chip->chip_shift);
2155         chip->select_chip(mtd, chipnr);
2156
2157         /* Check, if it is write protected */
2158         if (nand_check_wp(mtd))
2159                 return -EIO;
2160
2161         realpage = (int)(to >> chip->page_shift);
2162         page = realpage & chip->pagemask;
2163         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2164
2165         /* Invalidate the page cache, when we write to the cached page */
2166         if (to <= (chip->pagebuf << chip->page_shift) &&
2167             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2168                 chip->pagebuf = -1;
2169
2170         /* If we're not given explicit OOB data, let it be 0xFF */
2171         if (likely(!oob))
2172                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2173
2174         while(1) {
2175                 int bytes = mtd->writesize;
2176                 int cached = writelen > bytes && page != blockmask;
2177                 uint8_t *wbuf = buf;
2178
2179                 /* Partial page write ? */
2180                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2181                         cached = 0;
2182                         bytes = min_t(int, bytes - column, (int) writelen);
2183                         chip->pagebuf = -1;
2184                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2185                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2186                         wbuf = chip->buffers->databuf;
2187                 }
2188
2189                 if (unlikely(oob))
2190                         oob = nand_fill_oob(chip, oob, ops);
2191
2192                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2193                                        (ops->mode == MTD_OOB_RAW));
2194                 if (ret)
2195                         break;
2196
2197                 writelen -= bytes;
2198                 if (!writelen)
2199                         break;
2200
2201                 column = 0;
2202                 buf += bytes;
2203                 realpage++;
2204
2205                 page = realpage & chip->pagemask;
2206                 /* Check, if we cross a chip boundary */
2207                 if (!page) {
2208                         chipnr++;
2209                         chip->select_chip(mtd, -1);
2210                         chip->select_chip(mtd, chipnr);
2211                 }
2212         }
2213
2214         ops->retlen = ops->len - writelen;
2215         if (unlikely(oob))
2216                 ops->oobretlen = ops->ooblen;
2217         return ret;
2218 }
2219
2220 /**
2221  * panic_nand_write - [MTD Interface] NAND write with ECC
2222  * @mtd:        MTD device structure
2223  * @to:         offset to write to
2224  * @len:        number of bytes to write
2225  * @retlen:     pointer to variable to store the number of written bytes
2226  * @buf:        the data to write
2227  *
2228  * NAND write with ECC. Used when performing writes in interrupt context, this
2229  * may for example be called by mtdoops when writing an oops while in panic.
2230  */
2231 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2232                             size_t *retlen, const uint8_t *buf)
2233 {
2234         struct nand_chip *chip = mtd->priv;
2235         int ret;
2236
2237         /* Do not allow reads past end of device */
2238         if ((to + len) > mtd->size)
2239                 return -EINVAL;
2240         if (!len)
2241                 return 0;
2242
2243         /* Wait for the device to get ready.  */
2244         panic_nand_wait(mtd, chip, 400);
2245
2246         /* Grab the device.  */
2247         panic_nand_get_device(chip, mtd, FL_WRITING);
2248
2249         chip->ops.len = len;
2250         chip->ops.datbuf = (uint8_t *)buf;
2251         chip->ops.oobbuf = NULL;
2252
2253         ret = nand_do_write_ops(mtd, to, &chip->ops);
2254
2255         *retlen = chip->ops.retlen;
2256         return ret;
2257 }
2258
2259 /**
2260  * nand_write - [MTD Interface] NAND write with ECC
2261  * @mtd:        MTD device structure
2262  * @to:         offset to write to
2263  * @len:        number of bytes to write
2264  * @retlen:     pointer to variable to store the number of written bytes
2265  * @buf:        the data to write
2266  *
2267  * NAND write with ECC
2268  */
2269 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2270                           size_t *retlen, const uint8_t *buf)
2271 {
2272         struct nand_chip *chip = mtd->priv;
2273         int ret;
2274
2275         /* Do not allow reads past end of device */
2276         if ((to + len) > mtd->size)
2277                 return -EINVAL;
2278         if (!len)
2279                 return 0;
2280
2281         nand_get_device(chip, mtd, FL_WRITING);
2282
2283         chip->ops.len = len;
2284         chip->ops.datbuf = (uint8_t *)buf;
2285         chip->ops.oobbuf = NULL;
2286
2287         ret = nand_do_write_ops(mtd, to, &chip->ops);
2288
2289         *retlen = chip->ops.retlen;
2290
2291         nand_release_device(mtd);
2292
2293         return ret;
2294 }
2295
2296 /**
2297  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2298  * @mtd:        MTD device structure
2299  * @to:         offset to write to
2300  * @ops:        oob operation description structure
2301  *
2302  * NAND write out-of-band
2303  */
2304 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2305                              struct mtd_oob_ops *ops)
2306 {
2307         int chipnr, page, status, len;
2308         struct nand_chip *chip = mtd->priv;
2309
2310         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2311                          __func__, (unsigned int)to, (int)ops->ooblen);
2312
2313         if (ops->mode == MTD_OOB_AUTO)
2314                 len = chip->ecc.layout->oobavail;
2315         else
2316                 len = mtd->oobsize;
2317
2318         /* Do not allow write past end of page */
2319         if ((ops->ooboffs + ops->ooblen) > len) {
2320                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2321                                 "past end of page\n", __func__);
2322                 return -EINVAL;
2323         }
2324
2325         if (unlikely(ops->ooboffs >= len)) {
2326                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2327                                 "write outside oob\n", __func__);
2328                 return -EINVAL;
2329         }
2330
2331         /* Do not allow reads past end of device */
2332         if (unlikely(to >= mtd->size ||
2333                      ops->ooboffs + ops->ooblen >
2334                         ((mtd->size >> chip->page_shift) -
2335                          (to >> chip->page_shift)) * len)) {
2336                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2337                                 "end of device\n", __func__);
2338                 return -EINVAL;
2339         }
2340
2341         chipnr = (int)(to >> chip->chip_shift);
2342         chip->select_chip(mtd, chipnr);
2343
2344         /* Shift to get page */
2345         page = (int)(to >> chip->page_shift);
2346
2347         /*
2348          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2349          * of my DiskOnChip 2000 test units) will clear the whole data page too
2350          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2351          * it in the doc2000 driver in August 1999.  dwmw2.
2352          */
2353         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2354
2355         /* Check, if it is write protected */
2356         if (nand_check_wp(mtd))
2357                 return -EROFS;
2358
2359         /* Invalidate the page cache, if we write to the cached page */
2360         if (page == chip->pagebuf)
2361                 chip->pagebuf = -1;
2362
2363         memset(chip->oob_poi, 0xff, mtd->oobsize);
2364         nand_fill_oob(chip, ops->oobbuf, ops);
2365         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2366         memset(chip->oob_poi, 0xff, mtd->oobsize);
2367
2368         if (status)
2369                 return status;
2370
2371         ops->oobretlen = ops->ooblen;
2372
2373         return 0;
2374 }
2375
2376 /**
2377  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2378  * @mtd:        MTD device structure
2379  * @to:         offset to write to
2380  * @ops:        oob operation description structure
2381  */
2382 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2383                           struct mtd_oob_ops *ops)
2384 {
2385         struct nand_chip *chip = mtd->priv;
2386         int ret = -ENOTSUPP;
2387
2388         ops->retlen = 0;
2389
2390         /* Do not allow writes past end of device */
2391         if (ops->datbuf && (to + ops->len) > mtd->size) {
2392                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2393                                 "end of device\n", __func__);
2394                 return -EINVAL;
2395         }
2396
2397         nand_get_device(chip, mtd, FL_WRITING);
2398
2399         switch(ops->mode) {
2400         case MTD_OOB_PLACE:
2401         case MTD_OOB_AUTO:
2402         case MTD_OOB_RAW:
2403                 break;
2404
2405         default:
2406                 goto out;
2407         }
2408
2409         if (!ops->datbuf)
2410                 ret = nand_do_write_oob(mtd, to, ops);
2411         else
2412                 ret = nand_do_write_ops(mtd, to, ops);
2413
2414  out:
2415         nand_release_device(mtd);
2416         return ret;
2417 }
2418
2419 /**
2420  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2421  * @mtd:        MTD device structure
2422  * @page:       the page address of the block which will be erased
2423  *
2424  * Standard erase command for NAND chips
2425  */
2426 static void single_erase_cmd(struct mtd_info *mtd, int page)
2427 {
2428         struct nand_chip *chip = mtd->priv;
2429         /* Send commands to erase a block */
2430         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2431         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2432 }
2433
2434 /**
2435  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2436  * @mtd:        MTD device structure
2437  * @page:       the page address of the block which will be erased
2438  *
2439  * AND multi block erase command function
2440  * Erase 4 consecutive blocks
2441  */
2442 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2443 {
2444         struct nand_chip *chip = mtd->priv;
2445         /* Send commands to erase a block */
2446         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2447         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2448         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2449         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2450         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2451 }
2452
2453 /**
2454  * nand_erase - [MTD Interface] erase block(s)
2455  * @mtd:        MTD device structure
2456  * @instr:      erase instruction
2457  *
2458  * Erase one ore more blocks
2459  */
2460 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2461 {
2462         return nand_erase_nand(mtd, instr, 0);
2463 }
2464
2465 #define BBT_PAGE_MASK   0xffffff3f
2466 /**
2467  * nand_erase_nand - [Internal] erase block(s)
2468  * @mtd:        MTD device structure
2469  * @instr:      erase instruction
2470  * @allowbbt:   allow erasing the bbt area
2471  *
2472  * Erase one ore more blocks
2473  */
2474 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2475                     int allowbbt)
2476 {
2477         int page, status, pages_per_block, ret, chipnr;
2478         struct nand_chip *chip = mtd->priv;
2479         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2480         unsigned int bbt_masked_page = 0xffffffff;
2481         loff_t len;
2482
2483         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2484                                 __func__, (unsigned long long)instr->addr,
2485                                 (unsigned long long)instr->len);
2486
2487         if (check_offs_len(mtd, instr->addr, instr->len))
2488                 return -EINVAL;
2489
2490         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2491
2492         /* Grab the lock and see if the device is available */
2493         nand_get_device(chip, mtd, FL_ERASING);
2494
2495         /* Shift to get first page */
2496         page = (int)(instr->addr >> chip->page_shift);
2497         chipnr = (int)(instr->addr >> chip->chip_shift);
2498
2499         /* Calculate pages in each block */
2500         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2501
2502         /* Select the NAND device */
2503         chip->select_chip(mtd, chipnr);
2504
2505         /* Check, if it is write protected */
2506         if (nand_check_wp(mtd)) {
2507                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2508                                         __func__);
2509                 instr->state = MTD_ERASE_FAILED;
2510                 goto erase_exit;
2511         }
2512
2513         /*
2514          * If BBT requires refresh, set the BBT page mask to see if the BBT
2515          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2516          * can not be matched. This is also done when the bbt is actually
2517          * erased to avoid recusrsive updates
2518          */
2519         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2520                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2521
2522         /* Loop through the pages */
2523         len = instr->len;
2524
2525         instr->state = MTD_ERASING;
2526
2527         while (len) {
2528                 /*
2529                  * heck if we have a bad block, we do not erase bad blocks !
2530                  */
2531                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2532                                         chip->page_shift, 0, allowbbt)) {
2533                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2534                                         "at page 0x%08x\n", __func__, page);
2535                         instr->state = MTD_ERASE_FAILED;
2536                         goto erase_exit;
2537                 }
2538
2539                 /*
2540                  * Invalidate the page cache, if we erase the block which
2541                  * contains the current cached page
2542                  */
2543                 if (page <= chip->pagebuf && chip->pagebuf <
2544                     (page + pages_per_block))
2545                         chip->pagebuf = -1;
2546
2547                 chip->erase_cmd(mtd, page & chip->pagemask);
2548
2549                 status = chip->waitfunc(mtd, chip);
2550
2551                 /*
2552                  * See if operation failed and additional status checks are
2553                  * available
2554                  */
2555                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2556                         status = chip->errstat(mtd, chip, FL_ERASING,
2557                                                status, page);
2558
2559                 /* See if block erase succeeded */
2560                 if (status & NAND_STATUS_FAIL) {
2561                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2562                                         "page 0x%08x\n", __func__, page);
2563                         instr->state = MTD_ERASE_FAILED;
2564                         instr->fail_addr =
2565                                 ((loff_t)page << chip->page_shift);
2566                         goto erase_exit;
2567                 }
2568
2569                 /*
2570                  * If BBT requires refresh, set the BBT rewrite flag to the
2571                  * page being erased
2572                  */
2573                 if (bbt_masked_page != 0xffffffff &&
2574                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2575                             rewrite_bbt[chipnr] =
2576                                         ((loff_t)page << chip->page_shift);
2577
2578                 /* Increment page address and decrement length */
2579                 len -= (1 << chip->phys_erase_shift);
2580                 page += pages_per_block;
2581
2582                 /* Check, if we cross a chip boundary */
2583                 if (len && !(page & chip->pagemask)) {
2584                         chipnr++;
2585                         chip->select_chip(mtd, -1);
2586                         chip->select_chip(mtd, chipnr);
2587
2588                         /*
2589                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2590                          * page mask to see if this BBT should be rewritten
2591                          */
2592                         if (bbt_masked_page != 0xffffffff &&
2593                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2594                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2595                                         BBT_PAGE_MASK;
2596                 }
2597         }
2598         instr->state = MTD_ERASE_DONE;
2599
2600  erase_exit:
2601
2602         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2603
2604         /* Deselect and wake up anyone waiting on the device */
2605         nand_release_device(mtd);
2606
2607         /* Do call back function */
2608         if (!ret)
2609                 mtd_erase_callback(instr);
2610
2611         /*
2612          * If BBT requires refresh and erase was successful, rewrite any
2613          * selected bad block tables
2614          */
2615         if (bbt_masked_page == 0xffffffff || ret)
2616                 return ret;
2617
2618         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2619                 if (!rewrite_bbt[chipnr])
2620                         continue;
2621                 /* update the BBT for chip */
2622                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2623                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2624                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2625                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2626         }
2627
2628         /* Return more or less happy */
2629         return ret;
2630 }
2631
2632 /**
2633  * nand_sync - [MTD Interface] sync
2634  * @mtd:        MTD device structure
2635  *
2636  * Sync is actually a wait for chip ready function
2637  */
2638 static void nand_sync(struct mtd_info *mtd)
2639 {
2640         struct nand_chip *chip = mtd->priv;
2641
2642         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2643
2644         /* Grab the lock and see if the device is available */
2645         nand_get_device(chip, mtd, FL_SYNCING);
2646         /* Release it and go back */
2647         nand_release_device(mtd);
2648 }
2649
2650 /**
2651  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2652  * @mtd:        MTD device structure
2653  * @offs:       offset relative to mtd start
2654  */
2655 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2656 {
2657         /* Check for invalid offset */
2658         if (offs > mtd->size)
2659                 return -EINVAL;
2660
2661         return nand_block_checkbad(mtd, offs, 1, 0);
2662 }
2663
2664 /**
2665  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2666  * @mtd:        MTD device structure
2667  * @ofs:        offset relative to mtd start
2668  */
2669 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2670 {
2671         struct nand_chip *chip = mtd->priv;
2672         int ret;
2673
2674         if ((ret = nand_block_isbad(mtd, ofs))) {
2675                 /* If it was bad already, return success and do nothing. */
2676                 if (ret > 0)
2677                         return 0;
2678                 return ret;
2679         }
2680
2681         return chip->block_markbad(mtd, ofs);
2682 }
2683
2684 /**
2685  * nand_suspend - [MTD Interface] Suspend the NAND flash
2686  * @mtd:        MTD device structure
2687  */
2688 static int nand_suspend(struct mtd_info *mtd)
2689 {
2690         struct nand_chip *chip = mtd->priv;
2691
2692         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2693 }
2694
2695 /**
2696  * nand_resume - [MTD Interface] Resume the NAND flash
2697  * @mtd:        MTD device structure
2698  */
2699 static void nand_resume(struct mtd_info *mtd)
2700 {
2701         struct nand_chip *chip = mtd->priv;
2702
2703         if (chip->state == FL_PM_SUSPENDED)
2704                 nand_release_device(mtd);
2705         else
2706                 printk(KERN_ERR "%s called for a chip which is not "
2707                        "in suspended state\n", __func__);
2708 }
2709
2710 /*
2711  * Set default functions
2712  */
2713 static void nand_set_defaults(struct nand_chip *chip, int busw)
2714 {
2715         /* check for proper chip_delay setup, set 20us if not */
2716         if (!chip->chip_delay)
2717                 chip->chip_delay = 20;
2718
2719         /* check, if a user supplied command function given */
2720         if (chip->cmdfunc == NULL)
2721                 chip->cmdfunc = nand_command;
2722
2723         /* check, if a user supplied wait function given */
2724         if (chip->waitfunc == NULL)
2725                 chip->waitfunc = nand_wait;
2726
2727         if (!chip->select_chip)
2728                 chip->select_chip = nand_select_chip;
2729         if (!chip->read_byte)
2730                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2731         if (!chip->read_word)
2732                 chip->read_word = nand_read_word;
2733         if (!chip->block_bad)
2734                 chip->block_bad = nand_block_bad;
2735         if (!chip->block_markbad)
2736                 chip->block_markbad = nand_default_block_markbad;
2737         if (!chip->write_buf)
2738                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2739         if (!chip->read_buf)
2740                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2741         if (!chip->verify_buf)
2742                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2743         if (!chip->scan_bbt)
2744                 chip->scan_bbt = nand_default_bbt;
2745
2746         if (!chip->controller) {
2747                 chip->controller = &chip->hwcontrol;
2748                 spin_lock_init(&chip->controller->lock);
2749                 init_waitqueue_head(&chip->controller->wq);
2750         }
2751
2752 }
2753
2754 /*
2755  * Get the flash and manufacturer id and lookup if the type is supported
2756  */
2757 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2758                                                   struct nand_chip *chip,
2759                                                   int busw, int *maf_id)
2760 {
2761         struct nand_flash_dev *type = NULL;
2762         int i, dev_id, maf_idx;
2763         int tmp_id, tmp_manf;
2764
2765         /* Select the device */
2766         chip->select_chip(mtd, 0);
2767
2768         /*
2769          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2770          * after power-up
2771          */
2772         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2773
2774         /* Send the command for reading device ID */
2775         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2776
2777         /* Read manufacturer and device IDs */
2778         *maf_id = chip->read_byte(mtd);
2779         dev_id = chip->read_byte(mtd);
2780
2781         /* Try again to make sure, as some systems the bus-hold or other
2782          * interface concerns can cause random data which looks like a
2783          * possibly credible NAND flash to appear. If the two results do
2784          * not match, ignore the device completely.
2785          */
2786
2787         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2788
2789         /* Read manufacturer and device IDs */
2790
2791         tmp_manf = chip->read_byte(mtd);
2792         tmp_id = chip->read_byte(mtd);
2793
2794         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2795                 printk(KERN_INFO "%s: second ID read did not match "
2796                        "%02x,%02x against %02x,%02x\n", __func__,
2797                        *maf_id, dev_id, tmp_manf, tmp_id);
2798                 return ERR_PTR(-ENODEV);
2799         }
2800
2801         /* Lookup the flash id */
2802         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2803                 if (dev_id == nand_flash_ids[i].id) {
2804                         type =  &nand_flash_ids[i];
2805                         break;
2806                 }
2807         }
2808
2809         if (!type)
2810                 return ERR_PTR(-ENODEV);
2811
2812         if (!mtd->name)
2813                 mtd->name = type->name;
2814
2815         chip->chipsize = (uint64_t)type->chipsize << 20;
2816
2817         /* Newer devices have all the information in additional id bytes */
2818         if (!type->pagesize) {
2819                 int extid;
2820                 /* The 3rd id byte holds MLC / multichip data */
2821                 chip->cellinfo = chip->read_byte(mtd);
2822                 /* The 4th id byte is the important one */
2823                 extid = chip->read_byte(mtd);
2824                 /* Calc pagesize */
2825                 mtd->writesize = 1024 << (extid & 0x3);
2826                 extid >>= 2;
2827                 /* Calc oobsize */
2828                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2829                 extid >>= 2;
2830                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2831                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2832                 extid >>= 2;
2833                 /* Get buswidth information */
2834                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2835
2836         } else {
2837                 /*
2838                  * Old devices have chip data hardcoded in the device id table
2839                  */
2840                 mtd->erasesize = type->erasesize;
2841                 mtd->writesize = type->pagesize;
2842                 mtd->oobsize = mtd->writesize / 32;
2843                 busw = type->options & NAND_BUSWIDTH_16;
2844         }
2845
2846         /* Try to identify manufacturer */
2847         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2848                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2849                         break;
2850         }
2851
2852         /*
2853          * Check, if buswidth is correct. Hardware drivers should set
2854          * chip correct !
2855          */
2856         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2857                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2858                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2859                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2860                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2861                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2862                        busw ? 16 : 8);
2863                 return ERR_PTR(-EINVAL);
2864         }
2865
2866         /* Calculate the address shift from the page size */
2867         chip->page_shift = ffs(mtd->writesize) - 1;
2868         /* Convert chipsize to number of pages per chip -1. */
2869         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2870
2871         chip->bbt_erase_shift = chip->phys_erase_shift =
2872                 ffs(mtd->erasesize) - 1;
2873         if (chip->chipsize & 0xffffffff)
2874                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2875         else
2876                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2877
2878         /* Set the bad block position */
2879         chip->badblockpos = mtd->writesize > 512 ?
2880                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2881
2882         /* Get chip options, preserve non chip based options */
2883         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2884         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2885
2886         /*
2887          * Set chip as a default. Board drivers can override it, if necessary
2888          */
2889         chip->options |= NAND_NO_AUTOINCR;
2890
2891         /* Check if chip is a not a samsung device. Do not clear the
2892          * options for chips which are not having an extended id.
2893          */
2894         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2895                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2896
2897         /* Check for AND chips with 4 page planes */
2898         if (chip->options & NAND_4PAGE_ARRAY)
2899                 chip->erase_cmd = multi_erase_cmd;
2900         else
2901                 chip->erase_cmd = single_erase_cmd;
2902
2903         /* Do not replace user supplied command function ! */
2904         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2905                 chip->cmdfunc = nand_command_lp;
2906
2907         printk(KERN_INFO "NAND device: Manufacturer ID:"
2908                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2909                nand_manuf_ids[maf_idx].name, type->name);
2910
2911         return type;
2912 }
2913
2914 /**
2915  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2916  * @mtd:             MTD device structure
2917  * @maxchips:        Number of chips to scan for
2918  *
2919  * This is the first phase of the normal nand_scan() function. It
2920  * reads the flash ID and sets up MTD fields accordingly.
2921  *
2922  * The mtd->owner field must be set to the module of the caller.
2923  */
2924 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2925 {
2926         int i, busw, nand_maf_id;
2927         struct nand_chip *chip = mtd->priv;
2928         struct nand_flash_dev *type;
2929
2930         /* Get buswidth to select the correct functions */
2931         busw = chip->options & NAND_BUSWIDTH_16;
2932         /* Set the default functions */
2933         nand_set_defaults(chip, busw);
2934
2935         /* Read the flash type */
2936         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2937
2938         if (IS_ERR(type)) {
2939                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2940                         printk(KERN_WARNING "No NAND device found.\n");
2941                 chip->select_chip(mtd, -1);
2942                 return PTR_ERR(type);
2943         }
2944
2945         /* Check for a chip array */
2946         for (i = 1; i < maxchips; i++) {
2947                 chip->select_chip(mtd, i);
2948                 /* See comment in nand_get_flash_type for reset */
2949                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2950                 /* Send the command for reading device ID */
2951                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2952                 /* Read manufacturer and device IDs */
2953                 if (nand_maf_id != chip->read_byte(mtd) ||
2954                     type->id != chip->read_byte(mtd))
2955                         break;
2956         }
2957         if (i > 1)
2958                 printk(KERN_INFO "%d NAND chips detected\n", i);
2959
2960         /* Store the number of chips and calc total size for mtd */
2961         chip->numchips = i;
2962         mtd->size = i * chip->chipsize;
2963
2964         return 0;
2965 }
2966
2967
2968 /**
2969  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2970  * @mtd:            MTD device structure
2971  *
2972  * This is the second phase of the normal nand_scan() function. It
2973  * fills out all the uninitialized function pointers with the defaults
2974  * and scans for a bad block table if appropriate.
2975  */
2976 int nand_scan_tail(struct mtd_info *mtd)
2977 {
2978         int i;
2979         struct nand_chip *chip = mtd->priv;
2980
2981         if (!(chip->options & NAND_OWN_BUFFERS))
2982                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2983         if (!chip->buffers)
2984                 return -ENOMEM;
2985
2986         /* Set the internal oob buffer location, just after the page data */
2987         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2988
2989         /*
2990          * If no default placement scheme is given, select an appropriate one
2991          */
2992         if (!chip->ecc.layout) {
2993                 switch (mtd->oobsize) {
2994                 case 8:
2995                         chip->ecc.layout = &nand_oob_8;
2996                         break;
2997                 case 16:
2998                         chip->ecc.layout = &nand_oob_16;
2999                         break;
3000                 case 64:
3001                         chip->ecc.layout = &nand_oob_64;
3002                         break;
3003                 case 128:
3004                         chip->ecc.layout = &nand_oob_128;
3005                         break;
3006                 default:
3007                         printk(KERN_WARNING "No oob scheme defined for "
3008                                "oobsize %d\n", mtd->oobsize);
3009                         BUG();
3010                 }
3011         }
3012
3013         if (!chip->write_page)
3014                 chip->write_page = nand_write_page;
3015
3016         /*
3017          * check ECC mode, default to software if 3byte/512byte hardware ECC is
3018          * selected and we have 256 byte pagesize fallback to software ECC
3019          */
3020
3021         switch (chip->ecc.mode) {
3022         case NAND_ECC_HW_OOB_FIRST:
3023                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3024                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3025                      !chip->ecc.hwctl) {
3026                         printk(KERN_WARNING "No ECC functions supplied; "
3027                                "Hardware ECC not possible\n");
3028                         BUG();
3029                 }
3030                 if (!chip->ecc.read_page)
3031                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3032
3033         case NAND_ECC_HW:
3034                 /* Use standard hwecc read page function ? */
3035                 if (!chip->ecc.read_page)
3036                         chip->ecc.read_page = nand_read_page_hwecc;
3037                 if (!chip->ecc.write_page)
3038                         chip->ecc.write_page = nand_write_page_hwecc;
3039                 if (!chip->ecc.read_page_raw)
3040                         chip->ecc.read_page_raw = nand_read_page_raw;
3041                 if (!chip->ecc.write_page_raw)
3042                         chip->ecc.write_page_raw = nand_write_page_raw;
3043                 if (!chip->ecc.read_oob)
3044                         chip->ecc.read_oob = nand_read_oob_std;
3045                 if (!chip->ecc.write_oob)
3046                         chip->ecc.write_oob = nand_write_oob_std;
3047
3048         case NAND_ECC_HW_SYNDROME:
3049                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3050                      !chip->ecc.hwctl) &&
3051                     (!chip->ecc.read_page ||
3052                      chip->ecc.read_page == nand_read_page_hwecc ||
3053                      !chip->ecc.write_page ||
3054                      chip->ecc.write_page == nand_write_page_hwecc)) {
3055                         printk(KERN_WARNING "No ECC functions supplied; "
3056                                "Hardware ECC not possible\n");
3057                         BUG();
3058                 }
3059                 /* Use standard syndrome read/write page function ? */
3060                 if (!chip->ecc.read_page)
3061                         chip->ecc.read_page = nand_read_page_syndrome;
3062                 if (!chip->ecc.write_page)
3063                         chip->ecc.write_page = nand_write_page_syndrome;
3064                 if (!chip->ecc.read_page_raw)
3065                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3066                 if (!chip->ecc.write_page_raw)
3067                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3068                 if (!chip->ecc.read_oob)
3069                         chip->ecc.read_oob = nand_read_oob_syndrome;
3070                 if (!chip->ecc.write_oob)
3071                         chip->ecc.write_oob = nand_write_oob_syndrome;
3072
3073                 if (mtd->writesize >= chip->ecc.size)
3074                         break;
3075                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3076                        "%d byte page size, fallback to SW ECC\n",
3077                        chip->ecc.size, mtd->writesize);
3078                 chip->ecc.mode = NAND_ECC_SOFT;
3079
3080         case NAND_ECC_SOFT:
3081                 chip->ecc.calculate = nand_calculate_ecc;
3082                 chip->ecc.correct = nand_correct_data;
3083                 chip->ecc.read_page = nand_read_page_swecc;
3084                 chip->ecc.read_subpage = nand_read_subpage;
3085                 chip->ecc.write_page = nand_write_page_swecc;
3086                 chip->ecc.read_page_raw = nand_read_page_raw;
3087                 chip->ecc.write_page_raw = nand_write_page_raw;
3088                 chip->ecc.read_oob = nand_read_oob_std;
3089                 chip->ecc.write_oob = nand_write_oob_std;
3090                 if (!chip->ecc.size)
3091                         chip->ecc.size = 256;
3092                 chip->ecc.bytes = 3;
3093                 break;
3094
3095         case NAND_ECC_NONE:
3096                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3097                        "This is not recommended !!\n");
3098                 chip->ecc.read_page = nand_read_page_raw;
3099                 chip->ecc.write_page = nand_write_page_raw;
3100                 chip->ecc.read_oob = nand_read_oob_std;
3101                 chip->ecc.read_page_raw = nand_read_page_raw;
3102                 chip->ecc.write_page_raw = nand_write_page_raw;
3103                 chip->ecc.write_oob = nand_write_oob_std;
3104                 chip->ecc.size = mtd->writesize;
3105                 chip->ecc.bytes = 0;
3106                 break;
3107
3108         default:
3109                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3110                        chip->ecc.mode);
3111                 BUG();
3112         }
3113
3114         /*
3115          * The number of bytes available for a client to place data into
3116          * the out of band area
3117          */
3118         chip->ecc.layout->oobavail = 0;
3119         for (i = 0; chip->ecc.layout->oobfree[i].length
3120                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3121                 chip->ecc.layout->oobavail +=
3122                         chip->ecc.layout->oobfree[i].length;
3123         mtd->oobavail = chip->ecc.layout->oobavail;
3124
3125         /*
3126          * Set the number of read / write steps for one page depending on ECC
3127          * mode
3128          */
3129         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3130         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3131                 printk(KERN_WARNING "Invalid ecc parameters\n");
3132                 BUG();
3133         }
3134         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3135
3136         /*
3137          * Allow subpage writes up to ecc.steps. Not possible for MLC
3138          * FLASH.
3139          */
3140         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3141             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3142                 switch(chip->ecc.steps) {
3143                 case 2:
3144                         mtd->subpage_sft = 1;
3145                         break;
3146                 case 4:
3147                 case 8:
3148                 case 16:
3149                         mtd->subpage_sft = 2;
3150                         break;
3151                 }
3152         }
3153         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3154
3155         /* Initialize state */
3156         chip->state = FL_READY;
3157
3158         /* De-select the device */
3159         chip->select_chip(mtd, -1);
3160
3161         /* Invalidate the pagebuffer reference */
3162         chip->pagebuf = -1;
3163
3164         /* Fill in remaining MTD driver data */
3165         mtd->type = MTD_NANDFLASH;
3166         mtd->flags = MTD_CAP_NANDFLASH;
3167         mtd->erase = nand_erase;
3168         mtd->point = NULL;
3169         mtd->unpoint = NULL;
3170         mtd->read = nand_read;
3171         mtd->write = nand_write;
3172         mtd->panic_write = panic_nand_write;
3173         mtd->read_oob = nand_read_oob;
3174         mtd->write_oob = nand_write_oob;
3175         mtd->sync = nand_sync;
3176         mtd->lock = NULL;
3177         mtd->unlock = NULL;
3178         mtd->suspend = nand_suspend;
3179         mtd->resume = nand_resume;
3180         mtd->block_isbad = nand_block_isbad;
3181         mtd->block_markbad = nand_block_markbad;
3182
3183         /* propagate ecc.layout to mtd_info */
3184         mtd->ecclayout = chip->ecc.layout;
3185
3186         /* Check, if we should skip the bad block table scan */
3187         if (chip->options & NAND_SKIP_BBTSCAN)
3188                 return 0;
3189
3190         /* Build bad block table */
3191         return chip->scan_bbt(mtd);
3192 }
3193
3194 /* is_module_text_address() isn't exported, and it's mostly a pointless
3195    test if this is a module _anyway_ -- they'd have to try _really_ hard
3196    to call us from in-kernel code if the core NAND support is modular. */
3197 #ifdef MODULE
3198 #define caller_is_module() (1)
3199 #else
3200 #define caller_is_module() \
3201         is_module_text_address((unsigned long)__builtin_return_address(0))
3202 #endif
3203
3204 /**
3205  * nand_scan - [NAND Interface] Scan for the NAND device
3206  * @mtd:        MTD device structure
3207  * @maxchips:   Number of chips to scan for
3208  *
3209  * This fills out all the uninitialized function pointers
3210  * with the defaults.
3211  * The flash ID is read and the mtd/chip structures are
3212  * filled with the appropriate values.
3213  * The mtd->owner field must be set to the module of the caller
3214  *
3215  */
3216 int nand_scan(struct mtd_info *mtd, int maxchips)
3217 {
3218         int ret;
3219
3220         /* Many callers got this wrong, so check for it for a while... */
3221         if (!mtd->owner && caller_is_module()) {
3222                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3223                                 __func__);
3224                 BUG();
3225         }
3226
3227         ret = nand_scan_ident(mtd, maxchips);
3228         if (!ret)
3229                 ret = nand_scan_tail(mtd);
3230         return ret;
3231 }
3232
3233 /**
3234  * nand_release - [NAND Interface] Free resources held by the NAND device
3235  * @mtd:        MTD device structure
3236 */
3237 void nand_release(struct mtd_info *mtd)
3238 {
3239         struct nand_chip *chip = mtd->priv;
3240
3241 #ifdef CONFIG_MTD_PARTITIONS
3242         /* Deregister partitions */
3243         del_mtd_partitions(mtd);
3244 #endif
3245         /* Deregister the device */
3246         del_mtd_device(mtd);
3247
3248         /* Free bad block table memory */
3249         kfree(chip->bbt);
3250         if (!(chip->options & NAND_OWN_BUFFERS))
3251                 kfree(chip->buffers);
3252 }
3253
3254 EXPORT_SYMBOL_GPL(nand_lock);
3255 EXPORT_SYMBOL_GPL(nand_unlock);
3256 EXPORT_SYMBOL_GPL(nand_scan);
3257 EXPORT_SYMBOL_GPL(nand_scan_ident);
3258 EXPORT_SYMBOL_GPL(nand_scan_tail);
3259 EXPORT_SYMBOL_GPL(nand_release);
3260
3261 static int __init nand_base_init(void)
3262 {
3263         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3264         return 0;
3265 }
3266
3267 static void __exit nand_base_exit(void)
3268 {
3269         led_trigger_unregister_simple(nand_led_trigger);
3270 }
3271
3272 module_init(nand_base_init);
3273 module_exit(nand_base_exit);
3274
3275 MODULE_LICENSE("GPL");
3276 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3277 MODULE_DESCRIPTION("Generic NAND flash driver code");