2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
40 #define DRIVER_NAME "mxc_nand"
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() cpu_is_mx51()
45 #define nfc_is_v3() nfc_is_v3_2()
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
60 #define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
61 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
62 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
63 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
65 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
66 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
67 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
68 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
69 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
70 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
71 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
72 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
73 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
74 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
76 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
79 * Operation modes for the NFC. Valid for v1, v2 and v3
82 #define NFC_CMD (1 << 0)
83 #define NFC_ADDR (1 << 1)
84 #define NFC_INPUT (1 << 2)
85 #define NFC_OUTPUT (1 << 3)
86 #define NFC_ID (1 << 4)
87 #define NFC_STATUS (1 << 5)
89 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
90 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
92 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
93 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
94 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
96 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
98 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
100 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
101 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
102 #define NFC_V3_WRPROT_LOCK (1 << 1)
103 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
104 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
106 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
108 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
109 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
110 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
111 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
112 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
113 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
114 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
115 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
116 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
117 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
119 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
120 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
121 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
123 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
124 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
125 #define NFC_V3_CONFIG3_FW8 (1 << 3)
126 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
127 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
128 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
129 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
131 #define NFC_V3_IPC (host->regs_ip + 0x2C)
132 #define NFC_V3_IPC_CREQ (1 << 0)
133 #define NFC_V3_IPC_INT (1 << 31)
135 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
137 struct mxc_nand_host {
139 struct nand_chip nand;
140 struct mtd_partition *parts;
148 void __iomem *regs_axi;
149 void __iomem *regs_ip;
156 struct completion op_completion;
159 unsigned int buf_start;
162 void (*preset)(struct mtd_info *);
163 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
164 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
165 void (*send_page)(struct mtd_info *, unsigned int);
166 void (*send_read_id)(struct mxc_nand_host *);
167 uint16_t (*get_dev_status)(struct mxc_nand_host *);
168 int (*check_int)(struct mxc_nand_host *);
169 void (*irq_control)(struct mxc_nand_host *, int);
172 /* OOB placement block for use with hardware ecc generation */
173 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
175 .eccpos = {6, 7, 8, 9, 10},
176 .oobfree = {{0, 5}, {12, 4}, }
179 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
181 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
182 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
183 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
186 /* OOB description for 512 byte pages with 16 byte OOB */
187 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
190 7, 8, 9, 10, 11, 12, 13, 14, 15
193 {.offset = 0, .length = 5}
197 /* OOB description for 2048 byte pages with 64 byte OOB */
198 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
201 7, 8, 9, 10, 11, 12, 13, 14, 15,
202 23, 24, 25, 26, 27, 28, 29, 30, 31,
203 39, 40, 41, 42, 43, 44, 45, 46, 47,
204 55, 56, 57, 58, 59, 60, 61, 62, 63
207 {.offset = 2, .length = 4},
208 {.offset = 16, .length = 7},
209 {.offset = 32, .length = 7},
210 {.offset = 48, .length = 7}
214 #ifdef CONFIG_MTD_PARTITIONS
215 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
218 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
220 struct mxc_nand_host *host = dev_id;
222 if (!host->check_int(host))
225 host->irq_control(host, 0);
227 complete(&host->op_completion);
232 static int check_int_v3(struct mxc_nand_host *host)
236 tmp = readl(NFC_V3_IPC);
237 if (!(tmp & NFC_V3_IPC_INT))
240 tmp &= ~NFC_V3_IPC_INT;
241 writel(tmp, NFC_V3_IPC);
246 static int check_int_v1_v2(struct mxc_nand_host *host)
250 tmp = readw(NFC_V1_V2_CONFIG2);
251 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
255 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
261 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
262 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
263 * driver can enable/disable the irq line rather than simply masking the
266 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
269 enable_irq(host->irq);
271 disable_irq_nosync(host->irq);
274 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
278 tmp = readw(NFC_V1_V2_CONFIG1);
281 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
283 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
285 writew(tmp, NFC_V1_V2_CONFIG1);
288 static void irq_control_v3(struct mxc_nand_host *host, int activate)
292 tmp = readl(NFC_V3_CONFIG2);
295 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
297 tmp |= NFC_V3_CONFIG2_INT_MSK;
299 writel(tmp, NFC_V3_CONFIG2);
302 /* This function polls the NANDFC to wait for the basic operation to
303 * complete by checking the INT bit of config2 register.
305 static void wait_op_done(struct mxc_nand_host *host, int useirq)
307 int max_retries = 8000;
310 if (!host->check_int(host)) {
311 INIT_COMPLETION(host->op_completion);
312 host->irq_control(host, 1);
313 wait_for_completion(&host->op_completion);
316 while (max_retries-- > 0) {
317 if (host->check_int(host))
323 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
328 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
331 writel(cmd, NFC_V3_FLASH_CMD);
333 /* send out command */
334 writel(NFC_CMD, NFC_V3_LAUNCH);
336 /* Wait for operation to complete */
337 wait_op_done(host, useirq);
340 /* This function issues the specified command to the NAND device and
341 * waits for completion. */
342 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
344 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
346 writew(cmd, NFC_V1_V2_FLASH_CMD);
347 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
349 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
350 int max_retries = 100;
351 /* Reset completion is indicated by NFC_CONFIG2 */
353 while (max_retries-- > 0) {
354 if (readw(NFC_V1_V2_CONFIG2) == 0) {
360 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
363 /* Wait for operation to complete */
364 wait_op_done(host, useirq);
368 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
371 writel(addr, NFC_V3_FLASH_ADDR0);
373 /* send out address */
374 writel(NFC_ADDR, NFC_V3_LAUNCH);
376 wait_op_done(host, 0);
379 /* This function sends an address (or partial address) to the
380 * NAND device. The address is used to select the source/destination for
382 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
384 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
386 writew(addr, NFC_V1_V2_FLASH_ADDR);
387 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
389 /* Wait for operation to complete */
390 wait_op_done(host, islast);
393 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
395 struct nand_chip *nand_chip = mtd->priv;
396 struct mxc_nand_host *host = nand_chip->priv;
399 tmp = readl(NFC_V3_CONFIG1);
401 writel(tmp, NFC_V3_CONFIG1);
403 /* transfer data from NFC ram to nand */
404 writel(ops, NFC_V3_LAUNCH);
406 wait_op_done(host, false);
409 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
411 struct nand_chip *nand_chip = mtd->priv;
412 struct mxc_nand_host *host = nand_chip->priv;
415 if (nfc_is_v1() && mtd->writesize > 512)
420 for (i = 0; i < bufs; i++) {
422 /* NANDFC buffer 0 is used for page read/write */
423 writew(i, NFC_V1_V2_BUF_ADDR);
425 writew(ops, NFC_V1_V2_CONFIG2);
427 /* Wait for operation to complete */
428 wait_op_done(host, true);
432 static void send_read_id_v3(struct mxc_nand_host *host)
434 /* Read ID into main buffer */
435 writel(NFC_ID, NFC_V3_LAUNCH);
437 wait_op_done(host, true);
439 memcpy(host->data_buf, host->main_area0, 16);
442 /* Request the NANDFC to perform a read of the NAND device ID. */
443 static void send_read_id_v1_v2(struct mxc_nand_host *host)
445 struct nand_chip *this = &host->nand;
447 /* NANDFC buffer 0 is used for device ID output */
448 writew(0x0, NFC_V1_V2_BUF_ADDR);
450 writew(NFC_ID, NFC_V1_V2_CONFIG2);
452 /* Wait for operation to complete */
453 wait_op_done(host, true);
455 memcpy(host->data_buf, host->main_area0, 16);
457 if (this->options & NAND_BUSWIDTH_16) {
458 /* compress the ID info */
459 host->data_buf[1] = host->data_buf[2];
460 host->data_buf[2] = host->data_buf[4];
461 host->data_buf[3] = host->data_buf[6];
462 host->data_buf[4] = host->data_buf[8];
463 host->data_buf[5] = host->data_buf[10];
467 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
469 writew(NFC_STATUS, NFC_V3_LAUNCH);
470 wait_op_done(host, true);
472 return readl(NFC_V3_CONFIG1) >> 16;
475 /* This function requests the NANDFC to perform a read of the
476 * NAND device status and returns the current status. */
477 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
479 void __iomem *main_buf = host->main_area0;
483 writew(0x0, NFC_V1_V2_BUF_ADDR);
486 * The device status is stored in main_area0. To
487 * prevent corruption of the buffer save the value
488 * and restore it afterwards.
490 store = readl(main_buf);
492 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
493 wait_op_done(host, true);
495 ret = readw(main_buf);
497 writel(store, main_buf);
502 /* This functions is used by upper layer to checks if device is ready */
503 static int mxc_nand_dev_ready(struct mtd_info *mtd)
506 * NFC handles R/B internally. Therefore, this function
507 * always returns status as ready.
512 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
515 * If HW ECC is enabled, we turn it on during init. There is
516 * no need to enable again here.
520 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
521 u_char *read_ecc, u_char *calc_ecc)
523 struct nand_chip *nand_chip = mtd->priv;
524 struct mxc_nand_host *host = nand_chip->priv;
527 * 1-Bit errors are automatically corrected in HW. No need for
528 * additional correction. 2-Bit errors cannot be corrected by
529 * HW ECC, so we need to return failure
531 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
533 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
534 DEBUG(MTD_DEBUG_LEVEL0,
535 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
542 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
543 u_char *read_ecc, u_char *calc_ecc)
545 struct nand_chip *nand_chip = mtd->priv;
546 struct mxc_nand_host *host = nand_chip->priv;
550 u8 ecc_bit_mask, err_limit;
552 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
553 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
555 no_subpages = mtd->writesize >> 9;
558 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
560 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
563 err = ecc_stat & ecc_bit_mask;
564 if (err > err_limit) {
565 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
571 } while (--no_subpages);
573 mtd->ecc_stats.corrected += ret;
574 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
579 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
585 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
587 struct nand_chip *nand_chip = mtd->priv;
588 struct mxc_nand_host *host = nand_chip->priv;
591 /* Check for status request */
592 if (host->status_request)
593 return host->get_dev_status(host) & 0xFF;
595 ret = *(uint8_t *)(host->data_buf + host->buf_start);
601 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
603 struct nand_chip *nand_chip = mtd->priv;
604 struct mxc_nand_host *host = nand_chip->priv;
607 ret = *(uint16_t *)(host->data_buf + host->buf_start);
608 host->buf_start += 2;
613 /* Write data of length len to buffer buf. The data to be
614 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
615 * Operation by the NFC, the data is written to NAND Flash */
616 static void mxc_nand_write_buf(struct mtd_info *mtd,
617 const u_char *buf, int len)
619 struct nand_chip *nand_chip = mtd->priv;
620 struct mxc_nand_host *host = nand_chip->priv;
621 u16 col = host->buf_start;
622 int n = mtd->oobsize + mtd->writesize - col;
626 memcpy(host->data_buf + col, buf, n);
628 host->buf_start += n;
631 /* Read the data buffer from the NAND Flash. To read the data from NAND
632 * Flash first the data output cycle is initiated by the NFC, which copies
633 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
635 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
637 struct nand_chip *nand_chip = mtd->priv;
638 struct mxc_nand_host *host = nand_chip->priv;
639 u16 col = host->buf_start;
640 int n = mtd->oobsize + mtd->writesize - col;
644 memcpy(buf, host->data_buf + col, len);
646 host->buf_start += len;
649 /* Used by the upper layer to verify the data in NAND Flash
650 * with the data in the buf. */
651 static int mxc_nand_verify_buf(struct mtd_info *mtd,
652 const u_char *buf, int len)
657 /* This function is used by upper layer for select and
658 * deselect of the NAND chip */
659 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
661 struct nand_chip *nand_chip = mtd->priv;
662 struct mxc_nand_host *host = nand_chip->priv;
666 /* Disable the NFC clock */
668 clk_disable(host->clk);
673 /* Enable the NFC clock */
674 if (!host->clk_act) {
675 clk_enable(host->clk);
686 * Function to transfer data to/from spare area.
688 static void copy_spare(struct mtd_info *mtd, bool bfrom)
690 struct nand_chip *this = mtd->priv;
691 struct mxc_nand_host *host = this->priv;
693 u16 n = mtd->writesize >> 9;
694 u8 *d = host->data_buf + mtd->writesize;
695 u8 *s = host->spare0;
696 u16 t = host->spare_len;
698 j = (mtd->oobsize / n >> 1) << 1;
701 for (i = 0; i < n - 1; i++)
702 memcpy(d + i * j, s + i * t, j);
704 /* the last section */
705 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
707 for (i = 0; i < n - 1; i++)
708 memcpy(&s[i * t], &d[i * j], j);
710 /* the last section */
711 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
715 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
717 struct nand_chip *nand_chip = mtd->priv;
718 struct mxc_nand_host *host = nand_chip->priv;
720 /* Write out column address, if necessary */
723 * MXC NANDFC can only perform full page+spare or
724 * spare-only read/write. When the upper layers
725 * perform a read/write buf operation, the saved column
726 * address is used to index into the full page.
728 host->send_addr(host, 0, page_addr == -1);
729 if (mtd->writesize > 512)
730 /* another col addr cycle for 2k page */
731 host->send_addr(host, 0, false);
734 /* Write out page address, if necessary */
735 if (page_addr != -1) {
736 /* paddr_0 - p_addr_7 */
737 host->send_addr(host, (page_addr & 0xff), false);
739 if (mtd->writesize > 512) {
740 if (mtd->size >= 0x10000000) {
741 /* paddr_8 - paddr_15 */
742 host->send_addr(host, (page_addr >> 8) & 0xff, false);
743 host->send_addr(host, (page_addr >> 16) & 0xff, true);
745 /* paddr_8 - paddr_15 */
746 host->send_addr(host, (page_addr >> 8) & 0xff, true);
748 /* One more address cycle for higher density devices */
749 if (mtd->size >= 0x4000000) {
750 /* paddr_8 - paddr_15 */
751 host->send_addr(host, (page_addr >> 8) & 0xff, false);
752 host->send_addr(host, (page_addr >> 16) & 0xff, true);
754 /* paddr_8 - paddr_15 */
755 host->send_addr(host, (page_addr >> 8) & 0xff, true);
761 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
762 * on how much oob the nand chip has. For 8bit ecc we need at least
763 * 26 bytes of oob data per 512 byte block.
765 static int get_eccsize(struct mtd_info *mtd)
767 int oobbytes_per_512 = 0;
769 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
771 if (oobbytes_per_512 < 26)
777 static void preset_v1_v2(struct mtd_info *mtd)
779 struct nand_chip *nand_chip = mtd->priv;
780 struct mxc_nand_host *host = nand_chip->priv;
781 uint16_t config1 = 0;
783 if (nand_chip->ecc.mode == NAND_ECC_HW)
784 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
787 config1 |= NFC_V2_CONFIG1_FP_INT;
790 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
792 if (nfc_is_v21() && mtd->writesize) {
793 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
795 host->eccsize = get_eccsize(mtd);
796 if (host->eccsize == 4)
797 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
799 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
804 writew(config1, NFC_V1_V2_CONFIG1);
805 /* preset operation */
807 /* Unlock the internal RAM Buffer */
808 writew(0x2, NFC_V1_V2_CONFIG);
810 /* Blocks to be unlocked */
812 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
813 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
814 } else if (nfc_is_v1()) {
815 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
816 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
820 /* Unlock Block Command for given address range */
821 writew(0x4, NFC_V1_V2_WRPROT);
824 static void preset_v3(struct mtd_info *mtd)
826 struct nand_chip *chip = mtd->priv;
827 struct mxc_nand_host *host = chip->priv;
828 uint32_t config2, config3;
831 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
832 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
834 /* Unlock the internal RAM Buffer */
835 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
838 /* Blocks to be unlocked */
839 for (i = 0; i < NAND_MAX_CHIPS; i++)
840 writel(0x0 | (0xffff << 16),
841 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
843 writel(0, NFC_V3_IPC);
845 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
846 NFC_V3_CONFIG2_2CMD_PHASES |
847 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
848 NFC_V3_CONFIG2_ST_CMD(0x70) |
849 NFC_V3_CONFIG2_INT_MSK |
850 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
852 if (chip->ecc.mode == NAND_ECC_HW)
853 config2 |= NFC_V3_CONFIG2_ECC_EN;
855 addr_phases = fls(chip->pagemask) >> 3;
857 if (mtd->writesize == 2048) {
858 config2 |= NFC_V3_CONFIG2_PS_2048;
859 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
860 } else if (mtd->writesize == 4096) {
861 config2 |= NFC_V3_CONFIG2_PS_4096;
862 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
864 config2 |= NFC_V3_CONFIG2_PS_512;
865 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
868 if (mtd->writesize) {
869 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
870 host->eccsize = get_eccsize(mtd);
871 if (host->eccsize == 8)
872 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
875 writel(config2, NFC_V3_CONFIG2);
877 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
878 NFC_V3_CONFIG3_NO_SDMA |
879 NFC_V3_CONFIG3_RBB_MODE |
880 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
881 NFC_V3_CONFIG3_ADD_OP(0);
883 if (!(chip->options & NAND_BUSWIDTH_16))
884 config3 |= NFC_V3_CONFIG3_FW8;
886 writel(config3, NFC_V3_CONFIG3);
888 writel(0, NFC_V3_DELAY_LINE);
891 /* Used by the upper layer to write command to NAND Flash for
892 * different operations to be carried out on NAND Flash */
893 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
894 int column, int page_addr)
896 struct nand_chip *nand_chip = mtd->priv;
897 struct mxc_nand_host *host = nand_chip->priv;
899 DEBUG(MTD_DEBUG_LEVEL3,
900 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
901 command, column, page_addr);
903 /* Reset command state information */
904 host->status_request = false;
906 /* Command pre-processing step */
910 host->send_cmd(host, command, false);
913 case NAND_CMD_STATUS:
915 host->status_request = true;
917 host->send_cmd(host, command, true);
918 mxc_do_addr_cycle(mtd, column, page_addr);
922 case NAND_CMD_READOOB:
923 if (command == NAND_CMD_READ0)
924 host->buf_start = column;
926 host->buf_start = column + mtd->writesize;
928 command = NAND_CMD_READ0; /* only READ0 is valid */
930 host->send_cmd(host, command, false);
931 mxc_do_addr_cycle(mtd, column, page_addr);
933 if (mtd->writesize > 512)
934 host->send_cmd(host, NAND_CMD_READSTART, true);
936 host->send_page(mtd, NFC_OUTPUT);
938 memcpy(host->data_buf, host->main_area0, mtd->writesize);
939 copy_spare(mtd, true);
943 if (column >= mtd->writesize)
944 /* call ourself to read a page */
945 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
947 host->buf_start = column;
949 host->send_cmd(host, command, false);
950 mxc_do_addr_cycle(mtd, column, page_addr);
953 case NAND_CMD_PAGEPROG:
954 memcpy(host->main_area0, host->data_buf, mtd->writesize);
955 copy_spare(mtd, false);
956 host->send_page(mtd, NFC_INPUT);
957 host->send_cmd(host, command, true);
958 mxc_do_addr_cycle(mtd, column, page_addr);
961 case NAND_CMD_READID:
962 host->send_cmd(host, command, true);
963 mxc_do_addr_cycle(mtd, column, page_addr);
964 host->send_read_id(host);
965 host->buf_start = column;
968 case NAND_CMD_ERASE1:
969 case NAND_CMD_ERASE2:
970 host->send_cmd(host, command, false);
971 mxc_do_addr_cycle(mtd, column, page_addr);
978 * The generic flash bbt decriptors overlap with our ecc
979 * hardware, so define some i.MX specific ones.
981 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
982 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
984 static struct nand_bbt_descr bbt_main_descr = {
985 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
986 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
991 .pattern = bbt_pattern,
994 static struct nand_bbt_descr bbt_mirror_descr = {
995 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
996 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1001 .pattern = mirror_pattern,
1004 static int __init mxcnd_probe(struct platform_device *pdev)
1006 struct nand_chip *this;
1007 struct mtd_info *mtd;
1008 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1009 struct mxc_nand_host *host;
1010 struct resource *res;
1011 int err = 0, __maybe_unused nr_parts = 0;
1012 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1014 /* Allocate memory for MTD device structure and private data */
1015 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1016 NAND_MAX_OOBSIZE, GFP_KERNEL);
1020 host->data_buf = (uint8_t *)(host + 1);
1022 host->dev = &pdev->dev;
1023 /* structures must be linked */
1027 mtd->owner = THIS_MODULE;
1028 mtd->dev.parent = &pdev->dev;
1029 mtd->name = DRIVER_NAME;
1031 /* 50 us command delay time */
1032 this->chip_delay = 5;
1035 this->dev_ready = mxc_nand_dev_ready;
1036 this->cmdfunc = mxc_nand_command;
1037 this->select_chip = mxc_nand_select_chip;
1038 this->read_byte = mxc_nand_read_byte;
1039 this->read_word = mxc_nand_read_word;
1040 this->write_buf = mxc_nand_write_buf;
1041 this->read_buf = mxc_nand_read_buf;
1042 this->verify_buf = mxc_nand_verify_buf;
1044 host->clk = clk_get(&pdev->dev, "nfc");
1045 if (IS_ERR(host->clk)) {
1046 err = PTR_ERR(host->clk);
1050 clk_enable(host->clk);
1053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1059 host->base = ioremap(res->start, resource_size(res));
1065 host->main_area0 = host->base;
1067 if (nfc_is_v1() || nfc_is_v21()) {
1068 host->preset = preset_v1_v2;
1069 host->send_cmd = send_cmd_v1_v2;
1070 host->send_addr = send_addr_v1_v2;
1071 host->send_page = send_page_v1_v2;
1072 host->send_read_id = send_read_id_v1_v2;
1073 host->get_dev_status = get_dev_status_v1_v2;
1074 host->check_int = check_int_v1_v2;
1076 host->irq_control = irq_control_mx21;
1078 host->irq_control = irq_control_v1_v2;
1082 host->regs = host->base + 0x1e00;
1083 host->spare0 = host->base + 0x1000;
1084 host->spare_len = 64;
1085 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1086 oob_largepage = &nandv2_hw_eccoob_largepage;
1087 this->ecc.bytes = 9;
1088 } else if (nfc_is_v1()) {
1089 host->regs = host->base + 0xe00;
1090 host->spare0 = host->base + 0x800;
1091 host->spare_len = 16;
1092 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1093 oob_largepage = &nandv1_hw_eccoob_largepage;
1094 this->ecc.bytes = 3;
1096 } else if (nfc_is_v3_2()) {
1097 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1102 host->regs_ip = ioremap(res->start, resource_size(res));
1103 if (!host->regs_ip) {
1107 host->regs_axi = host->base + 0x1e00;
1108 host->spare0 = host->base + 0x1000;
1109 host->spare_len = 64;
1110 host->preset = preset_v3;
1111 host->send_cmd = send_cmd_v3;
1112 host->send_addr = send_addr_v3;
1113 host->send_page = send_page_v3;
1114 host->send_read_id = send_read_id_v3;
1115 host->check_int = check_int_v3;
1116 host->get_dev_status = get_dev_status_v3;
1117 host->irq_control = irq_control_v3;
1118 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1119 oob_largepage = &nandv2_hw_eccoob_largepage;
1123 this->ecc.size = 512;
1124 this->ecc.layout = oob_smallpage;
1126 if (pdata->hw_ecc) {
1127 this->ecc.calculate = mxc_nand_calculate_ecc;
1128 this->ecc.hwctl = mxc_nand_enable_hwecc;
1130 this->ecc.correct = mxc_nand_correct_data_v1;
1132 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1133 this->ecc.mode = NAND_ECC_HW;
1135 this->ecc.mode = NAND_ECC_SOFT;
1138 /* NAND bus width determines access funtions used by upper layer */
1139 if (pdata->width == 2)
1140 this->options |= NAND_BUSWIDTH_16;
1142 if (pdata->flash_bbt) {
1143 this->bbt_td = &bbt_main_descr;
1144 this->bbt_md = &bbt_mirror_descr;
1145 /* update flash based bbt */
1146 this->options |= NAND_USE_FLASH_BBT;
1149 init_completion(&host->op_completion);
1151 host->irq = platform_get_irq(pdev, 0);
1154 * mask the interrupt. For i.MX21 explicitely call
1155 * irq_control_v1_v2 to use the mask bit. We can't call
1156 * disable_irq_nosync() for an interrupt we do not own yet.
1159 irq_control_v1_v2(host, 0);
1161 host->irq_control(host, 0);
1163 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1167 host->irq_control(host, 0);
1170 * Now that the interrupt is disabled make sure the interrupt
1171 * mask bit is cleared on i.MX21. Otherwise we can't read
1172 * the interrupt status bit on this machine.
1175 irq_control_v1_v2(host, 1);
1177 /* first scan to find the device and get the page size */
1178 if (nand_scan_ident(mtd, 1, NULL)) {
1183 /* Call preset again, with correct writesize this time */
1186 if (mtd->writesize == 2048)
1187 this->ecc.layout = oob_largepage;
1189 /* second phase scan */
1190 if (nand_scan_tail(mtd)) {
1195 /* Register the partitions */
1196 #ifdef CONFIG_MTD_PARTITIONS
1198 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1200 add_mtd_partitions(mtd, host->parts, nr_parts);
1201 else if (pdata->parts)
1202 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1206 pr_info("Registering %s as whole device\n", mtd->name);
1207 add_mtd_device(mtd);
1210 platform_set_drvdata(pdev, host);
1215 free_irq(host->irq, host);
1218 iounmap(host->regs_ip);
1219 iounmap(host->base);
1228 static int __devexit mxcnd_remove(struct platform_device *pdev)
1230 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1234 platform_set_drvdata(pdev, NULL);
1236 nand_release(&host->mtd);
1237 free_irq(host->irq, host);
1239 iounmap(host->regs_ip);
1240 iounmap(host->base);
1246 static struct platform_driver mxcnd_driver = {
1248 .name = DRIVER_NAME,
1250 .remove = __devexit_p(mxcnd_remove),
1253 static int __init mxc_nd_init(void)
1255 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1258 static void __exit mxc_nd_cleanup(void)
1260 /* Unregister the device structure */
1261 platform_driver_unregister(&mxcnd_driver);
1264 module_init(mxc_nd_init);
1265 module_exit(mxc_nd_cleanup);
1267 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1268 MODULE_DESCRIPTION("MXC NAND MTD driver");
1269 MODULE_LICENSE("GPL");