1 /*****************************************************************************
2 * Copyright 2004 - 2009 Broadcom Corporation. All rights reserved.
4 * Unless you and Broadcom execute a separate written software license
5 * agreement governing use of this software, this software is licensed to you
6 * under the terms of the GNU General Public License version 2, available at
7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
9 * Notwithstanding the above, under no circumstances may you combine this
10 * software in any way with any other Broadcom software provided under a
11 * license other than the GPL, without Broadcom's express prior written
13 *****************************************************************************/
15 /* ---- Include Files ---------------------------------------------------- */
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/string.h>
22 #include <linux/ioport.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/nand_ecc.h>
31 #include <linux/mtd/partitions.h>
33 #include <asm/mach-types.h>
34 #include <asm/system.h>
36 #include <mach/reg_nand.h>
37 #include <mach/reg_umi.h>
39 #include "nand_bcm_umi.h"
41 #include <mach/memory_settings.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/completion.h>
48 /* ---- External Variable Declarations ----------------------------------- */
49 /* ---- External Function Prototypes ------------------------------------- */
50 /* ---- Public Variables ------------------------------------------------- */
51 /* ---- Private Constants and Types -------------------------------------- */
52 static const __devinitconst char gBanner[] = KERN_INFO \
53 "BCM UMI MTD NAND Driver: 1.00\n";
56 static uint8_t scan_ff_pattern[] = { 0xff };
58 static struct nand_bbt_descr largepage_bbt = {
62 .pattern = scan_ff_pattern
67 ** Preallocate a buffer to avoid having to do this every dma operation.
68 ** This is the size of the preallocated coherent DMA buffer.
71 #define DMA_MIN_BUFLEN 512
72 #define DMA_MAX_BUFLEN PAGE_SIZE
73 #define USE_DIRECT_IO(len) (((len) < DMA_MIN_BUFLEN) || \
74 ((len) > DMA_MAX_BUFLEN))
77 * The current NAND data space goes from 0x80001900 to 0x80001FFF,
78 * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
79 * size NAND flash. Need to break the DMA down to multiple 1Ks.
81 * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
83 #define DMA_MAX_LEN 1024
86 #define DMA_MIN_BUFLEN 0
87 #define DMA_MAX_BUFLEN 0
88 #define USE_DIRECT_IO(len) 1
90 /* ---- Private Function Prototypes -------------------------------------- */
91 static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
92 static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
95 /* ---- Private Variables ------------------------------------------------ */
96 static struct mtd_info *board_mtd;
97 static void __iomem *bcm_umi_io_base;
99 static dma_addr_t physPtr;
100 static struct completion nand_comp;
102 /* ---- Private Functions ------------------------------------------------ */
104 #include "bcm_umi_bch.c"
106 #include "bcm_umi_hamming.c"
111 /* Handler called when the DMA finishes. */
112 static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
114 complete(&nand_comp);
117 static int nand_dma_init(void)
121 rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
122 nand_dma_handler, NULL);
124 printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
129 dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
130 if (virtPtr == NULL) {
131 printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
138 static void nand_dma_term(void)
141 dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
144 static void nand_dma_read(void *buf, int len)
152 panic("nand_dma_read: virtPtr == NULL\n");
154 if ((void *)physPtr == NULL)
155 panic("nand_dma_read: physPtr == NULL\n");
157 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
160 "nand_dma_read: unable to allocate dma channel: %d\n",
165 while (len_left > 0) {
166 if (len_left > DMA_MAX_LEN) {
167 tmp_len = DMA_MAX_LEN;
168 len_left -= DMA_MAX_LEN;
174 init_completion(&nand_comp);
175 dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
176 physPtr + offset, tmp_len);
177 wait_for_completion(&nand_comp);
182 dma_free_channel(hndl);
185 memcpy(buf, virtPtr, len);
188 static void nand_dma_write(const void *buf, int len)
196 panic("nand_dma_write: buf == NULL\n");
199 panic("nand_dma_write: virtPtr == NULL\n");
201 if ((void *)physPtr == NULL)
202 panic("nand_dma_write: physPtr == NULL\n");
204 memcpy(virtPtr, buf, len);
207 hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
210 "nand_dma_write: unable to allocate dma channel: %d\n",
215 while (len_left > 0) {
216 if (len_left > DMA_MAX_LEN) {
217 tmp_len = DMA_MAX_LEN;
218 len_left -= DMA_MAX_LEN;
224 init_completion(&nand_comp);
225 dma_transfer_mem_to_mem(hndl, physPtr + offset,
226 REG_NAND_DATA_PADDR, tmp_len);
227 wait_for_completion(&nand_comp);
232 dma_free_channel(hndl);
237 static int nand_dev_ready(struct mtd_info *mtd)
239 return nand_bcm_umi_dev_ready();
242 /****************************************************************************
244 * bcm_umi_nand_inithw
246 * This routine does the necessary hardware (board-specific)
247 * initializations. This includes setting up the timings, etc.
249 ***************************************************************************/
250 int bcm_umi_nand_inithw(void)
252 /* Configure nand timing parameters */
253 REG_UMI_NAND_TCR &= ~0x7ffff;
254 REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
256 #if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
257 /* enable software control of CS */
258 REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
261 /* keep NAND chip select asserted */
262 REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
264 REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
265 /* enable writes to flash */
266 REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
268 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
269 nand_bcm_umi_wait_till_ready();
272 nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
278 /* Used to turn latch the proper register for access. */
279 static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
282 /* send command to hardware */
283 struct nand_chip *chip = mtd->priv;
284 if (ctrl & NAND_CTRL_CHANGE) {
285 if (ctrl & NAND_CLE) {
286 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
289 if (ctrl & NAND_ALE) {
291 bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
294 chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
298 /* Send command to chip directly */
299 if (cmd != NAND_CMD_NONE)
300 writeb(cmd, chip->IO_ADDR_W);
303 static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
306 if (USE_DIRECT_IO(len)) {
307 /* Do it the old way if the buffer is small or too large.
308 * Probably quicker than starting and checking dma. */
310 struct nand_chip *this = mtd->priv;
312 for (i = 0; i < len; i++)
313 writeb(buf[i], this->IO_ADDR_W);
317 nand_dma_write(buf, len);
321 static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
323 if (USE_DIRECT_IO(len)) {
325 struct nand_chip *this = mtd->priv;
327 for (i = 0; i < len; i++)
328 buf[i] = readb(this->IO_ADDR_R);
332 nand_dma_read(buf, len);
336 static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
337 static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
341 * Try to readback page with ECC correction. This is necessary
342 * for MLC parts which may have permanently stuck bits.
344 struct nand_chip *chip = mtd->priv;
345 int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0);
349 if (memcmp(readbackbuf, buf, len) == 0)
357 static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
359 struct nand_chip *this;
365 /* Allocate memory for MTD device structure and private data */
367 kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
371 "Unable to allocate NAND MTD device structure.\n");
375 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 /* map physical address */
383 bcm_umi_io_base = ioremap(r->start, resource_size(r));
385 if (!bcm_umi_io_base) {
386 printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
391 /* Get pointer to private data */
392 this = (struct nand_chip *)(&board_mtd[1]);
394 /* Initialize structures */
395 memset((char *)board_mtd, 0, sizeof(struct mtd_info));
396 memset((char *)this, 0, sizeof(struct nand_chip));
398 /* Link the private data with the MTD structure */
399 board_mtd->priv = this;
401 /* Initialize the NAND hardware. */
402 if (bcm_umi_nand_inithw() < 0) {
403 printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
408 /* Set address of NAND IO lines */
409 this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
410 this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
412 /* Set command delay time, see datasheet for correct value */
413 this->chip_delay = 0;
414 /* Assign the device ready function, if available */
415 this->dev_ready = nand_dev_ready;
418 this->write_buf = bcm_umi_nand_write_buf;
419 this->read_buf = bcm_umi_nand_read_buf;
420 this->verify_buf = bcm_umi_nand_verify_buf;
422 this->cmd_ctrl = bcm_umi_nand_hwcontrol;
423 this->ecc.mode = NAND_ECC_HW;
424 this->ecc.size = 512;
425 this->ecc.bytes = NAND_ECC_NUM_BYTES;
427 this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
428 this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
430 this->ecc.correct = nand_correct_data512;
431 this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
432 this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
436 err = nand_dma_init();
441 /* Figure out the size of the device that we have.
442 * We need to do this to figure out which ECC
443 * layout we'll be using.
446 err = nand_scan_ident(board_mtd, 1, NULL);
448 printk(KERN_ERR "nand_scan failed: %d\n", err);
452 /* Now that we know the nand size, we can setup the ECC layout */
454 switch (board_mtd->writesize) { /* writesize is the pagesize */
456 this->ecc.layout = &nand_hw_eccoob_4096;
459 this->ecc.layout = &nand_hw_eccoob_2048;
462 this->ecc.layout = &nand_hw_eccoob_512;
466 printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
467 board_mtd->writesize);
474 if (board_mtd->writesize > 512) {
475 if (this->bbt_options & NAND_BBT_USE_FLASH)
476 largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
477 this->badblock_pattern = &largepage_bbt;
481 * FIXME: ecc strength value of 6 bits per 512 bytes of data is a
482 * conservative guess, given 13 ecc bytes and using bch alg.
483 * (Assume Galois field order m=15 to allow a margin of error.)
485 this->ecc.strength = 6;
489 /* Now finish off the scan, now that ecc.layout has been initialized. */
491 err = nand_scan_tail(board_mtd);
493 printk(KERN_ERR "nand_scan failed: %d\n", err);
497 /* Register the partitions */
498 board_mtd->name = "bcm_umi-nand";
499 mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
504 iounmap(bcm_umi_io_base);
510 static int bcm_umi_nand_remove(struct platform_device *pdev)
516 /* Release resources, unregister device */
517 nand_release(board_mtd);
519 /* unmap physical address */
520 iounmap(bcm_umi_io_base);
522 /* Free the MTD device structure */
529 static int bcm_umi_nand_suspend(struct platform_device *pdev,
532 printk(KERN_ERR "MTD NAND suspend is being called\n");
536 static int bcm_umi_nand_resume(struct platform_device *pdev)
538 printk(KERN_ERR "MTD NAND resume is being called\n");
542 #define bcm_umi_nand_suspend NULL
543 #define bcm_umi_nand_resume NULL
546 static struct platform_driver nand_driver = {
549 .owner = THIS_MODULE,
551 .probe = bcm_umi_nand_probe,
552 .remove = bcm_umi_nand_remove,
553 .suspend = bcm_umi_nand_suspend,
554 .resume = bcm_umi_nand_resume,
557 module_platform_driver(nand_driver);
559 MODULE_LICENSE("GPL");
560 MODULE_AUTHOR("Broadcom");
561 MODULE_DESCRIPTION("BCM UMI MTD NAND driver");