2 * drivers/mtd/nand/au1550nd.c
4 * Copyright (C) 2004 Embedded Edge, LLC
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/slab.h>
13 #include <linux/gpio.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/mtd/partitions.h>
22 #ifdef CONFIG_MIPS_PB1550
23 #include <asm/mach-pb1x00/pb1550.h>
24 #elif defined(CONFIG_MIPS_DB1550)
25 #include <asm/mach-db1x00/db1x00.h>
27 #include <asm/mach-db1x00/bcsr.h>
30 * MTD structure for NAND controller
32 static struct mtd_info *au1550_mtd = NULL;
33 static void __iomem *p_nand;
34 static int nand_width = 1; /* default x8 */
35 static void (*au1550_write_byte)(struct mtd_info *, u_char);
38 * Define partitions for flash device
40 static const struct mtd_partition partition_info[] = {
44 .size = 8 * 1024 * 1024},
47 .offset = MTDPART_OFS_APPEND,
48 .size = MTDPART_SIZ_FULL}
52 * au_read_byte - read one byte from the chip
53 * @mtd: MTD device structure
55 * read function for 8bit buswidth
57 static u_char au_read_byte(struct mtd_info *mtd)
59 struct nand_chip *this = mtd->priv;
60 u_char ret = readb(this->IO_ADDR_R);
66 * au_write_byte - write one byte to the chip
67 * @mtd: MTD device structure
68 * @byte: pointer to data byte to write
70 * write function for 8it buswidth
72 static void au_write_byte(struct mtd_info *mtd, u_char byte)
74 struct nand_chip *this = mtd->priv;
75 writeb(byte, this->IO_ADDR_W);
80 * au_read_byte16 - read one byte endianness aware from the chip
81 * @mtd: MTD device structure
83 * read function for 16bit buswidth with endianness conversion
85 static u_char au_read_byte16(struct mtd_info *mtd)
87 struct nand_chip *this = mtd->priv;
88 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
94 * au_write_byte16 - write one byte endianness aware to the chip
95 * @mtd: MTD device structure
96 * @byte: pointer to data byte to write
98 * write function for 16bit buswidth with endianness conversion
100 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
102 struct nand_chip *this = mtd->priv;
103 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
108 * au_read_word - read one word from the chip
109 * @mtd: MTD device structure
111 * read function for 16bit buswidth without endianness conversion
113 static u16 au_read_word(struct mtd_info *mtd)
115 struct nand_chip *this = mtd->priv;
116 u16 ret = readw(this->IO_ADDR_R);
122 * au_write_buf - write buffer to chip
123 * @mtd: MTD device structure
125 * @len: number of bytes to write
127 * write function for 8bit buswidth
129 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
132 struct nand_chip *this = mtd->priv;
134 for (i = 0; i < len; i++) {
135 writeb(buf[i], this->IO_ADDR_W);
141 * au_read_buf - read chip data into buffer
142 * @mtd: MTD device structure
143 * @buf: buffer to store date
144 * @len: number of bytes to read
146 * read function for 8bit buswidth
148 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
151 struct nand_chip *this = mtd->priv;
153 for (i = 0; i < len; i++) {
154 buf[i] = readb(this->IO_ADDR_R);
160 * au_verify_buf - Verify chip data against buffer
161 * @mtd: MTD device structure
162 * @buf: buffer containing the data to compare
163 * @len: number of bytes to compare
165 * verify function for 8bit buswidth
167 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
170 struct nand_chip *this = mtd->priv;
172 for (i = 0; i < len; i++) {
173 if (buf[i] != readb(this->IO_ADDR_R))
182 * au_write_buf16 - write buffer to chip
183 * @mtd: MTD device structure
185 * @len: number of bytes to write
187 * write function for 16bit buswidth
189 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
192 struct nand_chip *this = mtd->priv;
193 u16 *p = (u16 *) buf;
196 for (i = 0; i < len; i++) {
197 writew(p[i], this->IO_ADDR_W);
204 * au_read_buf16 - read chip data into buffer
205 * @mtd: MTD device structure
206 * @buf: buffer to store date
207 * @len: number of bytes to read
209 * read function for 16bit buswidth
211 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
214 struct nand_chip *this = mtd->priv;
215 u16 *p = (u16 *) buf;
218 for (i = 0; i < len; i++) {
219 p[i] = readw(this->IO_ADDR_R);
225 * au_verify_buf16 - Verify chip data against buffer
226 * @mtd: MTD device structure
227 * @buf: buffer containing the data to compare
228 * @len: number of bytes to compare
230 * verify function for 16bit buswidth
232 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
235 struct nand_chip *this = mtd->priv;
236 u16 *p = (u16 *) buf;
239 for (i = 0; i < len; i++) {
240 if (p[i] != readw(this->IO_ADDR_R))
247 /* Select the chip by setting nCE to low */
248 #define NAND_CTL_SETNCE 1
249 /* Deselect the chip by setting nCE to high */
250 #define NAND_CTL_CLRNCE 2
251 /* Select the command latch by setting CLE to high */
252 #define NAND_CTL_SETCLE 3
253 /* Deselect the command latch by setting CLE to low */
254 #define NAND_CTL_CLRCLE 4
255 /* Select the address latch by setting ALE to high */
256 #define NAND_CTL_SETALE 5
257 /* Deselect the address latch by setting ALE to low */
258 #define NAND_CTL_CLRALE 6
260 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
262 register struct nand_chip *this = mtd->priv;
266 case NAND_CTL_SETCLE:
267 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
270 case NAND_CTL_CLRCLE:
271 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
274 case NAND_CTL_SETALE:
275 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
278 case NAND_CTL_CLRALE:
279 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
280 /* FIXME: Nobody knows why this is necessary,
281 * but it works only that way */
285 case NAND_CTL_SETNCE:
286 /* assert (force assert) chip enable */
287 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
290 case NAND_CTL_CLRNCE:
291 /* deassert chip enable */
292 au_writel(0, MEM_STNDCTL);
296 this->IO_ADDR_R = this->IO_ADDR_W;
298 /* Drain the writebuffer */
302 int au1550_device_ready(struct mtd_info *mtd)
304 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
310 * au1550_select_chip - control -CE line
311 * Forbid driving -CE manually permitting the NAND controller to do this.
312 * Keeping -CE asserted during the whole sector reads interferes with the
313 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
314 * We only have to hold -CE low for the NAND read commands since the flash
315 * chip needs it to be asserted during chip not ready time but the NAND
316 * controller keeps it released.
318 * @mtd: MTD device structure
319 * @chip: chipnumber to select, -1 for deselect
321 static void au1550_select_chip(struct mtd_info *mtd, int chip)
326 * au1550_command - Send command to NAND device
327 * @mtd: MTD device structure
328 * @command: the command to be sent
329 * @column: the column address for this command, -1 if none
330 * @page_addr: the page address for this command, -1 if none
332 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
334 register struct nand_chip *this = mtd->priv;
335 int ce_override = 0, i;
338 /* Begin command latch cycle */
339 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
341 * Write out the command to the device.
343 if (command == NAND_CMD_SEQIN) {
346 if (column >= mtd->writesize) {
348 column -= mtd->writesize;
349 readcmd = NAND_CMD_READOOB;
350 } else if (column < 256) {
351 /* First 256 bytes --> READ0 */
352 readcmd = NAND_CMD_READ0;
355 readcmd = NAND_CMD_READ1;
357 au1550_write_byte(mtd, readcmd);
359 au1550_write_byte(mtd, command);
361 /* Set ALE and clear CLE to start address cycle */
362 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
364 if (column != -1 || page_addr != -1) {
365 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
367 /* Serially input address */
369 /* Adjust columns for 16 bit buswidth */
370 if (this->options & NAND_BUSWIDTH_16)
372 au1550_write_byte(mtd, column);
374 if (page_addr != -1) {
375 au1550_write_byte(mtd, (u8)(page_addr & 0xff));
377 if (command == NAND_CMD_READ0 ||
378 command == NAND_CMD_READ1 ||
379 command == NAND_CMD_READOOB) {
381 * NAND controller will release -CE after
382 * the last address byte is written, so we'll
383 * have to forcibly assert it. No interrupts
384 * are allowed while we do this as we don't
385 * want the NOR flash or PCMCIA drivers to
386 * steal our precious bytes of data...
389 local_irq_save(flags);
390 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
393 au1550_write_byte(mtd, (u8)(page_addr >> 8));
395 /* One more address cycle for devices > 32MiB */
396 if (this->chipsize > (32 << 20))
397 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
399 /* Latch in address */
400 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
404 * Program and erase have their own busy handlers.
405 * Status and sequential in need no delay.
409 case NAND_CMD_PAGEPROG:
410 case NAND_CMD_ERASE1:
411 case NAND_CMD_ERASE2:
413 case NAND_CMD_STATUS:
421 case NAND_CMD_READOOB:
422 /* Check if we're really driving -CE low (just in case) */
423 if (unlikely(!ce_override))
426 /* Apply a short delay always to ensure that we do wait tWB. */
428 /* Wait for a chip to become ready... */
429 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
432 /* Release -CE and re-enable interrupts. */
433 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
434 local_irq_restore(flags);
437 /* Apply this short delay always to ensure that we do wait tWB. */
440 while(!this->dev_ready(mtd));
445 * Main initialization routine
447 static int __init au1xxx_nand_init(void)
449 struct nand_chip *this;
450 u16 boot_swapboot = 0; /* default value */
455 /* Allocate memory for MTD device structure and private data */
456 au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
458 printk("Unable to allocate NAND MTD dev structure.\n");
462 /* Get pointer to private data */
463 this = (struct nand_chip *)(&au1550_mtd[1]);
465 /* Link the private data with the MTD structure */
466 au1550_mtd->priv = this;
467 au1550_mtd->owner = THIS_MODULE;
470 /* MEM_STNDCTL: disable ints, disable nand boot */
471 au_writel(0, MEM_STNDCTL);
473 #ifdef CONFIG_MIPS_PB1550
474 /* set gpio206 high */
475 gpio_direction_input(206);
477 boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
479 switch (boot_swapboot) {
497 printk("Pb1550 NAND: bad boot:swap\n");
503 /* Configure chip-select; normally done by boot code, e.g. YAMON */
506 au_writel(NAND_STCFG, MEM_STCFG0);
507 au_writel(NAND_STTIME, MEM_STTIME0);
508 au_writel(NAND_STADDR, MEM_STADDR0);
511 au_writel(NAND_STCFG, MEM_STCFG1);
512 au_writel(NAND_STTIME, MEM_STTIME1);
513 au_writel(NAND_STADDR, MEM_STADDR1);
516 au_writel(NAND_STCFG, MEM_STCFG2);
517 au_writel(NAND_STTIME, MEM_STTIME2);
518 au_writel(NAND_STADDR, MEM_STADDR2);
521 au_writel(NAND_STCFG, MEM_STCFG3);
522 au_writel(NAND_STTIME, MEM_STTIME3);
523 au_writel(NAND_STADDR, MEM_STADDR3);
527 /* Locate NAND chip-select in order to determine NAND phys address */
528 mem_staddr = 0x00000000;
529 if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
530 mem_staddr = au_readl(MEM_STADDR0);
531 else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
532 mem_staddr = au_readl(MEM_STADDR1);
533 else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
534 mem_staddr = au_readl(MEM_STADDR2);
535 else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
536 mem_staddr = au_readl(MEM_STADDR3);
538 if (mem_staddr == 0x00000000) {
539 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
543 nand_phys = (mem_staddr << 4) & 0xFFFC0000;
545 p_nand = ioremap(nand_phys, 0x1000);
547 /* make controller and MTD agree */
549 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
551 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
553 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
555 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
557 /* Set address of hardware control function */
558 this->dev_ready = au1550_device_ready;
559 this->select_chip = au1550_select_chip;
560 this->cmdfunc = au1550_command;
562 /* 30 us command delay time */
563 this->chip_delay = 30;
564 this->ecc.mode = NAND_ECC_SOFT;
566 this->options = NAND_NO_AUTOINCR;
569 this->options |= NAND_BUSWIDTH_16;
571 this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
572 au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
573 this->read_word = au_read_word;
574 this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
575 this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
576 this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
578 /* Scan to find existence of the device */
579 if (nand_scan(au1550_mtd, 1)) {
584 /* Register the partitions */
585 mtd_device_register(au1550_mtd, partition_info,
586 ARRAY_SIZE(partition_info));
598 module_init(au1xxx_nand_init);
603 static void __exit au1550_cleanup(void)
605 /* Release resources, unregister device */
606 nand_release(au1550_mtd);
608 /* Free the MTD device structure */
615 module_exit(au1550_cleanup);
617 MODULE_LICENSE("GPL");
618 MODULE_AUTHOR("Embedded Edge, LLC");
619 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");