2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
28 #include <asm/byteorder.h>
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
77 static void cfi_amdstd_destroy(struct mtd_info *);
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
101 /* #define DEBUG_CFI_FEATURES */
104 #ifdef DEBUG_CFI_FEATURES
105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
156 static void fixup_amd_bootblock(struct mtd_info *mtd)
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
195 extp->TopBottom = 2; /* bottom boot */
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
205 static void fixup_use_write_buffers(struct mtd_info *mtd)
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n");
211 mtd->_write = cfi_amdstd_write_buffers;
215 /* Atmel chips don't use the same PRI format as AMD chips */
216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
236 if (atmel_pri.BottomBoot)
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
247 static void fixup_use_secsi(struct mtd_info *mtd)
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
254 static void fixup_use_erase_chip(struct mtd_info *mtd)
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
287 cfi->cfiq->NumEraseRegions = 1;
290 static void fixup_sst39vf(struct mtd_info *mtd)
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
295 fixup_old_sst_eraseregion(mtd);
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
306 fixup_old_sst_eraseregion(mtd);
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
311 cfi->sector_erase_cmd = CMD(0x50);
314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
319 fixup_sst39vf_rev_b(mtd);
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
332 struct map_info *map = mtd->priv;
333 struct cfi_private *cfi = map->fldrv_priv;
335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
344 struct map_info *map = mtd->priv;
345 struct cfi_private *cfi = map->fldrv_priv;
347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
356 struct map_info *map = mtd->priv;
357 struct cfi_private *cfi = map->fldrv_priv;
360 * S29NS512P flash uses more than 8bits to report number of sectors,
361 * which is not permitted by CFI.
363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
368 /* Used to fix CFI-Tables of chips without Extended Query Tables */
369 static struct cfi_fixup cfi_nopri_fixup_table[] = {
370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
381 static struct cfi_fixup cfi_fixup_table[] = {
382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
383 #ifdef AMD_BOOTLOC_BUG
384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
403 #if !FORCE_WORD_WRITE
404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
408 static struct cfi_fixup jedec_fixup_table[] = {
409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
415 static struct cfi_fixup fixup_table[] = {
416 /* The CFI vendor ids and the JEDEC vendor IDs appear
417 * to be common. It is like the devices id's are as
418 * well. This table is to pick all cases where
419 * we know that is the case.
421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
427 static void cfi_fixup_major_minor(struct cfi_private *cfi,
428 struct cfi_pri_amdstd *extp)
430 if (cfi->mfr == CFI_MFR_SAMSUNG) {
431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
434 * Samsung K8P2815UQB and K8D6x16UxM chips
435 * report major=0 / minor=0.
436 * K8D3x16UxC chips report major=3 / minor=3.
438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
439 " Extended Query version to 1.%c\n",
441 extp->MajorVersion = '1';
446 * SST 38VF640x chips report major=0xFF / minor=0xFF.
448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
449 extp->MajorVersion = '1';
450 extp->MinorVersion = '0';
454 static int is_m29ew(struct cfi_private *cfi)
456 if (cfi->mfr == CFI_MFR_INTEL &&
457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
465 * Some revisions of the M29EW suffer from erase suspend hang ups. In
466 * particular, it can occur when the sequence
467 * Erase Confirm -> Suspend -> Program -> Resume
468 * causes a lockup due to internal timing issues. The consequence is that the
469 * erase cannot be resumed without inserting a dummy command after programming
470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
471 * that writes an F0 command code before the RESUME command.
473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
476 struct cfi_private *cfi = map->fldrv_priv;
477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
479 map_write(map, CMD(0xF0), adr);
483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
485 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
487 * command is issued after an ERASE RESUME operation without waiting for a
488 * minimum delay. The result is that once the ERASE seems to be completed
489 * (no bits are toggling), the contents of the Flash memory block on which
490 * the erase was ongoing could be inconsistent with the expected values
491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
492 * values), causing a consequent failure of the ERASE operation.
493 * The occurrence of this issue could be high, especially when file system
494 * operations on the Flash are intensive. As a result, it is recommended
495 * that a patch be applied. Intensive file system operations can cause many
496 * calls to the garbage routine to free Flash space (also by erasing physical
497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
498 * commands can occur. The problem disappears when a delay is inserted after
499 * the RESUME command by using the udelay() function available in Linux.
500 * The DELAY value must be tuned based on the customer's platform.
501 * The maximum value that fixes the problem in all cases is 500us.
502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
504 * We have chosen 500µs because this latency is acceptable.
506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
509 * Resolving the Delay After Resume Issue see Micron TN-13-07
510 * Worst case delay must be 500µs but 30-50µs should be ok as well
516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
518 struct cfi_private *cfi = map->fldrv_priv;
519 struct device_node __maybe_unused *np = map->device_node;
520 struct mtd_info *mtd;
523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
527 mtd->type = MTD_NORFLASH;
529 /* Fill in the default mtd operations */
530 mtd->_erase = cfi_amdstd_erase_varsize;
531 mtd->_write = cfi_amdstd_write_words;
532 mtd->_read = cfi_amdstd_read;
533 mtd->_sync = cfi_amdstd_sync;
534 mtd->_suspend = cfi_amdstd_suspend;
535 mtd->_resume = cfi_amdstd_resume;
536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
542 mtd->flags = MTD_CAP_NORFLASH;
543 mtd->name = map->name;
545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
547 pr_debug("MTD %s(): write buffer size %d\n", __func__,
550 mtd->_panic_write = cfi_amdstd_panic_write;
551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
553 if (cfi->cfi_mode==CFI_MODE_CFI){
554 unsigned char bootloc;
555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
556 struct cfi_pri_amdstd *extp;
558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
561 * It's a real CFI chip, not one for which the probe
562 * routine faked a CFI structure.
564 cfi_fixup_major_minor(cfi, extp);
567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
573 if (extp->MajorVersion != '1' ||
574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
576 "version %c.%c (%#02x/%#02x).\n",
577 extp->MajorVersion, extp->MinorVersion,
578 extp->MajorVersion, extp->MinorVersion);
584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
585 extp->MajorVersion, extp->MinorVersion);
587 /* Install our own private info structure */
588 cfi->cmdset_priv = extp;
590 /* Apply cfi device specific fixups */
591 cfi_fixup(mtd, cfi_fixup_table);
593 #ifdef DEBUG_CFI_FEATURES
594 /* Tell the user about it in lots of lovely detail */
595 cfi_tell_features(extp);
599 if (np && of_property_read_bool(
600 np, "use-advanced-sector-protection")
601 && extp->BlkProtUnprot == 8) {
602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
603 mtd->_lock = cfi_ppb_lock;
604 mtd->_unlock = cfi_ppb_unlock;
605 mtd->_is_locked = cfi_ppb_is_locked;
609 bootloc = extp->TopBottom;
610 if ((bootloc < 2) || (bootloc > 5)) {
611 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
612 "bank location (%d). Assuming bottom.\n",
617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
621 int j = (cfi->cfiq->NumEraseRegions-1)-i;
623 swap(cfi->cfiq->EraseRegionInfo[i],
624 cfi->cfiq->EraseRegionInfo[j]);
627 /* Set the default CFI lock/unlock addresses */
628 cfi->addr_unlock1 = 0x555;
629 cfi->addr_unlock2 = 0x2aa;
631 cfi_fixup(mtd, cfi_nopri_fixup_table);
633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
640 /* Apply jedec specific fixups */
641 cfi_fixup(mtd, jedec_fixup_table);
643 /* Apply generic fixups */
644 cfi_fixup(mtd, fixup_table);
646 for (i=0; i< cfi->numchips; i++) {
647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
651 * First calculate the timeout max according to timeout field
652 * of struct cfi_ident that probed from chip's CFI aera, if
653 * available. Specify a minimum of 2000us, in case the CFI data
656 if (cfi->cfiq->BufWriteTimeoutTyp &&
657 cfi->cfiq->BufWriteTimeoutMax)
658 cfi->chips[i].buffer_write_time_max =
659 1 << (cfi->cfiq->BufWriteTimeoutTyp +
660 cfi->cfiq->BufWriteTimeoutMax);
662 cfi->chips[i].buffer_write_time_max = 0;
664 cfi->chips[i].buffer_write_time_max =
665 max(cfi->chips[i].buffer_write_time_max, 2000);
667 cfi->chips[i].ref_point_counter = 0;
668 init_waitqueue_head(&(cfi->chips[i].wq));
671 map->fldrv = &cfi_amdstd_chipdrv;
673 return cfi_amdstd_setup(mtd);
675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
683 struct map_info *map = mtd->priv;
684 struct cfi_private *cfi = map->fldrv_priv;
685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
686 unsigned long offset = 0;
689 printk(KERN_NOTICE "number of %s chips: %d\n",
690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
691 /* Select the correct geometry setup */
692 mtd->size = devsize * cfi->numchips;
694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
695 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
696 * mtd->numeraseregions, GFP_KERNEL);
697 if (!mtd->eraseregions)
700 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
701 unsigned long ernum, ersize;
702 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
703 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
705 if (mtd->erasesize < ersize) {
706 mtd->erasesize = ersize;
708 for (j=0; j<cfi->numchips; j++) {
709 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
713 offset += (ersize * ernum);
715 if (offset != devsize) {
717 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
721 __module_get(THIS_MODULE);
722 register_reboot_notifier(&mtd->reboot_notifier);
726 kfree(mtd->eraseregions);
728 kfree(cfi->cmdset_priv);
734 * Return true if the chip is ready.
736 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
737 * non-suspended sector) and is indicated by no toggle bits toggling.
739 * Note that anything more complicated than checking if no bits are toggling
740 * (including checking DQ5 for an error status) is tricky to get working
741 * correctly and is therefore not done (particularly with interleaved chips
742 * as each chip must be checked independently of the others).
744 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
748 d = map_read(map, addr);
749 t = map_read(map, addr);
751 return map_word_equal(map, d, t);
755 * Return true if the chip is ready and has the correct value.
757 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
758 * non-suspended sector) and it is indicated by no bits toggling.
760 * Error are indicated by toggling bits or bits held with the wrong value,
761 * or with bits toggling.
763 * Note that anything more complicated than checking if no bits are toggling
764 * (including checking DQ5 for an error status) is tricky to get working
765 * correctly and is therefore not done (particularly with interleaved chips
766 * as each chip must be checked independently of the others).
769 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
773 oldd = map_read(map, addr);
774 curd = map_read(map, addr);
776 return map_word_equal(map, oldd, curd) &&
777 map_word_equal(map, curd, expected);
780 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
782 DECLARE_WAITQUEUE(wait, current);
783 struct cfi_private *cfi = map->fldrv_priv;
785 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
788 timeo = jiffies + HZ;
790 switch (chip->state) {
794 if (chip_ready(map, adr))
797 if (time_after(jiffies, timeo)) {
798 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
801 mutex_unlock(&chip->mutex);
803 mutex_lock(&chip->mutex);
804 /* Someone else might have been playing with it. */
814 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
815 !(mode == FL_READY || mode == FL_POINT ||
816 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
819 /* Do not allow suspend iff read/write to EB address */
820 if ((adr & chip->in_progress_block_mask) ==
821 chip->in_progress_block_addr)
825 /* It's harmless to issue the Erase-Suspend and Erase-Resume
826 * commands when the erase algorithm isn't in progress. */
827 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
828 chip->oldstate = FL_ERASING;
829 chip->state = FL_ERASE_SUSPENDING;
830 chip->erase_suspended = 1;
832 if (chip_ready(map, adr))
835 if (time_after(jiffies, timeo)) {
836 /* Should have suspended the erase by now.
837 * Send an Erase-Resume command as either
838 * there was an error (so leave the erase
839 * routine to recover from it) or we trying to
840 * use the erase-in-progress sector. */
841 put_chip(map, chip, adr);
842 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
846 mutex_unlock(&chip->mutex);
848 mutex_lock(&chip->mutex);
849 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
850 So we can just loop here. */
852 chip->state = FL_READY;
855 case FL_XIP_WHILE_ERASING:
856 if (mode != FL_READY && mode != FL_POINT &&
857 (!cfip || !(cfip->EraseSuspend&2)))
859 chip->oldstate = chip->state;
860 chip->state = FL_READY;
864 /* The machine is rebooting */
868 /* Only if there's no operation suspended... */
869 if (mode == FL_READY && chip->oldstate == FL_READY)
874 set_current_state(TASK_UNINTERRUPTIBLE);
875 add_wait_queue(&chip->wq, &wait);
876 mutex_unlock(&chip->mutex);
878 remove_wait_queue(&chip->wq, &wait);
879 mutex_lock(&chip->mutex);
885 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
887 struct cfi_private *cfi = map->fldrv_priv;
889 switch(chip->oldstate) {
891 cfi_fixup_m29ew_erase_suspend(map,
892 chip->in_progress_block_addr);
893 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
894 cfi_fixup_m29ew_delay_after_resume(cfi);
895 chip->oldstate = FL_READY;
896 chip->state = FL_ERASING;
899 case FL_XIP_WHILE_ERASING:
900 chip->state = chip->oldstate;
901 chip->oldstate = FL_READY;
908 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
913 #ifdef CONFIG_MTD_XIP
916 * No interrupt what so ever can be serviced while the flash isn't in array
917 * mode. This is ensured by the xip_disable() and xip_enable() functions
918 * enclosing any code path where the flash is known not to be in array mode.
919 * And within a XIP disabled code path, only functions marked with __xipram
920 * may be called and nothing else (it's a good thing to inspect generated
921 * assembly to make sure inline functions were actually inlined and that gcc
922 * didn't emit calls to its own support functions). Also configuring MTD CFI
923 * support to a single buswidth and a single interleave is also recommended.
926 static void xip_disable(struct map_info *map, struct flchip *chip,
929 /* TODO: chips with no XIP use should ignore and return */
930 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
934 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
937 struct cfi_private *cfi = map->fldrv_priv;
939 if (chip->state != FL_POINT && chip->state != FL_READY) {
940 map_write(map, CMD(0xf0), adr);
941 chip->state = FL_READY;
943 (void) map_read(map, adr);
949 * When a delay is required for the flash operation to complete, the
950 * xip_udelay() function is polling for both the given timeout and pending
951 * (but still masked) hardware interrupts. Whenever there is an interrupt
952 * pending then the flash erase operation is suspended, array mode restored
953 * and interrupts unmasked. Task scheduling might also happen at that
954 * point. The CPU eventually returns from the interrupt or the call to
955 * schedule() and the suspended flash operation is resumed for the remaining
956 * of the delay period.
958 * Warning: this function _will_ fool interrupt latency tracing tools.
961 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
962 unsigned long adr, int usec)
964 struct cfi_private *cfi = map->fldrv_priv;
965 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
966 map_word status, OK = CMD(0x80);
967 unsigned long suspended, start = xip_currtime();
972 if (xip_irqpending() && extp &&
973 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
974 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
976 * Let's suspend the erase operation when supported.
977 * Note that we currently don't try to suspend
978 * interleaved chips if there is already another
979 * operation suspended (imagine what happens
980 * when one chip was already done with the current
981 * operation while another chip suspended it, then
982 * we resume the whole thing at once). Yes, it
985 map_write(map, CMD(0xb0), adr);
986 usec -= xip_elapsed_since(start);
987 suspended = xip_currtime();
989 if (xip_elapsed_since(suspended) > 100000) {
991 * The chip doesn't want to suspend
992 * after waiting for 100 msecs.
993 * This is a critical error but there
994 * is not much we can do here.
998 status = map_read(map, adr);
999 } while (!map_word_andequal(map, status, OK, OK));
1001 /* Suspend succeeded */
1002 oldstate = chip->state;
1003 if (!map_word_bitsset(map, status, CMD(0x40)))
1005 chip->state = FL_XIP_WHILE_ERASING;
1006 chip->erase_suspended = 1;
1007 map_write(map, CMD(0xf0), adr);
1008 (void) map_read(map, adr);
1011 mutex_unlock(&chip->mutex);
1016 * We're back. However someone else might have
1017 * decided to go write to the chip if we are in
1018 * a suspended erase state. If so let's wait
1021 mutex_lock(&chip->mutex);
1022 while (chip->state != FL_XIP_WHILE_ERASING) {
1023 DECLARE_WAITQUEUE(wait, current);
1024 set_current_state(TASK_UNINTERRUPTIBLE);
1025 add_wait_queue(&chip->wq, &wait);
1026 mutex_unlock(&chip->mutex);
1028 remove_wait_queue(&chip->wq, &wait);
1029 mutex_lock(&chip->mutex);
1031 /* Disallow XIP again */
1032 local_irq_disable();
1034 /* Correct Erase Suspend Hangups for M29EW */
1035 cfi_fixup_m29ew_erase_suspend(map, adr);
1036 /* Resume the write or erase operation */
1037 map_write(map, cfi->sector_erase_cmd, adr);
1038 chip->state = oldstate;
1039 start = xip_currtime();
1040 } else if (usec >= 1000000/HZ) {
1042 * Try to save on CPU power when waiting delay
1043 * is at least a system timer tick period.
1044 * No need to be extremely accurate here.
1048 status = map_read(map, adr);
1049 } while (!map_word_andequal(map, status, OK, OK)
1050 && xip_elapsed_since(start) < usec);
1053 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1056 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1057 * the flash is actively programming or erasing since we have to poll for
1058 * the operation to complete anyway. We can't do that in a generic way with
1059 * a XIP setup so do it before the actual flash operation in this case
1060 * and stub it out from INVALIDATE_CACHE_UDELAY.
1062 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1063 INVALIDATE_CACHED_RANGE(map, from, size)
1065 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1066 UDELAY(map, chip, adr, usec)
1071 * Activating this XIP support changes the way the code works a bit. For
1072 * example the code to suspend the current process when concurrent access
1073 * happens is never executed because xip_udelay() will always return with the
1074 * same chip state as it was entered with. This is why there is no care for
1075 * the presence of add_wait_queue() or schedule() calls from within a couple
1076 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1077 * The queueing and scheduling are always happening within xip_udelay().
1079 * Similarly, get_chip() and put_chip() just happen to always be executed
1080 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1081 * is in array mode, therefore never executing many cases therein and not
1082 * causing any problem with XIP.
1087 #define xip_disable(map, chip, adr)
1088 #define xip_enable(map, chip, adr)
1089 #define XIP_INVAL_CACHED_RANGE(x...)
1091 #define UDELAY(map, chip, adr, usec) \
1093 mutex_unlock(&chip->mutex); \
1095 mutex_lock(&chip->mutex); \
1098 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1100 mutex_unlock(&chip->mutex); \
1101 INVALIDATE_CACHED_RANGE(map, adr, len); \
1103 mutex_lock(&chip->mutex); \
1108 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1110 unsigned long cmd_addr;
1111 struct cfi_private *cfi = map->fldrv_priv;
1116 /* Ensure cmd read/writes are aligned. */
1117 cmd_addr = adr & ~(map_bankwidth(map)-1);
1119 mutex_lock(&chip->mutex);
1120 ret = get_chip(map, chip, cmd_addr, FL_READY);
1122 mutex_unlock(&chip->mutex);
1126 if (chip->state != FL_POINT && chip->state != FL_READY) {
1127 map_write(map, CMD(0xf0), cmd_addr);
1128 chip->state = FL_READY;
1131 map_copy_from(map, buf, adr, len);
1133 put_chip(map, chip, cmd_addr);
1135 mutex_unlock(&chip->mutex);
1140 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1142 struct map_info *map = mtd->priv;
1143 struct cfi_private *cfi = map->fldrv_priv;
1148 /* ofs: offset within the first chip that the first read should start */
1149 chipnum = (from >> cfi->chipshift);
1150 ofs = from - (chipnum << cfi->chipshift);
1153 unsigned long thislen;
1155 if (chipnum >= cfi->numchips)
1158 if ((len + ofs -1) >> cfi->chipshift)
1159 thislen = (1<<cfi->chipshift) - ofs;
1163 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1177 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1178 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1180 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1181 loff_t adr, size_t len)
1183 struct cfi_private *cfi = map->fldrv_priv;
1185 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1186 cfi->device_type, NULL);
1187 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1188 cfi->device_type, NULL);
1189 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1190 cfi->device_type, NULL);
1192 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1195 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1196 loff_t adr, size_t len)
1198 struct cfi_private *cfi = map->fldrv_priv;
1200 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1201 cfi->device_type, NULL);
1202 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1203 cfi->device_type, NULL);
1204 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1205 cfi->device_type, NULL);
1206 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1207 cfi->device_type, NULL);
1209 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1212 static inline int do_read_secsi_onechip(struct map_info *map,
1213 struct flchip *chip, loff_t adr,
1214 size_t len, u_char *buf,
1217 DECLARE_WAITQUEUE(wait, current);
1218 unsigned long timeo = jiffies + HZ;
1221 mutex_lock(&chip->mutex);
1223 if (chip->state != FL_READY){
1224 set_current_state(TASK_UNINTERRUPTIBLE);
1225 add_wait_queue(&chip->wq, &wait);
1227 mutex_unlock(&chip->mutex);
1230 remove_wait_queue(&chip->wq, &wait);
1231 timeo = jiffies + HZ;
1238 chip->state = FL_READY;
1240 otp_enter(map, chip, adr, len);
1241 map_copy_from(map, buf, adr, len);
1242 otp_exit(map, chip, adr, len);
1245 mutex_unlock(&chip->mutex);
1250 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1252 struct map_info *map = mtd->priv;
1253 struct cfi_private *cfi = map->fldrv_priv;
1258 /* ofs: offset within the first chip that the first read should start */
1259 /* 8 secsi bytes per chip */
1264 unsigned long thislen;
1266 if (chipnum >= cfi->numchips)
1269 if ((len + ofs -1) >> 3)
1270 thislen = (1<<3) - ofs;
1274 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1289 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1290 unsigned long adr, map_word datum,
1293 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1294 size_t len, u_char *buf, size_t grouplen)
1298 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1299 int gap = adr - bus_ofs;
1300 int n = min_t(int, len, map_bankwidth(map) - gap);
1301 map_word datum = map_word_ff(map);
1303 if (n != map_bankwidth(map)) {
1304 /* partial write of a word, load old contents */
1305 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1306 datum = map_read(map, bus_ofs);
1307 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1310 datum = map_word_load_partial(map, datum, buf, gap, n);
1311 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1323 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1324 size_t len, u_char *buf, size_t grouplen)
1326 struct cfi_private *cfi = map->fldrv_priv;
1328 unsigned long timeo;
1331 /* make sure area matches group boundaries */
1332 if ((adr != 0) || (len != grouplen))
1335 mutex_lock(&chip->mutex);
1336 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1338 mutex_unlock(&chip->mutex);
1341 chip->state = FL_LOCKING;
1343 /* Enter lock register command */
1344 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1345 cfi->device_type, NULL);
1346 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1347 cfi->device_type, NULL);
1348 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1349 cfi->device_type, NULL);
1351 /* read lock register */
1352 lockreg = cfi_read_query(map, 0);
1354 /* set bit 0 to protect extended memory block */
1357 /* set bit 0 to protect extended memory block */
1358 /* write lock register */
1359 map_write(map, CMD(0xA0), chip->start);
1360 map_write(map, CMD(lockreg), chip->start);
1362 /* wait for chip to become ready */
1363 timeo = jiffies + msecs_to_jiffies(2);
1365 if (chip_ready(map, adr))
1368 if (time_after(jiffies, timeo)) {
1369 pr_err("Waiting for chip to be ready timed out.\n");
1373 UDELAY(map, chip, 0, 1);
1376 /* exit protection commands */
1377 map_write(map, CMD(0x90), chip->start);
1378 map_write(map, CMD(0x00), chip->start);
1380 chip->state = FL_READY;
1381 put_chip(map, chip, chip->start);
1382 mutex_unlock(&chip->mutex);
1387 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1388 size_t *retlen, u_char *buf,
1389 otp_op_t action, int user_regs)
1391 struct map_info *map = mtd->priv;
1392 struct cfi_private *cfi = map->fldrv_priv;
1393 int ofs_factor = cfi->interleave * cfi->device_type;
1396 struct flchip *chip;
1397 uint8_t otp, lockreg;
1400 size_t user_size, factory_size, otpsize;
1401 loff_t user_offset, factory_offset, otpoffset;
1402 int user_locked = 0, otplocked;
1406 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1407 chip = &cfi->chips[chipnum];
1411 /* Micron M29EW family */
1412 if (is_m29ew(cfi)) {
1415 /* check whether secsi area is factory locked
1417 mutex_lock(&chip->mutex);
1418 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1420 mutex_unlock(&chip->mutex);
1423 cfi_qry_mode_on(base, map, cfi);
1424 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1425 cfi_qry_mode_off(base, map, cfi);
1426 put_chip(map, chip, base);
1427 mutex_unlock(&chip->mutex);
1430 /* factory locked */
1432 factory_size = 0x100;
1434 /* customer lockable */
1438 mutex_lock(&chip->mutex);
1439 ret = get_chip(map, chip, base, FL_LOCKING);
1441 mutex_unlock(&chip->mutex);
1445 /* Enter lock register command */
1446 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1447 chip->start, map, cfi,
1448 cfi->device_type, NULL);
1449 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1450 chip->start, map, cfi,
1451 cfi->device_type, NULL);
1452 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1453 chip->start, map, cfi,
1454 cfi->device_type, NULL);
1455 /* read lock register */
1456 lockreg = cfi_read_query(map, 0);
1457 /* exit protection commands */
1458 map_write(map, CMD(0x90), chip->start);
1459 map_write(map, CMD(0x00), chip->start);
1460 put_chip(map, chip, chip->start);
1461 mutex_unlock(&chip->mutex);
1463 user_locked = ((lockreg & 0x01) == 0x00);
1467 otpsize = user_regs ? user_size : factory_size;
1470 otpoffset = user_regs ? user_offset : factory_offset;
1471 otplocked = user_regs ? user_locked : 1;
1474 /* return otpinfo */
1475 struct otp_info *otpinfo;
1476 len -= sizeof(*otpinfo);
1479 otpinfo = (struct otp_info *)buf;
1480 otpinfo->start = from;
1481 otpinfo->length = otpsize;
1482 otpinfo->locked = otplocked;
1483 buf += sizeof(*otpinfo);
1484 *retlen += sizeof(*otpinfo);
1486 } else if ((from < otpsize) && (len > 0)) {
1488 size = (len < otpsize - from) ? len : otpsize - from;
1489 ret = action(map, chip, otpoffset + from, size, buf,
1505 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1506 size_t *retlen, struct otp_info *buf)
1508 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1512 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1513 size_t *retlen, struct otp_info *buf)
1515 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1519 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1520 size_t len, size_t *retlen,
1523 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1524 buf, do_read_secsi_onechip, 0);
1527 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1528 size_t len, size_t *retlen,
1531 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1532 buf, do_read_secsi_onechip, 1);
1535 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1536 size_t len, size_t *retlen,
1539 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1543 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1547 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1551 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1552 unsigned long adr, map_word datum,
1555 struct cfi_private *cfi = map->fldrv_priv;
1556 unsigned long timeo = jiffies + HZ;
1558 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1559 * have a max write time of a few hundreds usec). However, we should
1560 * use the maximum timeout value given by the chip at probe time
1561 * instead. Unfortunately, struct flchip does have a field for
1562 * maximum timeout, only for typical which can be far too short
1563 * depending of the conditions. The ' + 1' is to avoid having a
1564 * timeout of 0 jiffies if HZ is smaller than 1000.
1566 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1573 mutex_lock(&chip->mutex);
1574 ret = get_chip(map, chip, adr, mode);
1576 mutex_unlock(&chip->mutex);
1580 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1581 __func__, adr, datum.x[0]);
1583 if (mode == FL_OTP_WRITE)
1584 otp_enter(map, chip, adr, map_bankwidth(map));
1587 * Check for a NOP for the case when the datum to write is already
1588 * present - it saves time and works around buggy chips that corrupt
1589 * data at other locations when 0xff is written to a location that
1590 * already contains 0xff.
1592 oldd = map_read(map, adr);
1593 if (map_word_equal(map, oldd, datum)) {
1594 pr_debug("MTD %s(): NOP\n",
1599 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1601 xip_disable(map, chip, adr);
1604 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1605 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1606 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1607 map_write(map, datum, adr);
1610 INVALIDATE_CACHE_UDELAY(map, chip,
1611 adr, map_bankwidth(map),
1612 chip->word_write_time);
1614 /* See comment above for timeout value. */
1615 timeo = jiffies + uWriteTimeout;
1617 if (chip->state != mode) {
1618 /* Someone's suspended the write. Sleep */
1619 DECLARE_WAITQUEUE(wait, current);
1621 set_current_state(TASK_UNINTERRUPTIBLE);
1622 add_wait_queue(&chip->wq, &wait);
1623 mutex_unlock(&chip->mutex);
1625 remove_wait_queue(&chip->wq, &wait);
1626 timeo = jiffies + (HZ / 2); /* FIXME */
1627 mutex_lock(&chip->mutex);
1631 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1632 xip_enable(map, chip, adr);
1633 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1634 xip_disable(map, chip, adr);
1638 if (chip_ready(map, adr))
1641 /* Latency issues. Drop the lock, wait a while and retry */
1642 UDELAY(map, chip, adr, 1);
1644 /* Did we succeed? */
1645 if (!chip_good(map, adr, datum)) {
1646 /* reset on all failures. */
1647 map_write(map, CMD(0xF0), chip->start);
1648 /* FIXME - should have reset delay before continuing */
1650 if (++retry_cnt <= MAX_RETRIES)
1655 xip_enable(map, chip, adr);
1657 if (mode == FL_OTP_WRITE)
1658 otp_exit(map, chip, adr, map_bankwidth(map));
1659 chip->state = FL_READY;
1661 put_chip(map, chip, adr);
1662 mutex_unlock(&chip->mutex);
1668 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1669 size_t *retlen, const u_char *buf)
1671 struct map_info *map = mtd->priv;
1672 struct cfi_private *cfi = map->fldrv_priv;
1675 unsigned long ofs, chipstart;
1676 DECLARE_WAITQUEUE(wait, current);
1678 chipnum = to >> cfi->chipshift;
1679 ofs = to - (chipnum << cfi->chipshift);
1680 chipstart = cfi->chips[chipnum].start;
1682 /* If it's not bus-aligned, do the first byte write */
1683 if (ofs & (map_bankwidth(map)-1)) {
1684 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1685 int i = ofs - bus_ofs;
1690 mutex_lock(&cfi->chips[chipnum].mutex);
1692 if (cfi->chips[chipnum].state != FL_READY) {
1693 set_current_state(TASK_UNINTERRUPTIBLE);
1694 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1696 mutex_unlock(&cfi->chips[chipnum].mutex);
1699 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1703 /* Load 'tmp_buf' with old contents of flash */
1704 tmp_buf = map_read(map, bus_ofs+chipstart);
1706 mutex_unlock(&cfi->chips[chipnum].mutex);
1708 /* Number of bytes to copy from buffer */
1709 n = min_t(int, len, map_bankwidth(map)-i);
1711 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1713 ret = do_write_oneword(map, &cfi->chips[chipnum],
1714 bus_ofs, tmp_buf, FL_WRITING);
1723 if (ofs >> cfi->chipshift) {
1726 if (chipnum == cfi->numchips)
1731 /* We are now aligned, write as much as possible */
1732 while(len >= map_bankwidth(map)) {
1735 datum = map_word_load(map, buf);
1737 ret = do_write_oneword(map, &cfi->chips[chipnum],
1738 ofs, datum, FL_WRITING);
1742 ofs += map_bankwidth(map);
1743 buf += map_bankwidth(map);
1744 (*retlen) += map_bankwidth(map);
1745 len -= map_bankwidth(map);
1747 if (ofs >> cfi->chipshift) {
1750 if (chipnum == cfi->numchips)
1752 chipstart = cfi->chips[chipnum].start;
1756 /* Write the trailing bytes if any */
1757 if (len & (map_bankwidth(map)-1)) {
1761 mutex_lock(&cfi->chips[chipnum].mutex);
1763 if (cfi->chips[chipnum].state != FL_READY) {
1764 set_current_state(TASK_UNINTERRUPTIBLE);
1765 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1767 mutex_unlock(&cfi->chips[chipnum].mutex);
1770 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1774 tmp_buf = map_read(map, ofs + chipstart);
1776 mutex_unlock(&cfi->chips[chipnum].mutex);
1778 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1780 ret = do_write_oneword(map, &cfi->chips[chipnum],
1781 ofs, tmp_buf, FL_WRITING);
1793 * FIXME: interleaved mode not tested, and probably not supported!
1795 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1796 unsigned long adr, const u_char *buf,
1799 struct cfi_private *cfi = map->fldrv_priv;
1800 unsigned long timeo = jiffies + HZ;
1802 * Timeout is calculated according to CFI data, if available.
1803 * See more comments in cfi_cmdset_0002().
1805 unsigned long uWriteTimeout =
1806 usecs_to_jiffies(chip->buffer_write_time_max);
1808 unsigned long cmd_adr;
1815 mutex_lock(&chip->mutex);
1816 ret = get_chip(map, chip, adr, FL_WRITING);
1818 mutex_unlock(&chip->mutex);
1822 datum = map_word_load(map, buf);
1824 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1825 __func__, adr, datum.x[0]);
1827 XIP_INVAL_CACHED_RANGE(map, adr, len);
1829 xip_disable(map, chip, cmd_adr);
1831 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1832 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1834 /* Write Buffer Load */
1835 map_write(map, CMD(0x25), cmd_adr);
1837 chip->state = FL_WRITING_TO_BUFFER;
1839 /* Write length of data to come */
1840 words = len / map_bankwidth(map);
1841 map_write(map, CMD(words - 1), cmd_adr);
1844 while(z < words * map_bankwidth(map)) {
1845 datum = map_word_load(map, buf);
1846 map_write(map, datum, adr + z);
1848 z += map_bankwidth(map);
1849 buf += map_bankwidth(map);
1851 z -= map_bankwidth(map);
1855 /* Write Buffer Program Confirm: GO GO GO */
1856 map_write(map, CMD(0x29), cmd_adr);
1857 chip->state = FL_WRITING;
1859 INVALIDATE_CACHE_UDELAY(map, chip,
1860 adr, map_bankwidth(map),
1861 chip->word_write_time);
1863 timeo = jiffies + uWriteTimeout;
1866 if (chip->state != FL_WRITING) {
1867 /* Someone's suspended the write. Sleep */
1868 DECLARE_WAITQUEUE(wait, current);
1870 set_current_state(TASK_UNINTERRUPTIBLE);
1871 add_wait_queue(&chip->wq, &wait);
1872 mutex_unlock(&chip->mutex);
1874 remove_wait_queue(&chip->wq, &wait);
1875 timeo = jiffies + (HZ / 2); /* FIXME */
1876 mutex_lock(&chip->mutex);
1880 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1883 if (chip_good(map, adr, datum)) {
1884 xip_enable(map, chip, adr);
1888 /* Latency issues. Drop the lock, wait a while and retry */
1889 UDELAY(map, chip, adr, 1);
1893 * Recovery from write-buffer programming failures requires
1894 * the write-to-buffer-reset sequence. Since the last part
1895 * of the sequence also works as a normal reset, we can run
1896 * the same commands regardless of why we are here.
1898 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1900 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1901 cfi->device_type, NULL);
1902 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1903 cfi->device_type, NULL);
1904 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1905 cfi->device_type, NULL);
1906 xip_enable(map, chip, adr);
1907 /* FIXME - should have reset delay before continuing */
1909 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1914 chip->state = FL_READY;
1916 put_chip(map, chip, adr);
1917 mutex_unlock(&chip->mutex);
1923 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1924 size_t *retlen, const u_char *buf)
1926 struct map_info *map = mtd->priv;
1927 struct cfi_private *cfi = map->fldrv_priv;
1928 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1933 chipnum = to >> cfi->chipshift;
1934 ofs = to - (chipnum << cfi->chipshift);
1936 /* If it's not bus-aligned, do the first word write */
1937 if (ofs & (map_bankwidth(map)-1)) {
1938 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1939 if (local_len > len)
1941 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1942 local_len, retlen, buf);
1949 if (ofs >> cfi->chipshift) {
1952 if (chipnum == cfi->numchips)
1957 /* Write buffer is worth it only if more than one word to write... */
1958 while (len >= map_bankwidth(map) * 2) {
1959 /* We must not cross write block boundaries */
1960 int size = wbufsize - (ofs & (wbufsize-1));
1964 if (size % map_bankwidth(map))
1965 size -= size % map_bankwidth(map);
1967 ret = do_write_buffer(map, &cfi->chips[chipnum],
1977 if (ofs >> cfi->chipshift) {
1980 if (chipnum == cfi->numchips)
1986 size_t retlen_dregs = 0;
1988 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1989 len, &retlen_dregs, buf);
1991 *retlen += retlen_dregs;
1999 * Wait for the flash chip to become ready to write data
2001 * This is only called during the panic_write() path. When panic_write()
2002 * is called, the kernel is in the process of a panic, and will soon be
2003 * dead. Therefore we don't take any locks, and attempt to get access
2004 * to the chip as soon as possible.
2006 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2009 struct cfi_private *cfi = map->fldrv_priv;
2014 * If the driver thinks the chip is idle, and no toggle bits
2015 * are changing, then the chip is actually idle for sure.
2017 if (chip->state == FL_READY && chip_ready(map, adr))
2021 * Try several times to reset the chip and then wait for it
2022 * to become idle. The upper limit of a few milliseconds of
2023 * delay isn't a big problem: the kernel is dying anyway. It
2024 * is more important to save the messages.
2026 while (retries > 0) {
2027 const unsigned long timeo = (HZ / 1000) + 1;
2029 /* send the reset command */
2030 map_write(map, CMD(0xF0), chip->start);
2032 /* wait for the chip to become ready */
2033 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2034 if (chip_ready(map, adr))
2043 /* the chip never became ready */
2048 * Write out one word of data to a single flash chip during a kernel panic
2050 * This is only called during the panic_write() path. When panic_write()
2051 * is called, the kernel is in the process of a panic, and will soon be
2052 * dead. Therefore we don't take any locks, and attempt to get access
2053 * to the chip as soon as possible.
2055 * The implementation of this routine is intentionally similar to
2056 * do_write_oneword(), in order to ease code maintenance.
2058 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2059 unsigned long adr, map_word datum)
2061 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2062 struct cfi_private *cfi = map->fldrv_priv;
2070 ret = cfi_amdstd_panic_wait(map, chip, adr);
2074 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2075 __func__, adr, datum.x[0]);
2078 * Check for a NOP for the case when the datum to write is already
2079 * present - it saves time and works around buggy chips that corrupt
2080 * data at other locations when 0xff is written to a location that
2081 * already contains 0xff.
2083 oldd = map_read(map, adr);
2084 if (map_word_equal(map, oldd, datum)) {
2085 pr_debug("MTD %s(): NOP\n", __func__);
2092 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2093 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2094 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2095 map_write(map, datum, adr);
2097 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2098 if (chip_ready(map, adr))
2104 if (!chip_good(map, adr, datum)) {
2105 /* reset on all failures. */
2106 map_write(map, CMD(0xF0), chip->start);
2107 /* FIXME - should have reset delay before continuing */
2109 if (++retry_cnt <= MAX_RETRIES)
2121 * Write out some data during a kernel panic
2123 * This is used by the mtdoops driver to save the dying messages from a
2124 * kernel which has panic'd.
2126 * This routine ignores all of the locking used throughout the rest of the
2127 * driver, in order to ensure that the data gets written out no matter what
2128 * state this driver (and the flash chip itself) was in when the kernel crashed.
2130 * The implementation of this routine is intentionally similar to
2131 * cfi_amdstd_write_words(), in order to ease code maintenance.
2133 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2134 size_t *retlen, const u_char *buf)
2136 struct map_info *map = mtd->priv;
2137 struct cfi_private *cfi = map->fldrv_priv;
2138 unsigned long ofs, chipstart;
2142 chipnum = to >> cfi->chipshift;
2143 ofs = to - (chipnum << cfi->chipshift);
2144 chipstart = cfi->chips[chipnum].start;
2146 /* If it's not bus aligned, do the first byte write */
2147 if (ofs & (map_bankwidth(map) - 1)) {
2148 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2149 int i = ofs - bus_ofs;
2153 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2157 /* Load 'tmp_buf' with old contents of flash */
2158 tmp_buf = map_read(map, bus_ofs + chipstart);
2160 /* Number of bytes to copy from buffer */
2161 n = min_t(int, len, map_bankwidth(map) - i);
2163 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2165 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2175 if (ofs >> cfi->chipshift) {
2178 if (chipnum == cfi->numchips)
2183 /* We are now aligned, write as much as possible */
2184 while (len >= map_bankwidth(map)) {
2187 datum = map_word_load(map, buf);
2189 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2194 ofs += map_bankwidth(map);
2195 buf += map_bankwidth(map);
2196 (*retlen) += map_bankwidth(map);
2197 len -= map_bankwidth(map);
2199 if (ofs >> cfi->chipshift) {
2202 if (chipnum == cfi->numchips)
2205 chipstart = cfi->chips[chipnum].start;
2209 /* Write the trailing bytes if any */
2210 if (len & (map_bankwidth(map) - 1)) {
2213 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2217 tmp_buf = map_read(map, ofs + chipstart);
2219 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2221 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2234 * Handle devices with one erase region, that only implement
2235 * the chip erase command.
2237 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2239 struct cfi_private *cfi = map->fldrv_priv;
2240 unsigned long timeo = jiffies + HZ;
2241 unsigned long int adr;
2242 DECLARE_WAITQUEUE(wait, current);
2246 adr = cfi->addr_unlock1;
2248 mutex_lock(&chip->mutex);
2249 ret = get_chip(map, chip, adr, FL_WRITING);
2251 mutex_unlock(&chip->mutex);
2255 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2256 __func__, chip->start);
2258 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2260 xip_disable(map, chip, adr);
2263 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2264 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2265 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2266 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2267 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2268 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2270 chip->state = FL_ERASING;
2271 chip->erase_suspended = 0;
2272 chip->in_progress_block_addr = adr;
2273 chip->in_progress_block_mask = ~(map->size - 1);
2275 INVALIDATE_CACHE_UDELAY(map, chip,
2277 chip->erase_time*500);
2279 timeo = jiffies + (HZ*20);
2282 if (chip->state != FL_ERASING) {
2283 /* Someone's suspended the erase. Sleep */
2284 set_current_state(TASK_UNINTERRUPTIBLE);
2285 add_wait_queue(&chip->wq, &wait);
2286 mutex_unlock(&chip->mutex);
2288 remove_wait_queue(&chip->wq, &wait);
2289 mutex_lock(&chip->mutex);
2292 if (chip->erase_suspended) {
2293 /* This erase was suspended and resumed.
2294 Adjust the timeout */
2295 timeo = jiffies + (HZ*20); /* FIXME */
2296 chip->erase_suspended = 0;
2299 if (chip_good(map, adr, map_word_ff(map)))
2302 if (time_after(jiffies, timeo)) {
2303 printk(KERN_WARNING "MTD %s(): software timeout\n",
2309 /* Latency issues. Drop the lock, wait a while and retry */
2310 UDELAY(map, chip, adr, 1000000/HZ);
2312 /* Did we succeed? */
2314 /* reset on all failures. */
2315 map_write(map, CMD(0xF0), chip->start);
2316 /* FIXME - should have reset delay before continuing */
2318 if (++retry_cnt <= MAX_RETRIES) {
2324 chip->state = FL_READY;
2325 xip_enable(map, chip, adr);
2327 put_chip(map, chip, adr);
2328 mutex_unlock(&chip->mutex);
2334 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2336 struct cfi_private *cfi = map->fldrv_priv;
2337 unsigned long timeo = jiffies + HZ;
2338 DECLARE_WAITQUEUE(wait, current);
2344 mutex_lock(&chip->mutex);
2345 ret = get_chip(map, chip, adr, FL_ERASING);
2347 mutex_unlock(&chip->mutex);
2351 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2354 XIP_INVAL_CACHED_RANGE(map, adr, len);
2356 xip_disable(map, chip, adr);
2359 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2360 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2361 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2362 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2363 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2364 map_write(map, cfi->sector_erase_cmd, adr);
2366 chip->state = FL_ERASING;
2367 chip->erase_suspended = 0;
2368 chip->in_progress_block_addr = adr;
2369 chip->in_progress_block_mask = ~(len - 1);
2371 INVALIDATE_CACHE_UDELAY(map, chip,
2373 chip->erase_time*500);
2375 timeo = jiffies + (HZ*20);
2378 if (chip->state != FL_ERASING) {
2379 /* Someone's suspended the erase. Sleep */
2380 set_current_state(TASK_UNINTERRUPTIBLE);
2381 add_wait_queue(&chip->wq, &wait);
2382 mutex_unlock(&chip->mutex);
2384 remove_wait_queue(&chip->wq, &wait);
2385 mutex_lock(&chip->mutex);
2388 if (chip->erase_suspended) {
2389 /* This erase was suspended and resumed.
2390 Adjust the timeout */
2391 timeo = jiffies + (HZ*20); /* FIXME */
2392 chip->erase_suspended = 0;
2395 if (chip_good(map, adr, map_word_ff(map)))
2398 if (time_after(jiffies, timeo)) {
2399 printk(KERN_WARNING "MTD %s(): software timeout\n",
2405 /* Latency issues. Drop the lock, wait a while and retry */
2406 UDELAY(map, chip, adr, 1000000/HZ);
2408 /* Did we succeed? */
2410 /* reset on all failures. */
2411 map_write(map, CMD(0xF0), chip->start);
2412 /* FIXME - should have reset delay before continuing */
2414 if (++retry_cnt <= MAX_RETRIES) {
2420 chip->state = FL_READY;
2421 xip_enable(map, chip, adr);
2423 put_chip(map, chip, adr);
2424 mutex_unlock(&chip->mutex);
2429 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2431 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2436 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2438 struct map_info *map = mtd->priv;
2439 struct cfi_private *cfi = map->fldrv_priv;
2441 if (instr->addr != 0)
2444 if (instr->len != mtd->size)
2447 return do_erase_chip(map, &cfi->chips[0]);
2450 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2451 unsigned long adr, int len, void *thunk)
2453 struct cfi_private *cfi = map->fldrv_priv;
2456 mutex_lock(&chip->mutex);
2457 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2460 chip->state = FL_LOCKING;
2462 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2464 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2465 cfi->device_type, NULL);
2466 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2467 cfi->device_type, NULL);
2468 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2469 cfi->device_type, NULL);
2470 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2471 cfi->device_type, NULL);
2472 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2473 cfi->device_type, NULL);
2474 map_write(map, CMD(0x40), chip->start + adr);
2476 chip->state = FL_READY;
2477 put_chip(map, chip, adr + chip->start);
2481 mutex_unlock(&chip->mutex);
2485 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2486 unsigned long adr, int len, void *thunk)
2488 struct cfi_private *cfi = map->fldrv_priv;
2491 mutex_lock(&chip->mutex);
2492 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2495 chip->state = FL_UNLOCKING;
2497 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2499 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2500 cfi->device_type, NULL);
2501 map_write(map, CMD(0x70), adr);
2503 chip->state = FL_READY;
2504 put_chip(map, chip, adr + chip->start);
2508 mutex_unlock(&chip->mutex);
2512 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2514 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2517 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2519 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2523 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2527 struct flchip *chip;
2532 #define MAX_SECTORS 512
2534 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2535 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2536 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2538 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2539 struct flchip *chip,
2540 unsigned long adr, int len, void *thunk)
2542 struct cfi_private *cfi = map->fldrv_priv;
2543 unsigned long timeo;
2546 mutex_lock(&chip->mutex);
2547 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2549 mutex_unlock(&chip->mutex);
2553 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2555 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2556 cfi->device_type, NULL);
2557 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2558 cfi->device_type, NULL);
2559 /* PPB entry command */
2560 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2561 cfi->device_type, NULL);
2563 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2564 chip->state = FL_LOCKING;
2565 map_write(map, CMD(0xA0), chip->start + adr);
2566 map_write(map, CMD(0x00), chip->start + adr);
2567 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2569 * Unlocking of one specific sector is not supported, so we
2570 * have to unlock all sectors of this device instead
2572 chip->state = FL_UNLOCKING;
2573 map_write(map, CMD(0x80), chip->start);
2574 map_write(map, CMD(0x30), chip->start);
2575 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2576 chip->state = FL_JEDEC_QUERY;
2577 /* Return locked status: 0->locked, 1->unlocked */
2578 ret = !cfi_read_query(map, adr);
2583 * Wait for some time as unlocking of all sectors takes quite long
2585 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2587 if (chip_ready(map, adr))
2590 if (time_after(jiffies, timeo)) {
2591 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2596 UDELAY(map, chip, adr, 1);
2599 /* Exit BC commands */
2600 map_write(map, CMD(0x90), chip->start);
2601 map_write(map, CMD(0x00), chip->start);
2603 chip->state = FL_READY;
2604 put_chip(map, chip, adr + chip->start);
2605 mutex_unlock(&chip->mutex);
2610 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2613 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2614 DO_XXLOCK_ONEBLOCK_LOCK);
2617 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2620 struct mtd_erase_region_info *regions = mtd->eraseregions;
2621 struct map_info *map = mtd->priv;
2622 struct cfi_private *cfi = map->fldrv_priv;
2623 struct ppb_lock *sect;
2633 * PPB unlocking always unlocks all sectors of the flash chip.
2634 * We need to re-lock all previously locked sectors. So lets
2635 * first check the locking status of all sectors and save
2636 * it for future use.
2638 sect = kzalloc(MAX_SECTORS * sizeof(struct ppb_lock), GFP_KERNEL);
2643 * This code to walk all sectors is a slightly modified version
2644 * of the cfi_varsize_frob() code.
2654 int size = regions[i].erasesize;
2657 * Only test sectors that shall not be unlocked. The other
2658 * sectors shall be unlocked, so lets keep their locking
2659 * status at "unlocked" (locked=0) for the final re-locking.
2661 if ((adr < ofs) || (adr >= (ofs + len))) {
2662 sect[sectors].chip = &cfi->chips[chipnum];
2663 sect[sectors].offset = offset;
2664 sect[sectors].locked = do_ppb_xxlock(
2665 map, &cfi->chips[chipnum], adr, 0,
2666 DO_XXLOCK_ONEBLOCK_GETLOCK);
2673 if (offset == regions[i].offset + size * regions[i].numblocks)
2676 if (adr >> cfi->chipshift) {
2680 if (chipnum >= cfi->numchips)
2685 if (sectors >= MAX_SECTORS) {
2686 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2693 /* Now unlock the whole chip */
2694 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2695 DO_XXLOCK_ONEBLOCK_UNLOCK);
2702 * PPB unlocking always unlocks all sectors of the flash chip.
2703 * We need to re-lock all previously locked sectors.
2705 for (i = 0; i < sectors; i++) {
2707 do_ppb_xxlock(map, sect[i].chip, sect[i].offset, 0,
2708 DO_XXLOCK_ONEBLOCK_LOCK);
2715 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2718 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2719 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2722 static void cfi_amdstd_sync (struct mtd_info *mtd)
2724 struct map_info *map = mtd->priv;
2725 struct cfi_private *cfi = map->fldrv_priv;
2727 struct flchip *chip;
2729 DECLARE_WAITQUEUE(wait, current);
2731 for (i=0; !ret && i<cfi->numchips; i++) {
2732 chip = &cfi->chips[i];
2735 mutex_lock(&chip->mutex);
2737 switch(chip->state) {
2741 case FL_JEDEC_QUERY:
2742 chip->oldstate = chip->state;
2743 chip->state = FL_SYNCING;
2744 /* No need to wake_up() on this state change -
2745 * as the whole point is that nobody can do anything
2746 * with the chip now anyway.
2749 mutex_unlock(&chip->mutex);
2753 /* Not an idle state */
2754 set_current_state(TASK_UNINTERRUPTIBLE);
2755 add_wait_queue(&chip->wq, &wait);
2757 mutex_unlock(&chip->mutex);
2761 remove_wait_queue(&chip->wq, &wait);
2767 /* Unlock the chips again */
2769 for (i--; i >=0; i--) {
2770 chip = &cfi->chips[i];
2772 mutex_lock(&chip->mutex);
2774 if (chip->state == FL_SYNCING) {
2775 chip->state = chip->oldstate;
2778 mutex_unlock(&chip->mutex);
2783 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2785 struct map_info *map = mtd->priv;
2786 struct cfi_private *cfi = map->fldrv_priv;
2788 struct flchip *chip;
2791 for (i=0; !ret && i<cfi->numchips; i++) {
2792 chip = &cfi->chips[i];
2794 mutex_lock(&chip->mutex);
2796 switch(chip->state) {
2800 case FL_JEDEC_QUERY:
2801 chip->oldstate = chip->state;
2802 chip->state = FL_PM_SUSPENDED;
2803 /* No need to wake_up() on this state change -
2804 * as the whole point is that nobody can do anything
2805 * with the chip now anyway.
2807 case FL_PM_SUSPENDED:
2814 mutex_unlock(&chip->mutex);
2817 /* Unlock the chips again */
2820 for (i--; i >=0; i--) {
2821 chip = &cfi->chips[i];
2823 mutex_lock(&chip->mutex);
2825 if (chip->state == FL_PM_SUSPENDED) {
2826 chip->state = chip->oldstate;
2829 mutex_unlock(&chip->mutex);
2837 static void cfi_amdstd_resume(struct mtd_info *mtd)
2839 struct map_info *map = mtd->priv;
2840 struct cfi_private *cfi = map->fldrv_priv;
2842 struct flchip *chip;
2844 for (i=0; i<cfi->numchips; i++) {
2846 chip = &cfi->chips[i];
2848 mutex_lock(&chip->mutex);
2850 if (chip->state == FL_PM_SUSPENDED) {
2851 chip->state = FL_READY;
2852 map_write(map, CMD(0xF0), chip->start);
2856 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2858 mutex_unlock(&chip->mutex);
2864 * Ensure that the flash device is put back into read array mode before
2865 * unloading the driver or rebooting. On some systems, rebooting while
2866 * the flash is in query/program/erase mode will prevent the CPU from
2867 * fetching the bootloader code, requiring a hard reset or power cycle.
2869 static int cfi_amdstd_reset(struct mtd_info *mtd)
2871 struct map_info *map = mtd->priv;
2872 struct cfi_private *cfi = map->fldrv_priv;
2874 struct flchip *chip;
2876 for (i = 0; i < cfi->numchips; i++) {
2878 chip = &cfi->chips[i];
2880 mutex_lock(&chip->mutex);
2882 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2884 map_write(map, CMD(0xF0), chip->start);
2885 chip->state = FL_SHUTDOWN;
2886 put_chip(map, chip, chip->start);
2889 mutex_unlock(&chip->mutex);
2896 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2899 struct mtd_info *mtd;
2901 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2902 cfi_amdstd_reset(mtd);
2907 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2909 struct map_info *map = mtd->priv;
2910 struct cfi_private *cfi = map->fldrv_priv;
2912 cfi_amdstd_reset(mtd);
2913 unregister_reboot_notifier(&mtd->reboot_notifier);
2914 kfree(cfi->cmdset_priv);
2917 kfree(mtd->eraseregions);
2920 MODULE_LICENSE("GPL");
2921 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2922 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2923 MODULE_ALIAS("cfi_cmdset_0006");
2924 MODULE_ALIAS("cfi_cmdset_0701");