drivers/mmc/host/sunxi-mmc.c

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
   5  * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
   7  * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/err.h>
  22
  23 #include <linux/clk.h>
  24 #include <linux/gpio.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/scatterlist.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/slab.h>
  30 #include <linux/reset.h>
  31 #include <linux/regulator/consumer.h>
  32
  33 #include <linux/of_address.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/of_platform.h>
  36
  37 #include <linux/mmc/host.h>
  38 #include <linux/mmc/sd.h>
  39 #include <linux/mmc/sdio.h>
  40 #include <linux/mmc/mmc.h>
  41 #include <linux/mmc/core.h>
  42 #include <linux/mmc/card.h>
  43 #include <linux/mmc/slot-gpio.h>
  44
  45 /* register offset definitions */
  46 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
  47 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
  48 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
  49 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
  50 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
  51 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
  52 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
  53 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
  54 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
  55 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
  56 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
  57 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
  58 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
  59 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
  60 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
  61 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
  62 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
  63 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
  64 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
  65 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
  66 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
  67 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
  68 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
  69 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
  70 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
  71 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
  72 #define SDXC_REG_CHDA   (0x90)
  73 #define SDXC_REG_CBDA   (0x94)
  74
  75 #define mmc_readl(host, reg) \
  76         readl((host)->reg_base + SDXC_##reg)
  77 #define mmc_writel(host, reg, value) \
  78         writel((value), (host)->reg_base + SDXC_##reg)
  79
  80 /* global control register bits */
  81 #define SDXC_SOFT_RESET                 BIT(0)
  82 #define SDXC_FIFO_RESET                 BIT(1)
  83 #define SDXC_DMA_RESET                  BIT(2)
  84 #define SDXC_INTERRUPT_ENABLE_BIT       BIT(4)
  85 #define SDXC_DMA_ENABLE_BIT             BIT(5)
  86 #define SDXC_DEBOUNCE_ENABLE_BIT        BIT(8)
  87 #define SDXC_POSEDGE_LATCH_DATA         BIT(9)
  88 #define SDXC_DDR_MODE                   BIT(10)
  89 #define SDXC_MEMORY_ACCESS_DONE         BIT(29)
  90 #define SDXC_ACCESS_DONE_DIRECT         BIT(30)
  91 #define SDXC_ACCESS_BY_AHB              BIT(31)
  92 #define SDXC_ACCESS_BY_DMA              (0 << 31)
  93 #define SDXC_HARDWARE_RESET \
  94         (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
  95
  96 /* clock control bits */
  97 #define SDXC_CARD_CLOCK_ON              BIT(16)
  98 #define SDXC_LOW_POWER_ON               BIT(17)
  99
 100 /* bus width */
 101 #define SDXC_WIDTH1                     0
 102 #define SDXC_WIDTH4                     1
 103 #define SDXC_WIDTH8                     2
 104
 105 /* smc command bits */
 106 #define SDXC_RESP_EXPIRE                BIT(6)
 107 #define SDXC_LONG_RESPONSE              BIT(7)
 108 #define SDXC_CHECK_RESPONSE_CRC         BIT(8)
 109 #define SDXC_DATA_EXPIRE                BIT(9)
 110 #define SDXC_WRITE                      BIT(10)
 111 #define SDXC_SEQUENCE_MODE              BIT(11)
 112 #define SDXC_SEND_AUTO_STOP             BIT(12)
 113 #define SDXC_WAIT_PRE_OVER              BIT(13)
 114 #define SDXC_STOP_ABORT_CMD             BIT(14)
 115 #define SDXC_SEND_INIT_SEQUENCE         BIT(15)
 116 #define SDXC_UPCLK_ONLY                 BIT(21)
 117 #define SDXC_READ_CEATA_DEV             BIT(22)
 118 #define SDXC_CCS_EXPIRE                 BIT(23)
 119 #define SDXC_ENABLE_BIT_BOOT            BIT(24)
 120 #define SDXC_ALT_BOOT_OPTIONS           BIT(25)
 121 #define SDXC_BOOT_ACK_EXPIRE            BIT(26)
 122 #define SDXC_BOOT_ABORT                 BIT(27)
 123 #define SDXC_VOLTAGE_SWITCH             BIT(28)
 124 #define SDXC_USE_HOLD_REGISTER          BIT(29)
 125 #define SDXC_START                      BIT(31)
 126
 127 /* interrupt bits */
 128 #define SDXC_RESP_ERROR                 BIT(1)
 129 #define SDXC_COMMAND_DONE               BIT(2)
 130 #define SDXC_DATA_OVER                  BIT(3)
 131 #define SDXC_TX_DATA_REQUEST            BIT(4)
 132 #define SDXC_RX_DATA_REQUEST            BIT(5)
 133 #define SDXC_RESP_CRC_ERROR             BIT(6)
 134 #define SDXC_DATA_CRC_ERROR             BIT(7)
 135 #define SDXC_RESP_TIMEOUT               BIT(8)
 136 #define SDXC_DATA_TIMEOUT               BIT(9)
 137 #define SDXC_VOLTAGE_CHANGE_DONE        BIT(10)
 138 #define SDXC_FIFO_RUN_ERROR             BIT(11)
 139 #define SDXC_HARD_WARE_LOCKED           BIT(12)
 140 #define SDXC_START_BIT_ERROR            BIT(13)
 141 #define SDXC_AUTO_COMMAND_DONE          BIT(14)
 142 #define SDXC_END_BIT_ERROR              BIT(15)
 143 #define SDXC_SDIO_INTERRUPT             BIT(16)
 144 #define SDXC_CARD_INSERT                BIT(30)
 145 #define SDXC_CARD_REMOVE                BIT(31)
 146 #define SDXC_INTERRUPT_ERROR_BIT \
 147         (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
 148          SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
 149          SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
 150 #define SDXC_INTERRUPT_DONE_BIT \
 151         (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
 152          SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
 153
 154 /* status */
 155 #define SDXC_RXWL_FLAG                  BIT(0)
 156 #define SDXC_TXWL_FLAG                  BIT(1)
 157 #define SDXC_FIFO_EMPTY                 BIT(2)
 158 #define SDXC_FIFO_FULL                  BIT(3)
 159 #define SDXC_CARD_PRESENT               BIT(8)
 160 #define SDXC_CARD_DATA_BUSY             BIT(9)
 161 #define SDXC_DATA_FSM_BUSY              BIT(10)
 162 #define SDXC_DMA_REQUEST                BIT(31)
 163 #define SDXC_FIFO_SIZE                  16
 164
 165 /* Function select */
 166 #define SDXC_CEATA_ON                   (0xceaa << 16)
 167 #define SDXC_SEND_IRQ_RESPONSE          BIT(0)
 168 #define SDXC_SDIO_READ_WAIT             BIT(1)
 169 #define SDXC_ABORT_READ_DATA            BIT(2)
 170 #define SDXC_SEND_CCSD                  BIT(8)
 171 #define SDXC_SEND_AUTO_STOPCCSD         BIT(9)
 172 #define SDXC_CEATA_DEV_IRQ_ENABLE       BIT(10)
 173
 174 /* IDMA controller bus mod bit field */
 175 #define SDXC_IDMAC_SOFT_RESET           BIT(0)
 176 #define SDXC_IDMAC_FIX_BURST            BIT(1)
 177 #define SDXC_IDMAC_IDMA_ON              BIT(7)
 178 #define SDXC_IDMAC_REFETCH_DES          BIT(31)
 179
 180 /* IDMA status bit field */
 181 #define SDXC_IDMAC_TRANSMIT_INTERRUPT           BIT(0)
 182 #define SDXC_IDMAC_RECEIVE_INTERRUPT            BIT(1)
 183 #define SDXC_IDMAC_FATAL_BUS_ERROR              BIT(2)
 184 #define SDXC_IDMAC_DESTINATION_INVALID          BIT(4)
 185 #define SDXC_IDMAC_CARD_ERROR_SUM               BIT(5)
 186 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM         BIT(8)
 187 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM       BIT(9)
 188 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT         BIT(10)
 189 #define SDXC_IDMAC_IDLE                         (0 << 13)
 190 #define SDXC_IDMAC_SUSPEND                      (1 << 13)
 191 #define SDXC_IDMAC_DESC_READ                    (2 << 13)
 192 #define SDXC_IDMAC_DESC_CHECK                   (3 << 13)
 193 #define SDXC_IDMAC_READ_REQUEST_WAIT            (4 << 13)
 194 #define SDXC_IDMAC_WRITE_REQUEST_WAIT           (5 << 13)
 195 #define SDXC_IDMAC_READ                         (6 << 13)
 196 #define SDXC_IDMAC_WRITE                        (7 << 13)
 197 #define SDXC_IDMAC_DESC_CLOSE                   (8 << 13)
 198
 199 /*
 200 * If the idma-des-size-bits of property is ie 13, bufsize bits are:
 201 *  Bits  0-12: buf1 size
 202 *  Bits 13-25: buf2 size
 203 *  Bits 26-31: not used
 204 * Since we only ever set buf1 size, we can simply store it directly.
 205 */
 206 #define SDXC_IDMAC_DES0_DIC     BIT(1)  /* disable interrupt on completion */
 207 #define SDXC_IDMAC_DES0_LD      BIT(2)  /* last descriptor */
 208 #define SDXC_IDMAC_DES0_FD      BIT(3)  /* first descriptor */
 209 #define SDXC_IDMAC_DES0_CH      BIT(4)  /* chain mode */
 210 #define SDXC_IDMAC_DES0_ER      BIT(5)  /* end of ring */
 211 #define SDXC_IDMAC_DES0_CES     BIT(30) /* card error summary */
 212 #define SDXC_IDMAC_DES0_OWN     BIT(31) /* 1-idma owns it, 0-host owns it */
 213
 214 #define SDXC_CLK_400K           0
 215 #define SDXC_CLK_25M            1
 216 #define SDXC_CLK_50M            2
 217 #define SDXC_CLK_50M_DDR        3
 218
 219 struct sunxi_mmc_clk_delay {
 220         u32 output;
 221         u32 sample;
 222 };
 223
 224 struct sunxi_idma_des {
 225         u32     config;
 226         u32     buf_size;
 227         u32     buf_addr_ptr1;
 228         u32     buf_addr_ptr2;
 229 };
 230
 231 struct sunxi_mmc_host {
 232         struct mmc_host *mmc;
 233         struct reset_control *reset;
 234
 235         /* IO mapping base */
 236         void __iomem    *reg_base;
 237
 238         /* clock management */
 239         struct clk      *clk_ahb;
 240         struct clk      *clk_mmc;
 241         struct clk      *clk_sample;
 242         struct clk      *clk_output;
 243         const struct sunxi_mmc_clk_delay *clk_delays;
 244
 245         /* irq */
 246         spinlock_t      lock;
 247         int             irq;
 248         u32             int_sum;
 249         u32             sdio_imask;
 250
 251         /* dma */
 252         u32             idma_des_size_bits;
 253         dma_addr_t      sg_dma;
 254         void            *sg_cpu;
 255         bool            wait_dma;
 256
 257         struct mmc_request *mrq;
 258         struct mmc_request *manual_stop_mrq;
 259         int             ferror;
 260
 261         /* vqmmc */
 262         bool            vqmmc_enabled;
 263 };
 264
 265 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
 266 {
 267         unsigned long expire = jiffies + msecs_to_jiffies(250);
 268         u32 rval;
 269
 270         mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
 271         do {
 272                 rval = mmc_readl(host, REG_GCTRL);
 273         } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
 274
 275         if (rval & SDXC_HARDWARE_RESET) {
 276                 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
 277                 return -EIO;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int sunxi_mmc_init_host(struct mmc_host *mmc)
 284 {
 285         u32 rval;
 286         struct sunxi_mmc_host *host = mmc_priv(mmc);
 287
 288         if (sunxi_mmc_reset_host(host))
 289                 return -EIO;
 290
 291         /*
 292          * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
 293          *
 294          * TODO: sun9i has a larger FIFO and supports higher trigger values
 295          */
 296         mmc_writel(host, REG_FTRGL, 0x20070008);
 297         /* Maximum timeout value */
 298         mmc_writel(host, REG_TMOUT, 0xffffffff);
 299         /* Unmask SDIO interrupt if needed */
 300         mmc_writel(host, REG_IMASK, host->sdio_imask);
 301         /* Clear all pending interrupts */
 302         mmc_writel(host, REG_RINTR, 0xffffffff);
 303         /* Debug register? undocumented */
 304         mmc_writel(host, REG_DBGC, 0xdeb);
 305         /* Enable CEATA support */
 306         mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
 307         /* Set DMA descriptor list base address */
 308         mmc_writel(host, REG_DLBA, host->sg_dma);
 309
 310         rval = mmc_readl(host, REG_GCTRL);
 311         rval |= SDXC_INTERRUPT_ENABLE_BIT;
 312         /* Undocumented, but found in Allwinner code */
 313         rval &= ~SDXC_ACCESS_DONE_DIRECT;
 314         mmc_writel(host, REG_GCTRL, rval);
 315
 316         return 0;
 317 }
 318
 319 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
 320                                     struct mmc_data *data)
 321 {
 322         struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
 323         dma_addr_t next_desc = host->sg_dma;
 324         int i, max_len = (1 << host->idma_des_size_bits);
 325
 326         for (i = 0; i < data->sg_len; i++) {
 327                 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
 328                                  SDXC_IDMAC_DES0_DIC;
 329
 330                 if (data->sg[i].length == max_len)
 331                         pdes[i].buf_size = 0; /* 0 == max_len */
 332                 else
 333                         pdes[i].buf_size = data->sg[i].length;
 334
 335                 next_desc += sizeof(struct sunxi_idma_des);
 336                 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
 337                 pdes[i].buf_addr_ptr2 = (u32)next_desc;
 338         }
 339
 340         pdes[0].config |= SDXC_IDMAC_DES0_FD;
 341         pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER;
 342         pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC;
 343         pdes[i - 1].buf_addr_ptr2 = 0;
 344
 345         /*
 346          * Avoid the io-store starting the idmac hitting io-mem before the
 347          * descriptors hit the main-mem.
 348          */
 349         wmb();
 350 }
 351
 352 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
 353 {
 354         if (data->flags & MMC_DATA_WRITE)
 355                 return DMA_TO_DEVICE;
 356         else
 357                 return DMA_FROM_DEVICE;
 358 }
 359
 360 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
 361                              struct mmc_data *data)
 362 {
 363         u32 i, dma_len;
 364         struct scatterlist *sg;
 365
 366         dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 367                              sunxi_mmc_get_dma_dir(data));
 368         if (dma_len == 0) {
 369                 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
 370                 return -ENOMEM;
 371         }
 372
 373         for_each_sg(data->sg, sg, data->sg_len, i) {
 374                 if (sg->offset & 3 || sg->length & 3) {
 375                         dev_err(mmc_dev(host->mmc),
 376                                 "unaligned scatterlist: os %x length %d\n",
 377                                 sg->offset, sg->length);
 378                         return -EINVAL;
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
 386                                 struct mmc_data *data)
 387 {
 388         u32 rval;
 389
 390         sunxi_mmc_init_idma_des(host, data);
 391
 392         rval = mmc_readl(host, REG_GCTRL);
 393         rval |= SDXC_DMA_ENABLE_BIT;
 394         mmc_writel(host, REG_GCTRL, rval);
 395         rval |= SDXC_DMA_RESET;
 396         mmc_writel(host, REG_GCTRL, rval);
 397
 398         mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
 399
 400         if (!(data->flags & MMC_DATA_WRITE))
 401                 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
 402
 403         mmc_writel(host, REG_DMAC,
 404                    SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
 405 }
 406
 407 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
 408                                        struct mmc_request *req)
 409 {
 410         u32 arg, cmd_val, ri;
 411         unsigned long expire = jiffies + msecs_to_jiffies(1000);
 412
 413         cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
 414                   SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
 415
 416         if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
 417                 cmd_val |= SD_IO_RW_DIRECT;
 418                 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 419                       ((req->cmd->arg >> 28) & 0x7);
 420         } else {
 421                 cmd_val |= MMC_STOP_TRANSMISSION;
 422                 arg = 0;
 423         }
 424
 425         mmc_writel(host, REG_CARG, arg);
 426         mmc_writel(host, REG_CMDR, cmd_val);
 427
 428         do {
 429                 ri = mmc_readl(host, REG_RINTR);
 430         } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
 431                  time_before(jiffies, expire));
 432
 433         if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
 434                 dev_err(mmc_dev(host->mmc), "send stop command failed\n");
 435                 if (req->stop)
 436                         req->stop->resp[0] = -ETIMEDOUT;
 437         } else {
 438                 if (req->stop)
 439                         req->stop->resp[0] = mmc_readl(host, REG_RESP0);
 440         }
 441
 442         mmc_writel(host, REG_RINTR, 0xffff);
 443 }
 444
 445 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
 446 {
 447         struct mmc_command *cmd = host->mrq->cmd;
 448         struct mmc_data *data = host->mrq->data;
 449
 450         /* For some cmds timeout is normal with sd/mmc cards */
 451         if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
 452                 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
 453                                       cmd->opcode == SD_IO_RW_DIRECT))
 454                 return;
 455
 456         dev_err(mmc_dev(host->mmc),
 457                 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
 458                 host->mmc->index, cmd->opcode,
 459                 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
 460                 host->int_sum & SDXC_RESP_ERROR     ? " RE"     : "",
 461                 host->int_sum & SDXC_RESP_CRC_ERROR  ? " RCE"    : "",
 462                 host->int_sum & SDXC_DATA_CRC_ERROR  ? " DCE"    : "",
 463                 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO"    : "",
 464                 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO"    : "",
 465                 host->int_sum & SDXC_FIFO_RUN_ERROR  ? " FE"     : "",
 466                 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL"     : "",
 467                 host->int_sum & SDXC_START_BIT_ERROR ? " SBE"    : "",
 468                 host->int_sum & SDXC_END_BIT_ERROR   ? " EBE"    : ""
 469                 );
 470 }
 471
 472 /* Called in interrupt context! */
 473 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
 474 {
 475         struct mmc_request *mrq = host->mrq;
 476         struct mmc_data *data = mrq->data;
 477         u32 rval;
 478
 479         mmc_writel(host, REG_IMASK, host->sdio_imask);
 480         mmc_writel(host, REG_IDIE, 0);
 481
 482         if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
 483                 sunxi_mmc_dump_errinfo(host);
 484                 mrq->cmd->error = -ETIMEDOUT;
 485
 486                 if (data) {
 487                         data->error = -ETIMEDOUT;
 488                         host->manual_stop_mrq = mrq;
 489                 }
 490
 491                 if (mrq->stop)
 492                         mrq->stop->error = -ETIMEDOUT;
 493         } else {
 494                 if (mrq->cmd->flags & MMC_RSP_136) {
 495                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
 496                         mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
 497                         mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
 498                         mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
 499                 } else {
 500                         mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
 501                 }
 502
 503                 if (data)
 504                         data->bytes_xfered = data->blocks * data->blksz;
 505         }
 506
 507         if (data) {
 508                 mmc_writel(host, REG_IDST, 0x337);
 509                 mmc_writel(host, REG_DMAC, 0);
 510                 rval = mmc_readl(host, REG_GCTRL);
 511                 rval |= SDXC_DMA_RESET;
 512                 mmc_writel(host, REG_GCTRL, rval);
 513                 rval &= ~SDXC_DMA_ENABLE_BIT;
 514                 mmc_writel(host, REG_GCTRL, rval);
 515                 rval |= SDXC_FIFO_RESET;
 516                 mmc_writel(host, REG_GCTRL, rval);
 517                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 518                                      sunxi_mmc_get_dma_dir(data));
 519         }
 520
 521         mmc_writel(host, REG_RINTR, 0xffff);
 522
 523         host->mrq = NULL;
 524         host->int_sum = 0;
 525         host->wait_dma = false;
 526
 527         return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
 528 }
 529
 530 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
 531 {
 532         struct sunxi_mmc_host *host = dev_id;
 533         struct mmc_request *mrq;
 534         u32 msk_int, idma_int;
 535         bool finalize = false;
 536         bool sdio_int = false;
 537         irqreturn_t ret = IRQ_HANDLED;
 538
 539         spin_lock(&host->lock);
 540
 541         idma_int  = mmc_readl(host, REG_IDST);
 542         msk_int   = mmc_readl(host, REG_MISTA);
 543
 544         dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
 545                 host->mrq, msk_int, idma_int);
 546
 547         mrq = host->mrq;
 548         if (mrq) {
 549                 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
 550                         host->wait_dma = false;
 551
 552                 host->int_sum |= msk_int;
 553
 554                 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
 555                 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
 556                                 !(host->int_sum & SDXC_COMMAND_DONE))
 557                         mmc_writel(host, REG_IMASK,
 558                                    host->sdio_imask | SDXC_COMMAND_DONE);
 559                 /* Don't wait for dma on error */
 560                 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
 561                         finalize = true;
 562                 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
 563                                 !host->wait_dma)
 564                         finalize = true;
 565         }
 566
 567         if (msk_int & SDXC_SDIO_INTERRUPT)
 568                 sdio_int = true;
 569
 570         mmc_writel(host, REG_RINTR, msk_int);
 571         mmc_writel(host, REG_IDST, idma_int);
 572
 573         if (finalize)
 574                 ret = sunxi_mmc_finalize_request(host);
 575
 576         spin_unlock(&host->lock);
 577
 578         if (finalize && ret == IRQ_HANDLED)
 579                 mmc_request_done(host->mmc, mrq);
 580
 581         if (sdio_int)
 582                 mmc_signal_sdio_irq(host->mmc);
 583
 584         return ret;
 585 }
 586
 587 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
 588 {
 589         struct sunxi_mmc_host *host = dev_id;
 590         struct mmc_request *mrq;
 591         unsigned long iflags;
 592
 593         spin_lock_irqsave(&host->lock, iflags);
 594         mrq = host->manual_stop_mrq;
 595         spin_unlock_irqrestore(&host->lock, iflags);
 596
 597         if (!mrq) {
 598                 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
 599                 return IRQ_HANDLED;
 600         }
 601
 602         dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
 603
 604         /*
 605          * We will never have more than one outstanding request,
 606          * and we do not complete the request until after
 607          * we've cleared host->manual_stop_mrq so we do not need to
 608          * spin lock this function.
 609          * Additionally we have wait states within this function
 610          * so having it in a lock is a very bad idea.
 611          */
 612         sunxi_mmc_send_manual_stop(host, mrq);
 613
 614         spin_lock_irqsave(&host->lock, iflags);
 615         host->manual_stop_mrq = NULL;
 616         spin_unlock_irqrestore(&host->lock, iflags);
 617
 618         mmc_request_done(host->mmc, mrq);
 619
 620         return IRQ_HANDLED;
 621 }
 622
 623 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 624 {
 625         unsigned long expire = jiffies + msecs_to_jiffies(750);
 626         u32 rval;
 627
 628         rval = mmc_readl(host, REG_CLKCR);
 629         rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
 630
 631         if (oclk_en)
 632                 rval |= SDXC_CARD_CLOCK_ON;
 633
 634         mmc_writel(host, REG_CLKCR, rval);
 635
 636         rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
 637         mmc_writel(host, REG_CMDR, rval);
 638
 639         do {
 640                 rval = mmc_readl(host, REG_CMDR);
 641         } while (time_before(jiffies, expire) && (rval & SDXC_START));
 642
 643         /* clear irq status bits set by the command */
 644         mmc_writel(host, REG_RINTR,
 645                    mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
 646
 647         if (rval & SDXC_START) {
 648                 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
 649                 return -EIO;
 650         }
 651
 652         return 0;
 653 }
 654
 655 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 656                                   struct mmc_ios *ios)
 657 {
 658         u32 rate, oclk_dly, rval, sclk_dly;
 659         int ret;
 660
 661         rate = clk_round_rate(host->clk_mmc, ios->clock);
 662         dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
 663                 ios->clock, rate);
 664
 665         /* setting clock rate */
 666         ret = clk_set_rate(host->clk_mmc, rate);
 667         if (ret) {
 668                 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
 669                         rate, ret);
 670                 return ret;
 671         }
 672
 673         ret = sunxi_mmc_oclk_onoff(host, 0);
 674         if (ret)
 675                 return ret;
 676
 677         /* clear internal divider */
 678         rval = mmc_readl(host, REG_CLKCR);
 679         rval &= ~0xff;
 680         mmc_writel(host, REG_CLKCR, rval);
 681
 682         /* determine delays */
 683         if (rate <= 400000) {
 684                 oclk_dly = host->clk_delays[SDXC_CLK_400K].output;
 685                 sclk_dly = host->clk_delays[SDXC_CLK_400K].sample;
 686         } else if (rate <= 25000000) {
 687                 oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
 688                 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
 689         } else if (rate <= 50000000) {
 690                 if (ios->timing == MMC_TIMING_UHS_DDR50) {
 691                         oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
 692                         sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
 693                 } else {
 694                         oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
 695                         sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
 696                 }
 697         } else {
 698                 return -EINVAL;
 699         }
 700
 701         clk_set_phase(host->clk_sample, sclk_dly);
 702         clk_set_phase(host->clk_output, oclk_dly);
 703
 704         return sunxi_mmc_oclk_onoff(host, 1);
 705 }
 706
 707 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 708 {
 709         struct sunxi_mmc_host *host = mmc_priv(mmc);
 710         u32 rval;
 711
 712         /* Set the power state */
 713         switch (ios->power_mode) {
 714         case MMC_POWER_ON:
 715                 break;
 716
 717         case MMC_POWER_UP:
 718                 host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
 719                                                      ios->vdd);
 720                 if (host->ferror)
 721                         return;
 722
 723                 if (!IS_ERR(mmc->supply.vqmmc)) {
 724                         host->ferror = regulator_enable(mmc->supply.vqmmc);
 725                         if (host->ferror) {
 726                                 dev_err(mmc_dev(mmc),
 727                                         "failed to enable vqmmc\n");
 728                                 return;
 729                         }
 730                         host->vqmmc_enabled = true;
 731                 }
 732
 733                 host->ferror = sunxi_mmc_init_host(mmc);
 734                 if (host->ferror)
 735                         return;
 736
 737                 dev_dbg(mmc_dev(mmc), "power on!\n");
 738                 break;
 739
 740         case MMC_POWER_OFF:
 741                 dev_dbg(mmc_dev(mmc), "power off!\n");
 742                 sunxi_mmc_reset_host(host);
 743                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 744                 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
 745                         regulator_disable(mmc->supply.vqmmc);
 746                 host->vqmmc_enabled = false;
 747                 break;
 748         }
 749
 750         /* set bus width */
 751         switch (ios->bus_width) {
 752         case MMC_BUS_WIDTH_1:
 753                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
 754                 break;
 755         case MMC_BUS_WIDTH_4:
 756                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
 757                 break;
 758         case MMC_BUS_WIDTH_8:
 759                 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
 760                 break;
 761         }
 762
 763         /* set ddr mode */
 764         rval = mmc_readl(host, REG_GCTRL);
 765         if (ios->timing == MMC_TIMING_UHS_DDR50)
 766                 rval |= SDXC_DDR_MODE;
 767         else
 768                 rval &= ~SDXC_DDR_MODE;
 769         mmc_writel(host, REG_GCTRL, rval);
 770
 771         /* set up clock */
 772         if (ios->clock && ios->power_mode) {
 773                 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
 774                 /* Android code had a usleep_range(50000, 55000); here */
 775         }
 776 }
 777
 778 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
 779 {
 780         /* vqmmc regulator is available */
 781         if (!IS_ERR(mmc->supply.vqmmc))
 782                 return mmc_regulator_set_vqmmc(mmc, ios);
 783
 784         /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
 785         if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 786                 return 0;
 787
 788         return -EINVAL;
 789 }
 790
 791 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 792 {
 793         struct sunxi_mmc_host *host = mmc_priv(mmc);
 794         unsigned long flags;
 795         u32 imask;
 796
 797         spin_lock_irqsave(&host->lock, flags);
 798
 799         imask = mmc_readl(host, REG_IMASK);
 800         if (enable) {
 801                 host->sdio_imask = SDXC_SDIO_INTERRUPT;
 802                 imask |= SDXC_SDIO_INTERRUPT;
 803         } else {
 804                 host->sdio_imask = 0;
 805                 imask &= ~SDXC_SDIO_INTERRUPT;
 806         }
 807         mmc_writel(host, REG_IMASK, imask);
 808         spin_unlock_irqrestore(&host->lock, flags);
 809 }
 810
 811 static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
 812 {
 813         struct sunxi_mmc_host *host = mmc_priv(mmc);
 814         mmc_writel(host, REG_HWRST, 0);
 815         udelay(10);
 816         mmc_writel(host, REG_HWRST, 1);
 817         udelay(300);
 818 }
 819
 820 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 821 {
 822         struct sunxi_mmc_host *host = mmc_priv(mmc);
 823         struct mmc_command *cmd = mrq->cmd;
 824         struct mmc_data *data = mrq->data;
 825         unsigned long iflags;
 826         u32 imask = SDXC_INTERRUPT_ERROR_BIT;
 827         u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
 828         bool wait_dma = host->wait_dma;
 829         int ret;
 830
 831         /* Check for set_ios errors (should never happen) */
 832         if (host->ferror) {
 833                 mrq->cmd->error = host->ferror;
 834                 mmc_request_done(mmc, mrq);
 835                 return;
 836         }
 837
 838         if (data) {
 839                 ret = sunxi_mmc_map_dma(host, data);
 840                 if (ret < 0) {
 841                         dev_err(mmc_dev(mmc), "map DMA failed\n");
 842                         cmd->error = ret;
 843                         data->error = ret;
 844                         mmc_request_done(mmc, mrq);
 845                         return;
 846                 }
 847         }
 848
 849         if (cmd->opcode == MMC_GO_IDLE_STATE) {
 850                 cmd_val |= SDXC_SEND_INIT_SEQUENCE;
 851                 imask |= SDXC_COMMAND_DONE;
 852         }
 853
 854         if (cmd->flags & MMC_RSP_PRESENT) {
 855                 cmd_val |= SDXC_RESP_EXPIRE;
 856                 if (cmd->flags & MMC_RSP_136)
 857                         cmd_val |= SDXC_LONG_RESPONSE;
 858                 if (cmd->flags & MMC_RSP_CRC)
 859                         cmd_val |= SDXC_CHECK_RESPONSE_CRC;
 860
 861                 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
 862                         cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
 863                         if (cmd->data->flags & MMC_DATA_STREAM) {
 864                                 imask |= SDXC_AUTO_COMMAND_DONE;
 865                                 cmd_val |= SDXC_SEQUENCE_MODE |
 866                                            SDXC_SEND_AUTO_STOP;
 867                         }
 868
 869                         if (cmd->data->stop) {
 870                                 imask |= SDXC_AUTO_COMMAND_DONE;
 871                                 cmd_val |= SDXC_SEND_AUTO_STOP;
 872                         } else {
 873                                 imask |= SDXC_DATA_OVER;
 874                         }
 875
 876                         if (cmd->data->flags & MMC_DATA_WRITE)
 877                                 cmd_val |= SDXC_WRITE;
 878                         else
 879                                 wait_dma = true;
 880                 } else {
 881                         imask |= SDXC_COMMAND_DONE;
 882                 }
 883         } else {
 884                 imask |= SDXC_COMMAND_DONE;
 885         }
 886
 887         dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
 888                 cmd_val & 0x3f, cmd_val, cmd->arg, imask,
 889                 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
 890
 891         spin_lock_irqsave(&host->lock, iflags);
 892
 893         if (host->mrq || host->manual_stop_mrq) {
 894                 spin_unlock_irqrestore(&host->lock, iflags);
 895
 896                 if (data)
 897                         dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
 898                                      sunxi_mmc_get_dma_dir(data));
 899
 900                 dev_err(mmc_dev(mmc), "request already pending\n");
 901                 mrq->cmd->error = -EBUSY;
 902                 mmc_request_done(mmc, mrq);
 903                 return;
 904         }
 905
 906         if (data) {
 907                 mmc_writel(host, REG_BLKSZ, data->blksz);
 908                 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
 909                 sunxi_mmc_start_dma(host, data);
 910         }
 911
 912         host->mrq = mrq;
 913         host->wait_dma = wait_dma;
 914         mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
 915         mmc_writel(host, REG_CARG, cmd->arg);
 916         mmc_writel(host, REG_CMDR, cmd_val);
 917
 918         spin_unlock_irqrestore(&host->lock, iflags);
 919 }
 920
 921 static int sunxi_mmc_card_busy(struct mmc_host *mmc)
 922 {
 923         struct sunxi_mmc_host *host = mmc_priv(mmc);
 924
 925         return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
 926 }
 927
 928 static const struct of_device_id sunxi_mmc_of_match[] = {
 929         { .compatible = "allwinner,sun4i-a10-mmc", },
 930         { .compatible = "allwinner,sun5i-a13-mmc", },
 931         { .compatible = "allwinner,sun9i-a80-mmc", },
 932         { /* sentinel */ }
 933 };
 934 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
 935
 936 static struct mmc_host_ops sunxi_mmc_ops = {
 937         .request         = sunxi_mmc_request,
 938         .set_ios         = sunxi_mmc_set_ios,
 939         .get_ro          = mmc_gpio_get_ro,
 940         .get_cd          = mmc_gpio_get_cd,
 941         .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
 942         .start_signal_voltage_switch = sunxi_mmc_volt_switch,
 943         .hw_reset        = sunxi_mmc_hw_reset,
 944         .card_busy       = sunxi_mmc_card_busy,
 945 };
 946
 947 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
 948         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
 949         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
 950         [SDXC_CLK_50M]          = { .output =  90, .sample = 120 },
 951         [SDXC_CLK_50M_DDR]      = { .output =  60, .sample = 120 },
 952 };
 953
 954 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 955         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
 956         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
 957         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
 958         [SDXC_CLK_50M_DDR]      = { .output =  90, .sample = 120 },
 959 };
 960
 961 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
 962                                       struct platform_device *pdev)
 963 {
 964         struct device_node *np = pdev->dev.of_node;
 965         int ret;
 966
 967         if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
 968                 host->idma_des_size_bits = 13;
 969         else
 970                 host->idma_des_size_bits = 16;
 971
 972         if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
 973                 host->clk_delays = sun9i_mmc_clk_delays;
 974         else
 975                 host->clk_delays = sunxi_mmc_clk_delays;
 976
 977         ret = mmc_regulator_get_supply(host->mmc);
 978         if (ret) {
 979                 if (ret != -EPROBE_DEFER)
 980                         dev_err(&pdev->dev, "Could not get vmmc supply\n");
 981                 return ret;
 982         }
 983
 984         host->reg_base = devm_ioremap_resource(&pdev->dev,
 985                               platform_get_resource(pdev, IORESOURCE_MEM, 0));
 986         if (IS_ERR(host->reg_base))
 987                 return PTR_ERR(host->reg_base);
 988
 989         host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 990         if (IS_ERR(host->clk_ahb)) {
 991                 dev_err(&pdev->dev, "Could not get ahb clock\n");
 992                 return PTR_ERR(host->clk_ahb);
 993         }
 994
 995         host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
 996         if (IS_ERR(host->clk_mmc)) {
 997                 dev_err(&pdev->dev, "Could not get mmc clock\n");
 998                 return PTR_ERR(host->clk_mmc);
 999         }
1000
1001         host->clk_output = devm_clk_get(&pdev->dev, "output");
1002         if (IS_ERR(host->clk_output)) {
1003                 dev_err(&pdev->dev, "Could not get output clock\n");
1004                 return PTR_ERR(host->clk_output);
1005         }
1006
1007         host->clk_sample = devm_clk_get(&pdev->dev, "sample");
1008         if (IS_ERR(host->clk_sample)) {
1009                 dev_err(&pdev->dev, "Could not get sample clock\n");
1010                 return PTR_ERR(host->clk_sample);
1011         }
1012
1013         host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
1014         if (PTR_ERR(host->reset) == -EPROBE_DEFER)
1015                 return PTR_ERR(host->reset);
1016
1017         ret = clk_prepare_enable(host->clk_ahb);
1018         if (ret) {
1019                 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret);
1020                 return ret;
1021         }
1022
1023         ret = clk_prepare_enable(host->clk_mmc);
1024         if (ret) {
1025                 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
1026                 goto error_disable_clk_ahb;
1027         }
1028
1029         ret = clk_prepare_enable(host->clk_output);
1030         if (ret) {
1031                 dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
1032                 goto error_disable_clk_mmc;
1033         }
1034
1035         ret = clk_prepare_enable(host->clk_sample);
1036         if (ret) {
1037                 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
1038                 goto error_disable_clk_output;
1039         }
1040
1041         if (!IS_ERR(host->reset)) {
1042                 ret = reset_control_deassert(host->reset);
1043                 if (ret) {
1044                         dev_err(&pdev->dev, "reset err %d\n", ret);
1045                         goto error_disable_clk_sample;
1046                 }
1047         }
1048
1049         /*
1050          * Sometimes the controller asserts the irq on boot for some reason,
1051          * make sure the controller is in a sane state before enabling irqs.
1052          */
1053         ret = sunxi_mmc_reset_host(host);
1054         if (ret)
1055                 goto error_assert_reset;
1056
1057         host->irq = platform_get_irq(pdev, 0);
1058         return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
1059                         sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
1060
1061 error_assert_reset:
1062         if (!IS_ERR(host->reset))
1063                 reset_control_assert(host->reset);
1064 error_disable_clk_sample:
1065         clk_disable_unprepare(host->clk_sample);
1066 error_disable_clk_output:
1067         clk_disable_unprepare(host->clk_output);
1068 error_disable_clk_mmc:
1069         clk_disable_unprepare(host->clk_mmc);
1070 error_disable_clk_ahb:
1071         clk_disable_unprepare(host->clk_ahb);
1072         return ret;
1073 }
1074
1075 static int sunxi_mmc_probe(struct platform_device *pdev)
1076 {
1077         struct sunxi_mmc_host *host;
1078         struct mmc_host *mmc;
1079         int ret;
1080
1081         mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
1082         if (!mmc) {
1083                 dev_err(&pdev->dev, "mmc alloc host failed\n");
1084                 return -ENOMEM;
1085         }
1086
1087         host = mmc_priv(mmc);
1088         host->mmc = mmc;
1089         spin_lock_init(&host->lock);
1090
1091         ret = sunxi_mmc_resource_request(host, pdev);
1092         if (ret)
1093                 goto error_free_host;
1094
1095         host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1096                                           &host->sg_dma, GFP_KERNEL);
1097         if (!host->sg_cpu) {
1098                 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
1099                 ret = -ENOMEM;
1100                 goto error_free_host;
1101         }
1102
1103         mmc->ops                = &sunxi_mmc_ops;
1104         mmc->max_blk_count      = 8192;
1105         mmc->max_blk_size       = 4096;
1106         mmc->max_segs           = PAGE_SIZE / sizeof(struct sunxi_idma_des);
1107         mmc->max_seg_size       = (1 << host->idma_des_size_bits);
1108         mmc->max_req_size       = mmc->max_seg_size * mmc->max_segs;
1109         /* 400kHz ~ 50MHz */
1110         mmc->f_min              =   400000;
1111         mmc->f_max              = 50000000;
1112         mmc->caps              |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1113                                   MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
1114
1115         ret = mmc_of_parse(mmc);
1116         if (ret)
1117                 goto error_free_dma;
1118
1119         ret = mmc_add_host(mmc);
1120         if (ret)
1121                 goto error_free_dma;
1122
1123         dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
1124         platform_set_drvdata(pdev, mmc);
1125         return 0;
1126
1127 error_free_dma:
1128         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1129 error_free_host:
1130         mmc_free_host(mmc);
1131         return ret;
1132 }
1133
1134 static int sunxi_mmc_remove(struct platform_device *pdev)
1135 {
1136         struct mmc_host *mmc = platform_get_drvdata(pdev);
1137         struct sunxi_mmc_host *host = mmc_priv(mmc);
1138
1139         mmc_remove_host(mmc);
1140         disable_irq(host->irq);
1141         sunxi_mmc_reset_host(host);
1142
1143         if (!IS_ERR(host->reset))
1144                 reset_control_assert(host->reset);
1145
1146         clk_disable_unprepare(host->clk_mmc);
1147         clk_disable_unprepare(host->clk_ahb);
1148
1149         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1150         mmc_free_host(mmc);
1151
1152         return 0;
1153 }
1154
1155 static struct platform_driver sunxi_mmc_driver = {
1156         .driver = {
1157                 .name   = "sunxi-mmc",
1158                 .of_match_table = of_match_ptr(sunxi_mmc_of_match),
1159         },
1160         .probe          = sunxi_mmc_probe,
1161         .remove         = sunxi_mmc_remove,
1162 };
1163 module_platform_driver(sunxi_mmc_driver);
1164
1165 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
1166 MODULE_LICENSE("GPL v2");
1167 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>");
1168 MODULE_ALIAS("platform:sunxi-mmc");