1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
9 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/property.h>
14 #include <linux/regmap.h>
15 #include <linux/sys_soc.h>
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
21 /* CTL_CFG Registers */
22 #define CTL_CFG_2 0x14
23 #define CTL_CFG_3 0x18
25 #define SLOTTYPE_MASK GENMASK(31, 30)
26 #define SLOTTYPE_EMBEDDED BIT(30)
27 #define TUNINGFORSDR50_MASK BIT(13)
30 #define PHY_CTRL1 0x100
31 #define PHY_CTRL2 0x104
32 #define PHY_CTRL3 0x108
33 #define PHY_CTRL4 0x10C
34 #define PHY_CTRL5 0x110
35 #define PHY_CTRL6 0x114
36 #define PHY_STAT1 0x130
37 #define PHY_STAT2 0x134
39 #define IOMUX_ENABLE_SHIFT 31
40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
41 #define OTAPDLYENA_SHIFT 20
42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
43 #define OTAPDLYSEL_SHIFT 12
44 #define OTAPDLYSEL_MASK GENMASK(15, 12)
45 #define STRBSEL_SHIFT 24
46 #define STRBSEL_4BIT_MASK GENMASK(27, 24)
47 #define STRBSEL_8BIT_MASK GENMASK(31, 24)
49 #define SEL50_MASK BIT(SEL50_SHIFT)
50 #define SEL100_SHIFT 9
51 #define SEL100_MASK BIT(SEL100_SHIFT)
52 #define FREQSEL_SHIFT 8
53 #define FREQSEL_MASK GENMASK(10, 8)
54 #define CLKBUFSEL_SHIFT 0
55 #define CLKBUFSEL_MASK GENMASK(2, 0)
56 #define DLL_TRIM_ICP_SHIFT 4
57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
58 #define DR_TY_SHIFT 20
59 #define DR_TY_MASK GENMASK(22, 20)
61 #define ENDLL_MASK BIT(ENDLL_SHIFT)
62 #define DLLRDY_SHIFT 0
63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
65 #define PDB_MASK BIT(PDB_SHIFT)
66 #define CALDONE_SHIFT 1
67 #define CALDONE_MASK BIT(CALDONE_SHIFT)
68 #define RETRIM_SHIFT 17
69 #define RETRIM_MASK BIT(RETRIM_SHIFT)
70 #define SELDLYTXCLK_SHIFT 17
71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
72 #define SELDLYRXCLK_SHIFT 16
73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
74 #define ITAPDLYSEL_SHIFT 0
75 #define ITAPDLYSEL_MASK GENMASK(4, 0)
76 #define ITAPDLYENA_SHIFT 8
77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
78 #define ITAPCHGWIN_SHIFT 9
79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
81 #define DRIVER_STRENGTH_50_OHM 0x0
82 #define DRIVER_STRENGTH_33_OHM 0x1
83 #define DRIVER_STRENGTH_66_OHM 0x2
84 #define DRIVER_STRENGTH_100_OHM 0x3
85 #define DRIVER_STRENGTH_40_OHM 0x4
87 #define CLOCK_TOO_SLOW_HZ 50000000
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
90 /* Command Queue Host Controller Interface Base address */
91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200
93 static struct regmap_config sdhci_am654_regmap_config = {
101 const char *otap_binding;
102 const char *itap_binding;
106 static const struct timing_data td[] = {
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
112 MMC_CAP_MMC_HIGHSPEED},
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
115 MMC_CAP_SD_HIGHSPEED},
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
142 struct sdhci_am654_data {
144 u32 otap_del_sel[ARRAY_SIZE(td)];
145 u32 itap_del_sel[ARRAY_SIZE(td)];
146 u32 itap_del_ena[ARRAY_SIZE(td)];
155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0)
164 struct sdhci_am654_driver_data {
165 const struct sdhci_pltfm_data *pdata;
167 #define IOMUX_PRESENT (1 << 0)
168 #define FREQSEL_2_BIT (1 << 1)
169 #define STRBSEL_4_BIT (1 << 2)
170 #define DLL_PRESENT (1 << 3)
171 #define DLL_CALIB (1 << 4)
174 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
178 int sel50, sel100, freqsel;
182 /* Disable delay chain mode */
183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
186 if (sdhci_am654->flags & FREQSEL_2_BIT) {
201 /* Configure PHY DLL frequency */
202 mask = SEL50_MASK | SEL100_MASK;
203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
216 freqsel << FREQSEL_SHIFT);
218 /* Configure DLL TRIM */
219 mask = DLL_TRIM_ICP_MASK;
220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
222 /* Configure DLL driver strength */
224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
231 * Poll for DLL ready. Use a one second timeout.
232 * Works in all experiments done so far
234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
235 val & DLLRDY_MASK, 1000, 1000000);
237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
242 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
243 u32 itapdly, u32 enable)
245 /* Set ITAPCHGWIN before writing to ITAPDLY */
246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
247 1 << ITAPCHGWIN_SHIFT);
248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
249 enable << ITAPDLYENA_SHIFT);
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
251 itapdly << ITAPDLYSEL_SHIFT);
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
255 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
256 unsigned char timing)
260 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
262 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
263 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
264 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
266 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
267 sdhci_am654->itap_del_ena[timing]);
270 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
273 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
274 unsigned char timing = host->mmc->ios.timing;
278 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
280 sdhci_set_clock(host, clock);
282 /* Setup Output TAP delay */
283 otap_del_sel = sdhci_am654->otap_del_sel[timing];
285 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
286 val = (0x1 << OTAPDLYENA_SHIFT) |
287 (otap_del_sel << OTAPDLYSEL_SHIFT);
289 /* Write to STRBSEL for HS400 speed mode */
290 if (timing == MMC_TIMING_MMC_HS400) {
291 if (sdhci_am654->flags & STRBSEL_4_BIT)
292 mask |= STRBSEL_4BIT_MASK;
294 mask |= STRBSEL_8BIT_MASK;
296 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
301 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
302 sdhci_am654_setup_dll(host, clock);
303 sdhci_am654->dll_enable = true;
305 if (timing == MMC_TIMING_MMC_HS400) {
306 sdhci_am654->itap_del_ena[timing] = 0x1;
307 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1];
310 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing],
311 sdhci_am654->itap_del_ena[timing]);
313 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
314 sdhci_am654->dll_enable = false;
317 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
318 sdhci_am654->clkbuf_sel);
321 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
324 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
325 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
326 unsigned char timing = host->mmc->ios.timing;
332 /* Setup Output TAP delay */
333 otap_del_sel = sdhci_am654->otap_del_sel[timing];
335 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
336 val = (0x1 << OTAPDLYENA_SHIFT) |
337 (otap_del_sel << OTAPDLYSEL_SHIFT);
339 /* Setup Input TAP delay */
340 itap_del_ena = sdhci_am654->itap_del_ena[timing];
341 itap_del_sel = sdhci_am654->itap_del_sel[timing];
343 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK;
344 val |= (itap_del_ena << ITAPDLYENA_SHIFT) |
345 (itap_del_sel << ITAPDLYSEL_SHIFT);
347 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
348 1 << ITAPCHGWIN_SHIFT);
349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
351 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
352 sdhci_am654->clkbuf_sel);
354 sdhci_set_clock(host, clock);
357 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
359 writeb(val, host->ioaddr + reg);
360 usleep_range(1000, 10000);
361 return readb(host->ioaddr + reg);
364 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
365 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
367 unsigned char timing = host->mmc->ios.timing;
371 if (reg == SDHCI_HOST_CONTROL) {
374 * According to the data manual, HISPD bit
375 * should not be set in these speed modes.
377 case MMC_TIMING_SD_HS:
378 case MMC_TIMING_MMC_HS:
379 val &= ~SDHCI_CTRL_HISPD;
383 writeb(val, host->ioaddr + reg);
384 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
386 * Power on will not happen until the card detect debounce
387 * timer expires. Wait at least 1.5 seconds for the power on
390 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
391 pwr & SDHCI_POWER_ON, 0,
392 MAX_POWER_ON_TIMEOUT, false, host, val,
395 dev_info(mmc_dev(host->mmc), "Power on failed\n");
399 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask)
402 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
403 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
405 sdhci_and_cqhci_reset(host, mask);
407 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
408 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
409 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
410 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
414 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
416 struct sdhci_host *host = mmc_priv(mmc);
417 int err = sdhci_execute_tuning(mmc, opcode);
422 * Tuning data remains in the buffer after tuning.
423 * Do a command and data reset to get rid of it
425 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
430 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
435 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
438 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
443 #define ITAPDLY_LENGTH 32
444 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
446 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window
447 *fail_window, u8 num_fails, bool circular_buffer)
449 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0;
450 u8 first_fail_start = 0, last_fail_end = 0;
451 struct device *dev = mmc_dev(host->mmc);
452 struct window pass_window = {0, 0, 0};
453 int prev_fail_end = -1;
457 return ITAPDLY_LAST_INDEX >> 1;
459 if (fail_window->length == ITAPDLY_LENGTH) {
460 dev_err(dev, "No passing ITAPDLY, return 0\n");
464 first_fail_start = fail_window->start;
465 last_fail_end = fail_window[num_fails - 1].end;
467 for (i = 0; i < num_fails; i++) {
468 start_fail = fail_window[i].start;
469 end_fail = fail_window[i].end;
470 pass_length = start_fail - (prev_fail_end + 1);
472 if (pass_length > pass_window.length) {
473 pass_window.start = prev_fail_end + 1;
474 pass_window.length = pass_length;
476 prev_fail_end = end_fail;
479 if (!circular_buffer)
480 pass_length = ITAPDLY_LAST_INDEX - last_fail_end;
482 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start;
484 if (pass_length > pass_window.length) {
485 pass_window.start = last_fail_end + 1;
486 pass_window.length = pass_length;
489 if (!circular_buffer)
490 itap = pass_window.start + (pass_window.length >> 1);
492 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH;
494 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap;
497 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
500 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
501 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
502 unsigned char timing = host->mmc->ios.timing;
503 struct window fail_window[ITAPDLY_LENGTH];
508 memset(fail_window, 0, sizeof(fail_window));
511 sdhci_am654->itap_del_ena[timing] = 0x1;
513 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) {
514 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
516 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL);
518 if (!curr_pass && prev_pass)
519 fail_window[fail_index].start = itap;
522 fail_window[fail_index].end = itap;
523 fail_window[fail_index].length++;
526 if (curr_pass && !prev_pass)
529 prev_pass = curr_pass;
532 if (fail_window[fail_index].length != 0)
535 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index,
536 sdhci_am654->dll_enable);
538 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]);
541 sdhci_am654->itap_del_sel[timing] = itap;
546 static const struct sdhci_ops sdhci_am654_ops = {
547 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
548 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
549 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
550 .set_uhs_signaling = sdhci_set_uhs_signaling,
551 .set_bus_width = sdhci_set_bus_width,
552 .set_power = sdhci_set_power_and_bus_voltage,
553 .set_clock = sdhci_am654_set_clock,
554 .write_b = sdhci_am654_write_b,
555 .irq = sdhci_am654_cqhci_irq,
556 .reset = sdhci_and_cqhci_reset,
559 static const struct sdhci_pltfm_data sdhci_am654_pdata = {
560 .ops = &sdhci_am654_ops,
561 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
562 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
565 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
566 .pdata = &sdhci_am654_pdata,
567 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
571 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
572 .pdata = &sdhci_am654_pdata,
573 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
576 static const struct sdhci_ops sdhci_j721e_8bit_ops = {
577 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
578 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
579 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
580 .set_uhs_signaling = sdhci_set_uhs_signaling,
581 .set_bus_width = sdhci_set_bus_width,
582 .set_power = sdhci_set_power_and_bus_voltage,
583 .set_clock = sdhci_am654_set_clock,
584 .write_b = sdhci_am654_write_b,
585 .irq = sdhci_am654_cqhci_irq,
586 .reset = sdhci_and_cqhci_reset,
589 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
590 .ops = &sdhci_j721e_8bit_ops,
591 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
592 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
595 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
596 .pdata = &sdhci_j721e_8bit_pdata,
597 .flags = DLL_PRESENT | DLL_CALIB,
600 static const struct sdhci_ops sdhci_j721e_4bit_ops = {
601 .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
602 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
603 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
604 .set_uhs_signaling = sdhci_set_uhs_signaling,
605 .set_bus_width = sdhci_set_bus_width,
606 .set_power = sdhci_set_power_and_bus_voltage,
607 .set_clock = sdhci_j721e_4bit_set_clock,
608 .write_b = sdhci_am654_write_b,
609 .irq = sdhci_am654_cqhci_irq,
610 .reset = sdhci_am654_reset,
613 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
614 .ops = &sdhci_j721e_4bit_ops,
615 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
616 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
619 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
620 .pdata = &sdhci_j721e_4bit_pdata,
621 .flags = IOMUX_PRESENT,
624 static const struct soc_device_attribute sdhci_am654_devices[] = {
627 .data = &sdhci_am654_sr1_drvdata
632 static void sdhci_am654_dumpregs(struct mmc_host *mmc)
634 sdhci_dumpregs(mmc_priv(mmc));
637 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
638 .enable = sdhci_cqe_enable,
639 .disable = sdhci_cqe_disable,
640 .dumpregs = sdhci_am654_dumpregs,
643 static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
645 struct cqhci_host *cq_host;
647 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host),
652 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
653 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
654 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
655 cq_host->ops = &sdhci_am654_cqhci_ops;
657 host->mmc->caps2 |= MMC_CAP2_CQE;
659 return cqhci_init(cq_host, host->mmc, 1);
662 static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
663 struct sdhci_am654_data *sdhci_am654)
665 struct device *dev = mmc_dev(host->mmc);
669 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) {
671 ret = device_property_read_u32(dev, td[i].otap_binding,
672 &sdhci_am654->otap_del_sel[i]);
674 if (i == MMC_TIMING_LEGACY) {
675 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n");
678 dev_dbg(dev, "Couldn't find %s\n",
681 * Remove the corresponding capability
682 * if an otap-del-sel value is not found
684 if (i <= MMC_TIMING_MMC_DDR52)
685 host->mmc->caps &= ~td[i].capability;
687 host->mmc->caps2 &= ~td[i].capability;
690 if (td[i].itap_binding) {
691 ret = device_property_read_u32(dev, td[i].itap_binding,
692 &sdhci_am654->itap_del_sel[i]);
694 sdhci_am654->itap_del_ena[i] = 0x1;
701 static int sdhci_am654_init(struct sdhci_host *host)
703 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
704 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
710 /* Reset OTAP to default value */
711 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
712 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
714 if (sdhci_am654->flags & DLL_CALIB) {
715 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
716 if (~val & CALDONE_MASK) {
717 /* Calibrate IO lines */
718 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
720 ret = regmap_read_poll_timeout(sdhci_am654->base,
729 /* Enable pins by setting IO mux to 0 */
730 if (sdhci_am654->flags & IOMUX_PRESENT)
731 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
732 IOMUX_ENABLE_MASK, 0);
734 /* Set slot type based on SD or eMMC */
735 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
736 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
738 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
741 /* Enable tuning for SDR50 */
742 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
743 TUNINGFORSDR50_MASK);
745 ret = sdhci_setup_host(host);
749 ret = sdhci_am654_cqe_add_host(host);
751 goto err_cleanup_host;
753 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
755 goto err_cleanup_host;
757 ret = __sdhci_add_host(host);
759 goto err_cleanup_host;
764 sdhci_cleanup_host(host);
768 static int sdhci_am654_get_of_property(struct platform_device *pdev,
769 struct sdhci_am654_data *sdhci_am654)
771 struct device *dev = &pdev->dev;
775 if (sdhci_am654->flags & DLL_PRESENT) {
776 ret = device_property_read_u32(dev, "ti,trm-icp",
777 &sdhci_am654->trm_icp);
781 ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
786 switch (drv_strength) {
788 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
791 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
794 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
797 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
800 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
803 dev_err(dev, "Invalid driver strength\n");
808 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
809 device_property_read_u32(dev, "ti,clkbuf-sel",
810 &sdhci_am654->clkbuf_sel);
812 if (device_property_read_bool(dev, "ti,fails-without-test-cd"))
813 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
815 sdhci_get_of_property(pdev);
820 static const struct of_device_id sdhci_am654_of_match[] = {
822 .compatible = "ti,am654-sdhci-5.1",
823 .data = &sdhci_am654_drvdata,
826 .compatible = "ti,j721e-sdhci-8bit",
827 .data = &sdhci_j721e_8bit_drvdata,
830 .compatible = "ti,j721e-sdhci-4bit",
831 .data = &sdhci_j721e_4bit_drvdata,
834 .compatible = "ti,am64-sdhci-8bit",
835 .data = &sdhci_j721e_8bit_drvdata,
838 .compatible = "ti,am64-sdhci-4bit",
839 .data = &sdhci_j721e_4bit_drvdata,
842 .compatible = "ti,am62-sdhci",
843 .data = &sdhci_j721e_4bit_drvdata,
847 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
849 static int sdhci_am654_probe(struct platform_device *pdev)
851 const struct sdhci_am654_driver_data *drvdata;
852 const struct soc_device_attribute *soc;
853 struct sdhci_pltfm_host *pltfm_host;
854 struct sdhci_am654_data *sdhci_am654;
855 const struct of_device_id *match;
856 struct sdhci_host *host;
858 struct device *dev = &pdev->dev;
862 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
863 drvdata = match->data;
865 /* Update drvdata based on SoC revision */
866 soc = soc_device_match(sdhci_am654_devices);
867 if (soc && soc->data)
870 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
872 return PTR_ERR(host);
874 pltfm_host = sdhci_priv(host);
875 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
876 sdhci_am654->flags = drvdata->flags;
878 clk_xin = devm_clk_get(dev, "clk_xin");
879 if (IS_ERR(clk_xin)) {
880 dev_err(dev, "clk_xin clock not found.\n");
881 ret = PTR_ERR(clk_xin);
885 pltfm_host->clk = clk_xin;
887 base = devm_platform_ioremap_resource(pdev, 1);
893 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
894 &sdhci_am654_regmap_config);
895 if (IS_ERR(sdhci_am654->base)) {
896 dev_err(dev, "Failed to initialize regmap\n");
897 ret = PTR_ERR(sdhci_am654->base);
901 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
905 ret = mmc_of_parse(host->mmc);
907 dev_err_probe(dev, ret, "parsing dt failed\n");
911 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
913 pm_runtime_get_noresume(dev);
914 ret = pm_runtime_set_active(dev);
917 pm_runtime_enable(dev);
918 ret = clk_prepare_enable(pltfm_host->clk);
922 ret = sdhci_am654_init(host);
926 /* Setting up autosuspend */
927 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY);
928 pm_runtime_use_autosuspend(dev);
929 pm_runtime_mark_last_busy(dev);
930 pm_runtime_put_autosuspend(dev);
934 clk_disable_unprepare(pltfm_host->clk);
936 pm_runtime_disable(dev);
938 pm_runtime_put_noidle(dev);
940 sdhci_pltfm_free(pdev);
944 static void sdhci_am654_remove(struct platform_device *pdev)
946 struct sdhci_host *host = platform_get_drvdata(pdev);
947 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
948 struct device *dev = &pdev->dev;
951 ret = pm_runtime_get_sync(dev);
953 dev_err(dev, "pm_runtime_get_sync() Failed\n");
955 sdhci_remove_host(host, true);
956 clk_disable_unprepare(pltfm_host->clk);
957 pm_runtime_disable(dev);
958 pm_runtime_put_noidle(dev);
959 sdhci_pltfm_free(pdev);
963 static int sdhci_am654_restore(struct sdhci_host *host)
965 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
966 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
971 if (sdhci_am654->flags & DLL_CALIB) {
972 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
973 if (~val & CALDONE_MASK) {
974 /* Calibrate IO lines */
975 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
977 ret = regmap_read_poll_timeout(sdhci_am654->base,
986 /* Enable pins by setting IO mux to 0 */
987 if (sdhci_am654->flags & IOMUX_PRESENT)
988 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
989 IOMUX_ENABLE_MASK, 0);
991 /* Set slot type based on SD or eMMC */
992 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
993 ctl_cfg_2 = SLOTTYPE_EMBEDDED;
995 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
998 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
999 if (~val & TUNINGFORSDR50_MASK)
1000 /* Enable tuning for SDR50 */
1001 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
1002 TUNINGFORSDR50_MASK);
1007 static int sdhci_am654_runtime_suspend(struct device *dev)
1009 struct sdhci_host *host = dev_get_drvdata(dev);
1010 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1013 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1014 mmc_retune_needed(host->mmc);
1016 ret = cqhci_suspend(host->mmc);
1020 ret = sdhci_runtime_suspend_host(host);
1024 /* disable the clock */
1025 clk_disable_unprepare(pltfm_host->clk);
1029 static int sdhci_am654_runtime_resume(struct device *dev)
1031 struct sdhci_host *host = dev_get_drvdata(dev);
1032 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1035 /* Enable the clock */
1036 ret = clk_prepare_enable(pltfm_host->clk);
1040 ret = sdhci_am654_restore(host);
1044 ret = sdhci_runtime_resume_host(host, 0);
1048 ret = cqhci_resume(host->mmc);
1056 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = {
1057 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend,
1058 sdhci_am654_runtime_resume, NULL)
1059 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1060 pm_runtime_force_resume)
1063 static struct platform_driver sdhci_am654_driver = {
1065 .name = "sdhci-am654",
1066 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1067 .pm = &sdhci_am654_dev_pm_ops,
1068 .of_match_table = sdhci_am654_of_match,
1070 .probe = sdhci_am654_probe,
1071 .remove_new = sdhci_am654_remove,
1074 module_platform_driver(sdhci_am654_driver);
1076 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
1077 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
1078 MODULE_LICENSE("GPL");