drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30
  31 #include "sdhci.h"
  32
  33 #define DRIVER_NAME "sdhci"
  34
  35 #define DBG(f, x...) \
  36         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  37
  38 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  39         defined(CONFIG_MMC_SDHCI_MODULE))
  40 #define SDHCI_USE_LEDS_CLASS
  41 #endif
  42
  43 #define MAX_TUNING_LOOP 40
  44
  45 static unsigned int debug_quirks = 0;
  46 static unsigned int debug_quirks2;
  47
  48 static void sdhci_finish_data(struct sdhci_host *);
  49
  50 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  51 static void sdhci_finish_command(struct sdhci_host *);
  52 static int sdhci_execute_tuning(struct mmc_host *mmc);
  53 static void sdhci_tuning_timer(unsigned long data);
  54
  55 #ifdef CONFIG_PM_RUNTIME
  56 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  57 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  58 #else
  59 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  60 {
  61         return 0;
  62 }
  63 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 #endif
  68
  69 static void sdhci_dumpregs(struct sdhci_host *host)
  70 {
  71         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  72                 mmc_hostname(host->mmc));
  73
  74         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  75                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  76                 sdhci_readw(host, SDHCI_HOST_VERSION));
  77         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  78                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  79                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  80         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  81                 sdhci_readl(host, SDHCI_ARGUMENT),
  82                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  83         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  84                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  85                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  86         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  87                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  88                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  89         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  90                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  91                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  92         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  93                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  94                 sdhci_readl(host, SDHCI_INT_STATUS));
  95         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_INT_ENABLE),
  97                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  98         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  99                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 100                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 101         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 102                 sdhci_readl(host, SDHCI_CAPABILITIES),
 103                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 104         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 105                 sdhci_readw(host, SDHCI_COMMAND),
 106                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 107         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 108                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 109
 110         if (host->flags & SDHCI_USE_ADMA)
 111                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 112                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 113                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 114
 115         pr_debug(DRIVER_NAME ": ===========================================\n");
 116 }
 117
 118 /*****************************************************************************\
 119  *                                                                           *
 120  * Low level functions                                                       *
 121  *                                                                           *
 122 \*****************************************************************************/
 123
 124 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 125 {
 126         u32 ier;
 127
 128         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 129         ier &= ~clear;
 130         ier |= set;
 131         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 132         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 133 }
 134
 135 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 136 {
 137         sdhci_clear_set_irqs(host, 0, irqs);
 138 }
 139
 140 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 141 {
 142         sdhci_clear_set_irqs(host, irqs, 0);
 143 }
 144
 145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 146 {
 147         u32 present, irqs;
 148
 149         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 150             !mmc_card_is_removable(host->mmc))
 151                 return;
 152
 153         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                               SDHCI_CARD_PRESENT;
 155         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 156
 157         if (enable)
 158                 sdhci_unmask_irqs(host, irqs);
 159         else
 160                 sdhci_mask_irqs(host, irqs);
 161 }
 162
 163 static void sdhci_enable_card_detection(struct sdhci_host *host)
 164 {
 165         sdhci_set_card_detection(host, true);
 166 }
 167
 168 static void sdhci_disable_card_detection(struct sdhci_host *host)
 169 {
 170         sdhci_set_card_detection(host, false);
 171 }
 172
 173 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 174 {
 175         unsigned long timeout;
 176         u32 uninitialized_var(ier);
 177
 178         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 179                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 180                         SDHCI_CARD_PRESENT))
 181                         return;
 182         }
 183
 184         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 185                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 186
 187         if (host->ops->platform_reset_enter)
 188                 host->ops->platform_reset_enter(host, mask);
 189
 190         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 191
 192         if (mask & SDHCI_RESET_ALL)
 193                 host->clock = 0;
 194
 195         /* Wait max 100 ms */
 196         timeout = 100;
 197
 198         /* hw clears the bit when it's done */
 199         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 200                 if (timeout == 0) {
 201                         pr_err("%s: Reset 0x%x never completed.\n",
 202                                 mmc_hostname(host->mmc), (int)mask);
 203                         sdhci_dumpregs(host);
 204                         return;
 205                 }
 206                 timeout--;
 207                 mdelay(1);
 208         }
 209
 210         if (host->ops->platform_reset_exit)
 211                 host->ops->platform_reset_exit(host, mask);
 212
 213         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 214                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 215 }
 216
 217 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 218
 219 static void sdhci_init(struct sdhci_host *host, int soft)
 220 {
 221         if (soft)
 222                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 223         else
 224                 sdhci_reset(host, SDHCI_RESET_ALL);
 225
 226         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 227                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 228                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 229                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 230                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 231
 232         if (soft) {
 233                 /* force clock reconfiguration */
 234                 host->clock = 0;
 235                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 236         }
 237 }
 238
 239 static void sdhci_reinit(struct sdhci_host *host)
 240 {
 241         sdhci_init(host, 0);
 242         sdhci_enable_card_detection(host);
 243 }
 244
 245 static void sdhci_activate_led(struct sdhci_host *host)
 246 {
 247         u8 ctrl;
 248
 249         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 250         ctrl |= SDHCI_CTRL_LED;
 251         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 252 }
 253
 254 static void sdhci_deactivate_led(struct sdhci_host *host)
 255 {
 256         u8 ctrl;
 257
 258         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 259         ctrl &= ~SDHCI_CTRL_LED;
 260         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 261 }
 262
 263 #ifdef SDHCI_USE_LEDS_CLASS
 264 static void sdhci_led_control(struct led_classdev *led,
 265         enum led_brightness brightness)
 266 {
 267         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 268         unsigned long flags;
 269
 270         spin_lock_irqsave(&host->lock, flags);
 271
 272         if (host->runtime_suspended)
 273                 goto out;
 274
 275         if (brightness == LED_OFF)
 276                 sdhci_deactivate_led(host);
 277         else
 278                 sdhci_activate_led(host);
 279 out:
 280         spin_unlock_irqrestore(&host->lock, flags);
 281 }
 282 #endif
 283
 284 /*****************************************************************************\
 285  *                                                                           *
 286  * Core functions                                                            *
 287  *                                                                           *
 288 \*****************************************************************************/
 289
 290 static void sdhci_read_block_pio(struct sdhci_host *host)
 291 {
 292         unsigned long flags;
 293         size_t blksize, len, chunk;
 294         u32 uninitialized_var(scratch);
 295         u8 *buf;
 296
 297         DBG("PIO reading\n");
 298
 299         blksize = host->data->blksz;
 300         chunk = 0;
 301
 302         local_irq_save(flags);
 303
 304         while (blksize) {
 305                 if (!sg_miter_next(&host->sg_miter))
 306                         BUG();
 307
 308                 len = min(host->sg_miter.length, blksize);
 309
 310                 blksize -= len;
 311                 host->sg_miter.consumed = len;
 312
 313                 buf = host->sg_miter.addr;
 314
 315                 while (len) {
 316                         if (chunk == 0) {
 317                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 318                                 chunk = 4;
 319                         }
 320
 321                         *buf = scratch & 0xFF;
 322
 323                         buf++;
 324                         scratch >>= 8;
 325                         chunk--;
 326                         len--;
 327                 }
 328         }
 329
 330         sg_miter_stop(&host->sg_miter);
 331
 332         local_irq_restore(flags);
 333 }
 334
 335 static void sdhci_write_block_pio(struct sdhci_host *host)
 336 {
 337         unsigned long flags;
 338         size_t blksize, len, chunk;
 339         u32 scratch;
 340         u8 *buf;
 341
 342         DBG("PIO writing\n");
 343
 344         blksize = host->data->blksz;
 345         chunk = 0;
 346         scratch = 0;
 347
 348         local_irq_save(flags);
 349
 350         while (blksize) {
 351                 if (!sg_miter_next(&host->sg_miter))
 352                         BUG();
 353
 354                 len = min(host->sg_miter.length, blksize);
 355
 356                 blksize -= len;
 357                 host->sg_miter.consumed = len;
 358
 359                 buf = host->sg_miter.addr;
 360
 361                 while (len) {
 362                         scratch |= (u32)*buf << (chunk * 8);
 363
 364                         buf++;
 365                         chunk++;
 366                         len--;
 367
 368                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 369                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 370                                 chunk = 0;
 371                                 scratch = 0;
 372                         }
 373                 }
 374         }
 375
 376         sg_miter_stop(&host->sg_miter);
 377
 378         local_irq_restore(flags);
 379 }
 380
 381 static void sdhci_transfer_pio(struct sdhci_host *host)
 382 {
 383         u32 mask;
 384
 385         BUG_ON(!host->data);
 386
 387         if (host->blocks == 0)
 388                 return;
 389
 390         if (host->data->flags & MMC_DATA_READ)
 391                 mask = SDHCI_DATA_AVAILABLE;
 392         else
 393                 mask = SDHCI_SPACE_AVAILABLE;
 394
 395         /*
 396          * Some controllers (JMicron JMB38x) mess up the buffer bits
 397          * for transfers < 4 bytes. As long as it is just one block,
 398          * we can ignore the bits.
 399          */
 400         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 401                 (host->data->blocks == 1))
 402                 mask = ~0;
 403
 404         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 405                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 406                         udelay(100);
 407
 408                 if (host->data->flags & MMC_DATA_READ)
 409                         sdhci_read_block_pio(host);
 410                 else
 411                         sdhci_write_block_pio(host);
 412
 413                 host->blocks--;
 414                 if (host->blocks == 0)
 415                         break;
 416         }
 417
 418         DBG("PIO transfer complete.\n");
 419 }
 420
 421 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 422 {
 423         local_irq_save(*flags);
 424         return kmap_atomic(sg_page(sg)) + sg->offset;
 425 }
 426
 427 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 428 {
 429         kunmap_atomic(buffer);
 430         local_irq_restore(*flags);
 431 }
 432
 433 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 434 {
 435         __le32 *dataddr = (__le32 __force *)(desc + 4);
 436         __le16 *cmdlen = (__le16 __force *)desc;
 437
 438         /* SDHCI specification says ADMA descriptors should be 4 byte
 439          * aligned, so using 16 or 32bit operations should be safe. */
 440
 441         cmdlen[0] = cpu_to_le16(cmd);
 442         cmdlen[1] = cpu_to_le16(len);
 443
 444         dataddr[0] = cpu_to_le32(addr);
 445 }
 446
 447 static int sdhci_adma_table_pre(struct sdhci_host *host,
 448         struct mmc_data *data)
 449 {
 450         int direction;
 451
 452         u8 *desc;
 453         u8 *align;
 454         dma_addr_t addr;
 455         dma_addr_t align_addr;
 456         int len, offset;
 457
 458         struct scatterlist *sg;
 459         int i;
 460         char *buffer;
 461         unsigned long flags;
 462
 463         /*
 464          * The spec does not specify endianness of descriptor table.
 465          * We currently guess that it is LE.
 466          */
 467
 468         if (data->flags & MMC_DATA_READ)
 469                 direction = DMA_FROM_DEVICE;
 470         else
 471                 direction = DMA_TO_DEVICE;
 472
 473         /*
 474          * The ADMA descriptor table is mapped further down as we
 475          * need to fill it with data first.
 476          */
 477
 478         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 479                 host->align_buffer, 128 * 4, direction);
 480         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 481                 goto fail;
 482         BUG_ON(host->align_addr & 0x3);
 483
 484         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 485                 data->sg, data->sg_len, direction);
 486         if (host->sg_count == 0)
 487                 goto unmap_align;
 488
 489         desc = host->adma_desc;
 490         align = host->align_buffer;
 491
 492         align_addr = host->align_addr;
 493
 494         for_each_sg(data->sg, sg, host->sg_count, i) {
 495                 addr = sg_dma_address(sg);
 496                 len = sg_dma_len(sg);
 497
 498                 /*
 499                  * The SDHCI specification states that ADMA
 500                  * addresses must be 32-bit aligned. If they
 501                  * aren't, then we use a bounce buffer for
 502                  * the (up to three) bytes that screw up the
 503                  * alignment.
 504                  */
 505                 offset = (4 - (addr & 0x3)) & 0x3;
 506                 if (offset) {
 507                         if (data->flags & MMC_DATA_WRITE) {
 508                                 buffer = sdhci_kmap_atomic(sg, &flags);
 509                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 510                                 memcpy(align, buffer, offset);
 511                                 sdhci_kunmap_atomic(buffer, &flags);
 512                         }
 513
 514                         /* tran, valid */
 515                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 516
 517                         BUG_ON(offset > 65536);
 518
 519                         align += 4;
 520                         align_addr += 4;
 521
 522                         desc += 8;
 523
 524                         addr += offset;
 525                         len -= offset;
 526                 }
 527
 528                 BUG_ON(len > 65536);
 529
 530                 /* tran, valid */
 531                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 532                 desc += 8;
 533
 534                 /*
 535                  * If this triggers then we have a calculation bug
 536                  * somewhere. :/
 537                  */
 538                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 539         }
 540
 541         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 542                 /*
 543                 * Mark the last descriptor as the terminating descriptor
 544                 */
 545                 if (desc != host->adma_desc) {
 546                         desc -= 8;
 547                         desc[0] |= 0x2; /* end */
 548                 }
 549         } else {
 550                 /*
 551                 * Add a terminating entry.
 552                 */
 553
 554                 /* nop, end, valid */
 555                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 556         }
 557
 558         /*
 559          * Resync align buffer as we might have changed it.
 560          */
 561         if (data->flags & MMC_DATA_WRITE) {
 562                 dma_sync_single_for_device(mmc_dev(host->mmc),
 563                         host->align_addr, 128 * 4, direction);
 564         }
 565
 566         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 567                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 568         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 569                 goto unmap_entries;
 570         BUG_ON(host->adma_addr & 0x3);
 571
 572         return 0;
 573
 574 unmap_entries:
 575         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 576                 data->sg_len, direction);
 577 unmap_align:
 578         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 579                 128 * 4, direction);
 580 fail:
 581         return -EINVAL;
 582 }
 583
 584 static void sdhci_adma_table_post(struct sdhci_host *host,
 585         struct mmc_data *data)
 586 {
 587         int direction;
 588
 589         struct scatterlist *sg;
 590         int i, size;
 591         u8 *align;
 592         char *buffer;
 593         unsigned long flags;
 594
 595         if (data->flags & MMC_DATA_READ)
 596                 direction = DMA_FROM_DEVICE;
 597         else
 598                 direction = DMA_TO_DEVICE;
 599
 600         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 601                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 602
 603         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 604                 128 * 4, direction);
 605
 606         if (data->flags & MMC_DATA_READ) {
 607                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 608                         data->sg_len, direction);
 609
 610                 align = host->align_buffer;
 611
 612                 for_each_sg(data->sg, sg, host->sg_count, i) {
 613                         if (sg_dma_address(sg) & 0x3) {
 614                                 size = 4 - (sg_dma_address(sg) & 0x3);
 615
 616                                 buffer = sdhci_kmap_atomic(sg, &flags);
 617                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 618                                 memcpy(buffer, align, size);
 619                                 sdhci_kunmap_atomic(buffer, &flags);
 620
 621                                 align += 4;
 622                         }
 623                 }
 624         }
 625
 626         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 627                 data->sg_len, direction);
 628 }
 629
 630 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 631 {
 632         u8 count;
 633         struct mmc_data *data = cmd->data;
 634         unsigned target_timeout, current_timeout;
 635
 636         /*
 637          * If the host controller provides us with an incorrect timeout
 638          * value, just skip the check and use 0xE.  The hardware may take
 639          * longer to time out, but that's much better than having a too-short
 640          * timeout value.
 641          */
 642         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 643                 return 0xE;
 644
 645         /* Unspecified timeout, assume max */
 646         if (!data && !cmd->cmd_timeout_ms)
 647                 return 0xE;
 648
 649         /* timeout in us */
 650         if (!data)
 651                 target_timeout = cmd->cmd_timeout_ms * 1000;
 652         else {
 653                 target_timeout = data->timeout_ns / 1000;
 654                 if (host->clock)
 655                         target_timeout += data->timeout_clks / host->clock;
 656         }
 657
 658         /*
 659          * Figure out needed cycles.
 660          * We do this in steps in order to fit inside a 32 bit int.
 661          * The first step is the minimum timeout, which will have a
 662          * minimum resolution of 6 bits:
 663          * (1) 2^13*1000 > 2^22,
 664          * (2) host->timeout_clk < 2^16
 665          *     =>
 666          *     (1) / (2) > 2^6
 667          */
 668         count = 0;
 669         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 670         while (current_timeout < target_timeout) {
 671                 count++;
 672                 current_timeout <<= 1;
 673                 if (count >= 0xF)
 674                         break;
 675         }
 676
 677         if (count >= 0xF) {
 678                 pr_warning("%s: Too large timeout requested for CMD%d!\n",
 679                        mmc_hostname(host->mmc), cmd->opcode);
 680                 count = 0xE;
 681         }
 682
 683         return count;
 684 }
 685
 686 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 687 {
 688         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 689         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 690
 691         if (host->flags & SDHCI_REQ_USE_DMA)
 692                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 693         else
 694                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 695 }
 696
 697 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 698 {
 699         u8 count;
 700         u8 ctrl;
 701         struct mmc_data *data = cmd->data;
 702         int ret;
 703
 704         WARN_ON(host->data);
 705
 706         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 707                 count = sdhci_calc_timeout(host, cmd);
 708                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 709         }
 710
 711         if (!data)
 712                 return;
 713
 714         /* Sanity checks */
 715         BUG_ON(data->blksz * data->blocks > 524288);
 716         BUG_ON(data->blksz > host->mmc->max_blk_size);
 717         BUG_ON(data->blocks > 65535);
 718
 719         host->data = data;
 720         host->data_early = 0;
 721         host->data->bytes_xfered = 0;
 722
 723         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 724                 host->flags |= SDHCI_REQ_USE_DMA;
 725
 726         /*
 727          * FIXME: This doesn't account for merging when mapping the
 728          * scatterlist.
 729          */
 730         if (host->flags & SDHCI_REQ_USE_DMA) {
 731                 int broken, i;
 732                 struct scatterlist *sg;
 733
 734                 broken = 0;
 735                 if (host->flags & SDHCI_USE_ADMA) {
 736                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 737                                 broken = 1;
 738                 } else {
 739                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 740                                 broken = 1;
 741                 }
 742
 743                 if (unlikely(broken)) {
 744                         for_each_sg(data->sg, sg, data->sg_len, i) {
 745                                 if (sg->length & 0x3) {
 746                                         DBG("Reverting to PIO because of "
 747                                                 "transfer size (%d)\n",
 748                                                 sg->length);
 749                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 750                                         break;
 751                                 }
 752                         }
 753                 }
 754         }
 755
 756         /*
 757          * The assumption here being that alignment is the same after
 758          * translation to device address space.
 759          */
 760         if (host->flags & SDHCI_REQ_USE_DMA) {
 761                 int broken, i;
 762                 struct scatterlist *sg;
 763
 764                 broken = 0;
 765                 if (host->flags & SDHCI_USE_ADMA) {
 766                         /*
 767                          * As we use 3 byte chunks to work around
 768                          * alignment problems, we need to check this
 769                          * quirk.
 770                          */
 771                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 772                                 broken = 1;
 773                 } else {
 774                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 775                                 broken = 1;
 776                 }
 777
 778                 if (unlikely(broken)) {
 779                         for_each_sg(data->sg, sg, data->sg_len, i) {
 780                                 if (sg->offset & 0x3) {
 781                                         DBG("Reverting to PIO because of "
 782                                                 "bad alignment\n");
 783                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 784                                         break;
 785                                 }
 786                         }
 787                 }
 788         }
 789
 790         if (host->flags & SDHCI_REQ_USE_DMA) {
 791                 if (host->flags & SDHCI_USE_ADMA) {
 792                         ret = sdhci_adma_table_pre(host, data);
 793                         if (ret) {
 794                                 /*
 795                                  * This only happens when someone fed
 796                                  * us an invalid request.
 797                                  */
 798                                 WARN_ON(1);
 799                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 800                         } else {
 801                                 sdhci_writel(host, host->adma_addr,
 802                                         SDHCI_ADMA_ADDRESS);
 803                         }
 804                 } else {
 805                         int sg_cnt;
 806
 807                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 808                                         data->sg, data->sg_len,
 809                                         (data->flags & MMC_DATA_READ) ?
 810                                                 DMA_FROM_DEVICE :
 811                                                 DMA_TO_DEVICE);
 812                         if (sg_cnt == 0) {
 813                                 /*
 814                                  * This only happens when someone fed
 815                                  * us an invalid request.
 816                                  */
 817                                 WARN_ON(1);
 818                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 819                         } else {
 820                                 WARN_ON(sg_cnt != 1);
 821                                 sdhci_writel(host, sg_dma_address(data->sg),
 822                                         SDHCI_DMA_ADDRESS);
 823                         }
 824                 }
 825         }
 826
 827         /*
 828          * Always adjust the DMA selection as some controllers
 829          * (e.g. JMicron) can't do PIO properly when the selection
 830          * is ADMA.
 831          */
 832         if (host->version >= SDHCI_SPEC_200) {
 833                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 834                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 835                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 836                         (host->flags & SDHCI_USE_ADMA))
 837                         ctrl |= SDHCI_CTRL_ADMA32;
 838                 else
 839                         ctrl |= SDHCI_CTRL_SDMA;
 840                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 841         }
 842
 843         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 844                 int flags;
 845
 846                 flags = SG_MITER_ATOMIC;
 847                 if (host->data->flags & MMC_DATA_READ)
 848                         flags |= SG_MITER_TO_SG;
 849                 else
 850                         flags |= SG_MITER_FROM_SG;
 851                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 852                 host->blocks = data->blocks;
 853         }
 854
 855         sdhci_set_transfer_irqs(host);
 856
 857         /* Set the DMA boundary value and block size */
 858         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 859                 data->blksz), SDHCI_BLOCK_SIZE);
 860         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 861 }
 862
 863 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 864         struct mmc_command *cmd)
 865 {
 866         u16 mode;
 867         struct mmc_data *data = cmd->data;
 868
 869         if (data == NULL)
 870                 return;
 871
 872         WARN_ON(!host->data);
 873
 874         mode = SDHCI_TRNS_BLK_CNT_EN;
 875         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 876                 mode |= SDHCI_TRNS_MULTI;
 877                 /*
 878                  * If we are sending CMD23, CMD12 never gets sent
 879                  * on successful completion (so no Auto-CMD12).
 880                  */
 881                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 882                         mode |= SDHCI_TRNS_AUTO_CMD12;
 883                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 884                         mode |= SDHCI_TRNS_AUTO_CMD23;
 885                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 886                 }
 887         }
 888
 889         if (data->flags & MMC_DATA_READ)
 890                 mode |= SDHCI_TRNS_READ;
 891         if (host->flags & SDHCI_REQ_USE_DMA)
 892                 mode |= SDHCI_TRNS_DMA;
 893
 894         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 895 }
 896
 897 static void sdhci_finish_data(struct sdhci_host *host)
 898 {
 899         struct mmc_data *data;
 900
 901         BUG_ON(!host->data);
 902
 903         data = host->data;
 904         host->data = NULL;
 905
 906         if (host->flags & SDHCI_REQ_USE_DMA) {
 907                 if (host->flags & SDHCI_USE_ADMA)
 908                         sdhci_adma_table_post(host, data);
 909                 else {
 910                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 911                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 912                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 913                 }
 914         }
 915
 916         /*
 917          * The specification states that the block count register must
 918          * be updated, but it does not specify at what point in the
 919          * data flow. That makes the register entirely useless to read
 920          * back so we have to assume that nothing made it to the card
 921          * in the event of an error.
 922          */
 923         if (data->error)
 924                 data->bytes_xfered = 0;
 925         else
 926                 data->bytes_xfered = data->blksz * data->blocks;
 927
 928         /*
 929          * Need to send CMD12 if -
 930          * a) open-ended multiblock transfer (no CMD23)
 931          * b) error in multiblock transfer
 932          */
 933         if (data->stop &&
 934             (data->error ||
 935              !host->mrq->sbc)) {
 936
 937                 /*
 938                  * The controller needs a reset of internal state machines
 939                  * upon error conditions.
 940                  */
 941                 if (data->error) {
 942                         sdhci_reset(host, SDHCI_RESET_CMD);
 943                         sdhci_reset(host, SDHCI_RESET_DATA);
 944                 }
 945
 946                 sdhci_send_command(host, data->stop);
 947         } else
 948                 tasklet_schedule(&host->finish_tasklet);
 949 }
 950
 951 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 952 {
 953         int flags;
 954         u32 mask;
 955         unsigned long timeout;
 956
 957         WARN_ON(host->cmd);
 958
 959         /* Wait max 10 ms */
 960         timeout = 10;
 961
 962         mask = SDHCI_CMD_INHIBIT;
 963         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 964                 mask |= SDHCI_DATA_INHIBIT;
 965
 966         /* We shouldn't wait for data inihibit for stop commands, even
 967            though they might use busy signaling */
 968         if (host->mrq->data && (cmd == host->mrq->data->stop))
 969                 mask &= ~SDHCI_DATA_INHIBIT;
 970
 971         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 972                 if (timeout == 0) {
 973                         pr_err("%s: Controller never released "
 974                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 975                         sdhci_dumpregs(host);
 976                         cmd->error = -EIO;
 977                         tasklet_schedule(&host->finish_tasklet);
 978                         return;
 979                 }
 980                 timeout--;
 981                 mdelay(1);
 982         }
 983
 984         mod_timer(&host->timer, jiffies + 10 * HZ);
 985
 986         host->cmd = cmd;
 987
 988         sdhci_prepare_data(host, cmd);
 989
 990         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 991
 992         sdhci_set_transfer_mode(host, cmd);
 993
 994         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 995                 pr_err("%s: Unsupported response type!\n",
 996                         mmc_hostname(host->mmc));
 997                 cmd->error = -EINVAL;
 998                 tasklet_schedule(&host->finish_tasklet);
 999                 return;
1000         }
1001
1002         if (!(cmd->flags & MMC_RSP_PRESENT))
1003                 flags = SDHCI_CMD_RESP_NONE;
1004         else if (cmd->flags & MMC_RSP_136)
1005                 flags = SDHCI_CMD_RESP_LONG;
1006         else if (cmd->flags & MMC_RSP_BUSY)
1007                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1008         else
1009                 flags = SDHCI_CMD_RESP_SHORT;
1010
1011         if (cmd->flags & MMC_RSP_CRC)
1012                 flags |= SDHCI_CMD_CRC;
1013         if (cmd->flags & MMC_RSP_OPCODE)
1014                 flags |= SDHCI_CMD_INDEX;
1015
1016         /* CMD19 is special in that the Data Present Select should be set */
1017         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
1018                 flags |= SDHCI_CMD_DATA;
1019
1020         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1021 }
1022
1023 static void sdhci_finish_command(struct sdhci_host *host)
1024 {
1025         int i;
1026
1027         BUG_ON(host->cmd == NULL);
1028
1029         if (host->cmd->flags & MMC_RSP_PRESENT) {
1030                 if (host->cmd->flags & MMC_RSP_136) {
1031                         /* CRC is stripped so we need to do some shifting. */
1032                         for (i = 0;i < 4;i++) {
1033                                 host->cmd->resp[i] = sdhci_readl(host,
1034                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1035                                 if (i != 3)
1036                                         host->cmd->resp[i] |=
1037                                                 sdhci_readb(host,
1038                                                 SDHCI_RESPONSE + (3-i)*4-1);
1039                         }
1040                 } else {
1041                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1042                 }
1043         }
1044
1045         host->cmd->error = 0;
1046
1047         /* Finished CMD23, now send actual command. */
1048         if (host->cmd == host->mrq->sbc) {
1049                 host->cmd = NULL;
1050                 sdhci_send_command(host, host->mrq->cmd);
1051         } else {
1052
1053                 /* Processed actual command. */
1054                 if (host->data && host->data_early)
1055                         sdhci_finish_data(host);
1056
1057                 if (!host->cmd->data)
1058                         tasklet_schedule(&host->finish_tasklet);
1059
1060                 host->cmd = NULL;
1061         }
1062 }
1063
1064 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1065 {
1066         int div = 0; /* Initialized for compiler warning */
1067         int real_div = div, clk_mul = 1;
1068         u16 clk = 0;
1069         unsigned long timeout;
1070
1071         if (clock && clock == host->clock)
1072                 return;
1073
1074         host->mmc->actual_clock = 0;
1075
1076         if (host->ops->set_clock) {
1077                 host->ops->set_clock(host, clock);
1078                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1079                         return;
1080         }
1081
1082         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1083
1084         if (clock == 0)
1085                 goto out;
1086
1087         if (host->version >= SDHCI_SPEC_300) {
1088                 /*
1089                  * Check if the Host Controller supports Programmable Clock
1090                  * Mode.
1091                  */
1092                 if (host->clk_mul) {
1093                         u16 ctrl;
1094
1095                         /*
1096                          * We need to figure out whether the Host Driver needs
1097                          * to select Programmable Clock Mode, or the value can
1098                          * be set automatically by the Host Controller based on
1099                          * the Preset Value registers.
1100                          */
1101                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1102                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1103                                 for (div = 1; div <= 1024; div++) {
1104                                         if (((host->max_clk * host->clk_mul) /
1105                                               div) <= clock)
1106                                                 break;
1107                                 }
1108                                 /*
1109                                  * Set Programmable Clock Mode in the Clock
1110                                  * Control register.
1111                                  */
1112                                 clk = SDHCI_PROG_CLOCK_MODE;
1113                                 real_div = div;
1114                                 clk_mul = host->clk_mul;
1115                                 div--;
1116                         }
1117                 } else {
1118                         /* Version 3.00 divisors must be a multiple of 2. */
1119                         if (host->max_clk <= clock)
1120                                 div = 1;
1121                         else {
1122                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1123                                      div += 2) {
1124                                         if ((host->max_clk / div) <= clock)
1125                                                 break;
1126                                 }
1127                         }
1128                         real_div = div;
1129                         div >>= 1;
1130                 }
1131         } else {
1132                 /* Version 2.00 divisors must be a power of 2. */
1133                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1134                         if ((host->max_clk / div) <= clock)
1135                                 break;
1136                 }
1137                 real_div = div;
1138                 div >>= 1;
1139         }
1140
1141         if (real_div)
1142                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1143
1144         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1145         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1146                 << SDHCI_DIVIDER_HI_SHIFT;
1147         clk |= SDHCI_CLOCK_INT_EN;
1148         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1149
1150         /* Wait max 20 ms */
1151         timeout = 20;
1152         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1153                 & SDHCI_CLOCK_INT_STABLE)) {
1154                 if (timeout == 0) {
1155                         pr_err("%s: Internal clock never "
1156                                 "stabilised.\n", mmc_hostname(host->mmc));
1157                         sdhci_dumpregs(host);
1158                         return;
1159                 }
1160                 timeout--;
1161                 mdelay(1);
1162         }
1163
1164         clk |= SDHCI_CLOCK_CARD_EN;
1165         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1166
1167 out:
1168         host->clock = clock;
1169 }
1170
1171 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1172 {
1173         u8 pwr = 0;
1174
1175         if (power != (unsigned short)-1) {
1176                 switch (1 << power) {
1177                 case MMC_VDD_165_195:
1178                         pwr = SDHCI_POWER_180;
1179                         break;
1180                 case MMC_VDD_29_30:
1181                 case MMC_VDD_30_31:
1182                         pwr = SDHCI_POWER_300;
1183                         break;
1184                 case MMC_VDD_32_33:
1185                 case MMC_VDD_33_34:
1186                         pwr = SDHCI_POWER_330;
1187                         break;
1188                 default:
1189                         BUG();
1190                 }
1191         }
1192
1193         if (host->pwr == pwr)
1194                 return -1;
1195
1196         host->pwr = pwr;
1197
1198         if (pwr == 0) {
1199                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1200                 return 0;
1201         }
1202
1203         /*
1204          * Spec says that we should clear the power reg before setting
1205          * a new value. Some controllers don't seem to like this though.
1206          */
1207         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1208                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1209
1210         /*
1211          * At least the Marvell CaFe chip gets confused if we set the voltage
1212          * and set turn on power at the same time, so set the voltage first.
1213          */
1214         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1215                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1216
1217         pwr |= SDHCI_POWER_ON;
1218
1219         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1220
1221         /*
1222          * Some controllers need an extra 10ms delay of 10ms before they
1223          * can apply clock after applying power
1224          */
1225         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1226                 mdelay(10);
1227
1228         return power;
1229 }
1230
1231 /*****************************************************************************\
1232  *                                                                           *
1233  * MMC callbacks                                                             *
1234  *                                                                           *
1235 \*****************************************************************************/
1236
1237 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1238 {
1239         struct sdhci_host *host;
1240         bool present;
1241         unsigned long flags;
1242
1243         host = mmc_priv(mmc);
1244
1245         sdhci_runtime_pm_get(host);
1246
1247         spin_lock_irqsave(&host->lock, flags);
1248
1249         WARN_ON(host->mrq != NULL);
1250
1251 #ifndef SDHCI_USE_LEDS_CLASS
1252         sdhci_activate_led(host);
1253 #endif
1254
1255         /*
1256          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1257          * requests if Auto-CMD12 is enabled.
1258          */
1259         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1260                 if (mrq->stop) {
1261                         mrq->data->stop = NULL;
1262                         mrq->stop = NULL;
1263                 }
1264         }
1265
1266         host->mrq = mrq;
1267
1268         /* If polling, assume that the card is always present. */
1269         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1270                 present = true;
1271         else
1272                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1273                                 SDHCI_CARD_PRESENT;
1274
1275         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1276                 host->mrq->cmd->error = -ENOMEDIUM;
1277                 tasklet_schedule(&host->finish_tasklet);
1278         } else {
1279                 u32 present_state;
1280
1281                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1282                 /*
1283                  * Check if the re-tuning timer has already expired and there
1284                  * is no on-going data transfer. If so, we need to execute
1285                  * tuning procedure before sending command.
1286                  */
1287                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1288                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1289                         spin_unlock_irqrestore(&host->lock, flags);
1290                         sdhci_execute_tuning(mmc);
1291                         spin_lock_irqsave(&host->lock, flags);
1292
1293                         /* Restore original mmc_request structure */
1294                         host->mrq = mrq;
1295                 }
1296
1297                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1298                         sdhci_send_command(host, mrq->sbc);
1299                 else
1300                         sdhci_send_command(host, mrq->cmd);
1301         }
1302
1303         mmiowb();
1304         spin_unlock_irqrestore(&host->lock, flags);
1305 }
1306
1307 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1308 {
1309         unsigned long flags;
1310         int vdd_bit = -1;
1311         u8 ctrl;
1312
1313         spin_lock_irqsave(&host->lock, flags);
1314
1315         if (host->flags & SDHCI_DEVICE_DEAD) {
1316                 spin_unlock_irqrestore(&host->lock, flags);
1317                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1318                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1319                 return;
1320         }
1321
1322         /*
1323          * Reset the chip on each power off.
1324          * Should clear out any weird states.
1325          */
1326         if (ios->power_mode == MMC_POWER_OFF) {
1327                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1328                 sdhci_reinit(host);
1329         }
1330
1331         sdhci_set_clock(host, ios->clock);
1332
1333         if (ios->power_mode == MMC_POWER_OFF)
1334                 vdd_bit = sdhci_set_power(host, -1);
1335         else
1336                 vdd_bit = sdhci_set_power(host, ios->vdd);
1337
1338         if (host->vmmc && vdd_bit != -1) {
1339                 spin_unlock_irqrestore(&host->lock, flags);
1340                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1341                 spin_lock_irqsave(&host->lock, flags);
1342         }
1343
1344         if (host->ops->platform_send_init_74_clocks)
1345                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1346
1347         /*
1348          * If your platform has 8-bit width support but is not a v3 controller,
1349          * or if it requires special setup code, you should implement that in
1350          * platform_8bit_width().
1351          */
1352         if (host->ops->platform_8bit_width)
1353                 host->ops->platform_8bit_width(host, ios->bus_width);
1354         else {
1355                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1356                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1357                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1358                         if (host->version >= SDHCI_SPEC_300)
1359                                 ctrl |= SDHCI_CTRL_8BITBUS;
1360                 } else {
1361                         if (host->version >= SDHCI_SPEC_300)
1362                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1363                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1364                                 ctrl |= SDHCI_CTRL_4BITBUS;
1365                         else
1366                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1367                 }
1368                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1369         }
1370
1371         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1372
1373         if ((ios->timing == MMC_TIMING_SD_HS ||
1374              ios->timing == MMC_TIMING_MMC_HS)
1375             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1376                 ctrl |= SDHCI_CTRL_HISPD;
1377         else
1378                 ctrl &= ~SDHCI_CTRL_HISPD;
1379
1380         if (host->version >= SDHCI_SPEC_300) {
1381                 u16 clk, ctrl_2;
1382                 unsigned int clock;
1383
1384                 /* In case of UHS-I modes, set High Speed Enable */
1385                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1386                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1387                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1388                     (ios->timing == MMC_TIMING_UHS_SDR25) ||
1389                     (ios->timing == MMC_TIMING_UHS_SDR12))
1390                         ctrl |= SDHCI_CTRL_HISPD;
1391
1392                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1393                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1394                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1395                         /*
1396                          * We only need to set Driver Strength if the
1397                          * preset value enable is not set.
1398                          */
1399                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1400                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1401                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1402                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1403                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1404
1405                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1406                 } else {
1407                         /*
1408                          * According to SDHC Spec v3.00, if the Preset Value
1409                          * Enable in the Host Control 2 register is set, we
1410                          * need to reset SD Clock Enable before changing High
1411                          * Speed Enable to avoid generating clock gliches.
1412                          */
1413
1414                         /* Reset SD Clock Enable */
1415                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1416                         clk &= ~SDHCI_CLOCK_CARD_EN;
1417                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1418
1419                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1420
1421                         /* Re-enable SD Clock */
1422                         clock = host->clock;
1423                         host->clock = 0;
1424                         sdhci_set_clock(host, clock);
1425                 }
1426
1427
1428                 /* Reset SD Clock Enable */
1429                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1430                 clk &= ~SDHCI_CLOCK_CARD_EN;
1431                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1432
1433                 if (host->ops->set_uhs_signaling)
1434                         host->ops->set_uhs_signaling(host, ios->timing);
1435                 else {
1436                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1437                         /* Select Bus Speed Mode for host */
1438                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1439                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1440                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1441                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1442                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1443                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1444                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1445                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1446                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1447                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1448                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1449                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1450                 }
1451
1452                 /* Re-enable SD Clock */
1453                 clock = host->clock;
1454                 host->clock = 0;
1455                 sdhci_set_clock(host, clock);
1456         } else
1457                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1458
1459         /*
1460          * Some (ENE) controllers go apeshit on some ios operation,
1461          * signalling timeout and CRC errors even on CMD0. Resetting
1462          * it on each ios seems to solve the problem.
1463          */
1464         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1465                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1466
1467         mmiowb();
1468         spin_unlock_irqrestore(&host->lock, flags);
1469 }
1470
1471 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1472 {
1473         struct sdhci_host *host = mmc_priv(mmc);
1474
1475         sdhci_runtime_pm_get(host);
1476         sdhci_do_set_ios(host, ios);
1477         sdhci_runtime_pm_put(host);
1478 }
1479
1480 static int sdhci_check_ro(struct sdhci_host *host)
1481 {
1482         unsigned long flags;
1483         int is_readonly;
1484
1485         spin_lock_irqsave(&host->lock, flags);
1486
1487         if (host->flags & SDHCI_DEVICE_DEAD)
1488                 is_readonly = 0;
1489         else if (host->ops->get_ro)
1490                 is_readonly = host->ops->get_ro(host);
1491         else
1492                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1493                                 & SDHCI_WRITE_PROTECT);
1494
1495         spin_unlock_irqrestore(&host->lock, flags);
1496
1497         /* This quirk needs to be replaced by a callback-function later */
1498         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1499                 !is_readonly : is_readonly;
1500 }
1501
1502 #define SAMPLE_COUNT    5
1503
1504 static int sdhci_do_get_ro(struct sdhci_host *host)
1505 {
1506         int i, ro_count;
1507
1508         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1509                 return sdhci_check_ro(host);
1510
1511         ro_count = 0;
1512         for (i = 0; i < SAMPLE_COUNT; i++) {
1513                 if (sdhci_check_ro(host)) {
1514                         if (++ro_count > SAMPLE_COUNT / 2)
1515                                 return 1;
1516                 }
1517                 msleep(30);
1518         }
1519         return 0;
1520 }
1521
1522 static void sdhci_hw_reset(struct mmc_host *mmc)
1523 {
1524         struct sdhci_host *host = mmc_priv(mmc);
1525
1526         if (host->ops && host->ops->hw_reset)
1527                 host->ops->hw_reset(host);
1528 }
1529
1530 static int sdhci_get_ro(struct mmc_host *mmc)
1531 {
1532         struct sdhci_host *host = mmc_priv(mmc);
1533         int ret;
1534
1535         sdhci_runtime_pm_get(host);
1536         ret = sdhci_do_get_ro(host);
1537         sdhci_runtime_pm_put(host);
1538         return ret;
1539 }
1540
1541 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1542 {
1543         if (host->flags & SDHCI_DEVICE_DEAD)
1544                 goto out;
1545
1546         if (enable)
1547                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1548         else
1549                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1550
1551         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1552         if (host->runtime_suspended)
1553                 goto out;
1554
1555         if (enable)
1556                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1557         else
1558                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1559 out:
1560         mmiowb();
1561 }
1562
1563 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1564 {
1565         struct sdhci_host *host = mmc_priv(mmc);
1566         unsigned long flags;
1567
1568         spin_lock_irqsave(&host->lock, flags);
1569         sdhci_enable_sdio_irq_nolock(host, enable);
1570         spin_unlock_irqrestore(&host->lock, flags);
1571 }
1572
1573 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1574                                                 struct mmc_ios *ios)
1575 {
1576         u8 pwr;
1577         u16 clk, ctrl;
1578         u32 present_state;
1579
1580         /*
1581          * Signal Voltage Switching is only applicable for Host Controllers
1582          * v3.00 and above.
1583          */
1584         if (host->version < SDHCI_SPEC_300)
1585                 return 0;
1586
1587         /*
1588          * We first check whether the request is to set signalling voltage
1589          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1590          */
1591         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1592         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1593                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1594                 ctrl &= ~SDHCI_CTRL_VDD_180;
1595                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1596
1597                 /* Wait for 5ms */
1598                 usleep_range(5000, 5500);
1599
1600                 /* 3.3V regulator output should be stable within 5 ms */
1601                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1602                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1603                         return 0;
1604                 else {
1605                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1606                                 "signalling voltage failed\n");
1607                         return -EIO;
1608                 }
1609         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1610                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1611                 /* Stop SDCLK */
1612                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1613                 clk &= ~SDHCI_CLOCK_CARD_EN;
1614                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1615
1616                 /* Check whether DAT[3:0] is 0000 */
1617                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1618                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1619                        SDHCI_DATA_LVL_SHIFT)) {
1620                         /*
1621                          * Enable 1.8V Signal Enable in the Host Control2
1622                          * register
1623                          */
1624                         ctrl |= SDHCI_CTRL_VDD_180;
1625                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1626
1627                         /* Wait for 5ms */
1628                         usleep_range(5000, 5500);
1629
1630                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1631                         if (ctrl & SDHCI_CTRL_VDD_180) {
1632                                 /* Provide SDCLK again and wait for 1ms*/
1633                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1634                                 clk |= SDHCI_CLOCK_CARD_EN;
1635                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1636                                 usleep_range(1000, 1500);
1637
1638                                 /*
1639                                  * If DAT[3:0] level is 1111b, then the card
1640                                  * was successfully switched to 1.8V signaling.
1641                                  */
1642                                 present_state = sdhci_readl(host,
1643                                                         SDHCI_PRESENT_STATE);
1644                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1645                                      SDHCI_DATA_LVL_MASK)
1646                                         return 0;
1647                         }
1648                 }
1649
1650                 /*
1651                  * If we are here, that means the switch to 1.8V signaling
1652                  * failed. We power cycle the card, and retry initialization
1653                  * sequence by setting S18R to 0.
1654                  */
1655                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1656                 pwr &= ~SDHCI_POWER_ON;
1657                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1658
1659                 /* Wait for 1ms as per the spec */
1660                 usleep_range(1000, 1500);
1661                 pwr |= SDHCI_POWER_ON;
1662                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1663
1664                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1665                         "voltage failed, retrying with S18R set to 0\n");
1666                 return -EAGAIN;
1667         } else
1668                 /* No signal voltage switch required */
1669                 return 0;
1670 }
1671
1672 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1673         struct mmc_ios *ios)
1674 {
1675         struct sdhci_host *host = mmc_priv(mmc);
1676         int err;
1677
1678         if (host->version < SDHCI_SPEC_300)
1679                 return 0;
1680         sdhci_runtime_pm_get(host);
1681         err = sdhci_do_start_signal_voltage_switch(host, ios);
1682         sdhci_runtime_pm_put(host);
1683         return err;
1684 }
1685
1686 static int sdhci_execute_tuning(struct mmc_host *mmc)
1687 {
1688         struct sdhci_host *host;
1689         u16 ctrl;
1690         u32 ier;
1691         int tuning_loop_counter = MAX_TUNING_LOOP;
1692         unsigned long timeout;
1693         int err = 0;
1694
1695         host = mmc_priv(mmc);
1696
1697         sdhci_runtime_pm_get(host);
1698         disable_irq(host->irq);
1699         spin_lock(&host->lock);
1700
1701         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1702
1703         /*
1704          * Host Controller needs tuning only in case of SDR104 mode
1705          * and for SDR50 mode when Use Tuning for SDR50 is set in
1706          * Capabilities register.
1707          */
1708         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1709             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1710             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1711                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1712         else {
1713                 spin_unlock(&host->lock);
1714                 enable_irq(host->irq);
1715                 sdhci_runtime_pm_put(host);
1716                 return 0;
1717         }
1718
1719         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1720
1721         /*
1722          * As per the Host Controller spec v3.00, tuning command
1723          * generates Buffer Read Ready interrupt, so enable that.
1724          *
1725          * Note: The spec clearly says that when tuning sequence
1726          * is being performed, the controller does not generate
1727          * interrupts other than Buffer Read Ready interrupt. But
1728          * to make sure we don't hit a controller bug, we _only_
1729          * enable Buffer Read Ready interrupt here.
1730          */
1731         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1732         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1733
1734         /*
1735          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1736          * of loops reaches 40 times or a timeout of 150ms occurs.
1737          */
1738         timeout = 150;
1739         do {
1740                 struct mmc_command cmd = {0};
1741                 struct mmc_request mrq = {NULL};
1742
1743                 if (!tuning_loop_counter && !timeout)
1744                         break;
1745
1746                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1747                 cmd.arg = 0;
1748                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1749                 cmd.retries = 0;
1750                 cmd.data = NULL;
1751                 cmd.error = 0;
1752
1753                 mrq.cmd = &cmd;
1754                 host->mrq = &mrq;
1755
1756                 /*
1757                  * In response to CMD19, the card sends 64 bytes of tuning
1758                  * block to the Host Controller. So we set the block size
1759                  * to 64 here.
1760                  */
1761                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1762
1763                 /*
1764                  * The tuning block is sent by the card to the host controller.
1765                  * So we set the TRNS_READ bit in the Transfer Mode register.
1766                  * This also takes care of setting DMA Enable and Multi Block
1767                  * Select in the same register to 0.
1768                  */
1769                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1770
1771                 sdhci_send_command(host, &cmd);
1772
1773                 host->cmd = NULL;
1774                 host->mrq = NULL;
1775
1776                 spin_unlock(&host->lock);
1777                 enable_irq(host->irq);
1778
1779                 /* Wait for Buffer Read Ready interrupt */
1780                 wait_event_interruptible_timeout(host->buf_ready_int,
1781                                         (host->tuning_done == 1),
1782                                         msecs_to_jiffies(50));
1783                 disable_irq(host->irq);
1784                 spin_lock(&host->lock);
1785
1786                 if (!host->tuning_done) {
1787                         pr_info(DRIVER_NAME ": Timeout waiting for "
1788                                 "Buffer Read Ready interrupt during tuning "
1789                                 "procedure, falling back to fixed sampling "
1790                                 "clock\n");
1791                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1792                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1793                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1794                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1795
1796                         err = -EIO;
1797                         goto out;
1798                 }
1799
1800                 host->tuning_done = 0;
1801
1802                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803                 tuning_loop_counter--;
1804                 timeout--;
1805                 mdelay(1);
1806         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1807
1808         /*
1809          * The Host Driver has exhausted the maximum number of loops allowed,
1810          * so use fixed sampling frequency.
1811          */
1812         if (!tuning_loop_counter || !timeout) {
1813                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1814                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1815         } else {
1816                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1817                         pr_info(DRIVER_NAME ": Tuning procedure"
1818                                 " failed, falling back to fixed sampling"
1819                                 " clock\n");
1820                         err = -EIO;
1821                 }
1822         }
1823
1824 out:
1825         /*
1826          * If this is the very first time we are here, we start the retuning
1827          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1828          * flag won't be set, we check this condition before actually starting
1829          * the timer.
1830          */
1831         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1832             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1833                 mod_timer(&host->tuning_timer, jiffies +
1834                         host->tuning_count * HZ);
1835                 /* Tuning mode 1 limits the maximum data length to 4MB */
1836                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1837         } else {
1838                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1839                 /* Reload the new initial value for timer */
1840                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1841                         mod_timer(&host->tuning_timer, jiffies +
1842                                 host->tuning_count * HZ);
1843         }
1844
1845         /*
1846          * In case tuning fails, host controllers which support re-tuning can
1847          * try tuning again at a later time, when the re-tuning timer expires.
1848          * So for these controllers, we return 0. Since there might be other
1849          * controllers who do not have this capability, we return error for
1850          * them.
1851          */
1852         if (err && host->tuning_count &&
1853             host->tuning_mode == SDHCI_TUNING_MODE_1)
1854                 err = 0;
1855
1856         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1857         spin_unlock(&host->lock);
1858         enable_irq(host->irq);
1859         sdhci_runtime_pm_put(host);
1860
1861         return err;
1862 }
1863
1864 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1865 {
1866         u16 ctrl;
1867         unsigned long flags;
1868
1869         /* Host Controller v3.00 defines preset value registers */
1870         if (host->version < SDHCI_SPEC_300)
1871                 return;
1872
1873         spin_lock_irqsave(&host->lock, flags);
1874
1875         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1876
1877         /*
1878          * We only enable or disable Preset Value if they are not already
1879          * enabled or disabled respectively. Otherwise, we bail out.
1880          */
1881         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1882                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1883                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1884                 host->flags |= SDHCI_PV_ENABLED;
1885         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1886                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1887                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1888                 host->flags &= ~SDHCI_PV_ENABLED;
1889         }
1890
1891         spin_unlock_irqrestore(&host->lock, flags);
1892 }
1893
1894 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1895 {
1896         struct sdhci_host *host = mmc_priv(mmc);
1897
1898         sdhci_runtime_pm_get(host);
1899         sdhci_do_enable_preset_value(host, enable);
1900         sdhci_runtime_pm_put(host);
1901 }
1902
1903 static const struct mmc_host_ops sdhci_ops = {
1904         .request        = sdhci_request,
1905         .set_ios        = sdhci_set_ios,
1906         .get_ro         = sdhci_get_ro,
1907         .hw_reset       = sdhci_hw_reset,
1908         .enable_sdio_irq = sdhci_enable_sdio_irq,
1909         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1910         .execute_tuning                 = sdhci_execute_tuning,
1911         .enable_preset_value            = sdhci_enable_preset_value,
1912 };
1913
1914 /*****************************************************************************\
1915  *                                                                           *
1916  * Tasklets                                                                  *
1917  *                                                                           *
1918 \*****************************************************************************/
1919
1920 static void sdhci_tasklet_card(unsigned long param)
1921 {
1922         struct sdhci_host *host;
1923         unsigned long flags;
1924
1925         host = (struct sdhci_host*)param;
1926
1927         spin_lock_irqsave(&host->lock, flags);
1928
1929         /* Check host->mrq first in case we are runtime suspended */
1930         if (host->mrq &&
1931             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1932                 pr_err("%s: Card removed during transfer!\n",
1933                         mmc_hostname(host->mmc));
1934                 pr_err("%s: Resetting controller.\n",
1935                         mmc_hostname(host->mmc));
1936
1937                 sdhci_reset(host, SDHCI_RESET_CMD);
1938                 sdhci_reset(host, SDHCI_RESET_DATA);
1939
1940                 host->mrq->cmd->error = -ENOMEDIUM;
1941                 tasklet_schedule(&host->finish_tasklet);
1942         }
1943
1944         spin_unlock_irqrestore(&host->lock, flags);
1945
1946         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1947 }
1948
1949 static void sdhci_tasklet_finish(unsigned long param)
1950 {
1951         struct sdhci_host *host;
1952         unsigned long flags;
1953         struct mmc_request *mrq;
1954
1955         host = (struct sdhci_host*)param;
1956
1957         spin_lock_irqsave(&host->lock, flags);
1958
1959         /*
1960          * If this tasklet gets rescheduled while running, it will
1961          * be run again afterwards but without any active request.
1962          */
1963         if (!host->mrq) {
1964                 spin_unlock_irqrestore(&host->lock, flags);
1965                 return;
1966         }
1967
1968         del_timer(&host->timer);
1969
1970         mrq = host->mrq;
1971
1972         /*
1973          * The controller needs a reset of internal state machines
1974          * upon error conditions.
1975          */
1976         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1977             ((mrq->cmd && mrq->cmd->error) ||
1978                  (mrq->data && (mrq->data->error ||
1979                   (mrq->data->stop && mrq->data->stop->error))) ||
1980                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1981
1982                 /* Some controllers need this kick or reset won't work here */
1983                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1984                         unsigned int clock;
1985
1986                         /* This is to force an update */
1987                         clock = host->clock;
1988                         host->clock = 0;
1989                         sdhci_set_clock(host, clock);
1990                 }
1991
1992                 /* Spec says we should do both at the same time, but Ricoh
1993                    controllers do not like that. */
1994                 sdhci_reset(host, SDHCI_RESET_CMD);
1995                 sdhci_reset(host, SDHCI_RESET_DATA);
1996         }
1997
1998         host->mrq = NULL;
1999         host->cmd = NULL;
2000         host->data = NULL;
2001
2002 #ifndef SDHCI_USE_LEDS_CLASS
2003         sdhci_deactivate_led(host);
2004 #endif
2005
2006         mmiowb();
2007         spin_unlock_irqrestore(&host->lock, flags);
2008
2009         mmc_request_done(host->mmc, mrq);
2010         sdhci_runtime_pm_put(host);
2011 }
2012
2013 static void sdhci_timeout_timer(unsigned long data)
2014 {
2015         struct sdhci_host *host;
2016         unsigned long flags;
2017
2018         host = (struct sdhci_host*)data;
2019
2020         spin_lock_irqsave(&host->lock, flags);
2021
2022         if (host->mrq) {
2023                 pr_err("%s: Timeout waiting for hardware "
2024                         "interrupt.\n", mmc_hostname(host->mmc));
2025                 sdhci_dumpregs(host);
2026
2027                 if (host->data) {
2028                         host->data->error = -ETIMEDOUT;
2029                         sdhci_finish_data(host);
2030                 } else {
2031                         if (host->cmd)
2032                                 host->cmd->error = -ETIMEDOUT;
2033                         else
2034                                 host->mrq->cmd->error = -ETIMEDOUT;
2035
2036                         tasklet_schedule(&host->finish_tasklet);
2037                 }
2038         }
2039
2040         mmiowb();
2041         spin_unlock_irqrestore(&host->lock, flags);
2042 }
2043
2044 static void sdhci_tuning_timer(unsigned long data)
2045 {
2046         struct sdhci_host *host;
2047         unsigned long flags;
2048
2049         host = (struct sdhci_host *)data;
2050
2051         spin_lock_irqsave(&host->lock, flags);
2052
2053         host->flags |= SDHCI_NEEDS_RETUNING;
2054
2055         spin_unlock_irqrestore(&host->lock, flags);
2056 }
2057
2058 /*****************************************************************************\
2059  *                                                                           *
2060  * Interrupt handling                                                        *
2061  *                                                                           *
2062 \*****************************************************************************/
2063
2064 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2065 {
2066         BUG_ON(intmask == 0);
2067
2068         if (!host->cmd) {
2069                 pr_err("%s: Got command interrupt 0x%08x even "
2070                         "though no command operation was in progress.\n",
2071                         mmc_hostname(host->mmc), (unsigned)intmask);
2072                 sdhci_dumpregs(host);
2073                 return;
2074         }
2075
2076         if (intmask & SDHCI_INT_TIMEOUT)
2077                 host->cmd->error = -ETIMEDOUT;
2078         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2079                         SDHCI_INT_INDEX))
2080                 host->cmd->error = -EILSEQ;
2081
2082         if (host->cmd->error) {
2083                 tasklet_schedule(&host->finish_tasklet);
2084                 return;
2085         }
2086
2087         /*
2088          * The host can send and interrupt when the busy state has
2089          * ended, allowing us to wait without wasting CPU cycles.
2090          * Unfortunately this is overloaded on the "data complete"
2091          * interrupt, so we need to take some care when handling
2092          * it.
2093          *
2094          * Note: The 1.0 specification is a bit ambiguous about this
2095          *       feature so there might be some problems with older
2096          *       controllers.
2097          */
2098         if (host->cmd->flags & MMC_RSP_BUSY) {
2099                 if (host->cmd->data)
2100                         DBG("Cannot wait for busy signal when also "
2101                                 "doing a data transfer");
2102                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2103                         return;
2104
2105                 /* The controller does not support the end-of-busy IRQ,
2106                  * fall through and take the SDHCI_INT_RESPONSE */
2107         }
2108
2109         if (intmask & SDHCI_INT_RESPONSE)
2110                 sdhci_finish_command(host);
2111 }
2112
2113 #ifdef CONFIG_MMC_DEBUG
2114 static void sdhci_show_adma_error(struct sdhci_host *host)
2115 {
2116         const char *name = mmc_hostname(host->mmc);
2117         u8 *desc = host->adma_desc;
2118         __le32 *dma;
2119         __le16 *len;
2120         u8 attr;
2121
2122         sdhci_dumpregs(host);
2123
2124         while (true) {
2125                 dma = (__le32 *)(desc + 4);
2126                 len = (__le16 *)(desc + 2);
2127                 attr = *desc;
2128
2129                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2130                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2131
2132                 desc += 8;
2133
2134                 if (attr & 2)
2135                         break;
2136         }
2137 }
2138 #else
2139 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2140 #endif
2141
2142 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2143 {
2144         BUG_ON(intmask == 0);
2145
2146         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2147         if (intmask & SDHCI_INT_DATA_AVAIL) {
2148                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2149                     MMC_SEND_TUNING_BLOCK) {
2150                         host->tuning_done = 1;
2151                         wake_up(&host->buf_ready_int);
2152                         return;
2153                 }
2154         }
2155
2156         if (!host->data) {
2157                 /*
2158                  * The "data complete" interrupt is also used to
2159                  * indicate that a busy state has ended. See comment
2160                  * above in sdhci_cmd_irq().
2161                  */
2162                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2163                         if (intmask & SDHCI_INT_DATA_END) {
2164                                 sdhci_finish_command(host);
2165                                 return;
2166                         }
2167                 }
2168
2169                 pr_err("%s: Got data interrupt 0x%08x even "
2170                         "though no data operation was in progress.\n",
2171                         mmc_hostname(host->mmc), (unsigned)intmask);
2172                 sdhci_dumpregs(host);
2173
2174                 return;
2175         }
2176
2177         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2178                 host->data->error = -ETIMEDOUT;
2179         else if (intmask & SDHCI_INT_DATA_END_BIT)
2180                 host->data->error = -EILSEQ;
2181         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2182                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2183                         != MMC_BUS_TEST_R)
2184                 host->data->error = -EILSEQ;
2185         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2186                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2187                 sdhci_show_adma_error(host);
2188                 host->data->error = -EIO;
2189         }
2190
2191         if (host->data->error)
2192                 sdhci_finish_data(host);
2193         else {
2194                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2195                         sdhci_transfer_pio(host);
2196
2197                 /*
2198                  * We currently don't do anything fancy with DMA
2199                  * boundaries, but as we can't disable the feature
2200                  * we need to at least restart the transfer.
2201                  *
2202                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2203                  * should return a valid address to continue from, but as
2204                  * some controllers are faulty, don't trust them.
2205                  */
2206                 if (intmask & SDHCI_INT_DMA_END) {
2207                         u32 dmastart, dmanow;
2208                         dmastart = sg_dma_address(host->data->sg);
2209                         dmanow = dmastart + host->data->bytes_xfered;
2210                         /*
2211                          * Force update to the next DMA block boundary.
2212                          */
2213                         dmanow = (dmanow &
2214                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2215                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2216                         host->data->bytes_xfered = dmanow - dmastart;
2217                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2218                                 " next 0x%08x\n",
2219                                 mmc_hostname(host->mmc), dmastart,
2220                                 host->data->bytes_xfered, dmanow);
2221                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2222                 }
2223
2224                 if (intmask & SDHCI_INT_DATA_END) {
2225                         if (host->cmd) {
2226                                 /*
2227                                  * Data managed to finish before the
2228                                  * command completed. Make sure we do
2229                                  * things in the proper order.
2230                                  */
2231                                 host->data_early = 1;
2232                         } else {
2233                                 sdhci_finish_data(host);
2234                         }
2235                 }
2236         }
2237 }
2238
2239 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2240 {
2241         irqreturn_t result;
2242         struct sdhci_host *host = dev_id;
2243         u32 intmask;
2244         int cardint = 0;
2245
2246         spin_lock(&host->lock);
2247
2248         if (host->runtime_suspended) {
2249                 spin_unlock(&host->lock);
2250                 pr_warning("%s: got irq while runtime suspended\n",
2251                        mmc_hostname(host->mmc));
2252                 return IRQ_HANDLED;
2253         }
2254
2255         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2256
2257         if (!intmask || intmask == 0xffffffff) {
2258                 result = IRQ_NONE;
2259                 goto out;
2260         }
2261
2262         DBG("*** %s got interrupt: 0x%08x\n",
2263                 mmc_hostname(host->mmc), intmask);
2264
2265         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2266                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2267                               SDHCI_CARD_PRESENT;
2268
2269                 /*
2270                  * There is a observation on i.mx esdhc.  INSERT bit will be
2271                  * immediately set again when it gets cleared, if a card is
2272                  * inserted.  We have to mask the irq to prevent interrupt
2273                  * storm which will freeze the system.  And the REMOVE gets
2274                  * the same situation.
2275                  *
2276                  * More testing are needed here to ensure it works for other
2277                  * platforms though.
2278                  */
2279                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2280                                                 SDHCI_INT_CARD_REMOVE);
2281                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2282                                                   SDHCI_INT_CARD_INSERT);
2283
2284                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2285                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2286                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2287                 tasklet_schedule(&host->card_tasklet);
2288         }
2289
2290         if (intmask & SDHCI_INT_CMD_MASK) {
2291                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2292                         SDHCI_INT_STATUS);
2293                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2294         }
2295
2296         if (intmask & SDHCI_INT_DATA_MASK) {
2297                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2298                         SDHCI_INT_STATUS);
2299                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2300         }
2301
2302         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2303
2304         intmask &= ~SDHCI_INT_ERROR;
2305
2306         if (intmask & SDHCI_INT_BUS_POWER) {
2307                 pr_err("%s: Card is consuming too much power!\n",
2308                         mmc_hostname(host->mmc));
2309                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2310         }
2311
2312         intmask &= ~SDHCI_INT_BUS_POWER;
2313
2314         if (intmask & SDHCI_INT_CARD_INT)
2315                 cardint = 1;
2316
2317         intmask &= ~SDHCI_INT_CARD_INT;
2318
2319         if (intmask) {
2320                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2321                         mmc_hostname(host->mmc), intmask);
2322                 sdhci_dumpregs(host);
2323
2324                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2325         }
2326
2327         result = IRQ_HANDLED;
2328
2329         mmiowb();
2330 out:
2331         spin_unlock(&host->lock);
2332
2333         /*
2334          * We have to delay this as it calls back into the driver.
2335          */
2336         if (cardint)
2337                 mmc_signal_sdio_irq(host->mmc);
2338
2339         return result;
2340 }
2341
2342 /*****************************************************************************\
2343  *                                                                           *
2344  * Suspend/resume                                                            *
2345  *                                                                           *
2346 \*****************************************************************************/
2347
2348 #ifdef CONFIG_PM
2349
2350 int sdhci_suspend_host(struct sdhci_host *host)
2351 {
2352         int ret;
2353
2354         sdhci_disable_card_detection(host);
2355
2356         /* Disable tuning since we are suspending */
2357         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2358             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2359                 del_timer_sync(&host->tuning_timer);
2360                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2361         }
2362
2363         ret = mmc_suspend_host(host->mmc);
2364         if (ret)
2365                 return ret;
2366
2367         free_irq(host->irq, host);
2368
2369         return ret;
2370 }
2371
2372 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2373
2374 int sdhci_resume_host(struct sdhci_host *host)
2375 {
2376         int ret;
2377
2378         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2379                 if (host->ops->enable_dma)
2380                         host->ops->enable_dma(host);
2381         }
2382
2383         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2384                           mmc_hostname(host->mmc), host);
2385         if (ret)
2386                 return ret;
2387
2388         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2389         mmiowb();
2390
2391         ret = mmc_resume_host(host->mmc);
2392         sdhci_enable_card_detection(host);
2393
2394         /* Set the re-tuning expiration flag */
2395         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2396             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2397                 host->flags |= SDHCI_NEEDS_RETUNING;
2398
2399         return ret;
2400 }
2401
2402 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2403
2404 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2405 {
2406         u8 val;
2407         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2408         val |= SDHCI_WAKE_ON_INT;
2409         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2410 }
2411
2412 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2413
2414 #endif /* CONFIG_PM */
2415
2416 #ifdef CONFIG_PM_RUNTIME
2417
2418 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2419 {
2420         return pm_runtime_get_sync(host->mmc->parent);
2421 }
2422
2423 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2424 {
2425         pm_runtime_mark_last_busy(host->mmc->parent);
2426         return pm_runtime_put_autosuspend(host->mmc->parent);
2427 }
2428
2429 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2430 {
2431         unsigned long flags;
2432         int ret = 0;
2433
2434         /* Disable tuning since we are suspending */
2435         if (host->version >= SDHCI_SPEC_300 &&
2436             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2437                 del_timer_sync(&host->tuning_timer);
2438                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2439         }
2440
2441         spin_lock_irqsave(&host->lock, flags);
2442         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2443         spin_unlock_irqrestore(&host->lock, flags);
2444
2445         synchronize_irq(host->irq);
2446
2447         spin_lock_irqsave(&host->lock, flags);
2448         host->runtime_suspended = true;
2449         spin_unlock_irqrestore(&host->lock, flags);
2450
2451         return ret;
2452 }
2453 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2454
2455 int sdhci_runtime_resume_host(struct sdhci_host *host)
2456 {
2457         unsigned long flags;
2458         int ret = 0, host_flags = host->flags;
2459
2460         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2461                 if (host->ops->enable_dma)
2462                         host->ops->enable_dma(host);
2463         }
2464
2465         sdhci_init(host, 0);
2466
2467         /* Force clock and power re-program */
2468         host->pwr = 0;
2469         host->clock = 0;
2470         sdhci_do_set_ios(host, &host->mmc->ios);
2471
2472         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2473         if (host_flags & SDHCI_PV_ENABLED)
2474                 sdhci_do_enable_preset_value(host, true);
2475
2476         /* Set the re-tuning expiration flag */
2477         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2478             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2479                 host->flags |= SDHCI_NEEDS_RETUNING;
2480
2481         spin_lock_irqsave(&host->lock, flags);
2482
2483         host->runtime_suspended = false;
2484
2485         /* Enable SDIO IRQ */
2486         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2487                 sdhci_enable_sdio_irq_nolock(host, true);
2488
2489         /* Enable Card Detection */
2490         sdhci_enable_card_detection(host);
2491
2492         spin_unlock_irqrestore(&host->lock, flags);
2493
2494         return ret;
2495 }
2496 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2497
2498 #endif
2499
2500 /*****************************************************************************\
2501  *                                                                           *
2502  * Device allocation/registration                                            *
2503  *                                                                           *
2504 \*****************************************************************************/
2505
2506 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2507         size_t priv_size)
2508 {
2509         struct mmc_host *mmc;
2510         struct sdhci_host *host;
2511
2512         WARN_ON(dev == NULL);
2513
2514         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2515         if (!mmc)
2516                 return ERR_PTR(-ENOMEM);
2517
2518         host = mmc_priv(mmc);
2519         host->mmc = mmc;
2520
2521         return host;
2522 }
2523
2524 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2525
2526 int sdhci_add_host(struct sdhci_host *host)
2527 {
2528         struct mmc_host *mmc;
2529         u32 caps[2];
2530         u32 max_current_caps;
2531         unsigned int ocr_avail;
2532         int ret;
2533
2534         WARN_ON(host == NULL);
2535         if (host == NULL)
2536                 return -EINVAL;
2537
2538         mmc = host->mmc;
2539
2540         if (debug_quirks)
2541                 host->quirks = debug_quirks;
2542         if (debug_quirks2)
2543                 host->quirks2 = debug_quirks2;
2544
2545         sdhci_reset(host, SDHCI_RESET_ALL);
2546
2547         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2548         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2549                                 >> SDHCI_SPEC_VER_SHIFT;
2550         if (host->version > SDHCI_SPEC_300) {
2551                 pr_err("%s: Unknown controller version (%d). "
2552                         "You may experience problems.\n", mmc_hostname(mmc),
2553                         host->version);
2554         }
2555
2556         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2557                 sdhci_readl(host, SDHCI_CAPABILITIES);
2558
2559         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2560                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2561
2562         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2563                 host->flags |= SDHCI_USE_SDMA;
2564         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2565                 DBG("Controller doesn't have SDMA capability\n");
2566         else
2567                 host->flags |= SDHCI_USE_SDMA;
2568
2569         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2570                 (host->flags & SDHCI_USE_SDMA)) {
2571                 DBG("Disabling DMA as it is marked broken\n");
2572                 host->flags &= ~SDHCI_USE_SDMA;
2573         }
2574
2575         if ((host->version >= SDHCI_SPEC_200) &&
2576                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2577                 host->flags |= SDHCI_USE_ADMA;
2578
2579         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2580                 (host->flags & SDHCI_USE_ADMA)) {
2581                 DBG("Disabling ADMA as it is marked broken\n");
2582                 host->flags &= ~SDHCI_USE_ADMA;
2583         }
2584
2585         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2586                 if (host->ops->enable_dma) {
2587                         if (host->ops->enable_dma(host)) {
2588                                 pr_warning("%s: No suitable DMA "
2589                                         "available. Falling back to PIO.\n",
2590                                         mmc_hostname(mmc));
2591                                 host->flags &=
2592                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2593                         }
2594                 }
2595         }
2596
2597         if (host->flags & SDHCI_USE_ADMA) {
2598                 /*
2599                  * We need to allocate descriptors for all sg entries
2600                  * (128) and potentially one alignment transfer for
2601                  * each of those entries.
2602                  */
2603                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2604                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2605                 if (!host->adma_desc || !host->align_buffer) {
2606                         kfree(host->adma_desc);
2607                         kfree(host->align_buffer);
2608                         pr_warning("%s: Unable to allocate ADMA "
2609                                 "buffers. Falling back to standard DMA.\n",
2610                                 mmc_hostname(mmc));
2611                         host->flags &= ~SDHCI_USE_ADMA;
2612                 }
2613         }
2614
2615         /*
2616          * If we use DMA, then it's up to the caller to set the DMA
2617          * mask, but PIO does not need the hw shim so we set a new
2618          * mask here in that case.
2619          */
2620         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2621                 host->dma_mask = DMA_BIT_MASK(64);
2622                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2623         }
2624
2625         if (host->version >= SDHCI_SPEC_300)
2626                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2627                         >> SDHCI_CLOCK_BASE_SHIFT;
2628         else
2629                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2630                         >> SDHCI_CLOCK_BASE_SHIFT;
2631
2632         host->max_clk *= 1000000;
2633         if (host->max_clk == 0 || host->quirks &
2634                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2635                 if (!host->ops->get_max_clock) {
2636                         pr_err("%s: Hardware doesn't specify base clock "
2637                                "frequency.\n", mmc_hostname(mmc));
2638                         return -ENODEV;
2639                 }
2640                 host->max_clk = host->ops->get_max_clock(host);
2641         }
2642
2643         /*
2644          * In case of Host Controller v3.00, find out whether clock
2645          * multiplier is supported.
2646          */
2647         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2648                         SDHCI_CLOCK_MUL_SHIFT;
2649
2650         /*
2651          * In case the value in Clock Multiplier is 0, then programmable
2652          * clock mode is not supported, otherwise the actual clock
2653          * multiplier is one more than the value of Clock Multiplier
2654          * in the Capabilities Register.
2655          */
2656         if (host->clk_mul)
2657                 host->clk_mul += 1;
2658
2659         /*
2660          * Set host parameters.
2661          */
2662         mmc->ops = &sdhci_ops;
2663         mmc->f_max = host->max_clk;
2664         if (host->ops->get_min_clock)
2665                 mmc->f_min = host->ops->get_min_clock(host);
2666         else if (host->version >= SDHCI_SPEC_300) {
2667                 if (host->clk_mul) {
2668                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2669                         mmc->f_max = host->max_clk * host->clk_mul;
2670                 } else
2671                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2672         } else
2673                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2674
2675         host->timeout_clk =
2676                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2677         if (host->timeout_clk == 0) {
2678                 if (host->ops->get_timeout_clock) {
2679                         host->timeout_clk = host->ops->get_timeout_clock(host);
2680                 } else if (!(host->quirks &
2681                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2682                         pr_err("%s: Hardware doesn't specify timeout clock "
2683                                "frequency.\n", mmc_hostname(mmc));
2684                         return -ENODEV;
2685                 }
2686         }
2687         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2688                 host->timeout_clk *= 1000;
2689
2690         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2691                 host->timeout_clk = mmc->f_max / 1000;
2692
2693         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2694
2695         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2696
2697         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2698                 host->flags |= SDHCI_AUTO_CMD12;
2699
2700         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2701         if ((host->version >= SDHCI_SPEC_300) &&
2702             ((host->flags & SDHCI_USE_ADMA) ||
2703              !(host->flags & SDHCI_USE_SDMA))) {
2704                 host->flags |= SDHCI_AUTO_CMD23;
2705                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2706         } else {
2707                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2708         }
2709
2710         /*
2711          * A controller may support 8-bit width, but the board itself
2712          * might not have the pins brought out.  Boards that support
2713          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2714          * their platform code before calling sdhci_add_host(), and we
2715          * won't assume 8-bit width for hosts without that CAP.
2716          */
2717         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2718                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2719
2720         if (caps[0] & SDHCI_CAN_DO_HISPD)
2721                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2722
2723         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2724             mmc_card_is_removable(mmc))
2725                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2726
2727         /* UHS-I mode(s) supported by the host controller. */
2728         if (host->version >= SDHCI_SPEC_300)
2729                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2730
2731         /* SDR104 supports also implies SDR50 support */
2732         if (caps[1] & SDHCI_SUPPORT_SDR104)
2733                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2734         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2735                 mmc->caps |= MMC_CAP_UHS_SDR50;
2736
2737         if (caps[1] & SDHCI_SUPPORT_DDR50)
2738                 mmc->caps |= MMC_CAP_UHS_DDR50;
2739
2740         /* Does the host needs tuning for SDR50? */
2741         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2742                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2743
2744         /* Driver Type(s) (A, C, D) supported by the host */
2745         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2746                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2747         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2748                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2749         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2750                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2751
2752         /*
2753          * If Power Off Notify capability is enabled by the host,
2754          * set notify to short power off notify timeout value.
2755          */
2756         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2757                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2758         else
2759                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2760
2761         /* Initial value for re-tuning timer count */
2762         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2763                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2764
2765         /*
2766          * In case Re-tuning Timer is not disabled, the actual value of
2767          * re-tuning timer will be 2 ^ (n - 1).
2768          */
2769         if (host->tuning_count)
2770                 host->tuning_count = 1 << (host->tuning_count - 1);
2771
2772         /* Re-tuning mode supported by the Host Controller */
2773         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2774                              SDHCI_RETUNING_MODE_SHIFT;
2775
2776         ocr_avail = 0;
2777         /*
2778          * According to SD Host Controller spec v3.00, if the Host System
2779          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2780          * the value is meaningful only if Voltage Support in the Capabilities
2781          * register is set. The actual current value is 4 times the register
2782          * value.
2783          */
2784         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2785
2786         if (caps[0] & SDHCI_CAN_VDD_330) {
2787                 int max_current_330;
2788
2789                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2790
2791                 max_current_330 = ((max_current_caps &
2792                                    SDHCI_MAX_CURRENT_330_MASK) >>
2793                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2794                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2795
2796                 if (max_current_330 > 150)
2797                         mmc->caps |= MMC_CAP_SET_XPC_330;
2798         }
2799         if (caps[0] & SDHCI_CAN_VDD_300) {
2800                 int max_current_300;
2801
2802                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2803
2804                 max_current_300 = ((max_current_caps &
2805                                    SDHCI_MAX_CURRENT_300_MASK) >>
2806                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2807                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2808
2809                 if (max_current_300 > 150)
2810                         mmc->caps |= MMC_CAP_SET_XPC_300;
2811         }
2812         if (caps[0] & SDHCI_CAN_VDD_180) {
2813                 int max_current_180;
2814
2815                 ocr_avail |= MMC_VDD_165_195;
2816
2817                 max_current_180 = ((max_current_caps &
2818                                    SDHCI_MAX_CURRENT_180_MASK) >>
2819                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2820                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2821
2822                 if (max_current_180 > 150)
2823                         mmc->caps |= MMC_CAP_SET_XPC_180;
2824
2825                 /* Maximum current capabilities of the host at 1.8V */
2826                 if (max_current_180 >= 800)
2827                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2828                 else if (max_current_180 >= 600)
2829                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2830                 else if (max_current_180 >= 400)
2831                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2832                 else
2833                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2834         }
2835
2836         mmc->ocr_avail = ocr_avail;
2837         mmc->ocr_avail_sdio = ocr_avail;
2838         if (host->ocr_avail_sdio)
2839                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2840         mmc->ocr_avail_sd = ocr_avail;
2841         if (host->ocr_avail_sd)
2842                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2843         else /* normal SD controllers don't support 1.8V */
2844                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2845         mmc->ocr_avail_mmc = ocr_avail;
2846         if (host->ocr_avail_mmc)
2847                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2848
2849         if (mmc->ocr_avail == 0) {
2850                 pr_err("%s: Hardware doesn't report any "
2851                         "support voltages.\n", mmc_hostname(mmc));
2852                 return -ENODEV;
2853         }
2854
2855         spin_lock_init(&host->lock);
2856
2857         /*
2858          * Maximum number of segments. Depends on if the hardware
2859          * can do scatter/gather or not.
2860          */
2861         if (host->flags & SDHCI_USE_ADMA)
2862                 mmc->max_segs = 128;
2863         else if (host->flags & SDHCI_USE_SDMA)
2864                 mmc->max_segs = 1;
2865         else /* PIO */
2866                 mmc->max_segs = 128;
2867
2868         /*
2869          * Maximum number of sectors in one transfer. Limited by DMA boundary
2870          * size (512KiB).
2871          */
2872         mmc->max_req_size = 524288;
2873
2874         /*
2875          * Maximum segment size. Could be one segment with the maximum number
2876          * of bytes. When doing hardware scatter/gather, each entry cannot
2877          * be larger than 64 KiB though.
2878          */
2879         if (host->flags & SDHCI_USE_ADMA) {
2880                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2881                         mmc->max_seg_size = 65535;
2882                 else
2883                         mmc->max_seg_size = 65536;
2884         } else {
2885                 mmc->max_seg_size = mmc->max_req_size;
2886         }
2887
2888         /*
2889          * Maximum block size. This varies from controller to controller and
2890          * is specified in the capabilities register.
2891          */
2892         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2893                 mmc->max_blk_size = 2;
2894         } else {
2895                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2896                                 SDHCI_MAX_BLOCK_SHIFT;
2897                 if (mmc->max_blk_size >= 3) {
2898                         pr_warning("%s: Invalid maximum block size, "
2899                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2900                         mmc->max_blk_size = 0;
2901                 }
2902         }
2903
2904         mmc->max_blk_size = 512 << mmc->max_blk_size;
2905
2906         /*
2907          * Maximum block count.
2908          */
2909         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2910
2911         /*
2912          * Init tasklets.
2913          */
2914         tasklet_init(&host->card_tasklet,
2915                 sdhci_tasklet_card, (unsigned long)host);
2916         tasklet_init(&host->finish_tasklet,
2917                 sdhci_tasklet_finish, (unsigned long)host);
2918
2919         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2920
2921         if (host->version >= SDHCI_SPEC_300) {
2922                 init_waitqueue_head(&host->buf_ready_int);
2923
2924                 /* Initialize re-tuning timer */
2925                 init_timer(&host->tuning_timer);
2926                 host->tuning_timer.data = (unsigned long)host;
2927                 host->tuning_timer.function = sdhci_tuning_timer;
2928         }
2929
2930         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2931                 mmc_hostname(mmc), host);
2932         if (ret)
2933                 goto untasklet;
2934
2935         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2936         if (IS_ERR(host->vmmc)) {
2937                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2938                 host->vmmc = NULL;
2939         }
2940
2941         sdhci_init(host, 0);
2942
2943 #ifdef CONFIG_MMC_DEBUG
2944         sdhci_dumpregs(host);
2945 #endif
2946
2947 #ifdef SDHCI_USE_LEDS_CLASS
2948         snprintf(host->led_name, sizeof(host->led_name),
2949                 "%s::", mmc_hostname(mmc));
2950         host->led.name = host->led_name;
2951         host->led.brightness = LED_OFF;
2952         host->led.default_trigger = mmc_hostname(mmc);
2953         host->led.brightness_set = sdhci_led_control;
2954
2955         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2956         if (ret)
2957                 goto reset;
2958 #endif
2959
2960         mmiowb();
2961
2962         mmc_add_host(mmc);
2963
2964         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
2965                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2966                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2967                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2968
2969         sdhci_enable_card_detection(host);
2970
2971         return 0;
2972
2973 #ifdef SDHCI_USE_LEDS_CLASS
2974 reset:
2975         sdhci_reset(host, SDHCI_RESET_ALL);
2976         free_irq(host->irq, host);
2977 #endif
2978 untasklet:
2979         tasklet_kill(&host->card_tasklet);
2980         tasklet_kill(&host->finish_tasklet);
2981
2982         return ret;
2983 }
2984
2985 EXPORT_SYMBOL_GPL(sdhci_add_host);
2986
2987 void sdhci_remove_host(struct sdhci_host *host, int dead)
2988 {
2989         unsigned long flags;
2990
2991         if (dead) {
2992                 spin_lock_irqsave(&host->lock, flags);
2993
2994                 host->flags |= SDHCI_DEVICE_DEAD;
2995
2996                 if (host->mrq) {
2997                         pr_err("%s: Controller removed during "
2998                                 " transfer!\n", mmc_hostname(host->mmc));
2999
3000                         host->mrq->cmd->error = -ENOMEDIUM;
3001                         tasklet_schedule(&host->finish_tasklet);
3002                 }
3003
3004                 spin_unlock_irqrestore(&host->lock, flags);
3005         }
3006
3007         sdhci_disable_card_detection(host);
3008
3009         mmc_remove_host(host->mmc);
3010
3011 #ifdef SDHCI_USE_LEDS_CLASS
3012         led_classdev_unregister(&host->led);
3013 #endif
3014
3015         if (!dead)
3016                 sdhci_reset(host, SDHCI_RESET_ALL);
3017
3018         free_irq(host->irq, host);
3019
3020         del_timer_sync(&host->timer);
3021         if (host->version >= SDHCI_SPEC_300)
3022                 del_timer_sync(&host->tuning_timer);
3023
3024         tasklet_kill(&host->card_tasklet);
3025         tasklet_kill(&host->finish_tasklet);
3026
3027         if (host->vmmc)
3028                 regulator_put(host->vmmc);
3029
3030         kfree(host->adma_desc);
3031         kfree(host->align_buffer);
3032
3033         host->adma_desc = NULL;
3034         host->align_buffer = NULL;
3035 }
3036
3037 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3038
3039 void sdhci_free_host(struct sdhci_host *host)
3040 {
3041         mmc_free_host(host->mmc);
3042 }
3043
3044 EXPORT_SYMBOL_GPL(sdhci_free_host);
3045
3046 /*****************************************************************************\
3047  *                                                                           *
3048  * Driver init/exit                                                          *
3049  *                                                                           *
3050 \*****************************************************************************/
3051
3052 static int __init sdhci_drv_init(void)
3053 {
3054         pr_info(DRIVER_NAME
3055                 ": Secure Digital Host Controller Interface driver\n");
3056         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3057
3058         return 0;
3059 }
3060
3061 static void __exit sdhci_drv_exit(void)
3062 {
3063 }
3064
3065 module_init(sdhci_drv_init);
3066 module_exit(sdhci_drv_exit);
3067
3068 module_param(debug_quirks, uint, 0444);
3069 module_param(debug_quirks2, uint, 0444);
3070
3071 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3072 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3073 MODULE_LICENSE("GPL");
3074
3075 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3076 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");