drivers/mmc/host/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   4  *
   5  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   6  *
   7  * Thanks to the following companies for their support:
   8  *
   9  *     - JMicron (hardware and technical support)
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/ktime.h>
  15 #include <linux/highmem.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/slab.h>
  20 #include <linux/scatterlist.h>
  21 #include <linux/sizes.h>
  22 #include <linux/swiotlb.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/of.h>
  26
  27 #include <linux/leds.h>
  28
  29 #include <linux/mmc/mmc.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/card.h>
  32 #include <linux/mmc/sdio.h>
  33 #include <linux/mmc/slot-gpio.h>
  34
  35 #include "sdhci.h"
  36
  37 #define DRIVER_NAME "sdhci"
  38
  39 #define DBG(f, x...) \
  40         pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  41
  42 #define SDHCI_DUMP(f, x...) \
  43         pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  53
  54 void sdhci_dumpregs(struct sdhci_host *host)
  55 {
  56         SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  57
  58         SDHCI_DUMP("Sys addr:  0x%08x | Version:  0x%08x\n",
  59                    sdhci_readl(host, SDHCI_DMA_ADDRESS),
  60                    sdhci_readw(host, SDHCI_HOST_VERSION));
  61         SDHCI_DUMP("Blk size:  0x%08x | Blk cnt:  0x%08x\n",
  62                    sdhci_readw(host, SDHCI_BLOCK_SIZE),
  63                    sdhci_readw(host, SDHCI_BLOCK_COUNT));
  64         SDHCI_DUMP("Argument:  0x%08x | Trn mode: 0x%08x\n",
  65                    sdhci_readl(host, SDHCI_ARGUMENT),
  66                    sdhci_readw(host, SDHCI_TRANSFER_MODE));
  67         SDHCI_DUMP("Present:   0x%08x | Host ctl: 0x%08x\n",
  68                    sdhci_readl(host, SDHCI_PRESENT_STATE),
  69                    sdhci_readb(host, SDHCI_HOST_CONTROL));
  70         SDHCI_DUMP("Power:     0x%08x | Blk gap:  0x%08x\n",
  71                    sdhci_readb(host, SDHCI_POWER_CONTROL),
  72                    sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  73         SDHCI_DUMP("Wake-up:   0x%08x | Clock:    0x%08x\n",
  74                    sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  75                    sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  76         SDHCI_DUMP("Timeout:   0x%08x | Int stat: 0x%08x\n",
  77                    sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  78                    sdhci_readl(host, SDHCI_INT_STATUS));
  79         SDHCI_DUMP("Int enab:  0x%08x | Sig enab: 0x%08x\n",
  80                    sdhci_readl(host, SDHCI_INT_ENABLE),
  81                    sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  82         SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
  83                    sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
  84                    sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  85         SDHCI_DUMP("Caps:      0x%08x | Caps_1:   0x%08x\n",
  86                    sdhci_readl(host, SDHCI_CAPABILITIES),
  87                    sdhci_readl(host, SDHCI_CAPABILITIES_1));
  88         SDHCI_DUMP("Cmd:       0x%08x | Max curr: 0x%08x\n",
  89                    sdhci_readw(host, SDHCI_COMMAND),
  90                    sdhci_readl(host, SDHCI_MAX_CURRENT));
  91         SDHCI_DUMP("Resp[0]:   0x%08x | Resp[1]:  0x%08x\n",
  92                    sdhci_readl(host, SDHCI_RESPONSE),
  93                    sdhci_readl(host, SDHCI_RESPONSE + 4));
  94         SDHCI_DUMP("Resp[2]:   0x%08x | Resp[3]:  0x%08x\n",
  95                    sdhci_readl(host, SDHCI_RESPONSE + 8),
  96                    sdhci_readl(host, SDHCI_RESPONSE + 12));
  97         SDHCI_DUMP("Host ctl2: 0x%08x\n",
  98                    sdhci_readw(host, SDHCI_HOST_CONTROL2));
  99
 100         if (host->flags & SDHCI_USE_ADMA) {
 101                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
 102                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x%08x\n",
 103                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 104                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
 105                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 106                 } else {
 107                         SDHCI_DUMP("ADMA Err:  0x%08x | ADMA Ptr: 0x%08x\n",
 108                                    sdhci_readl(host, SDHCI_ADMA_ERROR),
 109                                    sdhci_readl(host, SDHCI_ADMA_ADDRESS));
 110                 }
 111         }
 112
 113         SDHCI_DUMP("============================================\n");
 114 }
 115 EXPORT_SYMBOL_GPL(sdhci_dumpregs);
 116
 117 /*****************************************************************************\
 118  *                                                                           *
 119  * Low level functions                                                       *
 120  *                                                                           *
 121 \*****************************************************************************/
 122
 123 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
 124 {
 125         u16 ctrl2;
 126
 127         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 128         if (ctrl2 & SDHCI_CTRL_V4_MODE)
 129                 return;
 130
 131         ctrl2 |= SDHCI_CTRL_V4_MODE;
 132         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 133 }
 134
 135 /*
 136  * This can be called before sdhci_add_host() by Vendor's host controller
 137  * driver to enable v4 mode if supported.
 138  */
 139 void sdhci_enable_v4_mode(struct sdhci_host *host)
 140 {
 141         host->v4_mode = true;
 142         sdhci_do_enable_v4_mode(host);
 143 }
 144 EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
 145
 146 static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
 147 {
 148         return cmd->data || cmd->flags & MMC_RSP_BUSY;
 149 }
 150
 151 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 152 {
 153         u32 present;
 154
 155         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 156             !mmc_card_is_removable(host->mmc))
 157                 return;
 158
 159         if (enable) {
 160                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 161                                       SDHCI_CARD_PRESENT;
 162
 163                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 164                                        SDHCI_INT_CARD_INSERT;
 165         } else {
 166                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 167         }
 168
 169         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 170         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 171 }
 172
 173 static void sdhci_enable_card_detection(struct sdhci_host *host)
 174 {
 175         sdhci_set_card_detection(host, true);
 176 }
 177
 178 static void sdhci_disable_card_detection(struct sdhci_host *host)
 179 {
 180         sdhci_set_card_detection(host, false);
 181 }
 182
 183 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
 184 {
 185         if (host->bus_on)
 186                 return;
 187         host->bus_on = true;
 188         pm_runtime_get_noresume(host->mmc->parent);
 189 }
 190
 191 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
 192 {
 193         if (!host->bus_on)
 194                 return;
 195         host->bus_on = false;
 196         pm_runtime_put_noidle(host->mmc->parent);
 197 }
 198
 199 void sdhci_reset(struct sdhci_host *host, u8 mask)
 200 {
 201         ktime_t timeout;
 202
 203         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 204
 205         if (mask & SDHCI_RESET_ALL) {
 206                 host->clock = 0;
 207                 /* Reset-all turns off SD Bus Power */
 208                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 209                         sdhci_runtime_pm_bus_off(host);
 210         }
 211
 212         /* Wait max 100 ms */
 213         timeout = ktime_add_ms(ktime_get(), 100);
 214
 215         /* hw clears the bit when it's done */
 216         while (1) {
 217                 bool timedout = ktime_after(ktime_get(), timeout);
 218
 219                 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
 220                         break;
 221                 if (timedout) {
 222                         pr_err("%s: Reset 0x%x never completed.\n",
 223                                 mmc_hostname(host->mmc), (int)mask);
 224                         sdhci_dumpregs(host);
 225                         return;
 226                 }
 227                 udelay(10);
 228         }
 229 }
 230 EXPORT_SYMBOL_GPL(sdhci_reset);
 231
 232 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 233 {
 234         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 235                 struct mmc_host *mmc = host->mmc;
 236
 237                 if (!mmc->ops->get_cd(mmc))
 238                         return;
 239         }
 240
 241         host->ops->reset(host, mask);
 242
 243         if (mask & SDHCI_RESET_ALL) {
 244                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 245                         if (host->ops->enable_dma)
 246                                 host->ops->enable_dma(host);
 247                 }
 248
 249                 /* Resetting the controller clears many */
 250                 host->preset_enabled = false;
 251         }
 252 }
 253
 254 static void sdhci_set_default_irqs(struct sdhci_host *host)
 255 {
 256         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 257                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 258                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 259                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 260                     SDHCI_INT_RESPONSE;
 261
 262         if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
 263             host->tuning_mode == SDHCI_TUNING_MODE_3)
 264                 host->ier |= SDHCI_INT_RETUNE;
 265
 266         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 267         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 268 }
 269
 270 static void sdhci_config_dma(struct sdhci_host *host)
 271 {
 272         u8 ctrl;
 273         u16 ctrl2;
 274
 275         if (host->version < SDHCI_SPEC_200)
 276                 return;
 277
 278         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 279
 280         /*
 281          * Always adjust the DMA selection as some controllers
 282          * (e.g. JMicron) can't do PIO properly when the selection
 283          * is ADMA.
 284          */
 285         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 286         if (!(host->flags & SDHCI_REQ_USE_DMA))
 287                 goto out;
 288
 289         /* Note if DMA Select is zero then SDMA is selected */
 290         if (host->flags & SDHCI_USE_ADMA)
 291                 ctrl |= SDHCI_CTRL_ADMA32;
 292
 293         if (host->flags & SDHCI_USE_64_BIT_DMA) {
 294                 /*
 295                  * If v4 mode, all supported DMA can be 64-bit addressing if
 296                  * controller supports 64-bit system address, otherwise only
 297                  * ADMA can support 64-bit addressing.
 298                  */
 299                 if (host->v4_mode) {
 300                         ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 301                         ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
 302                         sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
 303                 } else if (host->flags & SDHCI_USE_ADMA) {
 304                         /*
 305                          * Don't need to undo SDHCI_CTRL_ADMA32 in order to
 306                          * set SDHCI_CTRL_ADMA64.
 307                          */
 308                         ctrl |= SDHCI_CTRL_ADMA64;
 309                 }
 310         }
 311
 312 out:
 313         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 314 }
 315
 316 static void sdhci_init(struct sdhci_host *host, int soft)
 317 {
 318         struct mmc_host *mmc = host->mmc;
 319
 320         if (soft)
 321                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 322         else
 323                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 324
 325         if (host->v4_mode)
 326                 sdhci_do_enable_v4_mode(host);
 327
 328         sdhci_set_default_irqs(host);
 329
 330         host->cqe_on = false;
 331
 332         if (soft) {
 333                 /* force clock reconfiguration */
 334                 host->clock = 0;
 335                 mmc->ops->set_ios(mmc, &mmc->ios);
 336         }
 337 }
 338
 339 static void sdhci_reinit(struct sdhci_host *host)
 340 {
 341         u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 342
 343         sdhci_init(host, 0);
 344         sdhci_enable_card_detection(host);
 345
 346         /*
 347          * A change to the card detect bits indicates a change in present state,
 348          * refer sdhci_set_card_detection(). A card detect interrupt might have
 349          * been missed while the host controller was being reset, so trigger a
 350          * rescan to check.
 351          */
 352         if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
 353                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
 354 }
 355
 356 static void __sdhci_led_activate(struct sdhci_host *host)
 357 {
 358         u8 ctrl;
 359
 360         if (host->quirks & SDHCI_QUIRK_NO_LED)
 361                 return;
 362
 363         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 364         ctrl |= SDHCI_CTRL_LED;
 365         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 366 }
 367
 368 static void __sdhci_led_deactivate(struct sdhci_host *host)
 369 {
 370         u8 ctrl;
 371
 372         if (host->quirks & SDHCI_QUIRK_NO_LED)
 373                 return;
 374
 375         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 376         ctrl &= ~SDHCI_CTRL_LED;
 377         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 378 }
 379
 380 #if IS_REACHABLE(CONFIG_LEDS_CLASS)
 381 static void sdhci_led_control(struct led_classdev *led,
 382                               enum led_brightness brightness)
 383 {
 384         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 385         unsigned long flags;
 386
 387         spin_lock_irqsave(&host->lock, flags);
 388
 389         if (host->runtime_suspended)
 390                 goto out;
 391
 392         if (brightness == LED_OFF)
 393                 __sdhci_led_deactivate(host);
 394         else
 395                 __sdhci_led_activate(host);
 396 out:
 397         spin_unlock_irqrestore(&host->lock, flags);
 398 }
 399
 400 static int sdhci_led_register(struct sdhci_host *host)
 401 {
 402         struct mmc_host *mmc = host->mmc;
 403
 404         if (host->quirks & SDHCI_QUIRK_NO_LED)
 405                 return 0;
 406
 407         snprintf(host->led_name, sizeof(host->led_name),
 408                  "%s::", mmc_hostname(mmc));
 409
 410         host->led.name = host->led_name;
 411         host->led.brightness = LED_OFF;
 412         host->led.default_trigger = mmc_hostname(mmc);
 413         host->led.brightness_set = sdhci_led_control;
 414
 415         return led_classdev_register(mmc_dev(mmc), &host->led);
 416 }
 417
 418 static void sdhci_led_unregister(struct sdhci_host *host)
 419 {
 420         if (host->quirks & SDHCI_QUIRK_NO_LED)
 421                 return;
 422
 423         led_classdev_unregister(&host->led);
 424 }
 425
 426 static inline void sdhci_led_activate(struct sdhci_host *host)
 427 {
 428 }
 429
 430 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 431 {
 432 }
 433
 434 #else
 435
 436 static inline int sdhci_led_register(struct sdhci_host *host)
 437 {
 438         return 0;
 439 }
 440
 441 static inline void sdhci_led_unregister(struct sdhci_host *host)
 442 {
 443 }
 444
 445 static inline void sdhci_led_activate(struct sdhci_host *host)
 446 {
 447         __sdhci_led_activate(host);
 448 }
 449
 450 static inline void sdhci_led_deactivate(struct sdhci_host *host)
 451 {
 452         __sdhci_led_deactivate(host);
 453 }
 454
 455 #endif
 456
 457 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
 458                             unsigned long timeout)
 459 {
 460         if (sdhci_data_line_cmd(mrq->cmd))
 461                 mod_timer(&host->data_timer, timeout);
 462         else
 463                 mod_timer(&host->timer, timeout);
 464 }
 465
 466 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
 467 {
 468         if (sdhci_data_line_cmd(mrq->cmd))
 469                 del_timer(&host->data_timer);
 470         else
 471                 del_timer(&host->timer);
 472 }
 473
 474 static inline bool sdhci_has_requests(struct sdhci_host *host)
 475 {
 476         return host->cmd || host->data_cmd;
 477 }
 478
 479 /*****************************************************************************\
 480  *                                                                           *
 481  * Core functions                                                            *
 482  *                                                                           *
 483 \*****************************************************************************/
 484
 485 static void sdhci_read_block_pio(struct sdhci_host *host)
 486 {
 487         unsigned long flags;
 488         size_t blksize, len, chunk;
 489         u32 uninitialized_var(scratch);
 490         u8 *buf;
 491
 492         DBG("PIO reading\n");
 493
 494         blksize = host->data->blksz;
 495         chunk = 0;
 496
 497         local_irq_save(flags);
 498
 499         while (blksize) {
 500                 BUG_ON(!sg_miter_next(&host->sg_miter));
 501
 502                 len = min(host->sg_miter.length, blksize);
 503
 504                 blksize -= len;
 505                 host->sg_miter.consumed = len;
 506
 507                 buf = host->sg_miter.addr;
 508
 509                 while (len) {
 510                         if (chunk == 0) {
 511                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 512                                 chunk = 4;
 513                         }
 514
 515                         *buf = scratch & 0xFF;
 516
 517                         buf++;
 518                         scratch >>= 8;
 519                         chunk--;
 520                         len--;
 521                 }
 522         }
 523
 524         sg_miter_stop(&host->sg_miter);
 525
 526         local_irq_restore(flags);
 527 }
 528
 529 static void sdhci_write_block_pio(struct sdhci_host *host)
 530 {
 531         unsigned long flags;
 532         size_t blksize, len, chunk;
 533         u32 scratch;
 534         u8 *buf;
 535
 536         DBG("PIO writing\n");
 537
 538         blksize = host->data->blksz;
 539         chunk = 0;
 540         scratch = 0;
 541
 542         local_irq_save(flags);
 543
 544         while (blksize) {
 545                 BUG_ON(!sg_miter_next(&host->sg_miter));
 546
 547                 len = min(host->sg_miter.length, blksize);
 548
 549                 blksize -= len;
 550                 host->sg_miter.consumed = len;
 551
 552                 buf = host->sg_miter.addr;
 553
 554                 while (len) {
 555                         scratch |= (u32)*buf << (chunk * 8);
 556
 557                         buf++;
 558                         chunk++;
 559                         len--;
 560
 561                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 562                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 563                                 chunk = 0;
 564                                 scratch = 0;
 565                         }
 566                 }
 567         }
 568
 569         sg_miter_stop(&host->sg_miter);
 570
 571         local_irq_restore(flags);
 572 }
 573
 574 static void sdhci_transfer_pio(struct sdhci_host *host)
 575 {
 576         u32 mask;
 577
 578         if (host->blocks == 0)
 579                 return;
 580
 581         if (host->data->flags & MMC_DATA_READ)
 582                 mask = SDHCI_DATA_AVAILABLE;
 583         else
 584                 mask = SDHCI_SPACE_AVAILABLE;
 585
 586         /*
 587          * Some controllers (JMicron JMB38x) mess up the buffer bits
 588          * for transfers < 4 bytes. As long as it is just one block,
 589          * we can ignore the bits.
 590          */
 591         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 592                 (host->data->blocks == 1))
 593                 mask = ~0;
 594
 595         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 596                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 597                         udelay(100);
 598
 599                 if (host->data->flags & MMC_DATA_READ)
 600                         sdhci_read_block_pio(host);
 601                 else
 602                         sdhci_write_block_pio(host);
 603
 604                 host->blocks--;
 605                 if (host->blocks == 0)
 606                         break;
 607         }
 608
 609         DBG("PIO transfer complete.\n");
 610 }
 611
 612 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 613                                   struct mmc_data *data, int cookie)
 614 {
 615         int sg_count;
 616
 617         /*
 618          * If the data buffers are already mapped, return the previous
 619          * dma_map_sg() result.
 620          */
 621         if (data->host_cookie == COOKIE_PRE_MAPPED)
 622                 return data->sg_count;
 623
 624         /* Bounce write requests to the bounce buffer */
 625         if (host->bounce_buffer) {
 626                 unsigned int length = data->blksz * data->blocks;
 627
 628                 if (length > host->bounce_buffer_size) {
 629                         pr_err("%s: asked for transfer of %u bytes exceeds bounce buffer %u bytes\n",
 630                                mmc_hostname(host->mmc), length,
 631                                host->bounce_buffer_size);
 632                         return -EIO;
 633                 }
 634                 if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
 635                         /* Copy the data to the bounce buffer */
 636                         sg_copy_to_buffer(data->sg, data->sg_len,
 637                                           host->bounce_buffer,
 638                                           length);
 639                 }
 640                 /* Switch ownership to the DMA */
 641                 dma_sync_single_for_device(host->mmc->parent,
 642                                            host->bounce_addr,
 643                                            host->bounce_buffer_size,
 644                                            mmc_get_dma_dir(data));
 645                 /* Just a dummy value */
 646                 sg_count = 1;
 647         } else {
 648                 /* Just access the data directly from memory */
 649                 sg_count = dma_map_sg(mmc_dev(host->mmc),
 650                                       data->sg, data->sg_len,
 651                                       mmc_get_dma_dir(data));
 652         }
 653
 654         if (sg_count == 0)
 655                 return -ENOSPC;
 656
 657         data->sg_count = sg_count;
 658         data->host_cookie = cookie;
 659
 660         return sg_count;
 661 }
 662
 663 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 664 {
 665         local_irq_save(*flags);
 666         return kmap_atomic(sg_page(sg)) + sg->offset;
 667 }
 668
 669 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 670 {
 671         kunmap_atomic(buffer);
 672         local_irq_restore(*flags);
 673 }
 674
 675 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
 676                            dma_addr_t addr, int len, unsigned int cmd)
 677 {
 678         struct sdhci_adma2_64_desc *dma_desc = *desc;
 679
 680         /* 32-bit and 64-bit descriptors have these members in same position */
 681         dma_desc->cmd = cpu_to_le16(cmd);
 682         dma_desc->len = cpu_to_le16(len);
 683         dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
 684
 685         if (host->flags & SDHCI_USE_64_BIT_DMA)
 686                 dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
 687
 688         *desc += host->desc_sz;
 689 }
 690 EXPORT_SYMBOL_GPL(sdhci_adma_write_desc);
 691
 692 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
 693                                            void **desc, dma_addr_t addr,
 694                                            int len, unsigned int cmd)
 695 {
 696         if (host->ops->adma_write_desc)
 697                 host->ops->adma_write_desc(host, desc, addr, len, cmd);
 698         else
 699                 sdhci_adma_write_desc(host, desc, addr, len, cmd);
 700 }
 701
 702 static void sdhci_adma_mark_end(void *desc)
 703 {
 704         struct sdhci_adma2_64_desc *dma_desc = desc;
 705
 706         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 707         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 708 }
 709
 710 static void sdhci_adma_table_pre(struct sdhci_host *host,
 711         struct mmc_data *data, int sg_count)
 712 {
 713         struct scatterlist *sg;
 714         unsigned long flags;
 715         dma_addr_t addr, align_addr;
 716         void *desc, *align;
 717         char *buffer;
 718         int len, offset, i;
 719
 720         /*
 721          * The spec does not specify endianness of descriptor table.
 722          * We currently guess that it is LE.
 723          */
 724
 725         host->sg_count = sg_count;
 726
 727         desc = host->adma_table;
 728         align = host->align_buffer;
 729
 730         align_addr = host->align_addr;
 731
 732         for_each_sg(data->sg, sg, host->sg_count, i) {
 733                 addr = sg_dma_address(sg);
 734                 len = sg_dma_len(sg);
 735
 736                 /*
 737                  * The SDHCI specification states that ADMA addresses must
 738                  * be 32-bit aligned. If they aren't, then we use a bounce
 739                  * buffer for the (up to three) bytes that screw up the
 740                  * alignment.
 741                  */
 742                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 743                          SDHCI_ADMA2_MASK;
 744                 if (offset) {
 745                         if (data->flags & MMC_DATA_WRITE) {
 746                                 buffer = sdhci_kmap_atomic(sg, &flags);
 747                                 memcpy(align, buffer, offset);
 748                                 sdhci_kunmap_atomic(buffer, &flags);
 749                         }
 750
 751                         /* tran, valid */
 752                         __sdhci_adma_write_desc(host, &desc, align_addr,
 753                                                 offset, ADMA2_TRAN_VALID);
 754
 755                         BUG_ON(offset > 65536);
 756
 757                         align += SDHCI_ADMA2_ALIGN;
 758                         align_addr += SDHCI_ADMA2_ALIGN;
 759
 760                         addr += offset;
 761                         len -= offset;
 762                 }
 763
 764                 BUG_ON(len > 65536);
 765
 766                 /* tran, valid */
 767                 if (len)
 768                         __sdhci_adma_write_desc(host, &desc, addr, len,
 769                                                 ADMA2_TRAN_VALID);
 770
 771                 /*
 772                  * If this triggers then we have a calculation bug
 773                  * somewhere. :/
 774                  */
 775                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 776         }
 777
 778         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 779                 /* Mark the last descriptor as the terminating descriptor */
 780                 if (desc != host->adma_table) {
 781                         desc -= host->desc_sz;
 782                         sdhci_adma_mark_end(desc);
 783                 }
 784         } else {
 785                 /* Add a terminating entry - nop, end, valid */
 786                 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
 787         }
 788 }
 789
 790 static void sdhci_adma_table_post(struct sdhci_host *host,
 791         struct mmc_data *data)
 792 {
 793         struct scatterlist *sg;
 794         int i, size;
 795         void *align;
 796         char *buffer;
 797         unsigned long flags;
 798
 799         if (data->flags & MMC_DATA_READ) {
 800                 bool has_unaligned = false;
 801
 802                 /* Do a quick scan of the SG list for any unaligned mappings */
 803                 for_each_sg(data->sg, sg, host->sg_count, i)
 804                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 805                                 has_unaligned = true;
 806                                 break;
 807                         }
 808
 809                 if (has_unaligned) {
 810                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 811                                             data->sg_len, DMA_FROM_DEVICE);
 812
 813                         align = host->align_buffer;
 814
 815                         for_each_sg(data->sg, sg, host->sg_count, i) {
 816                                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 817                                         size = SDHCI_ADMA2_ALIGN -
 818                                                (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 819
 820                                         buffer = sdhci_kmap_atomic(sg, &flags);
 821                                         memcpy(buffer, align, size);
 822                                         sdhci_kunmap_atomic(buffer, &flags);
 823
 824                                         align += SDHCI_ADMA2_ALIGN;
 825                                 }
 826                         }
 827                 }
 828         }
 829 }
 830
 831 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
 832 {
 833         sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
 834         if (host->flags & SDHCI_USE_64_BIT_DMA)
 835                 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
 836 }
 837
 838 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
 839 {
 840         if (host->bounce_buffer)
 841                 return host->bounce_addr;
 842         else
 843                 return sg_dma_address(host->data->sg);
 844 }
 845
 846 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
 847 {
 848         if (host->v4_mode)
 849                 sdhci_set_adma_addr(host, addr);
 850         else
 851                 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
 852 }
 853
 854 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
 855                                          struct mmc_command *cmd,
 856                                          struct mmc_data *data)
 857 {
 858         unsigned int target_timeout;
 859
 860         /* timeout in us */
 861         if (!data) {
 862                 target_timeout = cmd->busy_timeout * 1000;
 863         } else {
 864                 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
 865                 if (host->clock && data->timeout_clks) {
 866                         unsigned long long val;
 867
 868                         /*
 869                          * data->timeout_clks is in units of clock cycles.
 870                          * host->clock is in Hz.  target_timeout is in us.
 871                          * Hence, us = 1000000 * cycles / Hz.  Round up.
 872                          */
 873                         val = 1000000ULL * data->timeout_clks;
 874                         if (do_div(val, host->clock))
 875                                 target_timeout++;
 876                         target_timeout += val;
 877                 }
 878         }
 879
 880         return target_timeout;
 881 }
 882
 883 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
 884                                   struct mmc_command *cmd)
 885 {
 886         struct mmc_data *data = cmd->data;
 887         struct mmc_host *mmc = host->mmc;
 888         struct mmc_ios *ios = &mmc->ios;
 889         unsigned char bus_width = 1 << ios->bus_width;
 890         unsigned int blksz;
 891         unsigned int freq;
 892         u64 target_timeout;
 893         u64 transfer_time;
 894
 895         target_timeout = sdhci_target_timeout(host, cmd, data);
 896         target_timeout *= NSEC_PER_USEC;
 897
 898         if (data) {
 899                 blksz = data->blksz;
 900                 freq = host->mmc->actual_clock ? : host->clock;
 901                 transfer_time = (u64)blksz * NSEC_PER_SEC * (8 / bus_width);
 902                 do_div(transfer_time, freq);
 903                 /* multiply by '2' to account for any unknowns */
 904                 transfer_time = transfer_time * 2;
 905                 /* calculate timeout for the entire data */
 906                 host->data_timeout = data->blocks * target_timeout +
 907                                      transfer_time;
 908         } else {
 909                 host->data_timeout = target_timeout;
 910         }
 911
 912         if (host->data_timeout)
 913                 host->data_timeout += MMC_CMD_TRANSFER_TIME;
 914 }
 915
 916 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
 917                              bool *too_big)
 918 {
 919         u8 count;
 920         struct mmc_data *data;
 921         unsigned target_timeout, current_timeout;
 922
 923         *too_big = true;
 924
 925         /*
 926          * If the host controller provides us with an incorrect timeout
 927          * value, just skip the check and use 0xE.  The hardware may take
 928          * longer to time out, but that's much better than having a too-short
 929          * timeout value.
 930          */
 931         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 932                 return 0xE;
 933
 934         /* Unspecified command, asume max */
 935         if (cmd == NULL)
 936                 return 0xE;
 937
 938         data = cmd->data;
 939         /* Unspecified timeout, assume max */
 940         if (!data && !cmd->busy_timeout)
 941                 return 0xE;
 942
 943         /* timeout in us */
 944         target_timeout = sdhci_target_timeout(host, cmd, data);
 945
 946         /*
 947          * Figure out needed cycles.
 948          * We do this in steps in order to fit inside a 32 bit int.
 949          * The first step is the minimum timeout, which will have a
 950          * minimum resolution of 6 bits:
 951          * (1) 2^13*1000 > 2^22,
 952          * (2) host->timeout_clk < 2^16
 953          *     =>
 954          *     (1) / (2) > 2^6
 955          */
 956         count = 0;
 957         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 958         while (current_timeout < target_timeout) {
 959                 count++;
 960                 current_timeout <<= 1;
 961                 if (count >= 0xF)
 962                         break;
 963         }
 964
 965         if (count >= 0xF) {
 966                 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
 967                         DBG("Too large timeout 0x%x requested for CMD%d!\n",
 968                             count, cmd->opcode);
 969                 count = 0xE;
 970         } else {
 971                 *too_big = false;
 972         }
 973
 974         return count;
 975 }
 976
 977 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 978 {
 979         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 980         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 981
 982         if (host->flags & SDHCI_REQ_USE_DMA)
 983                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 984         else
 985                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 986
 987         if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
 988                 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
 989         else
 990                 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
 991
 992         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 993         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 994 }
 995
 996 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
 997 {
 998         if (enable)
 999                 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1000         else
1001                 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1002         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1003         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1004 }
1005 EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
1006
1007 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1008 {
1009         bool too_big = false;
1010         u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1011
1012         if (too_big &&
1013             host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1014                 sdhci_calc_sw_timeout(host, cmd);
1015                 sdhci_set_data_timeout_irq(host, false);
1016         } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1017                 sdhci_set_data_timeout_irq(host, true);
1018         }
1019
1020         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1021 }
1022 EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
1023
1024 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1025 {
1026         if (host->ops->set_timeout)
1027                 host->ops->set_timeout(host, cmd);
1028         else
1029                 __sdhci_set_timeout(host, cmd);
1030 }
1031
1032 static void sdhci_initialize_data(struct sdhci_host *host,
1033                                   struct mmc_data *data)
1034 {
1035         WARN_ON(host->data);
1036
1037         /* Sanity checks */
1038         BUG_ON(data->blksz * data->blocks > 524288);
1039         BUG_ON(data->blksz > host->mmc->max_blk_size);
1040         BUG_ON(data->blocks > 65535);
1041
1042         host->data = data;
1043         host->data_early = 0;
1044         host->data->bytes_xfered = 0;
1045 }
1046
1047 static inline void sdhci_set_block_info(struct sdhci_host *host,
1048                                         struct mmc_data *data)
1049 {
1050         /* Set the DMA boundary value and block size */
1051         sdhci_writew(host,
1052                      SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1053                      SDHCI_BLOCK_SIZE);
1054         /*
1055          * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
1056          * can be supported, in that case 16-bit block count register must be 0.
1057          */
1058         if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1059             (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1060                 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1061                         sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1062                 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1063         } else {
1064                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1065         }
1066 }
1067
1068 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1069 {
1070         struct mmc_data *data = cmd->data;
1071
1072         sdhci_initialize_data(host, data);
1073
1074         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1075                 struct scatterlist *sg;
1076                 unsigned int length_mask, offset_mask;
1077                 int i;
1078
1079                 host->flags |= SDHCI_REQ_USE_DMA;
1080
1081                 /*
1082                  * FIXME: This doesn't account for merging when mapping the
1083                  * scatterlist.
1084                  *
1085                  * The assumption here being that alignment and lengths are
1086                  * the same after DMA mapping to device address space.
1087                  */
1088                 length_mask = 0;
1089                 offset_mask = 0;
1090                 if (host->flags & SDHCI_USE_ADMA) {
1091                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1092                                 length_mask = 3;
1093                                 /*
1094                                  * As we use up to 3 byte chunks to work
1095                                  * around alignment problems, we need to
1096                                  * check the offset as well.
1097                                  */
1098                                 offset_mask = 3;
1099                         }
1100                 } else {
1101                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1102                                 length_mask = 3;
1103                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1104                                 offset_mask = 3;
1105                 }
1106
1107                 if (unlikely(length_mask | offset_mask)) {
1108                         for_each_sg(data->sg, sg, data->sg_len, i) {
1109                                 if (sg->length & length_mask) {
1110                                         DBG("Reverting to PIO because of transfer size (%d)\n",
1111                                             sg->length);
1112                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1113                                         break;
1114                                 }
1115                                 if (sg->offset & offset_mask) {
1116                                         DBG("Reverting to PIO because of bad alignment\n");
1117                                         host->flags &= ~SDHCI_REQ_USE_DMA;
1118                                         break;
1119                                 }
1120                         }
1121                 }
1122         }
1123
1124         if (host->flags & SDHCI_REQ_USE_DMA) {
1125                 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1126
1127                 if (sg_cnt <= 0) {
1128                         /*
1129                          * This only happens when someone fed
1130                          * us an invalid request.
1131                          */
1132                         WARN_ON(1);
1133                         host->flags &= ~SDHCI_REQ_USE_DMA;
1134                 } else if (host->flags & SDHCI_USE_ADMA) {
1135                         sdhci_adma_table_pre(host, data, sg_cnt);
1136                         sdhci_set_adma_addr(host, host->adma_addr);
1137                 } else {
1138                         WARN_ON(sg_cnt != 1);
1139                         sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1140                 }
1141         }
1142
1143         sdhci_config_dma(host);
1144
1145         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1146                 int flags;
1147
1148                 flags = SG_MITER_ATOMIC;
1149                 if (host->data->flags & MMC_DATA_READ)
1150                         flags |= SG_MITER_TO_SG;
1151                 else
1152                         flags |= SG_MITER_FROM_SG;
1153                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1154                 host->blocks = data->blocks;
1155         }
1156
1157         sdhci_set_transfer_irqs(host);
1158
1159         sdhci_set_block_info(host, data);
1160 }
1161
1162 #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
1163
1164 static int sdhci_external_dma_init(struct sdhci_host *host)
1165 {
1166         int ret = 0;
1167         struct mmc_host *mmc = host->mmc;
1168
1169         host->tx_chan = dma_request_chan(mmc->parent, "tx");
1170         if (IS_ERR(host->tx_chan)) {
1171                 ret = PTR_ERR(host->tx_chan);
1172                 if (ret != -EPROBE_DEFER)
1173                         pr_warn("Failed to request TX DMA channel.\n");
1174                 host->tx_chan = NULL;
1175                 return ret;
1176         }
1177
1178         host->rx_chan = dma_request_chan(mmc->parent, "rx");
1179         if (IS_ERR(host->rx_chan)) {
1180                 if (host->tx_chan) {
1181                         dma_release_channel(host->tx_chan);
1182                         host->tx_chan = NULL;
1183                 }
1184
1185                 ret = PTR_ERR(host->rx_chan);
1186                 if (ret != -EPROBE_DEFER)
1187                         pr_warn("Failed to request RX DMA channel.\n");
1188                 host->rx_chan = NULL;
1189         }
1190
1191         return ret;
1192 }
1193
1194 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1195                                                    struct mmc_data *data)
1196 {
1197         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1198 }
1199
1200 static int sdhci_external_dma_setup(struct sdhci_host *host,
1201                                     struct mmc_command *cmd)
1202 {
1203         int ret, i;
1204         struct dma_async_tx_descriptor *desc;
1205         struct mmc_data *data = cmd->data;
1206         struct dma_chan *chan;
1207         struct dma_slave_config cfg;
1208         dma_cookie_t cookie;
1209         int sg_cnt;
1210
1211         if (!host->mapbase)
1212                 return -EINVAL;
1213
1214         cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1215         cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1216         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1217         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1218         cfg.src_maxburst = data->blksz / 4;
1219         cfg.dst_maxburst = data->blksz / 4;
1220
1221         /* Sanity check: all the SG entries must be aligned by block size. */
1222         for (i = 0; i < data->sg_len; i++) {
1223                 if ((data->sg + i)->length % data->blksz)
1224                         return -EINVAL;
1225         }
1226
1227         chan = sdhci_external_dma_channel(host, data);
1228
1229         ret = dmaengine_slave_config(chan, &cfg);
1230         if (ret)
1231                 return ret;
1232
1233         sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1234         if (sg_cnt <= 0)
1235                 return -EINVAL;
1236
1237         desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1238                                        mmc_get_dma_dir(data),
1239                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1240         if (!desc)
1241                 return -EINVAL;
1242
1243         desc->callback = NULL;
1244         desc->callback_param = NULL;
1245
1246         cookie = dmaengine_submit(desc);
1247         if (dma_submit_error(cookie))
1248                 ret = cookie;
1249
1250         return ret;
1251 }
1252
1253 static void sdhci_external_dma_release(struct sdhci_host *host)
1254 {
1255         if (host->tx_chan) {
1256                 dma_release_channel(host->tx_chan);
1257                 host->tx_chan = NULL;
1258         }
1259
1260         if (host->rx_chan) {
1261                 dma_release_channel(host->rx_chan);
1262                 host->rx_chan = NULL;
1263         }
1264
1265         sdhci_switch_external_dma(host, false);
1266 }
1267
1268 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1269                                               struct mmc_command *cmd)
1270 {
1271         struct mmc_data *data = cmd->data;
1272
1273         sdhci_initialize_data(host, data);
1274
1275         host->flags |= SDHCI_REQ_USE_DMA;
1276         sdhci_set_transfer_irqs(host);
1277
1278         sdhci_set_block_info(host, data);
1279 }
1280
1281 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1282                                             struct mmc_command *cmd)
1283 {
1284         if (!sdhci_external_dma_setup(host, cmd)) {
1285                 __sdhci_external_dma_prepare_data(host, cmd);
1286         } else {
1287                 sdhci_external_dma_release(host);
1288                 pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
1289                        mmc_hostname(host->mmc));
1290                 sdhci_prepare_data(host, cmd);
1291         }
1292 }
1293
1294 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1295                                             struct mmc_command *cmd)
1296 {
1297         struct dma_chan *chan;
1298
1299         if (!cmd->data)
1300                 return;
1301
1302         chan = sdhci_external_dma_channel(host, cmd->data);
1303         if (chan)
1304                 dma_async_issue_pending(chan);
1305 }
1306
1307 #else
1308
1309 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1310 {
1311         return -EOPNOTSUPP;
1312 }
1313
1314 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1315 {
1316 }
1317
1318 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1319                                                    struct mmc_command *cmd)
1320 {
1321         /* This should never happen */
1322         WARN_ON_ONCE(1);
1323 }
1324
1325 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1326                                                    struct mmc_command *cmd)
1327 {
1328 }
1329
1330 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1331                                                           struct mmc_data *data)
1332 {
1333         return NULL;
1334 }
1335
1336 #endif
1337
1338 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1339 {
1340         host->use_external_dma = en;
1341 }
1342 EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1343
1344 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1345                                     struct mmc_request *mrq)
1346 {
1347         return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1348                !mrq->cap_cmd_during_tfr;
1349 }
1350
1351 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1352                                          struct mmc_command *cmd,
1353                                          u16 *mode)
1354 {
1355         bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1356                          (cmd->opcode != SD_IO_RW_EXTENDED);
1357         bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1358         u16 ctrl2;
1359
1360         /*
1361          * In case of Version 4.10 or later, use of 'Auto CMD Auto
1362          * Select' is recommended rather than use of 'Auto CMD12
1363          * Enable' or 'Auto CMD23 Enable'.
1364          */
1365         if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) {
1366                 *mode |= SDHCI_TRNS_AUTO_SEL;
1367
1368                 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1369                 if (use_cmd23)
1370                         ctrl2 |= SDHCI_CMD23_ENABLE;
1371                 else
1372                         ctrl2 &= ~SDHCI_CMD23_ENABLE;
1373                 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1374
1375                 return;
1376         }
1377
1378         /*
1379          * If we are sending CMD23, CMD12 never gets sent
1380          * on successful completion (so no Auto-CMD12).
1381          */
1382         if (use_cmd12)
1383                 *mode |= SDHCI_TRNS_AUTO_CMD12;
1384         else if (use_cmd23)
1385                 *mode |= SDHCI_TRNS_AUTO_CMD23;
1386 }
1387
1388 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1389         struct mmc_command *cmd)
1390 {
1391         u16 mode = 0;
1392         struct mmc_data *data = cmd->data;
1393
1394         if (data == NULL) {
1395                 if (host->quirks2 &
1396                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
1397                         /* must not clear SDHCI_TRANSFER_MODE when tuning */
1398                         if (cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1399                                 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1400                 } else {
1401                 /* clear Auto CMD settings for no data CMDs */
1402                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1403                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1404                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
1405                 }
1406                 return;
1407         }
1408
1409         WARN_ON(!host->data);
1410
1411         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1412                 mode = SDHCI_TRNS_BLK_CNT_EN;
1413
1414         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
1415                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
1416                 sdhci_auto_cmd_select(host, cmd, &mode);
1417                 if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
1418                         sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1419         }
1420
1421         if (data->flags & MMC_DATA_READ)
1422                 mode |= SDHCI_TRNS_READ;
1423         if (host->flags & SDHCI_REQ_USE_DMA)
1424                 mode |= SDHCI_TRNS_DMA;
1425
1426         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1427 }
1428
1429 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1430 {
1431         return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1432                 ((mrq->cmd && mrq->cmd->error) ||
1433                  (mrq->sbc && mrq->sbc->error) ||
1434                  (mrq->data && mrq->data->stop && mrq->data->stop->error) ||
1435                  (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1436 }
1437
1438 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1439 {
1440         int i;
1441
1442         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1443                 if (host->mrqs_done[i] == mrq) {
1444                         WARN_ON(1);
1445                         return;
1446                 }
1447         }
1448
1449         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
1450                 if (!host->mrqs_done[i]) {
1451                         host->mrqs_done[i] = mrq;
1452                         break;
1453                 }
1454         }
1455
1456         WARN_ON(i >= SDHCI_MAX_MRQS);
1457 }
1458
1459 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1460 {
1461         if (host->cmd && host->cmd->mrq == mrq)
1462                 host->cmd = NULL;
1463
1464         if (host->data_cmd && host->data_cmd->mrq == mrq)
1465                 host->data_cmd = NULL;
1466
1467         if (host->data && host->data->mrq == mrq)
1468                 host->data = NULL;
1469
1470         if (sdhci_needs_reset(host, mrq))
1471                 host->pending_reset = true;
1472
1473         sdhci_set_mrq_done(host, mrq);
1474
1475         sdhci_del_timer(host, mrq);
1476
1477         if (!sdhci_has_requests(host))
1478                 sdhci_led_deactivate(host);
1479 }
1480
1481 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1482 {
1483         __sdhci_finish_mrq(host, mrq);
1484
1485         queue_work(host->complete_wq, &host->complete_work);
1486 }
1487
1488 static void sdhci_finish_data(struct sdhci_host *host)
1489 {
1490         struct mmc_command *data_cmd = host->data_cmd;
1491         struct mmc_data *data = host->data;
1492
1493         host->data = NULL;
1494         host->data_cmd = NULL;
1495
1496         /*
1497          * The controller needs a reset of internal state machines upon error
1498          * conditions.
1499          */
1500         if (data->error) {
1501                 if (!host->cmd || host->cmd == data_cmd)
1502                         sdhci_do_reset(host, SDHCI_RESET_CMD);
1503                 sdhci_do_reset(host, SDHCI_RESET_DATA);
1504         }
1505
1506         if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1507             (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1508                 sdhci_adma_table_post(host, data);
1509
1510         /*
1511          * The specification states that the block count register must
1512          * be updated, but it does not specify at what point in the
1513          * data flow. That makes the register entirely useless to read
1514          * back so we have to assume that nothing made it to the card
1515          * in the event of an error.
1516          */
1517         if (data->error)
1518                 data->bytes_xfered = 0;
1519         else
1520                 data->bytes_xfered = data->blksz * data->blocks;
1521
1522         /*
1523          * Need to send CMD12 if -
1524          * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1525          * b) error in multiblock transfer
1526          */
1527         if (data->stop &&
1528             ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1529              data->error)) {
1530                 /*
1531                  * 'cap_cmd_during_tfr' request must not use the command line
1532                  * after mmc_command_done() has been called. It is upper layer's
1533                  * responsibility to send the stop command if required.
1534                  */
1535                 if (data->mrq->cap_cmd_during_tfr) {
1536                         __sdhci_finish_mrq(host, data->mrq);
1537                 } else {
1538                         /* Avoid triggering warning in sdhci_send_command() */
1539                         host->cmd = NULL;
1540                         sdhci_send_command(host, data->stop);
1541                 }
1542         } else {
1543                 __sdhci_finish_mrq(host, data->mrq);
1544         }
1545 }
1546
1547 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1548 {
1549         int flags;
1550         u32 mask;
1551         unsigned long timeout;
1552
1553         WARN_ON(host->cmd);
1554
1555         /* Initially, a command has no error */
1556         cmd->error = 0;
1557
1558         if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1559             cmd->opcode == MMC_STOP_TRANSMISSION)
1560                 cmd->flags |= MMC_RSP_BUSY;
1561
1562         /* Wait max 10 ms */
1563         timeout = 10;
1564
1565         mask = SDHCI_CMD_INHIBIT;
1566         if (sdhci_data_line_cmd(cmd))
1567                 mask |= SDHCI_DATA_INHIBIT;
1568
1569         /* We shouldn't wait for data inihibit for stop commands, even
1570            though they might use busy signaling */
1571         if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1572                 mask &= ~SDHCI_DATA_INHIBIT;
1573
1574         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1575                 if (timeout == 0) {
1576                         pr_err("%s: Controller never released inhibit bit(s).\n",
1577                                mmc_hostname(host->mmc));
1578                         sdhci_dumpregs(host);
1579                         cmd->error = -EIO;
1580                         sdhci_finish_mrq(host, cmd->mrq);
1581                         return;
1582                 }
1583                 timeout--;
1584                 mdelay(1);
1585         }
1586
1587         host->cmd = cmd;
1588         host->data_timeout = 0;
1589         if (sdhci_data_line_cmd(cmd)) {
1590                 WARN_ON(host->data_cmd);
1591                 host->data_cmd = cmd;
1592                 sdhci_set_timeout(host, cmd);
1593         }
1594
1595         if (cmd->data) {
1596                 if (host->use_external_dma)
1597                         sdhci_external_dma_prepare_data(host, cmd);
1598                 else
1599                         sdhci_prepare_data(host, cmd);
1600         }
1601
1602         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1603
1604         sdhci_set_transfer_mode(host, cmd);
1605
1606         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1607                 pr_err("%s: Unsupported response type!\n",
1608                         mmc_hostname(host->mmc));
1609                 cmd->error = -EINVAL;
1610                 sdhci_finish_mrq(host, cmd->mrq);
1611                 return;
1612         }
1613
1614         if (!(cmd->flags & MMC_RSP_PRESENT))
1615                 flags = SDHCI_CMD_RESP_NONE;
1616         else if (cmd->flags & MMC_RSP_136)
1617                 flags = SDHCI_CMD_RESP_LONG;
1618         else if (cmd->flags & MMC_RSP_BUSY)
1619                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1620         else
1621                 flags = SDHCI_CMD_RESP_SHORT;
1622
1623         if (cmd->flags & MMC_RSP_CRC)
1624                 flags |= SDHCI_CMD_CRC;
1625         if (cmd->flags & MMC_RSP_OPCODE)
1626                 flags |= SDHCI_CMD_INDEX;
1627
1628         /* CMD19 is special in that the Data Present Select should be set */
1629         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1630             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1631                 flags |= SDHCI_CMD_DATA;
1632
1633         timeout = jiffies;
1634         if (host->data_timeout)
1635                 timeout += nsecs_to_jiffies(host->data_timeout);
1636         else if (!cmd->data && cmd->busy_timeout > 9000)
1637                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1638         else
1639                 timeout += 10 * HZ;
1640         sdhci_mod_timer(host, cmd->mrq, timeout);
1641
1642         if (host->use_external_dma)
1643                 sdhci_external_dma_pre_transfer(host, cmd);
1644
1645         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1646 }
1647 EXPORT_SYMBOL_GPL(sdhci_send_command);
1648
1649 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1650 {
1651         int i, reg;
1652
1653         for (i = 0; i < 4; i++) {
1654                 reg = SDHCI_RESPONSE + (3 - i) * 4;
1655                 cmd->resp[i] = sdhci_readl(host, reg);
1656         }
1657
1658         if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1659                 return;
1660
1661         /* CRC is stripped so we need to do some shifting */
1662         for (i = 0; i < 4; i++) {
1663                 cmd->resp[i] <<= 8;
1664                 if (i != 3)
1665                         cmd->resp[i] |= cmd->resp[i + 1] >> 24;
1666         }
1667 }
1668
1669 static void sdhci_finish_command(struct sdhci_host *host)
1670 {
1671         struct mmc_command *cmd = host->cmd;
1672
1673         host->cmd = NULL;
1674
1675         if (cmd->flags & MMC_RSP_PRESENT) {
1676                 if (cmd->flags & MMC_RSP_136) {
1677                         sdhci_read_rsp_136(host, cmd);
1678                 } else {
1679                         cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1680                 }
1681         }
1682
1683         if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1684                 mmc_command_done(host->mmc, cmd->mrq);
1685
1686         /*
1687          * The host can send and interrupt when the busy state has
1688          * ended, allowing us to wait without wasting CPU cycles.
1689          * The busy signal uses DAT0 so this is similar to waiting
1690          * for data to complete.
1691          *
1692          * Note: The 1.0 specification is a bit ambiguous about this
1693          *       feature so there might be some problems with older
1694          *       controllers.
1695          */
1696         if (cmd->flags & MMC_RSP_BUSY) {
1697                 if (cmd->data) {
1698                         DBG("Cannot wait for busy signal when also doing a data transfer");
1699                 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1700                            cmd == host->data_cmd) {
1701                         /* Command complete before busy is ended */
1702                         return;
1703                 }
1704         }
1705
1706         /* Finished CMD23, now send actual command. */
1707         if (cmd == cmd->mrq->sbc) {
1708                 sdhci_send_command(host, cmd->mrq->cmd);
1709         } else {
1710
1711                 /* Processed actual command. */
1712                 if (host->data && host->data_early)
1713                         sdhci_finish_data(host);
1714
1715                 if (!cmd->data)
1716                         __sdhci_finish_mrq(host, cmd->mrq);
1717         }
1718 }
1719
1720 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1721 {
1722         u16 preset = 0;
1723
1724         switch (host->timing) {
1725         case MMC_TIMING_UHS_SDR12:
1726                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1727                 break;
1728         case MMC_TIMING_UHS_SDR25:
1729                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1730                 break;
1731         case MMC_TIMING_UHS_SDR50:
1732                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1733                 break;
1734         case MMC_TIMING_UHS_SDR104:
1735         case MMC_TIMING_MMC_HS200:
1736                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1737                 break;
1738         case MMC_TIMING_UHS_DDR50:
1739         case MMC_TIMING_MMC_DDR52:
1740                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1741                 break;
1742         case MMC_TIMING_MMC_HS400:
1743                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1744                 break;
1745         default:
1746                 pr_warn("%s: Invalid UHS-I mode selected\n",
1747                         mmc_hostname(host->mmc));
1748                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1749                 break;
1750         }
1751         return preset;
1752 }
1753
1754 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1755                    unsigned int *actual_clock)
1756 {
1757         int div = 0; /* Initialized for compiler warning */
1758         int real_div = div, clk_mul = 1;
1759         u16 clk = 0;
1760         bool switch_base_clk = false;
1761
1762         if (host->version >= SDHCI_SPEC_300) {
1763                 if (host->preset_enabled) {
1764                         u16 pre_val;
1765
1766                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1767                         pre_val = sdhci_get_preset_value(host);
1768                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1769                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1770                         if (host->clk_mul &&
1771                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1772                                 clk = SDHCI_PROG_CLOCK_MODE;
1773                                 real_div = div + 1;
1774                                 clk_mul = host->clk_mul;
1775                         } else {
1776                                 real_div = max_t(int, 1, div << 1);
1777                         }
1778                         goto clock_set;
1779                 }
1780
1781                 /*
1782                  * Check if the Host Controller supports Programmable Clock
1783                  * Mode.
1784                  */
1785                 if (host->clk_mul) {
1786                         for (div = 1; div <= 1024; div++) {
1787                                 if ((host->max_clk * host->clk_mul / div)
1788                                         <= clock)
1789                                         break;
1790                         }
1791                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1792                                 /*
1793                                  * Set Programmable Clock Mode in the Clock
1794                                  * Control register.
1795                                  */
1796                                 clk = SDHCI_PROG_CLOCK_MODE;
1797                                 real_div = div;
1798                                 clk_mul = host->clk_mul;
1799                                 div--;
1800                         } else {
1801                                 /*
1802                                  * Divisor can be too small to reach clock
1803                                  * speed requirement. Then use the base clock.
1804                                  */
1805                                 switch_base_clk = true;
1806                         }
1807                 }
1808
1809                 if (!host->clk_mul || switch_base_clk) {
1810                         /* Version 3.00 divisors must be a multiple of 2. */
1811                         if (host->max_clk <= clock)
1812                                 div = 1;
1813                         else {
1814                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1815                                      div += 2) {
1816                                         if ((host->max_clk / div) <= clock)
1817                                                 break;
1818                                 }
1819                         }
1820                         real_div = div;
1821                         div >>= 1;
1822                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1823                                 && !div && host->max_clk <= 25000000)
1824                                 div = 1;
1825                 }
1826         } else {
1827                 /* Version 2.00 divisors must be a power of 2. */
1828                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1829                         if ((host->max_clk / div) <= clock)
1830                                 break;
1831                 }
1832                 real_div = div;
1833                 div >>= 1;
1834         }
1835
1836 clock_set:
1837         if (real_div)
1838                 *actual_clock = (host->max_clk * clk_mul) / real_div;
1839         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1840         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1841                 << SDHCI_DIVIDER_HI_SHIFT;
1842
1843         return clk;
1844 }
1845 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1846
1847 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1848 {
1849         ktime_t timeout;
1850
1851         clk |= SDHCI_CLOCK_INT_EN;
1852         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1853
1854         /* Wait max 150 ms */
1855         timeout = ktime_add_ms(ktime_get(), 150);
1856         while (1) {
1857                 bool timedout = ktime_after(ktime_get(), timeout);
1858
1859                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1860                 if (clk & SDHCI_CLOCK_INT_STABLE)
1861                         break;
1862                 if (timedout) {
1863                         pr_err("%s: Internal clock never stabilised.\n",
1864                                mmc_hostname(host->mmc));
1865                         sdhci_dumpregs(host);
1866                         return;
1867                 }
1868                 udelay(10);
1869         }
1870
1871         if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
1872                 clk |= SDHCI_CLOCK_PLL_EN;
1873                 clk &= ~SDHCI_CLOCK_INT_STABLE;
1874                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1875
1876                 /* Wait max 150 ms */
1877                 timeout = ktime_add_ms(ktime_get(), 150);
1878                 while (1) {
1879                         bool timedout = ktime_after(ktime_get(), timeout);
1880
1881                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1882                         if (clk & SDHCI_CLOCK_INT_STABLE)
1883                                 break;
1884                         if (timedout) {
1885                                 pr_err("%s: PLL clock never stabilised.\n",
1886                                        mmc_hostname(host->mmc));
1887                                 sdhci_dumpregs(host);
1888                                 return;
1889                         }
1890                         udelay(10);
1891                 }
1892         }
1893
1894         clk |= SDHCI_CLOCK_CARD_EN;
1895         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1896 }
1897 EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1898
1899 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1900 {
1901         u16 clk;
1902
1903         host->mmc->actual_clock = 0;
1904
1905         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1906
1907         if (clock == 0)
1908                 return;
1909
1910         clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1911         sdhci_enable_clk(host, clk);
1912 }
1913 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1914
1915 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1916                                 unsigned short vdd)
1917 {
1918         struct mmc_host *mmc = host->mmc;
1919
1920         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1921
1922         if (mode != MMC_POWER_OFF)
1923                 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1924         else
1925                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1926 }
1927
1928 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1929                            unsigned short vdd)
1930 {
1931         u8 pwr = 0;
1932
1933         if (mode != MMC_POWER_OFF) {
1934                 switch (1 << vdd) {
1935                 case MMC_VDD_165_195:
1936                 /*
1937                  * Without a regulator, SDHCI does not support 2.0v
1938                  * so we only get here if the driver deliberately
1939                  * added the 2.0v range to ocr_avail. Map it to 1.8v
1940                  * for the purpose of turning on the power.
1941                  */
1942                 case MMC_VDD_20_21:
1943                         pwr = SDHCI_POWER_180;
1944                         break;
1945                 case MMC_VDD_29_30:
1946                 case MMC_VDD_30_31:
1947                         pwr = SDHCI_POWER_300;
1948                         break;
1949                 case MMC_VDD_32_33:
1950                 case MMC_VDD_33_34:
1951                         pwr = SDHCI_POWER_330;
1952                         break;
1953                 default:
1954                         WARN(1, "%s: Invalid vdd %#x\n",
1955                              mmc_hostname(host->mmc), vdd);
1956                         break;
1957                 }
1958         }
1959
1960         if (host->pwr == pwr)
1961                 return;
1962
1963         host->pwr = pwr;
1964
1965         if (pwr == 0) {
1966                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1967                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1968                         sdhci_runtime_pm_bus_off(host);
1969         } else {
1970                 /*
1971                  * Spec says that we should clear the power reg before setting
1972                  * a new value. Some controllers don't seem to like this though.
1973                  */
1974                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1975                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1976
1977                 /*
1978                  * At least the Marvell CaFe chip gets confused if we set the
1979                  * voltage and set turn on power at the same time, so set the
1980                  * voltage first.
1981                  */
1982                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1983                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1984
1985                 pwr |= SDHCI_POWER_ON;
1986
1987                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1988
1989                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1990                         sdhci_runtime_pm_bus_on(host);
1991
1992                 /*
1993                  * Some controllers need an extra 10ms delay of 10ms before
1994                  * they can apply clock after applying power
1995                  */
1996                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1997                         mdelay(10);
1998         }
1999 }
2000 EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
2001
2002 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2003                      unsigned short vdd)
2004 {
2005         if (IS_ERR(host->mmc->supply.vmmc))
2006                 sdhci_set_power_noreg(host, mode, vdd);
2007         else
2008                 sdhci_set_power_reg(host, mode, vdd);
2009 }
2010 EXPORT_SYMBOL_GPL(sdhci_set_power);
2011
2012 /*****************************************************************************\
2013  *                                                                           *
2014  * MMC callbacks                                                             *
2015  *                                                                           *
2016 \*****************************************************************************/
2017
2018 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
2019 {
2020         struct sdhci_host *host;
2021         int present;
2022         unsigned long flags;
2023
2024         host = mmc_priv(mmc);
2025
2026         /* Firstly check card presence */
2027         present = mmc->ops->get_cd(mmc);
2028
2029         spin_lock_irqsave(&host->lock, flags);
2030
2031         sdhci_led_activate(host);
2032
2033         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
2034                 mrq->cmd->error = -ENOMEDIUM;
2035                 sdhci_finish_mrq(host, mrq);
2036         } else {
2037                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
2038                         sdhci_send_command(host, mrq->sbc);
2039                 else
2040                         sdhci_send_command(host, mrq->cmd);
2041         }
2042
2043         spin_unlock_irqrestore(&host->lock, flags);
2044 }
2045 EXPORT_SYMBOL_GPL(sdhci_request);
2046
2047 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2048 {
2049         u8 ctrl;
2050
2051         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2052         if (width == MMC_BUS_WIDTH_8) {
2053                 ctrl &= ~SDHCI_CTRL_4BITBUS;
2054                 ctrl |= SDHCI_CTRL_8BITBUS;
2055         } else {
2056                 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2057                         ctrl &= ~SDHCI_CTRL_8BITBUS;
2058                 if (width == MMC_BUS_WIDTH_4)
2059                         ctrl |= SDHCI_CTRL_4BITBUS;
2060                 else
2061                         ctrl &= ~SDHCI_CTRL_4BITBUS;
2062         }
2063         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2064 }
2065 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
2066
2067 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2068 {
2069         u16 ctrl_2;
2070
2071         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2072         /* Select Bus Speed Mode for host */
2073         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
2074         if ((timing == MMC_TIMING_MMC_HS200) ||
2075             (timing == MMC_TIMING_UHS_SDR104))
2076                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
2077         else if (timing == MMC_TIMING_UHS_SDR12)
2078                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
2079         else if (timing == MMC_TIMING_UHS_SDR25)
2080                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
2081         else if (timing == MMC_TIMING_UHS_SDR50)
2082                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
2083         else if ((timing == MMC_TIMING_UHS_DDR50) ||
2084                  (timing == MMC_TIMING_MMC_DDR52))
2085                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
2086         else if (timing == MMC_TIMING_MMC_HS400)
2087                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
2088         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2089 }
2090 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
2091
2092 void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2093 {
2094         struct sdhci_host *host = mmc_priv(mmc);
2095         u8 ctrl;
2096
2097         if (ios->power_mode == MMC_POWER_UNDEFINED)
2098                 return;
2099
2100         if (host->flags & SDHCI_DEVICE_DEAD) {
2101                 if (!IS_ERR(mmc->supply.vmmc) &&
2102                     ios->power_mode == MMC_POWER_OFF)
2103                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2104                 return;
2105         }
2106
2107         /*
2108          * Reset the chip on each power off.
2109          * Should clear out any weird states.
2110          */
2111         if (ios->power_mode == MMC_POWER_OFF) {
2112                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2113                 sdhci_reinit(host);
2114         }
2115
2116         if (host->version >= SDHCI_SPEC_300 &&
2117                 (ios->power_mode == MMC_POWER_UP) &&
2118                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2119                 sdhci_enable_preset_value(host, false);
2120
2121         if (!ios->clock || ios->clock != host->clock) {
2122                 host->ops->set_clock(host, ios->clock);
2123                 host->clock = ios->clock;
2124
2125                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2126                     host->clock) {
2127                         host->timeout_clk = host->mmc->actual_clock ?
2128                                                 host->mmc->actual_clock / 1000 :
2129                                                 host->clock / 1000;
2130                         host->mmc->max_busy_timeout =
2131                                 host->ops->get_max_timeout_count ?
2132                                 host->ops->get_max_timeout_count(host) :
2133                                 1 << 27;
2134                         host->mmc->max_busy_timeout /= host->timeout_clk;
2135                 }
2136         }
2137
2138         if (host->ops->set_power)
2139                 host->ops->set_power(host, ios->power_mode, ios->vdd);
2140         else
2141                 sdhci_set_power(host, ios->power_mode, ios->vdd);
2142
2143         if (host->ops->platform_send_init_74_clocks)
2144                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2145
2146         host->ops->set_bus_width(host, ios->bus_width);
2147
2148         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2149
2150         if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2151                 if (ios->timing == MMC_TIMING_SD_HS ||
2152                      ios->timing == MMC_TIMING_MMC_HS ||
2153                      ios->timing == MMC_TIMING_MMC_HS400 ||
2154                      ios->timing == MMC_TIMING_MMC_HS200 ||
2155                      ios->timing == MMC_TIMING_MMC_DDR52 ||
2156                      ios->timing == MMC_TIMING_UHS_SDR50 ||
2157                      ios->timing == MMC_TIMING_UHS_SDR104 ||
2158                      ios->timing == MMC_TIMING_UHS_DDR50 ||
2159                      ios->timing == MMC_TIMING_UHS_SDR25)
2160                         ctrl |= SDHCI_CTRL_HISPD;
2161                 else
2162                         ctrl &= ~SDHCI_CTRL_HISPD;
2163         }
2164
2165         if (host->version >= SDHCI_SPEC_300) {
2166                 u16 clk, ctrl_2;
2167
2168                 if (!host->preset_enabled) {
2169                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2170                         /*
2171                          * We only need to set Driver Strength if the
2172                          * preset value enable is not set.
2173                          */
2174                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2175                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
2176                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
2177                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
2178                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
2179                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2180                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
2181                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
2182                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
2183                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
2184                         else {
2185                                 pr_warn("%s: invalid driver type, default to driver type B\n",
2186                                         mmc_hostname(mmc));
2187                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
2188                         }
2189
2190                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2191                 } else {
2192                         /*
2193                          * According to SDHC Spec v3.00, if the Preset Value
2194                          * Enable in the Host Control 2 register is set, we
2195                          * need to reset SD Clock Enable before changing High
2196                          * Speed Enable to avoid generating clock gliches.
2197                          */
2198
2199                         /* Reset SD Clock Enable */
2200                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2201                         clk &= ~SDHCI_CLOCK_CARD_EN;
2202                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2203
2204                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2205
2206                         /* Re-enable SD Clock */
2207                         host->ops->set_clock(host, host->clock);
2208                 }
2209
2210                 /* Reset SD Clock Enable */
2211                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2212                 clk &= ~SDHCI_CLOCK_CARD_EN;
2213                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2214
2215                 host->ops->set_uhs_signaling(host, ios->timing);
2216                 host->timing = ios->timing;
2217
2218                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2219                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
2220                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
2221                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
2222                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
2223                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
2224                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
2225                         u16 preset;
2226
2227                         sdhci_enable_preset_value(host, true);
2228                         preset = sdhci_get_preset_value(host);
2229                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
2230                                 >> SDHCI_PRESET_DRV_SHIFT;
2231                 }
2232
2233                 /* Re-enable SD Clock */
2234                 host->ops->set_clock(host, host->clock);
2235         } else
2236                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2237
2238         /*
2239          * Some (ENE) controllers go apeshit on some ios operation,
2240          * signalling timeout and CRC errors even on CMD0. Resetting
2241          * it on each ios seems to solve the problem.
2242          */
2243         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
2244                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
2245 }
2246 EXPORT_SYMBOL_GPL(sdhci_set_ios);
2247
2248 static int sdhci_get_cd(struct mmc_host *mmc)
2249 {
2250         struct sdhci_host *host = mmc_priv(mmc);
2251         int gpio_cd = mmc_gpio_get_cd(mmc);
2252
2253         if (host->flags & SDHCI_DEVICE_DEAD)
2254                 return 0;
2255
2256         /* If nonremovable, assume that the card is always present. */
2257         if (!mmc_card_is_removable(host->mmc))
2258                 return 1;
2259
2260         /*
2261          * Try slot gpio detect, if defined it take precedence
2262          * over build in controller functionality
2263          */
2264         if (gpio_cd >= 0)
2265                 return !!gpio_cd;
2266
2267         /* If polling, assume that the card is always present. */
2268         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2269                 return 1;
2270
2271         /* Host native card detect */
2272         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2273 }
2274
2275 static int sdhci_check_ro(struct sdhci_host *host)
2276 {
2277         unsigned long flags;
2278         int is_readonly;
2279
2280         spin_lock_irqsave(&host->lock, flags);
2281
2282         if (host->flags & SDHCI_DEVICE_DEAD)
2283                 is_readonly = 0;
2284         else if (host->ops->get_ro)
2285                 is_readonly = host->ops->get_ro(host);
2286         else if (mmc_can_gpio_ro(host->mmc))
2287                 is_readonly = mmc_gpio_get_ro(host->mmc);
2288         else
2289                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2290                                 & SDHCI_WRITE_PROTECT);
2291
2292         spin_unlock_irqrestore(&host->lock, flags);
2293
2294         /* This quirk needs to be replaced by a callback-function later */
2295         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2296                 !is_readonly : is_readonly;
2297 }
2298
2299 #define SAMPLE_COUNT    5
2300
2301 static int sdhci_get_ro(struct mmc_host *mmc)
2302 {
2303         struct sdhci_host *host = mmc_priv(mmc);
2304         int i, ro_count;
2305
2306         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2307                 return sdhci_check_ro(host);
2308
2309         ro_count = 0;
2310         for (i = 0; i < SAMPLE_COUNT; i++) {
2311                 if (sdhci_check_ro(host)) {
2312                         if (++ro_count > SAMPLE_COUNT / 2)
2313                                 return 1;
2314                 }
2315                 msleep(30);
2316         }
2317         return 0;
2318 }
2319
2320 static void sdhci_hw_reset(struct mmc_host *mmc)
2321 {
2322         struct sdhci_host *host = mmc_priv(mmc);
2323
2324         if (host->ops && host->ops->hw_reset)
2325                 host->ops->hw_reset(host);
2326 }
2327
2328 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2329 {
2330         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2331                 if (enable)
2332                         host->ier |= SDHCI_INT_CARD_INT;
2333                 else
2334                         host->ier &= ~SDHCI_INT_CARD_INT;
2335
2336                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2337                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2338         }
2339 }
2340
2341 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
2342 {
2343         struct sdhci_host *host = mmc_priv(mmc);
2344         unsigned long flags;
2345
2346         if (enable)
2347                 pm_runtime_get_noresume(host->mmc->parent);
2348
2349         spin_lock_irqsave(&host->lock, flags);
2350         sdhci_enable_sdio_irq_nolock(host, enable);
2351         spin_unlock_irqrestore(&host->lock, flags);
2352
2353         if (!enable)
2354                 pm_runtime_put_noidle(host->mmc->parent);
2355 }
2356 EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
2357
2358 static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
2359 {
2360         struct sdhci_host *host = mmc_priv(mmc);
2361         unsigned long flags;
2362
2363         spin_lock_irqsave(&host->lock, flags);
2364         sdhci_enable_sdio_irq_nolock(host, true);
2365         spin_unlock_irqrestore(&host->lock, flags);
2366 }
2367
2368 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2369                                       struct mmc_ios *ios)
2370 {
2371         struct sdhci_host *host = mmc_priv(mmc);
2372         u16 ctrl;
2373         int ret;
2374
2375         /*
2376          * Signal Voltage Switching is only applicable for Host Controllers
2377          * v3.00 and above.
2378          */
2379         if (host->version < SDHCI_SPEC_300)
2380                 return 0;
2381
2382         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2383
2384         switch (ios->signal_voltage) {
2385         case MMC_SIGNAL_VOLTAGE_330:
2386                 if (!(host->flags & SDHCI_SIGNALING_330))
2387                         return -EINVAL;
2388                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2389                 ctrl &= ~SDHCI_CTRL_VDD_180;
2390                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2391
2392                 if (!IS_ERR(mmc->supply.vqmmc)) {
2393                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2394                         if (ret) {
2395                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2396                                         mmc_hostname(mmc));
2397                                 return -EIO;
2398                         }
2399                 }
2400                 /* Wait for 5ms */
2401                 usleep_range(5000, 5500);
2402
2403                 /* 3.3V regulator output should be stable within 5 ms */
2404                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2405                 if (!(ctrl & SDHCI_CTRL_VDD_180))
2406                         return 0;
2407
2408                 pr_warn("%s: 3.3V regulator output did not become stable\n",
2409                         mmc_hostname(mmc));
2410
2411                 return -EAGAIN;
2412         case MMC_SIGNAL_VOLTAGE_180:
2413                 if (!(host->flags & SDHCI_SIGNALING_180))
2414                         return -EINVAL;
2415                 if (!IS_ERR(mmc->supply.vqmmc)) {
2416                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2417                         if (ret) {
2418                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2419                                         mmc_hostname(mmc));
2420                                 return -EIO;
2421                         }
2422                 }
2423
2424                 /*
2425                  * Enable 1.8V Signal Enable in the Host Control2
2426                  * register
2427                  */
2428                 ctrl |= SDHCI_CTRL_VDD_180;
2429                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2430
2431                 /* Some controller need to do more when switching */
2432                 if (host->ops->voltage_switch)
2433                         host->ops->voltage_switch(host);
2434
2435                 /* 1.8V regulator output should be stable within 5 ms */
2436                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2437                 if (ctrl & SDHCI_CTRL_VDD_180)
2438                         return 0;
2439
2440                 pr_warn("%s: 1.8V regulator output did not become stable\n",
2441                         mmc_hostname(mmc));
2442
2443                 return -EAGAIN;
2444         case MMC_SIGNAL_VOLTAGE_120:
2445                 if (!(host->flags & SDHCI_SIGNALING_120))
2446                         return -EINVAL;
2447                 if (!IS_ERR(mmc->supply.vqmmc)) {
2448                         ret = mmc_regulator_set_vqmmc(mmc, ios);
2449                         if (ret) {
2450                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2451                                         mmc_hostname(mmc));
2452                                 return -EIO;
2453                         }
2454                 }
2455                 return 0;
2456         default:
2457                 /* No signal voltage switch required */
2458                 return 0;
2459         }
2460 }
2461 EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
2462
2463 static int sdhci_card_busy(struct mmc_host *mmc)
2464 {
2465         struct sdhci_host *host = mmc_priv(mmc);
2466         u32 present_state;
2467
2468         /* Check whether DAT[0] is 0 */
2469         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2470
2471         return !(present_state & SDHCI_DATA_0_LVL_MASK);
2472 }
2473
2474 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2475 {
2476         struct sdhci_host *host = mmc_priv(mmc);
2477         unsigned long flags;
2478
2479         spin_lock_irqsave(&host->lock, flags);
2480         host->flags |= SDHCI_HS400_TUNING;
2481         spin_unlock_irqrestore(&host->lock, flags);
2482
2483         return 0;
2484 }
2485
2486 void sdhci_start_tuning(struct sdhci_host *host)
2487 {
2488         u16 ctrl;
2489
2490         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2491         ctrl |= SDHCI_CTRL_EXEC_TUNING;
2492         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2493                 ctrl |= SDHCI_CTRL_TUNED_CLK;
2494         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2495
2496         /*
2497          * As per the Host Controller spec v3.00, tuning command
2498          * generates Buffer Read Ready interrupt, so enable that.
2499          *
2500          * Note: The spec clearly says that when tuning sequence
2501          * is being performed, the controller does not generate
2502          * interrupts other than Buffer Read Ready interrupt. But
2503          * to make sure we don't hit a controller bug, we _only_
2504          * enable Buffer Read Ready interrupt here.
2505          */
2506         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2507         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2508 }
2509 EXPORT_SYMBOL_GPL(sdhci_start_tuning);
2510
2511 void sdhci_end_tuning(struct sdhci_host *host)
2512 {
2513         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2514         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2515 }
2516 EXPORT_SYMBOL_GPL(sdhci_end_tuning);
2517
2518 void sdhci_reset_tuning(struct sdhci_host *host)
2519 {
2520         u16 ctrl;
2521
2522         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2523         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2524         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2525         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2526 }
2527 EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2528
2529 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2530 {
2531         sdhci_reset_tuning(host);
2532
2533         sdhci_do_reset(host, SDHCI_RESET_CMD);
2534         sdhci_do_reset(host, SDHCI_RESET_DATA);
2535
2536         sdhci_end_tuning(host);
2537
2538         mmc_abort_tuning(host->mmc, opcode);
2539 }
2540 EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2541
2542 /*
2543  * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2544  * tuning command does not have a data payload (or rather the hardware does it
2545  * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2546  * interrupt setup is different to other commands and there is no timeout
2547  * interrupt so special handling is needed.
2548  */
2549 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2550 {
2551         struct mmc_host *mmc = host->mmc;
2552         struct mmc_command cmd = {};
2553         struct mmc_request mrq = {};
2554         unsigned long flags;
2555         u32 b = host->sdma_boundary;
2556
2557         spin_lock_irqsave(&host->lock, flags);
2558
2559         cmd.opcode = opcode;
2560         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2561         cmd.mrq = &mrq;
2562
2563         mrq.cmd = &cmd;
2564         /*
2565          * In response to CMD19, the card sends 64 bytes of tuning
2566          * block to the Host Controller. So we set the block size
2567          * to 64 here.
2568          */
2569         if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2570             mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2571                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2572         else
2573                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2574
2575         /*
2576          * The tuning block is sent by the card to the host controller.
2577          * So we set the TRNS_READ bit in the Transfer Mode register.
2578          * This also takes care of setting DMA Enable and Multi Block
2579          * Select in the same register to 0.
2580          */
2581         sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2582
2583         sdhci_send_command(host, &cmd);
2584
2585         host->cmd = NULL;
2586
2587         sdhci_del_timer(host, &mrq);
2588
2589         host->tuning_done = 0;
2590
2591         spin_unlock_irqrestore(&host->lock, flags);
2592
2593         /* Wait for Buffer Read Ready interrupt */
2594         wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2595                            msecs_to_jiffies(50));
2596
2597 }
2598 EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2599
2600 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2601 {
2602         int i;
2603
2604         /*
2605          * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2606          * of loops reaches tuning loop count.
2607          */
2608         for (i = 0; i < host->tuning_loop_count; i++) {
2609                 u16 ctrl;
2610
2611                 sdhci_send_tuning(host, opcode);
2612
2613                 if (!host->tuning_done) {
2614                         pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2615                                  mmc_hostname(host->mmc));
2616                         sdhci_abort_tuning(host, opcode);
2617                         return -ETIMEDOUT;
2618                 }
2619
2620                 /* Spec does not require a delay between tuning cycles */
2621                 if (host->tuning_delay > 0)
2622                         mdelay(host->tuning_delay);
2623
2624                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2625                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2626                         if (ctrl & SDHCI_CTRL_TUNED_CLK)
2627                                 return 0; /* Success! */
2628                         break;
2629                 }
2630
2631         }
2632
2633         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2634                 mmc_hostname(host->mmc));
2635         sdhci_reset_tuning(host);
2636         return -EAGAIN;
2637 }
2638
2639 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2640 {
2641         struct sdhci_host *host = mmc_priv(mmc);
2642         int err = 0;
2643         unsigned int tuning_count = 0;
2644         bool hs400_tuning;
2645
2646         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2647
2648         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2649                 tuning_count = host->tuning_count;
2650
2651         /*
2652          * The Host Controller needs tuning in case of SDR104 and DDR50
2653          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2654          * the Capabilities register.
2655          * If the Host Controller supports the HS200 mode then the
2656          * tuning function has to be executed.
2657          */
2658         switch (host->timing) {
2659         /* HS400 tuning is done in HS200 mode */
2660         case MMC_TIMING_MMC_HS400:
2661                 err = -EINVAL;
2662                 goto out;
2663
2664         case MMC_TIMING_MMC_HS200:
2665                 /*
2666                  * Periodic re-tuning for HS400 is not expected to be needed, so
2667                  * disable it here.
2668                  */
2669                 if (hs400_tuning)
2670                         tuning_count = 0;
2671                 break;
2672
2673         case MMC_TIMING_UHS_SDR104:
2674         case MMC_TIMING_UHS_DDR50:
2675                 break;
2676
2677         case MMC_TIMING_UHS_SDR50:
2678                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2679                         break;
2680                 /* FALLTHROUGH */
2681
2682         default:
2683                 goto out;
2684         }
2685
2686         if (host->ops->platform_execute_tuning) {
2687                 err = host->ops->platform_execute_tuning(host, opcode);
2688                 goto out;
2689         }
2690
2691         host->mmc->retune_period = tuning_count;
2692
2693         if (host->tuning_delay < 0)
2694                 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2695
2696         sdhci_start_tuning(host);
2697
2698         host->tuning_err = __sdhci_execute_tuning(host, opcode);
2699
2700         sdhci_end_tuning(host);
2701 out:
2702         host->flags &= ~SDHCI_HS400_TUNING;
2703
2704         return err;
2705 }
2706 EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
2707
2708 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2709 {
2710         /* Host Controller v3.00 defines preset value registers */
2711         if (host->version < SDHCI_SPEC_300)
2712                 return;
2713
2714         /*
2715          * We only enable or disable Preset Value if they are not already
2716          * enabled or disabled respectively. Otherwise, we bail out.
2717          */
2718         if (host->preset_enabled != enable) {
2719                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2720
2721                 if (enable)
2722                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2723                 else
2724                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2725
2726                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2727
2728                 if (enable)
2729                         host->flags |= SDHCI_PV_ENABLED;
2730                 else
2731                         host->flags &= ~SDHCI_PV_ENABLED;
2732
2733                 host->preset_enabled = enable;
2734         }
2735 }
2736
2737 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2738                                 int err)
2739 {
2740         struct sdhci_host *host = mmc_priv(mmc);
2741         struct mmc_data *data = mrq->data;
2742
2743         if (data->host_cookie != COOKIE_UNMAPPED)
2744                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2745                              mmc_get_dma_dir(data));
2746
2747         data->host_cookie = COOKIE_UNMAPPED;
2748 }
2749
2750 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
2751 {
2752         struct sdhci_host *host = mmc_priv(mmc);
2753
2754         mrq->data->host_cookie = COOKIE_UNMAPPED;
2755
2756         /*
2757          * No pre-mapping in the pre hook if we're using the bounce buffer,
2758          * for that we would need two bounce buffers since one buffer is
2759          * in flight when this is getting called.
2760          */
2761         if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
2762                 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2763 }
2764
2765 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2766 {
2767         if (host->data_cmd) {
2768                 host->data_cmd->error = err;
2769                 sdhci_finish_mrq(host, host->data_cmd->mrq);
2770         }
2771
2772         if (host->cmd) {
2773                 host->cmd->error = err;
2774                 sdhci_finish_mrq(host, host->cmd->mrq);
2775         }
2776 }
2777
2778 static void sdhci_card_event(struct mmc_host *mmc)
2779 {
2780         struct sdhci_host *host = mmc_priv(mmc);
2781         unsigned long flags;
2782         int present;
2783
2784         /* First check if client has provided their own card event */
2785         if (host->ops->card_event)
2786                 host->ops->card_event(host);
2787
2788         present = mmc->ops->get_cd(mmc);
2789
2790         spin_lock_irqsave(&host->lock, flags);
2791
2792         /* Check sdhci_has_requests() first in case we are runtime suspended */
2793         if (sdhci_has_requests(host) && !present) {
2794                 pr_err("%s: Card removed during transfer!\n",
2795                         mmc_hostname(host->mmc));
2796                 pr_err("%s: Resetting controller.\n",
2797                         mmc_hostname(host->mmc));
2798
2799                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2800                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2801
2802                 sdhci_error_out_mrqs(host, -ENOMEDIUM);
2803         }
2804
2805         spin_unlock_irqrestore(&host->lock, flags);
2806 }
2807
2808 static const struct mmc_host_ops sdhci_ops = {
2809         .request        = sdhci_request,
2810         .post_req       = sdhci_post_req,
2811         .pre_req        = sdhci_pre_req,
2812         .set_ios        = sdhci_set_ios,
2813         .get_cd         = sdhci_get_cd,
2814         .get_ro         = sdhci_get_ro,
2815         .hw_reset       = sdhci_hw_reset,
2816         .enable_sdio_irq = sdhci_enable_sdio_irq,
2817         .ack_sdio_irq    = sdhci_ack_sdio_irq,
2818         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2819         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2820         .execute_tuning                 = sdhci_execute_tuning,
2821         .card_event                     = sdhci_card_event,
2822         .card_busy      = sdhci_card_busy,
2823 };
2824
2825 /*****************************************************************************\
2826  *                                                                           *
2827  * Request done                                                              *
2828  *                                                                           *
2829 \*****************************************************************************/
2830
2831 static bool sdhci_request_done(struct sdhci_host *host)
2832 {
2833         unsigned long flags;
2834         struct mmc_request *mrq;
2835         int i;
2836
2837         spin_lock_irqsave(&host->lock, flags);
2838
2839         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2840                 mrq = host->mrqs_done[i];
2841                 if (mrq)
2842                         break;
2843         }
2844
2845         if (!mrq) {
2846                 spin_unlock_irqrestore(&host->lock, flags);
2847                 return true;
2848         }
2849
2850         /*
2851          * Always unmap the data buffers if they were mapped by
2852          * sdhci_prepare_data() whenever we finish with a request.
2853          * This avoids leaking DMA mappings on error.
2854          */
2855         if (host->flags & SDHCI_REQ_USE_DMA) {
2856                 struct mmc_data *data = mrq->data;
2857
2858                 if (host->use_external_dma && data &&
2859                     (mrq->cmd->error || data->error)) {
2860                         struct dma_chan *chan = sdhci_external_dma_channel(host, data);
2861
2862                         host->mrqs_done[i] = NULL;
2863                         spin_unlock_irqrestore(&host->lock, flags);
2864                         dmaengine_terminate_sync(chan);
2865                         spin_lock_irqsave(&host->lock, flags);
2866                         sdhci_set_mrq_done(host, mrq);
2867                 }
2868
2869                 if (data && data->host_cookie == COOKIE_MAPPED) {
2870                         if (host->bounce_buffer) {
2871                                 /*
2872                                  * On reads, copy the bounced data into the
2873                                  * sglist
2874                                  */
2875                                 if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) {
2876                                         unsigned int length = data->bytes_xfered;
2877
2878                                         if (length > host->bounce_buffer_size) {
2879                                                 pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n",
2880                                                        mmc_hostname(host->mmc),
2881                                                        host->bounce_buffer_size,
2882                                                        data->bytes_xfered);
2883                                                 /* Cap it down and continue */
2884                                                 length = host->bounce_buffer_size;
2885                                         }
2886                                         dma_sync_single_for_cpu(
2887                                                 host->mmc->parent,
2888                                                 host->bounce_addr,
2889                                                 host->bounce_buffer_size,
2890                                                 DMA_FROM_DEVICE);
2891                                         sg_copy_from_buffer(data->sg,
2892                                                 data->sg_len,
2893                                                 host->bounce_buffer,
2894                                                 length);
2895                                 } else {
2896                                         /* No copying, just switch ownership */
2897                                         dma_sync_single_for_cpu(
2898                                                 host->mmc->parent,
2899                                                 host->bounce_addr,
2900                                                 host->bounce_buffer_size,
2901                                                 mmc_get_dma_dir(data));
2902                                 }
2903                         } else {
2904                                 /* Unmap the raw data */
2905                                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
2906                                              data->sg_len,
2907                                              mmc_get_dma_dir(data));
2908                         }
2909                         data->host_cookie = COOKIE_UNMAPPED;
2910                 }
2911         }
2912
2913         /*
2914          * The controller needs a reset of internal state machines
2915          * upon error conditions.
2916          */
2917         if (sdhci_needs_reset(host, mrq)) {
2918                 /*
2919                  * Do not finish until command and data lines are available for
2920                  * reset. Note there can only be one other mrq, so it cannot
2921                  * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2922                  * would both be null.
2923                  */
2924                 if (host->cmd || host->data_cmd) {
2925                         spin_unlock_irqrestore(&host->lock, flags);
2926                         return true;
2927                 }
2928
2929                 /* Some controllers need this kick or reset won't work here */
2930                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2931                         /* This is to force an update */
2932                         host->ops->set_clock(host, host->clock);
2933
2934                 /* Spec says we should do both at the same time, but Ricoh
2935                    controllers do not like that. */
2936                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2937                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2938
2939                 host->pending_reset = false;
2940         }
2941
2942         host->mrqs_done[i] = NULL;
2943
2944         spin_unlock_irqrestore(&host->lock, flags);
2945
2946         mmc_request_done(host->mmc, mrq);
2947
2948         return false;
2949 }
2950
2951 static void sdhci_complete_work(struct work_struct *work)
2952 {
2953         struct sdhci_host *host = container_of(work, struct sdhci_host,
2954                                                complete_work);
2955
2956         while (!sdhci_request_done(host))
2957                 ;
2958 }
2959
2960 static void sdhci_timeout_timer(struct timer_list *t)
2961 {
2962         struct sdhci_host *host;
2963         unsigned long flags;
2964
2965         host = from_timer(host, t, timer);
2966
2967         spin_lock_irqsave(&host->lock, flags);
2968
2969         if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2970                 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2971                        mmc_hostname(host->mmc));
2972                 sdhci_dumpregs(host);
2973
2974                 host->cmd->error = -ETIMEDOUT;
2975                 sdhci_finish_mrq(host, host->cmd->mrq);
2976         }
2977
2978         spin_unlock_irqrestore(&host->lock, flags);
2979 }
2980
2981 static void sdhci_timeout_data_timer(struct timer_list *t)
2982 {
2983         struct sdhci_host *host;
2984         unsigned long flags;
2985
2986         host = from_timer(host, t, data_timer);
2987
2988         spin_lock_irqsave(&host->lock, flags);
2989
2990         if (host->data || host->data_cmd ||
2991             (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2992                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2993                        mmc_hostname(host->mmc));
2994                 sdhci_dumpregs(host);
2995
2996                 if (host->data) {
2997                         host->data->error = -ETIMEDOUT;
2998                         sdhci_finish_data(host);
2999                         queue_work(host->complete_wq, &host->complete_work);
3000                 } else if (host->data_cmd) {
3001                         host->data_cmd->error = -ETIMEDOUT;
3002                         sdhci_finish_mrq(host, host->data_cmd->mrq);
3003                 } else {
3004                         host->cmd->error = -ETIMEDOUT;
3005                         sdhci_finish_mrq(host, host->cmd->mrq);
3006                 }
3007         }
3008
3009         spin_unlock_irqrestore(&host->lock, flags);
3010 }
3011
3012 /*****************************************************************************\
3013  *                                                                           *
3014  * Interrupt handling                                                        *
3015  *                                                                           *
3016 \*****************************************************************************/
3017
3018 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3019 {
3020         /* Handle auto-CMD12 error */
3021         if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3022                 struct mmc_request *mrq = host->data_cmd->mrq;
3023                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3024                 int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3025                                    SDHCI_INT_DATA_TIMEOUT :
3026                                    SDHCI_INT_DATA_CRC;
3027
3028                 /* Treat auto-CMD12 error the same as data error */
3029                 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3030                         *intmask_p |= data_err_bit;
3031                         return;
3032                 }
3033         }
3034
3035         if (!host->cmd) {
3036                 /*
3037                  * SDHCI recovers from errors by resetting the cmd and data
3038                  * circuits.  Until that is done, there very well might be more
3039                  * interrupts, so ignore them in that case.
3040                  */
3041                 if (host->pending_reset)
3042                         return;
3043                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
3044                        mmc_hostname(host->mmc), (unsigned)intmask);
3045                 sdhci_dumpregs(host);
3046                 return;
3047         }
3048
3049         if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
3050                        SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
3051                 if (intmask & SDHCI_INT_TIMEOUT)
3052                         host->cmd->error = -ETIMEDOUT;
3053                 else
3054                         host->cmd->error = -EILSEQ;
3055
3056                 /* Treat data command CRC error the same as data CRC error */
3057                 if (host->cmd->data &&
3058                     (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
3059                      SDHCI_INT_CRC) {
3060                         host->cmd = NULL;
3061                         *intmask_p |= SDHCI_INT_DATA_CRC;
3062                         return;
3063                 }
3064
3065                 __sdhci_finish_mrq(host, host->cmd->mrq);
3066                 return;
3067         }
3068
3069         /* Handle auto-CMD23 error */
3070         if (intmask & SDHCI_INT_AUTO_CMD_ERR) {
3071                 struct mmc_request *mrq = host->cmd->mrq;
3072                 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3073                 int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ?
3074                           -ETIMEDOUT :
3075                           -EILSEQ;
3076
3077                 if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
3078                         mrq->sbc->error = err;
3079                         __sdhci_finish_mrq(host, mrq);
3080                         return;
3081                 }
3082         }
3083
3084         if (intmask & SDHCI_INT_RESPONSE)
3085                 sdhci_finish_command(host);
3086 }
3087
3088 static void sdhci_adma_show_error(struct sdhci_host *host)
3089 {
3090         void *desc = host->adma_table;
3091         dma_addr_t dma = host->adma_addr;
3092
3093         sdhci_dumpregs(host);
3094
3095         while (true) {
3096                 struct sdhci_adma2_64_desc *dma_desc = desc;
3097
3098                 if (host->flags & SDHCI_USE_64_BIT_DMA)
3099                         SDHCI_DUMP("%08llx: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
3100                             (unsigned long long)dma,
3101                             le32_to_cpu(dma_desc->addr_hi),
3102                             le32_to_cpu(dma_desc->addr_lo),
3103                             le16_to_cpu(dma_desc->len),
3104                             le16_to_cpu(dma_desc->cmd));
3105                 else
3106                         SDHCI_DUMP("%08llx: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
3107                             (unsigned long long)dma,
3108                             le32_to_cpu(dma_desc->addr_lo),
3109                             le16_to_cpu(dma_desc->len),
3110                             le16_to_cpu(dma_desc->cmd));
3111
3112                 desc += host->desc_sz;
3113                 dma += host->desc_sz;
3114
3115                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
3116                         break;
3117         }
3118 }
3119
3120 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3121 {
3122         u32 command;
3123
3124         /* CMD19 generates _only_ Buffer Read Ready interrupt */
3125         if (intmask & SDHCI_INT_DATA_AVAIL) {
3126                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
3127                 if (command == MMC_SEND_TUNING_BLOCK ||
3128                     command == MMC_SEND_TUNING_BLOCK_HS200) {
3129                         host->tuning_done = 1;
3130                         wake_up(&host->buf_ready_int);
3131                         return;
3132                 }
3133         }
3134
3135         if (!host->data) {
3136                 struct mmc_command *data_cmd = host->data_cmd;
3137
3138                 /*
3139                  * The "data complete" interrupt is also used to
3140                  * indicate that a busy state has ended. See comment
3141                  * above in sdhci_cmd_irq().
3142                  */
3143                 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
3144                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
3145                                 host->data_cmd = NULL;
3146                                 data_cmd->error = -ETIMEDOUT;
3147                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3148                                 return;
3149                         }
3150                         if (intmask & SDHCI_INT_DATA_END) {
3151                                 host->data_cmd = NULL;
3152                                 /*
3153                                  * Some cards handle busy-end interrupt
3154                                  * before the command completed, so make
3155                                  * sure we do things in the proper order.
3156                                  */
3157                                 if (host->cmd == data_cmd)
3158                                         return;
3159
3160                                 __sdhci_finish_mrq(host, data_cmd->mrq);
3161                                 return;
3162                         }
3163                 }
3164
3165                 /*
3166                  * SDHCI recovers from errors by resetting the cmd and data
3167                  * circuits. Until that is done, there very well might be more
3168                  * interrupts, so ignore them in that case.
3169                  */
3170                 if (host->pending_reset)
3171                         return;
3172
3173                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
3174                        mmc_hostname(host->mmc), (unsigned)intmask);
3175                 sdhci_dumpregs(host);
3176
3177                 return;
3178         }
3179
3180         if (intmask & SDHCI_INT_DATA_TIMEOUT)
3181                 host->data->error = -ETIMEDOUT;
3182         else if (intmask & SDHCI_INT_DATA_END_BIT)
3183                 host->data->error = -EILSEQ;
3184         else if ((intmask & SDHCI_INT_DATA_CRC) &&
3185                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3186                         != MMC_BUS_TEST_R)
3187                 host->data->error = -EILSEQ;
3188         else if (intmask & SDHCI_INT_ADMA_ERROR) {
3189                 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3190                        intmask);
3191                 sdhci_adma_show_error(host);
3192                 host->data->error = -EIO;
3193                 if (host->ops->adma_workaround)
3194                         host->ops->adma_workaround(host, intmask);
3195         }
3196
3197         if (host->data->error)
3198                 sdhci_finish_data(host);
3199         else {
3200                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
3201                         sdhci_transfer_pio(host);
3202
3203                 /*
3204                  * We currently don't do anything fancy with DMA
3205                  * boundaries, but as we can't disable the feature
3206                  * we need to at least restart the transfer.
3207                  *
3208                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3209                  * should return a valid address to continue from, but as
3210                  * some controllers are faulty, don't trust them.
3211                  */
3212                 if (intmask & SDHCI_INT_DMA_END) {
3213                         dma_addr_t dmastart, dmanow;
3214
3215                         dmastart = sdhci_sdma_address(host);
3216                         dmanow = dmastart + host->data->bytes_xfered;
3217                         /*
3218                          * Force update to the next DMA block boundary.
3219                          */
3220                         dmanow = (dmanow &
3221                                 ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
3222                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
3223                         host->data->bytes_xfered = dmanow - dmastart;
3224                         DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
3225                             &dmastart, host->data->bytes_xfered, &dmanow);
3226                         sdhci_set_sdma_addr(host, dmanow);
3227                 }
3228
3229                 if (intmask & SDHCI_INT_DATA_END) {
3230                         if (host->cmd == host->data_cmd) {
3231                                 /*
3232                                  * Data managed to finish before the
3233                                  * command completed. Make sure we do
3234                                  * things in the proper order.
3235                                  */
3236                                 host->data_early = 1;
3237                         } else {
3238                                 sdhci_finish_data(host);
3239                         }
3240                 }
3241         }
3242 }
3243
3244 static inline bool sdhci_defer_done(struct sdhci_host *host,
3245                                     struct mmc_request *mrq)
3246 {
3247         struct mmc_data *data = mrq->data;
3248
3249         return host->pending_reset ||
3250                ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3251                 data->host_cookie == COOKIE_MAPPED);
3252 }
3253
3254 static irqreturn_t sdhci_irq(int irq, void *dev_id)
3255 {
3256         struct mmc_request *mrqs_done[SDHCI_MAX_MRQS] = {0};
3257         irqreturn_t result = IRQ_NONE;
3258         struct sdhci_host *host = dev_id;
3259         u32 intmask, mask, unexpected = 0;
3260         int max_loops = 16;
3261         int i;
3262
3263         spin_lock(&host->lock);
3264
3265         if (host->runtime_suspended) {
3266                 spin_unlock(&host->lock);
3267                 return IRQ_NONE;
3268         }
3269
3270         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3271         if (!intmask || intmask == 0xffffffff) {
3272                 result = IRQ_NONE;
3273                 goto out;
3274         }
3275
3276         do {
3277                 DBG("IRQ status 0x%08x\n", intmask);
3278
3279                 if (host->ops->irq) {
3280                         intmask = host->ops->irq(host, intmask);
3281                         if (!intmask)
3282                                 goto cont;
3283                 }
3284
3285                 /* Clear selected interrupts. */
3286                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3287                                   SDHCI_INT_BUS_POWER);
3288                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3289
3290                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3291                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3292                                       SDHCI_CARD_PRESENT;
3293
3294                         /*
3295                          * There is a observation on i.mx esdhc.  INSERT
3296                          * bit will be immediately set again when it gets
3297                          * cleared, if a card is inserted.  We have to mask
3298                          * the irq to prevent interrupt storm which will
3299                          * freeze the system.  And the REMOVE gets the
3300                          * same situation.
3301                          *
3302                          * More testing are needed here to ensure it works
3303                          * for other platforms though.
3304                          */
3305                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
3306                                        SDHCI_INT_CARD_REMOVE);
3307                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3308                                                SDHCI_INT_CARD_INSERT;
3309                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3310                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3311
3312                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3313                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3314
3315                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3316                                                        SDHCI_INT_CARD_REMOVE);
3317                         result = IRQ_WAKE_THREAD;
3318                 }
3319
3320                 if (intmask & SDHCI_INT_CMD_MASK)
3321                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3322
3323                 if (intmask & SDHCI_INT_DATA_MASK)
3324                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3325
3326                 if (intmask & SDHCI_INT_BUS_POWER)
3327                         pr_err("%s: Card is consuming too much power!\n",
3328                                 mmc_hostname(host->mmc));
3329
3330                 if (intmask & SDHCI_INT_RETUNE)
3331                         mmc_retune_needed(host->mmc);
3332
3333                 if ((intmask & SDHCI_INT_CARD_INT) &&
3334                     (host->ier & SDHCI_INT_CARD_INT)) {
3335                         sdhci_enable_sdio_irq_nolock(host, false);
3336                         sdio_signal_irq(host->mmc);
3337                 }
3338
3339                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
3340                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
3341                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
3342                              SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
3343
3344                 if (intmask) {
3345                         unexpected |= intmask;
3346                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3347                 }
3348 cont:
3349                 if (result == IRQ_NONE)
3350                         result = IRQ_HANDLED;
3351
3352                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3353         } while (intmask && --max_loops);
3354
3355         /* Determine if mrqs can be completed immediately */
3356         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3357                 struct mmc_request *mrq = host->mrqs_done[i];
3358
3359                 if (!mrq)
3360                         continue;
3361
3362                 if (sdhci_defer_done(host, mrq)) {
3363                         result = IRQ_WAKE_THREAD;
3364                 } else {
3365                         mrqs_done[i] = mrq;
3366                         host->mrqs_done[i] = NULL;
3367                 }
3368         }
3369 out:
3370         spin_unlock(&host->lock);
3371
3372         /* Process mrqs ready for immediate completion */
3373         for (i = 0; i < SDHCI_MAX_MRQS; i++) {
3374                 if (mrqs_done[i])
3375                         mmc_request_done(host->mmc, mrqs_done[i]);
3376         }
3377
3378         if (unexpected) {
3379                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3380                            mmc_hostname(host->mmc), unexpected);
3381                 sdhci_dumpregs(host);
3382         }
3383
3384         return result;
3385 }
3386
3387 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3388 {
3389         struct sdhci_host *host = dev_id;
3390         unsigned long flags;
3391         u32 isr;
3392
3393         while (!sdhci_request_done(host))
3394                 ;
3395
3396         spin_lock_irqsave(&host->lock, flags);
3397         isr = host->thread_isr;
3398         host->thread_isr = 0;
3399         spin_unlock_irqrestore(&host->lock, flags);
3400
3401         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
3402                 struct mmc_host *mmc = host->mmc;
3403
3404                 mmc->ops->card_event(mmc);
3405                 mmc_detect_change(mmc, msecs_to_jiffies(200));
3406         }
3407
3408         return IRQ_HANDLED;
3409 }
3410
3411 /*****************************************************************************\
3412  *                                                                           *
3413  * Suspend/resume                                                            *
3414  *                                                                           *
3415 \*****************************************************************************/
3416
3417 #ifdef CONFIG_PM
3418
3419 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3420 {
3421         return mmc_card_is_removable(host->mmc) &&
3422                !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3423                !mmc_can_gpio_cd(host->mmc);
3424 }
3425
3426 /*
3427  * To enable wakeup events, the corresponding events have to be enabled in
3428  * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
3429  * Table' in the SD Host Controller Standard Specification.
3430  * It is useless to restore SDHCI_INT_ENABLE state in
3431  * sdhci_disable_irq_wakeups() since it will be set by
3432  * sdhci_enable_card_detection() or sdhci_init().
3433  */
3434 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3435 {
3436         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
3437                   SDHCI_WAKE_ON_INT;
3438         u32 irq_val = 0;
3439         u8 wake_val = 0;
3440         u8 val;
3441
3442         if (sdhci_cd_irq_can_wakeup(host)) {
3443                 wake_val |= SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE;
3444                 irq_val |= SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE;
3445         }
3446
3447         if (mmc_card_wake_sdio_irq(host->mmc)) {
3448                 wake_val |= SDHCI_WAKE_ON_INT;
3449                 irq_val |= SDHCI_INT_CARD_INT;
3450         }
3451
3452         if (!irq_val)
3453                 return false;
3454
3455         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3456         val &= ~mask;
3457         val |= wake_val;
3458         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3459
3460         sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3461
3462         host->irq_wake_enabled = !enable_irq_wake(host->irq);
3463
3464         return host->irq_wake_enabled;
3465 }
3466
3467 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3468 {
3469         u8 val;
3470         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
3471                         | SDHCI_WAKE_ON_INT;
3472
3473         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3474         val &= ~mask;
3475         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3476
3477         disable_irq_wake(host->irq);
3478
3479         host->irq_wake_enabled = false;
3480 }
3481
3482 int sdhci_suspend_host(struct sdhci_host *host)
3483 {
3484         sdhci_disable_card_detection(host);
3485
3486         mmc_retune_timer_stop(host->mmc);
3487
3488         if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3489             !sdhci_enable_irq_wakeups(host)) {
3490                 host->ier = 0;
3491                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3492                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3493                 free_irq(host->irq, host);
3494         }
3495
3496         return 0;
3497 }
3498
3499 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
3500
3501 int sdhci_resume_host(struct sdhci_host *host)
3502 {
3503         struct mmc_host *mmc = host->mmc;
3504         int ret = 0;
3505
3506         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3507                 if (host->ops->enable_dma)
3508                         host->ops->enable_dma(host);
3509         }
3510
3511         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
3512             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3513                 /* Card keeps power but host controller does not */
3514                 sdhci_init(host, 0);
3515                 host->pwr = 0;
3516                 host->clock = 0;
3517                 mmc->ops->set_ios(mmc, &mmc->ios);
3518         } else {
3519                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3520         }
3521
3522         if (host->irq_wake_enabled) {
3523                 sdhci_disable_irq_wakeups(host);
3524         } else {
3525                 ret = request_threaded_irq(host->irq, sdhci_irq,
3526                                            sdhci_thread_irq, IRQF_SHARED,
3527                                            mmc_hostname(host->mmc), host);
3528                 if (ret)
3529                         return ret;
3530         }
3531
3532         sdhci_enable_card_detection(host);
3533
3534         return ret;
3535 }
3536
3537 EXPORT_SYMBOL_GPL(sdhci_resume_host);
3538
3539 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3540 {
3541         unsigned long flags;
3542
3543         mmc_retune_timer_stop(host->mmc);
3544
3545         spin_lock_irqsave(&host->lock, flags);
3546         host->ier &= SDHCI_INT_CARD_INT;
3547         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3548         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3549         spin_unlock_irqrestore(&host->lock, flags);
3550
3551         synchronize_hardirq(host->irq);
3552
3553         spin_lock_irqsave(&host->lock, flags);
3554         host->runtime_suspended = true;
3555         spin_unlock_irqrestore(&host->lock, flags);
3556
3557         return 0;
3558 }
3559 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3560
3561 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3562 {
3563         struct mmc_host *mmc = host->mmc;
3564         unsigned long flags;
3565         int host_flags = host->flags;
3566
3567         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3568                 if (host->ops->enable_dma)
3569                         host->ops->enable_dma(host);
3570         }
3571
3572         sdhci_init(host, soft_reset);
3573
3574         if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3575             mmc->ios.power_mode != MMC_POWER_OFF) {
3576                 /* Force clock and power re-program */
3577                 host->pwr = 0;
3578                 host->clock = 0;
3579                 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
3580                 mmc->ops->set_ios(mmc, &mmc->ios);
3581
3582                 if ((host_flags & SDHCI_PV_ENABLED) &&
3583                     !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3584                         spin_lock_irqsave(&host->lock, flags);
3585                         sdhci_enable_preset_value(host, true);
3586                         spin_unlock_irqrestore(&host->lock, flags);
3587                 }
3588
3589                 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
3590                     mmc->ops->hs400_enhanced_strobe)
3591                         mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
3592         }
3593
3594         spin_lock_irqsave(&host->lock, flags);
3595
3596         host->runtime_suspended = false;
3597
3598         /* Enable SDIO IRQ */
3599         if (sdio_irq_claimed(mmc))
3600                 sdhci_enable_sdio_irq_nolock(host, true);
3601
3602         /* Enable Card Detection */
3603         sdhci_enable_card_detection(host);
3604
3605         spin_unlock_irqrestore(&host->lock, flags);
3606
3607         return 0;
3608 }
3609 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
3610
3611 #endif /* CONFIG_PM */
3612
3613 /*****************************************************************************\
3614  *                                                                           *
3615  * Command Queue Engine (CQE) helpers                                        *
3616  *                                                                           *
3617 \*****************************************************************************/
3618
3619 void sdhci_cqe_enable(struct mmc_host *mmc)
3620 {
3621         struct sdhci_host *host = mmc_priv(mmc);
3622         unsigned long flags;
3623         u8 ctrl;
3624
3625         spin_lock_irqsave(&host->lock, flags);
3626
3627         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3628         ctrl &= ~SDHCI_CTRL_DMA_MASK;
3629         /*
3630          * Host from V4.10 supports ADMA3 DMA type.
3631          * ADMA3 performs integrated descriptor which is more suitable
3632          * for cmd queuing to fetch both command and transfer descriptors.
3633          */
3634         if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3635                 ctrl |= SDHCI_CTRL_ADMA3;
3636         else if (host->flags & SDHCI_USE_64_BIT_DMA)
3637                 ctrl |= SDHCI_CTRL_ADMA64;
3638         else
3639                 ctrl |= SDHCI_CTRL_ADMA32;
3640         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3641
3642         sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3643                      SDHCI_BLOCK_SIZE);
3644
3645         /* Set maximum timeout */
3646         sdhci_set_timeout(host, NULL);
3647
3648         host->ier = host->cqe_ier;
3649
3650         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3651         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3652
3653         host->cqe_on = true;
3654
3655         pr_debug("%s: sdhci: CQE on, IRQ mask %#x, IRQ status %#x\n",
3656                  mmc_hostname(mmc), host->ier,
3657                  sdhci_readl(host, SDHCI_INT_STATUS));
3658
3659         spin_unlock_irqrestore(&host->lock, flags);
3660 }
3661 EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
3662
3663 void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
3664 {
3665         struct sdhci_host *host = mmc_priv(mmc);
3666         unsigned long flags;
3667
3668         spin_lock_irqsave(&host->lock, flags);
3669
3670         sdhci_set_default_irqs(host);
3671
3672         host->cqe_on = false;
3673
3674         if (recovery) {
3675                 sdhci_do_reset(host, SDHCI_RESET_CMD);
3676                 sdhci_do_reset(host, SDHCI_RESET_DATA);
3677         }
3678
3679         pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
3680                  mmc_hostname(mmc), host->ier,
3681                  sdhci_readl(host, SDHCI_INT_STATUS));
3682
3683         spin_unlock_irqrestore(&host->lock, flags);
3684 }
3685 EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
3686
3687 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3688                    int *data_error)
3689 {
3690         u32 mask;
3691
3692         if (!host->cqe_on)
3693                 return false;
3694
3695         if (intmask & (SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC))
3696                 *cmd_error = -EILSEQ;
3697         else if (intmask & SDHCI_INT_TIMEOUT)
3698                 *cmd_error = -ETIMEDOUT;
3699         else
3700                 *cmd_error = 0;
3701
3702         if (intmask & (SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC))
3703                 *data_error = -EILSEQ;
3704         else if (intmask & SDHCI_INT_DATA_TIMEOUT)
3705                 *data_error = -ETIMEDOUT;
3706         else if (intmask & SDHCI_INT_ADMA_ERROR)
3707                 *data_error = -EIO;
3708         else
3709                 *data_error = 0;
3710
3711         /* Clear selected interrupts. */
3712         mask = intmask & host->cqe_ier;
3713         sdhci_writel(host, mask, SDHCI_INT_STATUS);
3714
3715         if (intmask & SDHCI_INT_BUS_POWER)
3716                 pr_err("%s: Card is consuming too much power!\n",
3717                        mmc_hostname(host->mmc));
3718
3719         intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
3720         if (intmask) {
3721                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3722                 pr_err("%s: CQE: Unexpected interrupt 0x%08x.\n",
3723                        mmc_hostname(host->mmc), intmask);
3724                 sdhci_dumpregs(host);
3725         }
3726
3727         return true;
3728 }
3729 EXPORT_SYMBOL_GPL(sdhci_cqe_irq);
3730
3731 /*****************************************************************************\
3732  *                                                                           *
3733  * Device allocation/registration                                            *
3734  *                                                                           *
3735 \*****************************************************************************/
3736
3737 struct sdhci_host *sdhci_alloc_host(struct device *dev,
3738         size_t priv_size)
3739 {
3740         struct mmc_host *mmc;
3741         struct sdhci_host *host;
3742
3743         WARN_ON(dev == NULL);
3744
3745         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
3746         if (!mmc)
3747                 return ERR_PTR(-ENOMEM);
3748
3749         host = mmc_priv(mmc);
3750         host->mmc = mmc;
3751         host->mmc_host_ops = sdhci_ops;
3752         mmc->ops = &host->mmc_host_ops;
3753
3754         host->flags = SDHCI_SIGNALING_330;
3755
3756         host->cqe_ier     = SDHCI_CQE_INT_MASK;
3757         host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3758
3759         host->tuning_delay = -1;
3760         host->tuning_loop_count = MAX_TUNING_LOOP;
3761
3762         host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3763
3764         /*
3765          * The DMA table descriptor count is calculated as the maximum
3766          * number of segments times 2, to allow for an alignment
3767          * descriptor for each segment, plus 1 for a nop end descriptor.
3768          */
3769         host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
3770
3771         return host;
3772 }
3773
3774 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
3775
3776 static int sdhci_set_dma_mask(struct sdhci_host *host)
3777 {
3778         struct mmc_host *mmc = host->mmc;
3779         struct device *dev = mmc_dev(mmc);
3780         int ret = -EINVAL;
3781
3782         if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3783                 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3784
3785         /* Try 64-bit mask if hardware is capable  of it */
3786         if (host->flags & SDHCI_USE_64_BIT_DMA) {
3787                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3788                 if (ret) {
3789                         pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3790                                 mmc_hostname(mmc));
3791                         host->flags &= ~SDHCI_USE_64_BIT_DMA;
3792                 }
3793         }
3794
3795         /* 32-bit mask as default & fallback */
3796         if (ret) {
3797                 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3798                 if (ret)
3799                         pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3800                                 mmc_hostname(mmc));
3801         }
3802
3803         return ret;
3804 }
3805
3806 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
3807                        const u32 *caps, const u32 *caps1)
3808 {
3809         u16 v;
3810         u64 dt_caps_mask = 0;
3811         u64 dt_caps = 0;
3812
3813         if (host->read_caps)
3814                 return;
3815
3816         host->read_caps = true;
3817
3818         if (debug_quirks)
3819                 host->quirks = debug_quirks;
3820
3821         if (debug_quirks2)
3822                 host->quirks2 = debug_quirks2;
3823
3824         sdhci_do_reset(host, SDHCI_RESET_ALL);
3825
3826         if (host->v4_mode)
3827                 sdhci_do_enable_v4_mode(host);
3828
3829         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3830                              "sdhci-caps-mask", &dt_caps_mask);
3831         of_property_read_u64(mmc_dev(host->mmc)->of_node,
3832                              "sdhci-caps", &dt_caps);
3833
3834         v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3835         host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3836
3837         if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3838                 return;
3839
3840         if (caps) {
3841                 host->caps = *caps;
3842         } else {
3843                 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3844                 host->caps &= ~lower_32_bits(dt_caps_mask);
3845                 host->caps |= lower_32_bits(dt_caps);
3846         }
3847
3848         if (host->version < SDHCI_SPEC_300)
3849                 return;
3850
3851         if (caps1) {
3852                 host->caps1 = *caps1;
3853         } else {
3854                 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3855                 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3856                 host->caps1 |= upper_32_bits(dt_caps);
3857         }
3858 }
3859 EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3860
3861 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3862 {
3863         struct mmc_host *mmc = host->mmc;
3864         unsigned int max_blocks;
3865         unsigned int bounce_size;
3866         int ret;
3867
3868         /*
3869          * Cap the bounce buffer at 64KB. Using a bigger bounce buffer
3870          * has diminishing returns, this is probably because SD/MMC
3871          * cards are usually optimized to handle this size of requests.
3872          */
3873         bounce_size = SZ_64K;
3874         /*
3875          * Adjust downwards to maximum request size if this is less
3876          * than our segment size, else hammer down the maximum
3877          * request size to the maximum buffer size.
3878          */
3879         if (mmc->max_req_size < bounce_size)
3880                 bounce_size = mmc->max_req_size;
3881         max_blocks = bounce_size / 512;
3882
3883         /*
3884          * When we just support one segment, we can get significant
3885          * speedups by the help of a bounce buffer to group scattered
3886          * reads/writes together.
3887          */
3888         host->bounce_buffer = devm_kmalloc(mmc->parent,
3889                                            bounce_size,
3890                                            GFP_KERNEL);
3891         if (!host->bounce_buffer) {
3892                 pr_err("%s: failed to allocate %u bytes for bounce buffer, falling back to single segments\n",
3893                        mmc_hostname(mmc),
3894                        bounce_size);
3895                 /*
3896                  * Exiting with zero here makes sure we proceed with
3897                  * mmc->max_segs == 1.
3898                  */
3899                 return;
3900         }
3901
3902         host->bounce_addr = dma_map_single(mmc->parent,
3903                                            host->bounce_buffer,
3904                                            bounce_size,
3905                                            DMA_BIDIRECTIONAL);
3906         ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3907         if (ret)
3908                 /* Again fall back to max_segs == 1 */
3909                 return;
3910         host->bounce_buffer_size = bounce_size;
3911
3912         /* Lie about this since we're bouncing */
3913         mmc->max_segs = max_blocks;
3914         mmc->max_seg_size = bounce_size;
3915         mmc->max_req_size = bounce_size;
3916
3917         pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3918                 mmc_hostname(mmc), max_blocks, bounce_size);
3919 }
3920
3921 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
3922 {
3923         /*
3924          * According to SD Host Controller spec v4.10, bit[27] added from
3925          * version 4.10 in Capabilities Register is used as 64-bit System
3926          * Address support for V4 mode.
3927          */
3928         if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
3929                 return host->caps & SDHCI_CAN_64BIT_V4;
3930
3931         return host->caps & SDHCI_CAN_64BIT;
3932 }
3933
3934 int sdhci_setup_host(struct sdhci_host *host)
3935 {
3936         struct mmc_host *mmc;
3937         u32 max_current_caps;
3938         unsigned int ocr_avail;
3939         unsigned int override_timeout_clk;
3940         u32 max_clk;
3941         int ret;
3942
3943         WARN_ON(host == NULL);
3944         if (host == NULL)
3945                 return -EINVAL;
3946
3947         mmc = host->mmc;
3948
3949         /*
3950          * If there are external regulators, get them. Note this must be done
3951          * early before resetting the host and reading the capabilities so that
3952          * the host can take the appropriate action if regulators are not
3953          * available.
3954          */
3955         ret = mmc_regulator_get_supply(mmc);
3956         if (ret)
3957                 return ret;
3958
3959         DBG("Version:   0x%08x | Present:  0x%08x\n",
3960             sdhci_readw(host, SDHCI_HOST_VERSION),
3961             sdhci_readl(host, SDHCI_PRESENT_STATE));
3962         DBG("Caps:      0x%08x | Caps_1:   0x%08x\n",
3963             sdhci_readl(host, SDHCI_CAPABILITIES),
3964             sdhci_readl(host, SDHCI_CAPABILITIES_1));
3965
3966         sdhci_read_caps(host);
3967
3968         override_timeout_clk = host->timeout_clk;
3969
3970         if (host->version > SDHCI_SPEC_420) {
3971                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3972                        mmc_hostname(mmc), host->version);
3973         }
3974
3975         if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
3976                 mmc->caps2 &= ~MMC_CAP2_CQE;
3977
3978         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3979                 host->flags |= SDHCI_USE_SDMA;
3980         else if (!(host->caps & SDHCI_CAN_DO_SDMA))
3981                 DBG("Controller doesn't have SDMA capability\n");
3982         else
3983                 host->flags |= SDHCI_USE_SDMA;
3984
3985         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
3986                 (host->flags & SDHCI_USE_SDMA)) {
3987                 DBG("Disabling DMA as it is marked broken\n");
3988                 host->flags &= ~SDHCI_USE_SDMA;
3989         }
3990
3991         if ((host->version >= SDHCI_SPEC_200) &&
3992                 (host->caps & SDHCI_CAN_DO_ADMA2))
3993                 host->flags |= SDHCI_USE_ADMA;
3994
3995         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3996                 (host->flags & SDHCI_USE_ADMA)) {
3997                 DBG("Disabling ADMA as it is marked broken\n");
3998                 host->flags &= ~SDHCI_USE_ADMA;
3999         }
4000
4001         if (sdhci_can_64bit_dma(host))
4002                 host->flags |= SDHCI_USE_64_BIT_DMA;
4003
4004         if (host->use_external_dma) {
4005                 ret = sdhci_external_dma_init(host);
4006                 if (ret == -EPROBE_DEFER)
4007                         goto unreg;
4008                 /*
4009                  * Fall back to use the DMA/PIO integrated in standard SDHCI
4010                  * instead of external DMA devices.
4011                  */
4012                 else if (ret)
4013                         sdhci_switch_external_dma(host, false);
4014                 /* Disable internal DMA sources */
4015                 else
4016                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4017         }
4018
4019         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4020                 if (host->ops->set_dma_mask)
4021                         ret = host->ops->set_dma_mask(host);
4022                 else
4023                         ret = sdhci_set_dma_mask(host);
4024
4025                 if (!ret && host->ops->enable_dma)
4026                         ret = host->ops->enable_dma(host);
4027
4028                 if (ret) {
4029                         pr_warn("%s: No suitable DMA available - falling back to PIO\n",
4030                                 mmc_hostname(mmc));
4031                         host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4032
4033                         ret = 0;
4034                 }
4035         }
4036
4037         /* SDMA does not support 64-bit DMA if v4 mode not set */
4038         if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4039                 host->flags &= ~SDHCI_USE_SDMA;
4040
4041         if (host->flags & SDHCI_USE_ADMA) {
4042                 dma_addr_t dma;
4043                 void *buf;
4044
4045                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4046                         host->adma_table_sz = host->adma_table_cnt *
4047                                               SDHCI_ADMA2_64_DESC_SZ(host);
4048                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4049                 } else {
4050                         host->adma_table_sz = host->adma_table_cnt *
4051                                               SDHCI_ADMA2_32_DESC_SZ;
4052                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4053                 }
4054
4055                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4056                 /*
4057                  * Use zalloc to zero the reserved high 32-bits of 128-bit
4058                  * descriptors so that they never need to be written.
4059                  */
4060                 buf = dma_alloc_coherent(mmc_dev(mmc),
4061                                          host->align_buffer_sz + host->adma_table_sz,
4062                                          &dma, GFP_KERNEL);
4063                 if (!buf) {
4064                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
4065                                 mmc_hostname(mmc));
4066                         host->flags &= ~SDHCI_USE_ADMA;
4067                 } else if ((dma + host->align_buffer_sz) &
4068                            (SDHCI_ADMA2_DESC_ALIGN - 1)) {
4069                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
4070                                 mmc_hostname(mmc));
4071                         host->flags &= ~SDHCI_USE_ADMA;
4072                         dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4073                                           host->adma_table_sz, buf, dma);
4074                 } else {
4075                         host->align_buffer = buf;
4076                         host->align_addr = dma;
4077
4078                         host->adma_table = buf + host->align_buffer_sz;
4079                         host->adma_addr = dma + host->align_buffer_sz;
4080                 }
4081         }
4082
4083         /*
4084          * If we use DMA, then it's up to the caller to set the DMA
4085          * mask, but PIO does not need the hw shim so we set a new
4086          * mask here in that case.
4087          */
4088         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4089                 host->dma_mask = DMA_BIT_MASK(64);
4090                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4091         }
4092
4093         if (host->version >= SDHCI_SPEC_300)
4094                 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
4095                         >> SDHCI_CLOCK_BASE_SHIFT;
4096         else
4097                 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
4098                         >> SDHCI_CLOCK_BASE_SHIFT;
4099
4100         host->max_clk *= 1000000;
4101         if (host->max_clk == 0 || host->quirks &
4102                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4103                 if (!host->ops->get_max_clock) {
4104                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4105                                mmc_hostname(mmc));
4106                         ret = -ENODEV;
4107                         goto undma;
4108                 }
4109                 host->max_clk = host->ops->get_max_clock(host);
4110         }
4111
4112         /*
4113          * In case of Host Controller v3.00, find out whether clock
4114          * multiplier is supported.
4115          */
4116         host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
4117                         SDHCI_CLOCK_MUL_SHIFT;
4118
4119         /*
4120          * In case the value in Clock Multiplier is 0, then programmable
4121          * clock mode is not supported, otherwise the actual clock
4122          * multiplier is one more than the value of Clock Multiplier
4123          * in the Capabilities Register.
4124          */
4125         if (host->clk_mul)
4126                 host->clk_mul += 1;
4127
4128         /*
4129          * Set host parameters.
4130          */
4131         max_clk = host->max_clk;
4132
4133         if (host->ops->get_min_clock)
4134                 mmc->f_min = host->ops->get_min_clock(host);
4135         else if (host->version >= SDHCI_SPEC_300) {
4136                 if (host->clk_mul)
4137                         max_clk = host->max_clk * host->clk_mul;
4138                 /*
4139                  * Divided Clock Mode minimum clock rate is always less than
4140                  * Programmable Clock Mode minimum clock rate.
4141                  */
4142                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4143         } else
4144                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4145
4146         if (!mmc->f_max || mmc->f_max > max_clk)
4147                 mmc->f_max = max_clk;
4148
4149         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4150                 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
4151                                         SDHCI_TIMEOUT_CLK_SHIFT;
4152
4153                 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4154                         host->timeout_clk *= 1000;
4155
4156                 if (host->timeout_clk == 0) {
4157                         if (!host->ops->get_timeout_clock) {
4158                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
4159                                         mmc_hostname(mmc));
4160                                 ret = -ENODEV;
4161                                 goto undma;
4162                         }
4163
4164                         host->timeout_clk =
4165                                 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4166                                              1000);
4167                 }
4168
4169                 if (override_timeout_clk)
4170                         host->timeout_clk = override_timeout_clk;
4171
4172                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4173                         host->ops->get_max_timeout_count(host) : 1 << 27;
4174                 mmc->max_busy_timeout /= host->timeout_clk;
4175         }
4176
4177         if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4178             !host->ops->get_max_timeout_count)
4179                 mmc->max_busy_timeout = 0;
4180
4181         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
4182         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
4183
4184         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4185                 host->flags |= SDHCI_AUTO_CMD12;
4186
4187         /*
4188          * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
4189          * For v4 mode, SDMA may use Auto-CMD23 as well.
4190          */
4191         if ((host->version >= SDHCI_SPEC_300) &&
4192             ((host->flags & SDHCI_USE_ADMA) ||
4193              !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4194              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4195                 host->flags |= SDHCI_AUTO_CMD23;
4196                 DBG("Auto-CMD23 available\n");
4197         } else {
4198                 DBG("Auto-CMD23 unavailable\n");
4199         }
4200
4201         /*
4202          * A controller may support 8-bit width, but the board itself
4203          * might not have the pins brought out.  Boards that support
4204          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
4205          * their platform code before calling sdhci_add_host(), and we
4206          * won't assume 8-bit width for hosts without that CAP.
4207          */
4208         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4209                 mmc->caps |= MMC_CAP_4_BIT_DATA;
4210
4211         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4212                 mmc->caps &= ~MMC_CAP_CMD23;
4213
4214         if (host->caps & SDHCI_CAN_DO_HISPD)
4215                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4216
4217         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4218             mmc_card_is_removable(mmc) &&
4219             mmc_gpio_get_cd(host->mmc) < 0)
4220                 mmc->caps |= MMC_CAP_NEEDS_POLL;
4221
4222         if (!IS_ERR(mmc->supply.vqmmc)) {
4223                 ret = regulator_enable(mmc->supply.vqmmc);
4224
4225                 /* If vqmmc provides no 1.8V signalling, then there's no UHS */
4226                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
4227                                                     1950000))
4228                         host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4229                                          SDHCI_SUPPORT_SDR50 |
4230                                          SDHCI_SUPPORT_DDR50);
4231
4232                 /* In eMMC case vqmmc might be a fixed 1.8V regulator */
4233                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
4234                                                     3600000))
4235                         host->flags &= ~SDHCI_SIGNALING_330;
4236
4237                 if (ret) {
4238                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
4239                                 mmc_hostname(mmc), ret);
4240                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
4241                 }
4242         }
4243
4244         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4245                 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4246                                  SDHCI_SUPPORT_DDR50);
4247                 /*
4248                  * The SDHCI controller in a SoC might support HS200/HS400
4249                  * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
4250                  * but if the board is modeled such that the IO lines are not
4251                  * connected to 1.8v then HS200/HS400 cannot be supported.
4252                  * Disable HS200/HS400 if the board does not have 1.8v connected
4253                  * to the IO lines. (Applicable for other modes in 1.8v)
4254                  */
4255                 mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
4256                 mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
4257         }
4258
4259         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
4260         if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4261                            SDHCI_SUPPORT_DDR50))
4262                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
4263
4264         /* SDR104 supports also implies SDR50 support */
4265         if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4266                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4267                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
4268                  * field can be promoted to support HS200.
4269                  */
4270                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4271                         mmc->caps2 |= MMC_CAP2_HS200;
4272         } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4273                 mmc->caps |= MMC_CAP_UHS_SDR50;
4274         }
4275
4276         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4277             (host->caps1 & SDHCI_SUPPORT_HS400))
4278                 mmc->caps2 |= MMC_CAP2_HS400;
4279
4280         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
4281             (IS_ERR(mmc->supply.vqmmc) ||
4282              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
4283                                              1300000)))
4284                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
4285
4286         if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4287             !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4288                 mmc->caps |= MMC_CAP_UHS_DDR50;
4289
4290         /* Does the host need tuning for SDR50? */
4291         if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4292                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4293
4294         /* Driver Type(s) (A, C, D) supported by the host */
4295         if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4296                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
4297         if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4298                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
4299         if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4300                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
4301
4302         /* Initial value for re-tuning timer count */
4303         host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
4304                              SDHCI_RETUNING_TIMER_COUNT_SHIFT;
4305
4306         /*
4307          * In case Re-tuning Timer is not disabled, the actual value of
4308          * re-tuning timer will be 2 ^ (n - 1).
4309          */
4310         if (host->tuning_count)
4311                 host->tuning_count = 1 << (host->tuning_count - 1);
4312
4313         /* Re-tuning mode supported by the Host Controller */
4314         host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
4315                              SDHCI_RETUNING_MODE_SHIFT;
4316
4317         ocr_avail = 0;
4318
4319         /*
4320          * According to SD Host Controller spec v3.00, if the Host System
4321          * can afford more than 150mA, Host Driver should set XPC to 1. Also
4322          * the value is meaningful only if Voltage Support in the Capabilities
4323          * register is set. The actual current value is 4 times the register
4324          * value.
4325          */
4326         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4327         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
4328                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
4329                 if (curr > 0) {
4330
4331                         /* convert to SDHCI_MAX_CURRENT format */
4332                         curr = curr/1000;  /* convert to mA */
4333                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
4334
4335                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
4336                         max_current_caps =
4337                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
4338                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
4339                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
4340                 }
4341         }
4342
4343         if (host->caps & SDHCI_CAN_VDD_330) {
4344                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
4345
4346                 mmc->max_current_330 = ((max_current_caps &
4347                                    SDHCI_MAX_CURRENT_330_MASK) >>
4348                                    SDHCI_MAX_CURRENT_330_SHIFT) *
4349                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4350         }
4351         if (host->caps & SDHCI_CAN_VDD_300) {
4352                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
4353
4354                 mmc->max_current_300 = ((max_current_caps &
4355                                    SDHCI_MAX_CURRENT_300_MASK) >>
4356                                    SDHCI_MAX_CURRENT_300_SHIFT) *
4357                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4358         }
4359         if (host->caps & SDHCI_CAN_VDD_180) {
4360                 ocr_avail |= MMC_VDD_165_195;
4361
4362                 mmc->max_current_180 = ((max_current_caps &
4363                                    SDHCI_MAX_CURRENT_180_MASK) >>
4364                                    SDHCI_MAX_CURRENT_180_SHIFT) *
4365                                    SDHCI_MAX_CURRENT_MULTIPLIER;
4366         }
4367
4368         /* If OCR set by host, use it instead. */
4369         if (host->ocr_mask)
4370                 ocr_avail = host->ocr_mask;
4371
4372         /* If OCR set by external regulators, give it highest prio. */
4373         if (mmc->ocr_avail)
4374                 ocr_avail = mmc->ocr_avail;
4375
4376         mmc->ocr_avail = ocr_avail;
4377         mmc->ocr_avail_sdio = ocr_avail;
4378         if (host->ocr_avail_sdio)
4379                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4380         mmc->ocr_avail_sd = ocr_avail;
4381         if (host->ocr_avail_sd)
4382                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4383         else /* normal SD controllers don't support 1.8V */
4384                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
4385         mmc->ocr_avail_mmc = ocr_avail;
4386         if (host->ocr_avail_mmc)
4387                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4388
4389         if (mmc->ocr_avail == 0) {
4390                 pr_err("%s: Hardware doesn't report any support voltages.\n",
4391                        mmc_hostname(mmc));
4392                 ret = -ENODEV;
4393                 goto unreg;
4394         }
4395
4396         if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
4397                           MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
4398                           MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
4399             (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
4400                 host->flags |= SDHCI_SIGNALING_180;
4401
4402         if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
4403                 host->flags |= SDHCI_SIGNALING_120;
4404
4405         spin_lock_init(&host->lock);
4406
4407         /*
4408          * Maximum number of sectors in one transfer. Limited by SDMA boundary
4409          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
4410          * is less anyway.
4411          */
4412         mmc->max_req_size = 524288;
4413
4414         /*
4415          * Maximum number of segments. Depends on if the hardware
4416          * can do scatter/gather or not.
4417          */
4418         if (host->flags & SDHCI_USE_ADMA) {
4419                 mmc->max_segs = SDHCI_MAX_SEGS;
4420         } else if (host->flags & SDHCI_USE_SDMA) {
4421                 mmc->max_segs = 1;
4422                 if (swiotlb_max_segment()) {
4423                         unsigned int max_req_size = (1 << IO_TLB_SHIFT) *
4424                                                 IO_TLB_SEGSIZE;
4425                         mmc->max_req_size = min(mmc->max_req_size,
4426                                                 max_req_size);
4427                 }
4428         } else { /* PIO */
4429                 mmc->max_segs = SDHCI_MAX_SEGS;
4430         }
4431
4432         /*
4433          * Maximum segment size. Could be one segment with the maximum number
4434          * of bytes. When doing hardware scatter/gather, each entry cannot
4435          * be larger than 64 KiB though.
4436          */
4437         if (host->flags & SDHCI_USE_ADMA) {
4438                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
4439                         mmc->max_seg_size = 65535;
4440                 else
4441                         mmc->max_seg_size = 65536;
4442         } else {
4443                 mmc->max_seg_size = mmc->max_req_size;
4444         }
4445
4446         /*
4447          * Maximum block size. This varies from controller to controller and
4448          * is specified in the capabilities register.
4449          */
4450         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4451                 mmc->max_blk_size = 2;
4452         } else {
4453                 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4454                                 SDHCI_MAX_BLOCK_SHIFT;
4455                 if (mmc->max_blk_size >= 3) {
4456                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
4457                                 mmc_hostname(mmc));
4458                         mmc->max_blk_size = 0;
4459                 }
4460         }
4461
4462         mmc->max_blk_size = 512 << mmc->max_blk_size;
4463
4464         /*
4465          * Maximum block count.
4466          */
4467         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4468
4469         if (mmc->max_segs == 1)
4470                 /* This may alter mmc->*_blk_* parameters */
4471                 sdhci_allocate_bounce_buffer(host);
4472
4473         return 0;
4474
4475 unreg:
4476         if (!IS_ERR(mmc->supply.vqmmc))
4477                 regulator_disable(mmc->supply.vqmmc);
4478 undma:
4479         if (host->align_buffer)
4480                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4481                                   host->adma_table_sz, host->align_buffer,
4482                                   host->align_addr);
4483         host->adma_table = NULL;
4484         host->align_buffer = NULL;
4485
4486         return ret;
4487 }
4488 EXPORT_SYMBOL_GPL(sdhci_setup_host);
4489
4490 void sdhci_cleanup_host(struct sdhci_host *host)
4491 {
4492         struct mmc_host *mmc = host->mmc;
4493
4494         if (!IS_ERR(mmc->supply.vqmmc))
4495                 regulator_disable(mmc->supply.vqmmc);
4496
4497         if (host->align_buffer)
4498                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4499                                   host->adma_table_sz, host->align_buffer,
4500                                   host->align_addr);
4501
4502         if (host->use_external_dma)
4503                 sdhci_external_dma_release(host);
4504
4505         host->adma_table = NULL;
4506         host->align_buffer = NULL;
4507 }
4508 EXPORT_SYMBOL_GPL(sdhci_cleanup_host);
4509
4510 int __sdhci_add_host(struct sdhci_host *host)
4511 {
4512         unsigned int flags = WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI;
4513         struct mmc_host *mmc = host->mmc;
4514         int ret;
4515
4516         host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4517         if (!host->complete_wq)
4518                 return -ENOMEM;
4519
4520         INIT_WORK(&host->complete_work, sdhci_complete_work);
4521
4522         timer_setup(&host->timer, sdhci_timeout_timer, 0);
4523         timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4524
4525         init_waitqueue_head(&host->buf_ready_int);
4526
4527         sdhci_init(host, 0);
4528
4529         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4530                                    IRQF_SHARED, mmc_hostname(mmc), host);
4531         if (ret) {
4532                 pr_err("%s: Failed to request IRQ %d: %d\n",
4533                        mmc_hostname(mmc), host->irq, ret);
4534                 goto unwq;
4535         }
4536
4537         ret = sdhci_led_register(host);
4538         if (ret) {
4539                 pr_err("%s: Failed to register LED device: %d\n",
4540                        mmc_hostname(mmc), ret);
4541                 goto unirq;
4542         }
4543
4544         ret = mmc_add_host(mmc);
4545         if (ret)
4546                 goto unled;
4547
4548         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4549                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4550                 host->use_external_dma ? "External DMA" :
4551                 (host->flags & SDHCI_USE_ADMA) ?
4552                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4553                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4554
4555         sdhci_enable_card_detection(host);
4556
4557         return 0;
4558
4559 unled:
4560         sdhci_led_unregister(host);
4561 unirq:
4562         sdhci_do_reset(host, SDHCI_RESET_ALL);
4563         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4564         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4565         free_irq(host->irq, host);
4566 unwq:
4567         destroy_workqueue(host->complete_wq);
4568
4569         return ret;
4570 }
4571 EXPORT_SYMBOL_GPL(__sdhci_add_host);
4572
4573 int sdhci_add_host(struct sdhci_host *host)
4574 {
4575         int ret;
4576
4577         ret = sdhci_setup_host(host);
4578         if (ret)
4579                 return ret;
4580
4581         ret = __sdhci_add_host(host);
4582         if (ret)
4583                 goto cleanup;
4584
4585         return 0;
4586
4587 cleanup:
4588         sdhci_cleanup_host(host);
4589
4590         return ret;
4591 }
4592 EXPORT_SYMBOL_GPL(sdhci_add_host);
4593
4594 void sdhci_remove_host(struct sdhci_host *host, int dead)
4595 {
4596         struct mmc_host *mmc = host->mmc;
4597         unsigned long flags;
4598
4599         if (dead) {
4600                 spin_lock_irqsave(&host->lock, flags);
4601
4602                 host->flags |= SDHCI_DEVICE_DEAD;
4603
4604                 if (sdhci_has_requests(host)) {
4605                         pr_err("%s: Controller removed during "
4606                                 " transfer!\n", mmc_hostname(mmc));
4607                         sdhci_error_out_mrqs(host, -ENOMEDIUM);
4608                 }
4609
4610                 spin_unlock_irqrestore(&host->lock, flags);
4611         }
4612
4613         sdhci_disable_card_detection(host);
4614
4615         mmc_remove_host(mmc);
4616
4617         sdhci_led_unregister(host);
4618
4619         if (!dead)
4620                 sdhci_do_reset(host, SDHCI_RESET_ALL);
4621
4622         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4623         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4624         free_irq(host->irq, host);
4625
4626         del_timer_sync(&host->timer);
4627         del_timer_sync(&host->data_timer);
4628
4629         destroy_workqueue(host->complete_wq);
4630
4631         if (!IS_ERR(mmc->supply.vqmmc))
4632                 regulator_disable(mmc->supply.vqmmc);
4633
4634         if (host->align_buffer)
4635                 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4636                                   host->adma_table_sz, host->align_buffer,
4637                                   host->align_addr);
4638
4639         if (host->use_external_dma)
4640                 sdhci_external_dma_release(host);
4641
4642         host->adma_table = NULL;
4643         host->align_buffer = NULL;
4644 }
4645
4646 EXPORT_SYMBOL_GPL(sdhci_remove_host);
4647
4648 void sdhci_free_host(struct sdhci_host *host)
4649 {
4650         mmc_free_host(host->mmc);
4651 }
4652
4653 EXPORT_SYMBOL_GPL(sdhci_free_host);
4654
4655 /*****************************************************************************\
4656  *                                                                           *
4657  * Driver init/exit                                                          *
4658  *                                                                           *
4659 \*****************************************************************************/
4660
4661 static int __init sdhci_drv_init(void)
4662 {
4663         pr_info(DRIVER_NAME
4664                 ": Secure Digital Host Controller Interface driver\n");
4665         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
4666
4667         return 0;
4668 }
4669
4670 static void __exit sdhci_drv_exit(void)
4671 {
4672 }
4673
4674 module_init(sdhci_drv_init);
4675 module_exit(sdhci_drv_exit);
4676
4677 module_param(debug_quirks, uint, 0444);
4678 module_param(debug_quirks2, uint, 0444);
4679
4680 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
4681 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
4682 MODULE_LICENSE("GPL");
4683
4684 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
4685 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");