drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_finish_command(struct sdhci_host *);
  53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  54 static void sdhci_tuning_timer(unsigned long data);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data,
  58                                         struct sdhci_host_next *next);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 210                         SDHCI_CARD_PRESENT))
 211                         return;
 212         }
 213
 214         host->ops->reset(host, mask);
 215
 216         if (mask & SDHCI_RESET_ALL) {
 217                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 218                         if (host->ops->enable_dma)
 219                                 host->ops->enable_dma(host);
 220                 }
 221
 222                 /* Resetting the controller clears many */
 223                 host->preset_enabled = false;
 224         }
 225 }
 226
 227 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 228
 229 static void sdhci_init(struct sdhci_host *host, int soft)
 230 {
 231         if (soft)
 232                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 233         else
 234                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 235
 236         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 237                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 238                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 239                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 240                     SDHCI_INT_RESPONSE;
 241
 242         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 243         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 244
 245         if (soft) {
 246                 /* force clock reconfiguration */
 247                 host->clock = 0;
 248                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 249         }
 250 }
 251
 252 static void sdhci_reinit(struct sdhci_host *host)
 253 {
 254         sdhci_init(host, 0);
 255         /*
 256          * Retuning stuffs are affected by different cards inserted and only
 257          * applicable to UHS-I cards. So reset these fields to their initial
 258          * value when card is removed.
 259          */
 260         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 261                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 262
 263                 del_timer_sync(&host->tuning_timer);
 264                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 265         }
 266         sdhci_enable_card_detection(host);
 267 }
 268
 269 static void sdhci_activate_led(struct sdhci_host *host)
 270 {
 271         u8 ctrl;
 272
 273         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 274         ctrl |= SDHCI_CTRL_LED;
 275         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 276 }
 277
 278 static void sdhci_deactivate_led(struct sdhci_host *host)
 279 {
 280         u8 ctrl;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283         ctrl &= ~SDHCI_CTRL_LED;
 284         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 285 }
 286
 287 #ifdef SDHCI_USE_LEDS_CLASS
 288 static void sdhci_led_control(struct led_classdev *led,
 289         enum led_brightness brightness)
 290 {
 291         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 292         unsigned long flags;
 293
 294         spin_lock_irqsave(&host->lock, flags);
 295
 296         if (host->runtime_suspended)
 297                 goto out;
 298
 299         if (brightness == LED_OFF)
 300                 sdhci_deactivate_led(host);
 301         else
 302                 sdhci_activate_led(host);
 303 out:
 304         spin_unlock_irqrestore(&host->lock, flags);
 305 }
 306 #endif
 307
 308 /*****************************************************************************\
 309  *                                                                           *
 310  * Core functions                                                            *
 311  *                                                                           *
 312 \*****************************************************************************/
 313
 314 static void sdhci_read_block_pio(struct sdhci_host *host)
 315 {
 316         unsigned long flags;
 317         size_t blksize, len, chunk;
 318         u32 uninitialized_var(scratch);
 319         u8 *buf;
 320
 321         DBG("PIO reading\n");
 322
 323         blksize = host->data->blksz;
 324         chunk = 0;
 325
 326         local_irq_save(flags);
 327
 328         while (blksize) {
 329                 if (!sg_miter_next(&host->sg_miter))
 330                         BUG();
 331
 332                 len = min(host->sg_miter.length, blksize);
 333
 334                 blksize -= len;
 335                 host->sg_miter.consumed = len;
 336
 337                 buf = host->sg_miter.addr;
 338
 339                 while (len) {
 340                         if (chunk == 0) {
 341                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 342                                 chunk = 4;
 343                         }
 344
 345                         *buf = scratch & 0xFF;
 346
 347                         buf++;
 348                         scratch >>= 8;
 349                         chunk--;
 350                         len--;
 351                 }
 352         }
 353
 354         sg_miter_stop(&host->sg_miter);
 355
 356         local_irq_restore(flags);
 357 }
 358
 359 static void sdhci_write_block_pio(struct sdhci_host *host)
 360 {
 361         unsigned long flags;
 362         size_t blksize, len, chunk;
 363         u32 scratch;
 364         u8 *buf;
 365
 366         DBG("PIO writing\n");
 367
 368         blksize = host->data->blksz;
 369         chunk = 0;
 370         scratch = 0;
 371
 372         local_irq_save(flags);
 373
 374         while (blksize) {
 375                 if (!sg_miter_next(&host->sg_miter))
 376                         BUG();
 377
 378                 len = min(host->sg_miter.length, blksize);
 379
 380                 blksize -= len;
 381                 host->sg_miter.consumed = len;
 382
 383                 buf = host->sg_miter.addr;
 384
 385                 while (len) {
 386                         scratch |= (u32)*buf << (chunk * 8);
 387
 388                         buf++;
 389                         chunk++;
 390                         len--;
 391
 392                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 393                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 394                                 chunk = 0;
 395                                 scratch = 0;
 396                         }
 397                 }
 398         }
 399
 400         sg_miter_stop(&host->sg_miter);
 401
 402         local_irq_restore(flags);
 403 }
 404
 405 static void sdhci_transfer_pio(struct sdhci_host *host)
 406 {
 407         u32 mask;
 408
 409         BUG_ON(!host->data);
 410
 411         if (host->blocks == 0)
 412                 return;
 413
 414         if (host->data->flags & MMC_DATA_READ)
 415                 mask = SDHCI_DATA_AVAILABLE;
 416         else
 417                 mask = SDHCI_SPACE_AVAILABLE;
 418
 419         /*
 420          * Some controllers (JMicron JMB38x) mess up the buffer bits
 421          * for transfers < 4 bytes. As long as it is just one block,
 422          * we can ignore the bits.
 423          */
 424         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 425                 (host->data->blocks == 1))
 426                 mask = ~0;
 427
 428         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 429                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 430                         udelay(100);
 431
 432                 if (host->data->flags & MMC_DATA_READ)
 433                         sdhci_read_block_pio(host);
 434                 else
 435                         sdhci_write_block_pio(host);
 436
 437                 host->blocks--;
 438                 if (host->blocks == 0)
 439                         break;
 440         }
 441
 442         DBG("PIO transfer complete.\n");
 443 }
 444
 445 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 446 {
 447         local_irq_save(*flags);
 448         return kmap_atomic(sg_page(sg)) + sg->offset;
 449 }
 450
 451 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 452 {
 453         kunmap_atomic(buffer);
 454         local_irq_restore(*flags);
 455 }
 456
 457 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 458                                   dma_addr_t addr, int len, unsigned cmd)
 459 {
 460         struct sdhci_adma2_64_desc *dma_desc = desc;
 461
 462         /* 32-bit and 64-bit descriptors have these members in same position */
 463         dma_desc->cmd = cpu_to_le16(cmd);
 464         dma_desc->len = cpu_to_le16(len);
 465         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 466
 467         if (host->flags & SDHCI_USE_64_BIT_DMA)
 468                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 469 }
 470
 471 static void sdhci_adma_mark_end(void *desc)
 472 {
 473         struct sdhci_adma2_64_desc *dma_desc = desc;
 474
 475         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 476         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 477 }
 478
 479 static int sdhci_adma_table_pre(struct sdhci_host *host,
 480         struct mmc_data *data)
 481 {
 482         int direction;
 483
 484         void *desc;
 485         void *align;
 486         dma_addr_t addr;
 487         dma_addr_t align_addr;
 488         int len, offset;
 489
 490         struct scatterlist *sg;
 491         int i;
 492         char *buffer;
 493         unsigned long flags;
 494
 495         /*
 496          * The spec does not specify endianness of descriptor table.
 497          * We currently guess that it is LE.
 498          */
 499
 500         if (data->flags & MMC_DATA_READ)
 501                 direction = DMA_FROM_DEVICE;
 502         else
 503                 direction = DMA_TO_DEVICE;
 504
 505         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 506                 host->align_buffer, host->align_buffer_sz, direction);
 507         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 508                 goto fail;
 509         BUG_ON(host->align_addr & host->align_mask);
 510
 511         host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
 512         if (host->sg_count < 0)
 513                 goto unmap_align;
 514
 515         desc = host->adma_table;
 516         align = host->align_buffer;
 517
 518         align_addr = host->align_addr;
 519
 520         for_each_sg(data->sg, sg, host->sg_count, i) {
 521                 addr = sg_dma_address(sg);
 522                 len = sg_dma_len(sg);
 523
 524                 /*
 525                  * The SDHCI specification states that ADMA
 526                  * addresses must be 32-bit aligned. If they
 527                  * aren't, then we use a bounce buffer for
 528                  * the (up to three) bytes that screw up the
 529                  * alignment.
 530                  */
 531                 offset = (host->align_sz - (addr & host->align_mask)) &
 532                          host->align_mask;
 533                 if (offset) {
 534                         if (data->flags & MMC_DATA_WRITE) {
 535                                 buffer = sdhci_kmap_atomic(sg, &flags);
 536                                 memcpy(align, buffer, offset);
 537                                 sdhci_kunmap_atomic(buffer, &flags);
 538                         }
 539
 540                         /* tran, valid */
 541                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 542                                               ADMA2_TRAN_VALID);
 543
 544                         BUG_ON(offset > 65536);
 545
 546                         align += host->align_sz;
 547                         align_addr += host->align_sz;
 548
 549                         desc += host->desc_sz;
 550
 551                         addr += offset;
 552                         len -= offset;
 553                 }
 554
 555                 BUG_ON(len > 65536);
 556
 557                 /* tran, valid */
 558                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
 559                 desc += host->desc_sz;
 560
 561                 /*
 562                  * If this triggers then we have a calculation bug
 563                  * somewhere. :/
 564                  */
 565                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 566         }
 567
 568         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 569                 /*
 570                 * Mark the last descriptor as the terminating descriptor
 571                 */
 572                 if (desc != host->adma_table) {
 573                         desc -= host->desc_sz;
 574                         sdhci_adma_mark_end(desc);
 575                 }
 576         } else {
 577                 /*
 578                 * Add a terminating entry.
 579                 */
 580
 581                 /* nop, end, valid */
 582                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 583         }
 584
 585         /*
 586          * Resync align buffer as we might have changed it.
 587          */
 588         if (data->flags & MMC_DATA_WRITE) {
 589                 dma_sync_single_for_device(mmc_dev(host->mmc),
 590                         host->align_addr, host->align_buffer_sz, direction);
 591         }
 592
 593         return 0;
 594
 595 unmap_align:
 596         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 597                 host->align_buffer_sz, direction);
 598 fail:
 599         return -EINVAL;
 600 }
 601
 602 static void sdhci_adma_table_post(struct sdhci_host *host,
 603         struct mmc_data *data)
 604 {
 605         int direction;
 606
 607         struct scatterlist *sg;
 608         int i, size;
 609         void *align;
 610         char *buffer;
 611         unsigned long flags;
 612         bool has_unaligned;
 613
 614         if (data->flags & MMC_DATA_READ)
 615                 direction = DMA_FROM_DEVICE;
 616         else
 617                 direction = DMA_TO_DEVICE;
 618
 619         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 620                 host->align_buffer_sz, direction);
 621
 622         /* Do a quick scan of the SG list for any unaligned mappings */
 623         has_unaligned = false;
 624         for_each_sg(data->sg, sg, host->sg_count, i)
 625                 if (sg_dma_address(sg) & host->align_mask) {
 626                         has_unaligned = true;
 627                         break;
 628                 }
 629
 630         if (has_unaligned && data->flags & MMC_DATA_READ) {
 631                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 632                         data->sg_len, direction);
 633
 634                 align = host->align_buffer;
 635
 636                 for_each_sg(data->sg, sg, host->sg_count, i) {
 637                         if (sg_dma_address(sg) & host->align_mask) {
 638                                 size = host->align_sz -
 639                                        (sg_dma_address(sg) & host->align_mask);
 640
 641                                 buffer = sdhci_kmap_atomic(sg, &flags);
 642                                 memcpy(buffer, align, size);
 643                                 sdhci_kunmap_atomic(buffer, &flags);
 644
 645                                 align += host->align_sz;
 646                         }
 647                 }
 648         }
 649
 650         if (!data->host_cookie)
 651                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 652                         data->sg_len, direction);
 653 }
 654
 655 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 656 {
 657         u8 count;
 658         struct mmc_data *data = cmd->data;
 659         unsigned target_timeout, current_timeout;
 660
 661         /*
 662          * If the host controller provides us with an incorrect timeout
 663          * value, just skip the check and use 0xE.  The hardware may take
 664          * longer to time out, but that's much better than having a too-short
 665          * timeout value.
 666          */
 667         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 668                 return 0xE;
 669
 670         /* Unspecified timeout, assume max */
 671         if (!data && !cmd->busy_timeout)
 672                 return 0xE;
 673
 674         /* timeout in us */
 675         if (!data)
 676                 target_timeout = cmd->busy_timeout * 1000;
 677         else {
 678                 target_timeout = data->timeout_ns / 1000;
 679                 if (host->clock)
 680                         target_timeout += data->timeout_clks / host->clock;
 681         }
 682
 683         /*
 684          * Figure out needed cycles.
 685          * We do this in steps in order to fit inside a 32 bit int.
 686          * The first step is the minimum timeout, which will have a
 687          * minimum resolution of 6 bits:
 688          * (1) 2^13*1000 > 2^22,
 689          * (2) host->timeout_clk < 2^16
 690          *     =>
 691          *     (1) / (2) > 2^6
 692          */
 693         count = 0;
 694         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 695         while (current_timeout < target_timeout) {
 696                 count++;
 697                 current_timeout <<= 1;
 698                 if (count >= 0xF)
 699                         break;
 700         }
 701
 702         if (count >= 0xF) {
 703                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 704                     mmc_hostname(host->mmc), count, cmd->opcode);
 705                 count = 0xE;
 706         }
 707
 708         return count;
 709 }
 710
 711 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 712 {
 713         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 714         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 715
 716         if (host->flags & SDHCI_REQ_USE_DMA)
 717                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 718         else
 719                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 720
 721         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 722         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 723 }
 724
 725 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 726 {
 727         u8 count;
 728
 729         if (host->ops->set_timeout) {
 730                 host->ops->set_timeout(host, cmd);
 731         } else {
 732                 count = sdhci_calc_timeout(host, cmd);
 733                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 734         }
 735 }
 736
 737 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 738 {
 739         u8 ctrl;
 740         struct mmc_data *data = cmd->data;
 741         int ret;
 742
 743         WARN_ON(host->data);
 744
 745         if (data || (cmd->flags & MMC_RSP_BUSY))
 746                 sdhci_set_timeout(host, cmd);
 747
 748         if (!data)
 749                 return;
 750
 751         /* Sanity checks */
 752         BUG_ON(data->blksz * data->blocks > 524288);
 753         BUG_ON(data->blksz > host->mmc->max_blk_size);
 754         BUG_ON(data->blocks > 65535);
 755
 756         host->data = data;
 757         host->data_early = 0;
 758         host->data->bytes_xfered = 0;
 759
 760         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 761                 host->flags |= SDHCI_REQ_USE_DMA;
 762
 763         /*
 764          * FIXME: This doesn't account for merging when mapping the
 765          * scatterlist.
 766          */
 767         if (host->flags & SDHCI_REQ_USE_DMA) {
 768                 int broken, i;
 769                 struct scatterlist *sg;
 770
 771                 broken = 0;
 772                 if (host->flags & SDHCI_USE_ADMA) {
 773                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 774                                 broken = 1;
 775                 } else {
 776                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 777                                 broken = 1;
 778                 }
 779
 780                 if (unlikely(broken)) {
 781                         for_each_sg(data->sg, sg, data->sg_len, i) {
 782                                 if (sg->length & 0x3) {
 783                                         DBG("Reverting to PIO because of "
 784                                                 "transfer size (%d)\n",
 785                                                 sg->length);
 786                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 787                                         break;
 788                                 }
 789                         }
 790                 }
 791         }
 792
 793         /*
 794          * The assumption here being that alignment is the same after
 795          * translation to device address space.
 796          */
 797         if (host->flags & SDHCI_REQ_USE_DMA) {
 798                 int broken, i;
 799                 struct scatterlist *sg;
 800
 801                 broken = 0;
 802                 if (host->flags & SDHCI_USE_ADMA) {
 803                         /*
 804                          * As we use 3 byte chunks to work around
 805                          * alignment problems, we need to check this
 806                          * quirk.
 807                          */
 808                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 809                                 broken = 1;
 810                 } else {
 811                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 812                                 broken = 1;
 813                 }
 814
 815                 if (unlikely(broken)) {
 816                         for_each_sg(data->sg, sg, data->sg_len, i) {
 817                                 if (sg->offset & 0x3) {
 818                                         DBG("Reverting to PIO because of "
 819                                                 "bad alignment\n");
 820                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 821                                         break;
 822                                 }
 823                         }
 824                 }
 825         }
 826
 827         if (host->flags & SDHCI_REQ_USE_DMA) {
 828                 if (host->flags & SDHCI_USE_ADMA) {
 829                         ret = sdhci_adma_table_pre(host, data);
 830                         if (ret) {
 831                                 /*
 832                                  * This only happens when someone fed
 833                                  * us an invalid request.
 834                                  */
 835                                 WARN_ON(1);
 836                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 837                         } else {
 838                                 sdhci_writel(host, host->adma_addr,
 839                                         SDHCI_ADMA_ADDRESS);
 840                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 841                                         sdhci_writel(host,
 842                                                      (u64)host->adma_addr >> 32,
 843                                                      SDHCI_ADMA_ADDRESS_HI);
 844                         }
 845                 } else {
 846                         int sg_cnt;
 847
 848                         sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
 849                         if (sg_cnt == 0) {
 850                                 /*
 851                                  * This only happens when someone fed
 852                                  * us an invalid request.
 853                                  */
 854                                 WARN_ON(1);
 855                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 856                         } else {
 857                                 WARN_ON(sg_cnt != 1);
 858                                 sdhci_writel(host, sg_dma_address(data->sg),
 859                                         SDHCI_DMA_ADDRESS);
 860                         }
 861                 }
 862         }
 863
 864         /*
 865          * Always adjust the DMA selection as some controllers
 866          * (e.g. JMicron) can't do PIO properly when the selection
 867          * is ADMA.
 868          */
 869         if (host->version >= SDHCI_SPEC_200) {
 870                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 871                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 872                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 873                         (host->flags & SDHCI_USE_ADMA)) {
 874                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 875                                 ctrl |= SDHCI_CTRL_ADMA64;
 876                         else
 877                                 ctrl |= SDHCI_CTRL_ADMA32;
 878                 } else {
 879                         ctrl |= SDHCI_CTRL_SDMA;
 880                 }
 881                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 882         }
 883
 884         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 885                 int flags;
 886
 887                 flags = SG_MITER_ATOMIC;
 888                 if (host->data->flags & MMC_DATA_READ)
 889                         flags |= SG_MITER_TO_SG;
 890                 else
 891                         flags |= SG_MITER_FROM_SG;
 892                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 893                 host->blocks = data->blocks;
 894         }
 895
 896         sdhci_set_transfer_irqs(host);
 897
 898         /* Set the DMA boundary value and block size */
 899         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 900                 data->blksz), SDHCI_BLOCK_SIZE);
 901         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 902 }
 903
 904 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 905         struct mmc_command *cmd)
 906 {
 907         u16 mode;
 908         struct mmc_data *data = cmd->data;
 909
 910         if (data == NULL) {
 911                 if (host->quirks2 &
 912                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 913                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 914                 } else {
 915                 /* clear Auto CMD settings for no data CMDs */
 916                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 917                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 918                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 919                 }
 920                 return;
 921         }
 922
 923         WARN_ON(!host->data);
 924
 925         mode = SDHCI_TRNS_BLK_CNT_EN;
 926         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 927                 mode |= SDHCI_TRNS_MULTI;
 928                 /*
 929                  * If we are sending CMD23, CMD12 never gets sent
 930                  * on successful completion (so no Auto-CMD12).
 931                  */
 932                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 933                         mode |= SDHCI_TRNS_AUTO_CMD12;
 934                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 935                         mode |= SDHCI_TRNS_AUTO_CMD23;
 936                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 937                 }
 938         }
 939
 940         if (data->flags & MMC_DATA_READ)
 941                 mode |= SDHCI_TRNS_READ;
 942         if (host->flags & SDHCI_REQ_USE_DMA)
 943                 mode |= SDHCI_TRNS_DMA;
 944
 945         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 946 }
 947
 948 static void sdhci_finish_data(struct sdhci_host *host)
 949 {
 950         struct mmc_data *data;
 951
 952         BUG_ON(!host->data);
 953
 954         data = host->data;
 955         host->data = NULL;
 956
 957         if (host->flags & SDHCI_REQ_USE_DMA) {
 958                 if (host->flags & SDHCI_USE_ADMA)
 959                         sdhci_adma_table_post(host, data);
 960                 else {
 961                         if (!data->host_cookie)
 962                                 dma_unmap_sg(mmc_dev(host->mmc),
 963                                         data->sg, data->sg_len,
 964                                         (data->flags & MMC_DATA_READ) ?
 965                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 966                 }
 967         }
 968
 969         /*
 970          * The specification states that the block count register must
 971          * be updated, but it does not specify at what point in the
 972          * data flow. That makes the register entirely useless to read
 973          * back so we have to assume that nothing made it to the card
 974          * in the event of an error.
 975          */
 976         if (data->error)
 977                 data->bytes_xfered = 0;
 978         else
 979                 data->bytes_xfered = data->blksz * data->blocks;
 980
 981         /*
 982          * Need to send CMD12 if -
 983          * a) open-ended multiblock transfer (no CMD23)
 984          * b) error in multiblock transfer
 985          */
 986         if (data->stop &&
 987             (data->error ||
 988              !host->mrq->sbc)) {
 989
 990                 /*
 991                  * The controller needs a reset of internal state machines
 992                  * upon error conditions.
 993                  */
 994                 if (data->error) {
 995                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 996                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 997                 }
 998
 999                 sdhci_send_command(host, data->stop);
1000         } else
1001                 tasklet_schedule(&host->finish_tasklet);
1002 }
1003
1004 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1005 {
1006         int flags;
1007         u32 mask;
1008         unsigned long timeout;
1009
1010         WARN_ON(host->cmd);
1011
1012         /* Wait max 10 ms */
1013         timeout = 10;
1014
1015         mask = SDHCI_CMD_INHIBIT;
1016         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1017                 mask |= SDHCI_DATA_INHIBIT;
1018
1019         /* We shouldn't wait for data inihibit for stop commands, even
1020            though they might use busy signaling */
1021         if (host->mrq->data && (cmd == host->mrq->data->stop))
1022                 mask &= ~SDHCI_DATA_INHIBIT;
1023
1024         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1025                 if (timeout == 0) {
1026                         pr_err("%s: Controller never released "
1027                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1028                         sdhci_dumpregs(host);
1029                         cmd->error = -EIO;
1030                         tasklet_schedule(&host->finish_tasklet);
1031                         return;
1032                 }
1033                 timeout--;
1034                 mdelay(1);
1035         }
1036
1037         timeout = jiffies;
1038         if (!cmd->data && cmd->busy_timeout > 9000)
1039                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1040         else
1041                 timeout += 10 * HZ;
1042         mod_timer(&host->timer, timeout);
1043
1044         host->cmd = cmd;
1045         host->busy_handle = 0;
1046
1047         sdhci_prepare_data(host, cmd);
1048
1049         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1050
1051         sdhci_set_transfer_mode(host, cmd);
1052
1053         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1054                 pr_err("%s: Unsupported response type!\n",
1055                         mmc_hostname(host->mmc));
1056                 cmd->error = -EINVAL;
1057                 tasklet_schedule(&host->finish_tasklet);
1058                 return;
1059         }
1060
1061         if (!(cmd->flags & MMC_RSP_PRESENT))
1062                 flags = SDHCI_CMD_RESP_NONE;
1063         else if (cmd->flags & MMC_RSP_136)
1064                 flags = SDHCI_CMD_RESP_LONG;
1065         else if (cmd->flags & MMC_RSP_BUSY)
1066                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1067         else
1068                 flags = SDHCI_CMD_RESP_SHORT;
1069
1070         if (cmd->flags & MMC_RSP_CRC)
1071                 flags |= SDHCI_CMD_CRC;
1072         if (cmd->flags & MMC_RSP_OPCODE)
1073                 flags |= SDHCI_CMD_INDEX;
1074
1075         /* CMD19 is special in that the Data Present Select should be set */
1076         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1077             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1078                 flags |= SDHCI_CMD_DATA;
1079
1080         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1081 }
1082 EXPORT_SYMBOL_GPL(sdhci_send_command);
1083
1084 static void sdhci_finish_command(struct sdhci_host *host)
1085 {
1086         int i;
1087
1088         BUG_ON(host->cmd == NULL);
1089
1090         if (host->cmd->flags & MMC_RSP_PRESENT) {
1091                 if (host->cmd->flags & MMC_RSP_136) {
1092                         /* CRC is stripped so we need to do some shifting. */
1093                         for (i = 0;i < 4;i++) {
1094                                 host->cmd->resp[i] = sdhci_readl(host,
1095                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1096                                 if (i != 3)
1097                                         host->cmd->resp[i] |=
1098                                                 sdhci_readb(host,
1099                                                 SDHCI_RESPONSE + (3-i)*4-1);
1100                         }
1101                 } else {
1102                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1103                 }
1104         }
1105
1106         host->cmd->error = 0;
1107
1108         /* Finished CMD23, now send actual command. */
1109         if (host->cmd == host->mrq->sbc) {
1110                 host->cmd = NULL;
1111                 sdhci_send_command(host, host->mrq->cmd);
1112         } else {
1113
1114                 /* Processed actual command. */
1115                 if (host->data && host->data_early)
1116                         sdhci_finish_data(host);
1117
1118                 if (!host->cmd->data)
1119                         tasklet_schedule(&host->finish_tasklet);
1120
1121                 host->cmd = NULL;
1122         }
1123 }
1124
1125 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1126 {
1127         u16 preset = 0;
1128
1129         switch (host->timing) {
1130         case MMC_TIMING_UHS_SDR12:
1131                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1132                 break;
1133         case MMC_TIMING_UHS_SDR25:
1134                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1135                 break;
1136         case MMC_TIMING_UHS_SDR50:
1137                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1138                 break;
1139         case MMC_TIMING_UHS_SDR104:
1140         case MMC_TIMING_MMC_HS200:
1141                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1142                 break;
1143         case MMC_TIMING_UHS_DDR50:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1145                 break;
1146         case MMC_TIMING_MMC_HS400:
1147                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1148                 break;
1149         default:
1150                 pr_warn("%s: Invalid UHS-I mode selected\n",
1151                         mmc_hostname(host->mmc));
1152                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1153                 break;
1154         }
1155         return preset;
1156 }
1157
1158 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1159 {
1160         int div = 0; /* Initialized for compiler warning */
1161         int real_div = div, clk_mul = 1;
1162         u16 clk = 0;
1163         unsigned long timeout;
1164
1165         host->mmc->actual_clock = 0;
1166
1167         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1168
1169         if (clock == 0)
1170                 return;
1171
1172         if (host->version >= SDHCI_SPEC_300) {
1173                 if (host->preset_enabled) {
1174                         u16 pre_val;
1175
1176                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1177                         pre_val = sdhci_get_preset_value(host);
1178                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1179                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1180                         if (host->clk_mul &&
1181                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1182                                 clk = SDHCI_PROG_CLOCK_MODE;
1183                                 real_div = div + 1;
1184                                 clk_mul = host->clk_mul;
1185                         } else {
1186                                 real_div = max_t(int, 1, div << 1);
1187                         }
1188                         goto clock_set;
1189                 }
1190
1191                 /*
1192                  * Check if the Host Controller supports Programmable Clock
1193                  * Mode.
1194                  */
1195                 if (host->clk_mul) {
1196                         for (div = 1; div <= 1024; div++) {
1197                                 if ((host->max_clk * host->clk_mul / div)
1198                                         <= clock)
1199                                         break;
1200                         }
1201                         /*
1202                          * Set Programmable Clock Mode in the Clock
1203                          * Control register.
1204                          */
1205                         clk = SDHCI_PROG_CLOCK_MODE;
1206                         real_div = div;
1207                         clk_mul = host->clk_mul;
1208                         div--;
1209                 } else {
1210                         /* Version 3.00 divisors must be a multiple of 2. */
1211                         if (host->max_clk <= clock)
1212                                 div = 1;
1213                         else {
1214                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1215                                      div += 2) {
1216                                         if ((host->max_clk / div) <= clock)
1217                                                 break;
1218                                 }
1219                         }
1220                         real_div = div;
1221                         div >>= 1;
1222                 }
1223         } else {
1224                 /* Version 2.00 divisors must be a power of 2. */
1225                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1226                         if ((host->max_clk / div) <= clock)
1227                                 break;
1228                 }
1229                 real_div = div;
1230                 div >>= 1;
1231         }
1232
1233 clock_set:
1234         if (real_div)
1235                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1236         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1237         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1238                 << SDHCI_DIVIDER_HI_SHIFT;
1239         clk |= SDHCI_CLOCK_INT_EN;
1240         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1241
1242         /* Wait max 20 ms */
1243         timeout = 20;
1244         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1245                 & SDHCI_CLOCK_INT_STABLE)) {
1246                 if (timeout == 0) {
1247                         pr_err("%s: Internal clock never "
1248                                 "stabilised.\n", mmc_hostname(host->mmc));
1249                         sdhci_dumpregs(host);
1250                         return;
1251                 }
1252                 timeout--;
1253                 mdelay(1);
1254         }
1255
1256         clk |= SDHCI_CLOCK_CARD_EN;
1257         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1258 }
1259 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1260
1261 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1262                             unsigned short vdd)
1263 {
1264         struct mmc_host *mmc = host->mmc;
1265         u8 pwr = 0;
1266
1267         if (!IS_ERR(mmc->supply.vmmc)) {
1268                 spin_unlock_irq(&host->lock);
1269                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1270                 spin_lock_irq(&host->lock);
1271
1272                 if (mode != MMC_POWER_OFF)
1273                         sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1274                 else
1275                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1276
1277                 return;
1278         }
1279
1280         if (mode != MMC_POWER_OFF) {
1281                 switch (1 << vdd) {
1282                 case MMC_VDD_165_195:
1283                         pwr = SDHCI_POWER_180;
1284                         break;
1285                 case MMC_VDD_29_30:
1286                 case MMC_VDD_30_31:
1287                         pwr = SDHCI_POWER_300;
1288                         break;
1289                 case MMC_VDD_32_33:
1290                 case MMC_VDD_33_34:
1291                         pwr = SDHCI_POWER_330;
1292                         break;
1293                 default:
1294                         BUG();
1295                 }
1296         }
1297
1298         if (host->pwr == pwr)
1299                 return;
1300
1301         host->pwr = pwr;
1302
1303         if (pwr == 0) {
1304                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1305                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1306                         sdhci_runtime_pm_bus_off(host);
1307                 vdd = 0;
1308         } else {
1309                 /*
1310                  * Spec says that we should clear the power reg before setting
1311                  * a new value. Some controllers don't seem to like this though.
1312                  */
1313                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1314                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1315
1316                 /*
1317                  * At least the Marvell CaFe chip gets confused if we set the
1318                  * voltage and set turn on power at the same time, so set the
1319                  * voltage first.
1320                  */
1321                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1322                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1323
1324                 pwr |= SDHCI_POWER_ON;
1325
1326                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1327
1328                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1329                         sdhci_runtime_pm_bus_on(host);
1330
1331                 /*
1332                  * Some controllers need an extra 10ms delay of 10ms before
1333                  * they can apply clock after applying power
1334                  */
1335                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1336                         mdelay(10);
1337         }
1338 }
1339
1340 /*****************************************************************************\
1341  *                                                                           *
1342  * MMC callbacks                                                             *
1343  *                                                                           *
1344 \*****************************************************************************/
1345
1346 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1347 {
1348         struct sdhci_host *host;
1349         int present;
1350         unsigned long flags;
1351         u32 tuning_opcode;
1352
1353         host = mmc_priv(mmc);
1354
1355         sdhci_runtime_pm_get(host);
1356
1357         present = mmc_gpio_get_cd(host->mmc);
1358
1359         spin_lock_irqsave(&host->lock, flags);
1360
1361         WARN_ON(host->mrq != NULL);
1362
1363 #ifndef SDHCI_USE_LEDS_CLASS
1364         sdhci_activate_led(host);
1365 #endif
1366
1367         /*
1368          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1369          * requests if Auto-CMD12 is enabled.
1370          */
1371         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1372                 if (mrq->stop) {
1373                         mrq->data->stop = NULL;
1374                         mrq->stop = NULL;
1375                 }
1376         }
1377
1378         host->mrq = mrq;
1379
1380         /*
1381          * Firstly check card presence from cd-gpio.  The return could
1382          * be one of the following possibilities:
1383          *     negative: cd-gpio is not available
1384          *     zero: cd-gpio is used, and card is removed
1385          *     one: cd-gpio is used, and card is present
1386          */
1387         if (present < 0) {
1388                 /* If polling, assume that the card is always present. */
1389                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1390                         present = 1;
1391                 else
1392                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1393                                         SDHCI_CARD_PRESENT;
1394         }
1395
1396         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1397                 host->mrq->cmd->error = -ENOMEDIUM;
1398                 tasklet_schedule(&host->finish_tasklet);
1399         } else {
1400                 u32 present_state;
1401
1402                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1403                 /*
1404                  * Check if the re-tuning timer has already expired and there
1405                  * is no on-going data transfer and DAT0 is not busy. If so,
1406                  * we need to execute tuning procedure before sending command.
1407                  */
1408                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1409                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1410                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1411                         if (mmc->card) {
1412                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1413                                 tuning_opcode =
1414                                         mmc->card->type == MMC_TYPE_MMC ?
1415                                         MMC_SEND_TUNING_BLOCK_HS200 :
1416                                         MMC_SEND_TUNING_BLOCK;
1417
1418                                 /* Here we need to set the host->mrq to NULL,
1419                                  * in case the pending finish_tasklet
1420                                  * finishes it incorrectly.
1421                                  */
1422                                 host->mrq = NULL;
1423
1424                                 spin_unlock_irqrestore(&host->lock, flags);
1425                                 sdhci_execute_tuning(mmc, tuning_opcode);
1426                                 spin_lock_irqsave(&host->lock, flags);
1427
1428                                 /* Restore original mmc_request structure */
1429                                 host->mrq = mrq;
1430                         }
1431                 }
1432
1433                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1434                         sdhci_send_command(host, mrq->sbc);
1435                 else
1436                         sdhci_send_command(host, mrq->cmd);
1437         }
1438
1439         mmiowb();
1440         spin_unlock_irqrestore(&host->lock, flags);
1441 }
1442
1443 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1444 {
1445         u8 ctrl;
1446
1447         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1448         if (width == MMC_BUS_WIDTH_8) {
1449                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1450                 if (host->version >= SDHCI_SPEC_300)
1451                         ctrl |= SDHCI_CTRL_8BITBUS;
1452         } else {
1453                 if (host->version >= SDHCI_SPEC_300)
1454                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1455                 if (width == MMC_BUS_WIDTH_4)
1456                         ctrl |= SDHCI_CTRL_4BITBUS;
1457                 else
1458                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1459         }
1460         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1461 }
1462 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1463
1464 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1465 {
1466         u16 ctrl_2;
1467
1468         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1469         /* Select Bus Speed Mode for host */
1470         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1471         if ((timing == MMC_TIMING_MMC_HS200) ||
1472             (timing == MMC_TIMING_UHS_SDR104))
1473                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1474         else if (timing == MMC_TIMING_UHS_SDR12)
1475                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1476         else if (timing == MMC_TIMING_UHS_SDR25)
1477                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1478         else if (timing == MMC_TIMING_UHS_SDR50)
1479                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1480         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1481                  (timing == MMC_TIMING_MMC_DDR52))
1482                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1483         else if (timing == MMC_TIMING_MMC_HS400)
1484                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1485         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1486 }
1487 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1488
1489 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1490 {
1491         unsigned long flags;
1492         u8 ctrl;
1493         struct mmc_host *mmc = host->mmc;
1494
1495         spin_lock_irqsave(&host->lock, flags);
1496
1497         if (host->flags & SDHCI_DEVICE_DEAD) {
1498                 spin_unlock_irqrestore(&host->lock, flags);
1499                 if (!IS_ERR(mmc->supply.vmmc) &&
1500                     ios->power_mode == MMC_POWER_OFF)
1501                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1502                 return;
1503         }
1504
1505         /*
1506          * Reset the chip on each power off.
1507          * Should clear out any weird states.
1508          */
1509         if (ios->power_mode == MMC_POWER_OFF) {
1510                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1511                 sdhci_reinit(host);
1512         }
1513
1514         if (host->version >= SDHCI_SPEC_300 &&
1515                 (ios->power_mode == MMC_POWER_UP) &&
1516                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1517                 sdhci_enable_preset_value(host, false);
1518
1519         if (!ios->clock || ios->clock != host->clock) {
1520                 host->ops->set_clock(host, ios->clock);
1521                 host->clock = ios->clock;
1522
1523                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1524                     host->clock) {
1525                         host->timeout_clk = host->mmc->actual_clock ?
1526                                                 host->mmc->actual_clock / 1000 :
1527                                                 host->clock / 1000;
1528                         host->mmc->max_busy_timeout =
1529                                 host->ops->get_max_timeout_count ?
1530                                 host->ops->get_max_timeout_count(host) :
1531                                 1 << 27;
1532                         host->mmc->max_busy_timeout /= host->timeout_clk;
1533                 }
1534         }
1535
1536         sdhci_set_power(host, ios->power_mode, ios->vdd);
1537
1538         if (host->ops->platform_send_init_74_clocks)
1539                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1540
1541         host->ops->set_bus_width(host, ios->bus_width);
1542
1543         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1544
1545         if ((ios->timing == MMC_TIMING_SD_HS ||
1546              ios->timing == MMC_TIMING_MMC_HS)
1547             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1548                 ctrl |= SDHCI_CTRL_HISPD;
1549         else
1550                 ctrl &= ~SDHCI_CTRL_HISPD;
1551
1552         if (host->version >= SDHCI_SPEC_300) {
1553                 u16 clk, ctrl_2;
1554
1555                 /* In case of UHS-I modes, set High Speed Enable */
1556                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1557                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1558                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1559                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1560                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1561                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1562                     (ios->timing == MMC_TIMING_UHS_SDR25))
1563                         ctrl |= SDHCI_CTRL_HISPD;
1564
1565                 if (!host->preset_enabled) {
1566                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1567                         /*
1568                          * We only need to set Driver Strength if the
1569                          * preset value enable is not set.
1570                          */
1571                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1572                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1573                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1574                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1575                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1576                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1577
1578                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1579                 } else {
1580                         /*
1581                          * According to SDHC Spec v3.00, if the Preset Value
1582                          * Enable in the Host Control 2 register is set, we
1583                          * need to reset SD Clock Enable before changing High
1584                          * Speed Enable to avoid generating clock gliches.
1585                          */
1586
1587                         /* Reset SD Clock Enable */
1588                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1589                         clk &= ~SDHCI_CLOCK_CARD_EN;
1590                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1591
1592                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1593
1594                         /* Re-enable SD Clock */
1595                         host->ops->set_clock(host, host->clock);
1596                 }
1597
1598                 /* Reset SD Clock Enable */
1599                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1600                 clk &= ~SDHCI_CLOCK_CARD_EN;
1601                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1602
1603                 host->ops->set_uhs_signaling(host, ios->timing);
1604                 host->timing = ios->timing;
1605
1606                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1607                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1608                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1609                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1610                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1611                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1612                         u16 preset;
1613
1614                         sdhci_enable_preset_value(host, true);
1615                         preset = sdhci_get_preset_value(host);
1616                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1617                                 >> SDHCI_PRESET_DRV_SHIFT;
1618                 }
1619
1620                 /* Re-enable SD Clock */
1621                 host->ops->set_clock(host, host->clock);
1622         } else
1623                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1624
1625         /*
1626          * Some (ENE) controllers go apeshit on some ios operation,
1627          * signalling timeout and CRC errors even on CMD0. Resetting
1628          * it on each ios seems to solve the problem.
1629          */
1630         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1631                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1632
1633         mmiowb();
1634         spin_unlock_irqrestore(&host->lock, flags);
1635 }
1636
1637 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1638 {
1639         struct sdhci_host *host = mmc_priv(mmc);
1640
1641         sdhci_runtime_pm_get(host);
1642         sdhci_do_set_ios(host, ios);
1643         sdhci_runtime_pm_put(host);
1644 }
1645
1646 static int sdhci_do_get_cd(struct sdhci_host *host)
1647 {
1648         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1649
1650         if (host->flags & SDHCI_DEVICE_DEAD)
1651                 return 0;
1652
1653         /* If polling/nonremovable, assume that the card is always present. */
1654         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1655             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1656                 return 1;
1657
1658         /* Try slot gpio detect */
1659         if (!IS_ERR_VALUE(gpio_cd))
1660                 return !!gpio_cd;
1661
1662         /* Host native card detect */
1663         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1664 }
1665
1666 static int sdhci_get_cd(struct mmc_host *mmc)
1667 {
1668         struct sdhci_host *host = mmc_priv(mmc);
1669         int ret;
1670
1671         sdhci_runtime_pm_get(host);
1672         ret = sdhci_do_get_cd(host);
1673         sdhci_runtime_pm_put(host);
1674         return ret;
1675 }
1676
1677 static int sdhci_check_ro(struct sdhci_host *host)
1678 {
1679         unsigned long flags;
1680         int is_readonly;
1681
1682         spin_lock_irqsave(&host->lock, flags);
1683
1684         if (host->flags & SDHCI_DEVICE_DEAD)
1685                 is_readonly = 0;
1686         else if (host->ops->get_ro)
1687                 is_readonly = host->ops->get_ro(host);
1688         else
1689                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1690                                 & SDHCI_WRITE_PROTECT);
1691
1692         spin_unlock_irqrestore(&host->lock, flags);
1693
1694         /* This quirk needs to be replaced by a callback-function later */
1695         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1696                 !is_readonly : is_readonly;
1697 }
1698
1699 #define SAMPLE_COUNT    5
1700
1701 static int sdhci_do_get_ro(struct sdhci_host *host)
1702 {
1703         int i, ro_count;
1704
1705         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1706                 return sdhci_check_ro(host);
1707
1708         ro_count = 0;
1709         for (i = 0; i < SAMPLE_COUNT; i++) {
1710                 if (sdhci_check_ro(host)) {
1711                         if (++ro_count > SAMPLE_COUNT / 2)
1712                                 return 1;
1713                 }
1714                 msleep(30);
1715         }
1716         return 0;
1717 }
1718
1719 static void sdhci_hw_reset(struct mmc_host *mmc)
1720 {
1721         struct sdhci_host *host = mmc_priv(mmc);
1722
1723         if (host->ops && host->ops->hw_reset)
1724                 host->ops->hw_reset(host);
1725 }
1726
1727 static int sdhci_get_ro(struct mmc_host *mmc)
1728 {
1729         struct sdhci_host *host = mmc_priv(mmc);
1730         int ret;
1731
1732         sdhci_runtime_pm_get(host);
1733         ret = sdhci_do_get_ro(host);
1734         sdhci_runtime_pm_put(host);
1735         return ret;
1736 }
1737
1738 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1739 {
1740         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1741                 if (enable)
1742                         host->ier |= SDHCI_INT_CARD_INT;
1743                 else
1744                         host->ier &= ~SDHCI_INT_CARD_INT;
1745
1746                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1747                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1748                 mmiowb();
1749         }
1750 }
1751
1752 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1753 {
1754         struct sdhci_host *host = mmc_priv(mmc);
1755         unsigned long flags;
1756
1757         sdhci_runtime_pm_get(host);
1758
1759         spin_lock_irqsave(&host->lock, flags);
1760         if (enable)
1761                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1762         else
1763                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1764
1765         sdhci_enable_sdio_irq_nolock(host, enable);
1766         spin_unlock_irqrestore(&host->lock, flags);
1767
1768         sdhci_runtime_pm_put(host);
1769 }
1770
1771 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1772                                                 struct mmc_ios *ios)
1773 {
1774         struct mmc_host *mmc = host->mmc;
1775         u16 ctrl;
1776         int ret;
1777
1778         /*
1779          * Signal Voltage Switching is only applicable for Host Controllers
1780          * v3.00 and above.
1781          */
1782         if (host->version < SDHCI_SPEC_300)
1783                 return 0;
1784
1785         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1786
1787         switch (ios->signal_voltage) {
1788         case MMC_SIGNAL_VOLTAGE_330:
1789                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1790                 ctrl &= ~SDHCI_CTRL_VDD_180;
1791                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1792
1793                 if (!IS_ERR(mmc->supply.vqmmc)) {
1794                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1795                                                     3600000);
1796                         if (ret) {
1797                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1798                                         mmc_hostname(mmc));
1799                                 return -EIO;
1800                         }
1801                 }
1802                 /* Wait for 5ms */
1803                 usleep_range(5000, 5500);
1804
1805                 /* 3.3V regulator output should be stable within 5 ms */
1806                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1807                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1808                         return 0;
1809
1810                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1811                         mmc_hostname(mmc));
1812
1813                 return -EAGAIN;
1814         case MMC_SIGNAL_VOLTAGE_180:
1815                 if (!IS_ERR(mmc->supply.vqmmc)) {
1816                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1817                                         1700000, 1950000);
1818                         if (ret) {
1819                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1820                                         mmc_hostname(mmc));
1821                                 return -EIO;
1822                         }
1823                 }
1824
1825                 /*
1826                  * Enable 1.8V Signal Enable in the Host Control2
1827                  * register
1828                  */
1829                 ctrl |= SDHCI_CTRL_VDD_180;
1830                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1831
1832                 /* 1.8V regulator output should be stable within 5 ms */
1833                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1834                 if (ctrl & SDHCI_CTRL_VDD_180)
1835                         return 0;
1836
1837                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1838                         mmc_hostname(mmc));
1839
1840                 return -EAGAIN;
1841         case MMC_SIGNAL_VOLTAGE_120:
1842                 if (!IS_ERR(mmc->supply.vqmmc)) {
1843                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1844                                                     1300000);
1845                         if (ret) {
1846                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1847                                         mmc_hostname(mmc));
1848                                 return -EIO;
1849                         }
1850                 }
1851                 return 0;
1852         default:
1853                 /* No signal voltage switch required */
1854                 return 0;
1855         }
1856 }
1857
1858 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1859         struct mmc_ios *ios)
1860 {
1861         struct sdhci_host *host = mmc_priv(mmc);
1862         int err;
1863
1864         if (host->version < SDHCI_SPEC_300)
1865                 return 0;
1866         sdhci_runtime_pm_get(host);
1867         err = sdhci_do_start_signal_voltage_switch(host, ios);
1868         sdhci_runtime_pm_put(host);
1869         return err;
1870 }
1871
1872 static int sdhci_card_busy(struct mmc_host *mmc)
1873 {
1874         struct sdhci_host *host = mmc_priv(mmc);
1875         u32 present_state;
1876
1877         sdhci_runtime_pm_get(host);
1878         /* Check whether DAT[3:0] is 0000 */
1879         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1880         sdhci_runtime_pm_put(host);
1881
1882         return !(present_state & SDHCI_DATA_LVL_MASK);
1883 }
1884
1885 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1886 {
1887         struct sdhci_host *host = mmc_priv(mmc);
1888         unsigned long flags;
1889
1890         spin_lock_irqsave(&host->lock, flags);
1891         host->flags |= SDHCI_HS400_TUNING;
1892         spin_unlock_irqrestore(&host->lock, flags);
1893
1894         return 0;
1895 }
1896
1897 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1898 {
1899         struct sdhci_host *host = mmc_priv(mmc);
1900         u16 ctrl;
1901         int tuning_loop_counter = MAX_TUNING_LOOP;
1902         int err = 0;
1903         unsigned long flags;
1904         unsigned int tuning_count = 0;
1905         bool hs400_tuning;
1906
1907         sdhci_runtime_pm_get(host);
1908         spin_lock_irqsave(&host->lock, flags);
1909
1910         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1911         host->flags &= ~SDHCI_HS400_TUNING;
1912
1913         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1914                 tuning_count = host->tuning_count;
1915
1916         /*
1917          * The Host Controller needs tuning only in case of SDR104 mode
1918          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1919          * Capabilities register.
1920          * If the Host Controller supports the HS200 mode then the
1921          * tuning function has to be executed.
1922          */
1923         switch (host->timing) {
1924         /* HS400 tuning is done in HS200 mode */
1925         case MMC_TIMING_MMC_HS400:
1926                 err = -EINVAL;
1927                 goto out_unlock;
1928
1929         case MMC_TIMING_MMC_HS200:
1930                 /*
1931                  * Periodic re-tuning for HS400 is not expected to be needed, so
1932                  * disable it here.
1933                  */
1934                 if (hs400_tuning)
1935                         tuning_count = 0;
1936                 break;
1937
1938         case MMC_TIMING_UHS_SDR104:
1939                 break;
1940
1941         case MMC_TIMING_UHS_SDR50:
1942                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1943                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1944                         break;
1945                 /* FALLTHROUGH */
1946
1947         default:
1948                 goto out_unlock;
1949         }
1950
1951         if (host->ops->platform_execute_tuning) {
1952                 spin_unlock_irqrestore(&host->lock, flags);
1953                 err = host->ops->platform_execute_tuning(host, opcode);
1954                 sdhci_runtime_pm_put(host);
1955                 return err;
1956         }
1957
1958         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1959         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1960         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1961
1962         /*
1963          * As per the Host Controller spec v3.00, tuning command
1964          * generates Buffer Read Ready interrupt, so enable that.
1965          *
1966          * Note: The spec clearly says that when tuning sequence
1967          * is being performed, the controller does not generate
1968          * interrupts other than Buffer Read Ready interrupt. But
1969          * to make sure we don't hit a controller bug, we _only_
1970          * enable Buffer Read Ready interrupt here.
1971          */
1972         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1973         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1974
1975         /*
1976          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1977          * of loops reaches 40 times or a timeout of 150ms occurs.
1978          */
1979         do {
1980                 struct mmc_command cmd = {0};
1981                 struct mmc_request mrq = {NULL};
1982
1983                 cmd.opcode = opcode;
1984                 cmd.arg = 0;
1985                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1986                 cmd.retries = 0;
1987                 cmd.data = NULL;
1988                 cmd.error = 0;
1989
1990                 if (tuning_loop_counter-- == 0)
1991                         break;
1992
1993                 mrq.cmd = &cmd;
1994                 host->mrq = &mrq;
1995
1996                 /*
1997                  * In response to CMD19, the card sends 64 bytes of tuning
1998                  * block to the Host Controller. So we set the block size
1999                  * to 64 here.
2000                  */
2001                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2002                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2003                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2004                                              SDHCI_BLOCK_SIZE);
2005                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2006                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2007                                              SDHCI_BLOCK_SIZE);
2008                 } else {
2009                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2010                                      SDHCI_BLOCK_SIZE);
2011                 }
2012
2013                 /*
2014                  * The tuning block is sent by the card to the host controller.
2015                  * So we set the TRNS_READ bit in the Transfer Mode register.
2016                  * This also takes care of setting DMA Enable and Multi Block
2017                  * Select in the same register to 0.
2018                  */
2019                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2020
2021                 sdhci_send_command(host, &cmd);
2022
2023                 host->cmd = NULL;
2024                 host->mrq = NULL;
2025
2026                 spin_unlock_irqrestore(&host->lock, flags);
2027                 /* Wait for Buffer Read Ready interrupt */
2028                 wait_event_interruptible_timeout(host->buf_ready_int,
2029                                         (host->tuning_done == 1),
2030                                         msecs_to_jiffies(50));
2031                 spin_lock_irqsave(&host->lock, flags);
2032
2033                 if (!host->tuning_done) {
2034                         pr_info(DRIVER_NAME ": Timeout waiting for "
2035                                 "Buffer Read Ready interrupt during tuning "
2036                                 "procedure, falling back to fixed sampling "
2037                                 "clock\n");
2038                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2039                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2040                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2041                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2042
2043                         err = -EIO;
2044                         goto out;
2045                 }
2046
2047                 host->tuning_done = 0;
2048
2049                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2050
2051                 /* eMMC spec does not require a delay between tuning cycles */
2052                 if (opcode == MMC_SEND_TUNING_BLOCK)
2053                         mdelay(1);
2054         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2055
2056         /*
2057          * The Host Driver has exhausted the maximum number of loops allowed,
2058          * so use fixed sampling frequency.
2059          */
2060         if (tuning_loop_counter < 0) {
2061                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2062                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2063         }
2064         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2065                 pr_info(DRIVER_NAME ": Tuning procedure"
2066                         " failed, falling back to fixed sampling"
2067                         " clock\n");
2068                 err = -EIO;
2069         }
2070
2071 out:
2072         host->flags &= ~SDHCI_NEEDS_RETUNING;
2073
2074         if (tuning_count) {
2075                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2076                 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
2077         }
2078
2079         /*
2080          * In case tuning fails, host controllers which support re-tuning can
2081          * try tuning again at a later time, when the re-tuning timer expires.
2082          * So for these controllers, we return 0. Since there might be other
2083          * controllers who do not have this capability, we return error for
2084          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2085          * a retuning timer to do the retuning for the card.
2086          */
2087         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2088                 err = 0;
2089
2090         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2091         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2092 out_unlock:
2093         spin_unlock_irqrestore(&host->lock, flags);
2094         sdhci_runtime_pm_put(host);
2095
2096         return err;
2097 }
2098
2099
2100 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2101 {
2102         /* Host Controller v3.00 defines preset value registers */
2103         if (host->version < SDHCI_SPEC_300)
2104                 return;
2105
2106         /*
2107          * We only enable or disable Preset Value if they are not already
2108          * enabled or disabled respectively. Otherwise, we bail out.
2109          */
2110         if (host->preset_enabled != enable) {
2111                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2112
2113                 if (enable)
2114                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2115                 else
2116                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2117
2118                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2119
2120                 if (enable)
2121                         host->flags |= SDHCI_PV_ENABLED;
2122                 else
2123                         host->flags &= ~SDHCI_PV_ENABLED;
2124
2125                 host->preset_enabled = enable;
2126         }
2127 }
2128
2129 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2130                                 int err)
2131 {
2132         struct sdhci_host *host = mmc_priv(mmc);
2133         struct mmc_data *data = mrq->data;
2134
2135         if (host->flags & SDHCI_REQ_USE_DMA) {
2136                 if (data->host_cookie)
2137                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2138                                          data->flags & MMC_DATA_WRITE ?
2139                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2140                 mrq->data->host_cookie = 0;
2141         }
2142 }
2143
2144 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2145                                        struct mmc_data *data,
2146                                        struct sdhci_host_next *next)
2147 {
2148         int sg_count;
2149
2150         if (!next && data->host_cookie &&
2151             data->host_cookie != host->next_data.cookie) {
2152                 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2153                         __func__, data->host_cookie, host->next_data.cookie);
2154                 data->host_cookie = 0;
2155         }
2156
2157         /* Check if next job is already prepared */
2158         if (next ||
2159             (!next && data->host_cookie != host->next_data.cookie)) {
2160                 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2161                                      data->sg_len,
2162                                      data->flags & MMC_DATA_WRITE ?
2163                                      DMA_TO_DEVICE : DMA_FROM_DEVICE);
2164
2165         } else {
2166                 sg_count = host->next_data.sg_count;
2167                 host->next_data.sg_count = 0;
2168         }
2169
2170
2171         if (sg_count == 0)
2172                 return -EINVAL;
2173
2174         if (next) {
2175                 next->sg_count = sg_count;
2176                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2177         } else
2178                 host->sg_count = sg_count;
2179
2180         return sg_count;
2181 }
2182
2183 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2184                                bool is_first_req)
2185 {
2186         struct sdhci_host *host = mmc_priv(mmc);
2187
2188         if (mrq->data->host_cookie) {
2189                 mrq->data->host_cookie = 0;
2190                 return;
2191         }
2192
2193         if (host->flags & SDHCI_REQ_USE_DMA)
2194                 if (sdhci_pre_dma_transfer(host,
2195                                         mrq->data,
2196                                         &host->next_data) < 0)
2197                         mrq->data->host_cookie = 0;
2198 }
2199
2200 static void sdhci_card_event(struct mmc_host *mmc)
2201 {
2202         struct sdhci_host *host = mmc_priv(mmc);
2203         unsigned long flags;
2204         int present;
2205
2206         /* First check if client has provided their own card event */
2207         if (host->ops->card_event)
2208                 host->ops->card_event(host);
2209
2210         present = sdhci_do_get_cd(host);
2211
2212         spin_lock_irqsave(&host->lock, flags);
2213
2214         /* Check host->mrq first in case we are runtime suspended */
2215         if (host->mrq && !present) {
2216                 pr_err("%s: Card removed during transfer!\n",
2217                         mmc_hostname(host->mmc));
2218                 pr_err("%s: Resetting controller.\n",
2219                         mmc_hostname(host->mmc));
2220
2221                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2222                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2223
2224                 host->mrq->cmd->error = -ENOMEDIUM;
2225                 tasklet_schedule(&host->finish_tasklet);
2226         }
2227
2228         spin_unlock_irqrestore(&host->lock, flags);
2229 }
2230
2231 static const struct mmc_host_ops sdhci_ops = {
2232         .request        = sdhci_request,
2233         .post_req       = sdhci_post_req,
2234         .pre_req        = sdhci_pre_req,
2235         .set_ios        = sdhci_set_ios,
2236         .get_cd         = sdhci_get_cd,
2237         .get_ro         = sdhci_get_ro,
2238         .hw_reset       = sdhci_hw_reset,
2239         .enable_sdio_irq = sdhci_enable_sdio_irq,
2240         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2241         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2242         .execute_tuning                 = sdhci_execute_tuning,
2243         .card_event                     = sdhci_card_event,
2244         .card_busy      = sdhci_card_busy,
2245 };
2246
2247 /*****************************************************************************\
2248  *                                                                           *
2249  * Tasklets                                                                  *
2250  *                                                                           *
2251 \*****************************************************************************/
2252
2253 static void sdhci_tasklet_finish(unsigned long param)
2254 {
2255         struct sdhci_host *host;
2256         unsigned long flags;
2257         struct mmc_request *mrq;
2258
2259         host = (struct sdhci_host*)param;
2260
2261         spin_lock_irqsave(&host->lock, flags);
2262
2263         /*
2264          * If this tasklet gets rescheduled while running, it will
2265          * be run again afterwards but without any active request.
2266          */
2267         if (!host->mrq) {
2268                 spin_unlock_irqrestore(&host->lock, flags);
2269                 return;
2270         }
2271
2272         del_timer(&host->timer);
2273
2274         mrq = host->mrq;
2275
2276         /*
2277          * The controller needs a reset of internal state machines
2278          * upon error conditions.
2279          */
2280         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2281             ((mrq->cmd && mrq->cmd->error) ||
2282              (mrq->sbc && mrq->sbc->error) ||
2283              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2284                             (mrq->data->stop && mrq->data->stop->error))) ||
2285              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2286
2287                 /* Some controllers need this kick or reset won't work here */
2288                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2289                         /* This is to force an update */
2290                         host->ops->set_clock(host, host->clock);
2291
2292                 /* Spec says we should do both at the same time, but Ricoh
2293                    controllers do not like that. */
2294                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2295                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2296         }
2297
2298         host->mrq = NULL;
2299         host->cmd = NULL;
2300         host->data = NULL;
2301
2302 #ifndef SDHCI_USE_LEDS_CLASS
2303         sdhci_deactivate_led(host);
2304 #endif
2305
2306         mmiowb();
2307         spin_unlock_irqrestore(&host->lock, flags);
2308
2309         mmc_request_done(host->mmc, mrq);
2310         sdhci_runtime_pm_put(host);
2311 }
2312
2313 static void sdhci_timeout_timer(unsigned long data)
2314 {
2315         struct sdhci_host *host;
2316         unsigned long flags;
2317
2318         host = (struct sdhci_host*)data;
2319
2320         spin_lock_irqsave(&host->lock, flags);
2321
2322         if (host->mrq) {
2323                 pr_err("%s: Timeout waiting for hardware "
2324                         "interrupt.\n", mmc_hostname(host->mmc));
2325                 sdhci_dumpregs(host);
2326
2327                 if (host->data) {
2328                         host->data->error = -ETIMEDOUT;
2329                         sdhci_finish_data(host);
2330                 } else {
2331                         if (host->cmd)
2332                                 host->cmd->error = -ETIMEDOUT;
2333                         else
2334                                 host->mrq->cmd->error = -ETIMEDOUT;
2335
2336                         tasklet_schedule(&host->finish_tasklet);
2337                 }
2338         }
2339
2340         mmiowb();
2341         spin_unlock_irqrestore(&host->lock, flags);
2342 }
2343
2344 static void sdhci_tuning_timer(unsigned long data)
2345 {
2346         struct sdhci_host *host;
2347         unsigned long flags;
2348
2349         host = (struct sdhci_host *)data;
2350
2351         spin_lock_irqsave(&host->lock, flags);
2352
2353         host->flags |= SDHCI_NEEDS_RETUNING;
2354
2355         spin_unlock_irqrestore(&host->lock, flags);
2356 }
2357
2358 /*****************************************************************************\
2359  *                                                                           *
2360  * Interrupt handling                                                        *
2361  *                                                                           *
2362 \*****************************************************************************/
2363
2364 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2365 {
2366         BUG_ON(intmask == 0);
2367
2368         if (!host->cmd) {
2369                 pr_err("%s: Got command interrupt 0x%08x even "
2370                         "though no command operation was in progress.\n",
2371                         mmc_hostname(host->mmc), (unsigned)intmask);
2372                 sdhci_dumpregs(host);
2373                 return;
2374         }
2375
2376         if (intmask & SDHCI_INT_TIMEOUT)
2377                 host->cmd->error = -ETIMEDOUT;
2378         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2379                         SDHCI_INT_INDEX))
2380                 host->cmd->error = -EILSEQ;
2381
2382         if (host->cmd->error) {
2383                 tasklet_schedule(&host->finish_tasklet);
2384                 return;
2385         }
2386
2387         /*
2388          * The host can send and interrupt when the busy state has
2389          * ended, allowing us to wait without wasting CPU cycles.
2390          * Unfortunately this is overloaded on the "data complete"
2391          * interrupt, so we need to take some care when handling
2392          * it.
2393          *
2394          * Note: The 1.0 specification is a bit ambiguous about this
2395          *       feature so there might be some problems with older
2396          *       controllers.
2397          */
2398         if (host->cmd->flags & MMC_RSP_BUSY) {
2399                 if (host->cmd->data)
2400                         DBG("Cannot wait for busy signal when also "
2401                                 "doing a data transfer");
2402                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2403                                 && !host->busy_handle) {
2404                         /* Mark that command complete before busy is ended */
2405                         host->busy_handle = 1;
2406                         return;
2407                 }
2408
2409                 /* The controller does not support the end-of-busy IRQ,
2410                  * fall through and take the SDHCI_INT_RESPONSE */
2411         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2412                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2413                 *mask &= ~SDHCI_INT_DATA_END;
2414         }
2415
2416         if (intmask & SDHCI_INT_RESPONSE)
2417                 sdhci_finish_command(host);
2418 }
2419
2420 #ifdef CONFIG_MMC_DEBUG
2421 static void sdhci_adma_show_error(struct sdhci_host *host)
2422 {
2423         const char *name = mmc_hostname(host->mmc);
2424         void *desc = host->adma_table;
2425
2426         sdhci_dumpregs(host);
2427
2428         while (true) {
2429                 struct sdhci_adma2_64_desc *dma_desc = desc;
2430
2431                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2432                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2433                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2434                             le32_to_cpu(dma_desc->addr_lo),
2435                             le16_to_cpu(dma_desc->len),
2436                             le16_to_cpu(dma_desc->cmd));
2437                 else
2438                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2439                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2440                             le16_to_cpu(dma_desc->len),
2441                             le16_to_cpu(dma_desc->cmd));
2442
2443                 desc += host->desc_sz;
2444
2445                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2446                         break;
2447         }
2448 }
2449 #else
2450 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2451 #endif
2452
2453 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2454 {
2455         u32 command;
2456         BUG_ON(intmask == 0);
2457
2458         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2459         if (intmask & SDHCI_INT_DATA_AVAIL) {
2460                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2461                 if (command == MMC_SEND_TUNING_BLOCK ||
2462                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2463                         host->tuning_done = 1;
2464                         wake_up(&host->buf_ready_int);
2465                         return;
2466                 }
2467         }
2468
2469         if (!host->data) {
2470                 /*
2471                  * The "data complete" interrupt is also used to
2472                  * indicate that a busy state has ended. See comment
2473                  * above in sdhci_cmd_irq().
2474                  */
2475                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2476                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2477                                 host->cmd->error = -ETIMEDOUT;
2478                                 tasklet_schedule(&host->finish_tasklet);
2479                                 return;
2480                         }
2481                         if (intmask & SDHCI_INT_DATA_END) {
2482                                 /*
2483                                  * Some cards handle busy-end interrupt
2484                                  * before the command completed, so make
2485                                  * sure we do things in the proper order.
2486                                  */
2487                                 if (host->busy_handle)
2488                                         sdhci_finish_command(host);
2489                                 else
2490                                         host->busy_handle = 1;
2491                                 return;
2492                         }
2493                 }
2494
2495                 pr_err("%s: Got data interrupt 0x%08x even "
2496                         "though no data operation was in progress.\n",
2497                         mmc_hostname(host->mmc), (unsigned)intmask);
2498                 sdhci_dumpregs(host);
2499
2500                 return;
2501         }
2502
2503         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2504                 host->data->error = -ETIMEDOUT;
2505         else if (intmask & SDHCI_INT_DATA_END_BIT)
2506                 host->data->error = -EILSEQ;
2507         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2508                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2509                         != MMC_BUS_TEST_R)
2510                 host->data->error = -EILSEQ;
2511         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2512                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2513                 sdhci_adma_show_error(host);
2514                 host->data->error = -EIO;
2515                 if (host->ops->adma_workaround)
2516                         host->ops->adma_workaround(host, intmask);
2517         }
2518
2519         if (host->data->error)
2520                 sdhci_finish_data(host);
2521         else {
2522                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2523                         sdhci_transfer_pio(host);
2524
2525                 /*
2526                  * We currently don't do anything fancy with DMA
2527                  * boundaries, but as we can't disable the feature
2528                  * we need to at least restart the transfer.
2529                  *
2530                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2531                  * should return a valid address to continue from, but as
2532                  * some controllers are faulty, don't trust them.
2533                  */
2534                 if (intmask & SDHCI_INT_DMA_END) {
2535                         u32 dmastart, dmanow;
2536                         dmastart = sg_dma_address(host->data->sg);
2537                         dmanow = dmastart + host->data->bytes_xfered;
2538                         /*
2539                          * Force update to the next DMA block boundary.
2540                          */
2541                         dmanow = (dmanow &
2542                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2543                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2544                         host->data->bytes_xfered = dmanow - dmastart;
2545                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2546                                 " next 0x%08x\n",
2547                                 mmc_hostname(host->mmc), dmastart,
2548                                 host->data->bytes_xfered, dmanow);
2549                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2550                 }
2551
2552                 if (intmask & SDHCI_INT_DATA_END) {
2553                         if (host->cmd) {
2554                                 /*
2555                                  * Data managed to finish before the
2556                                  * command completed. Make sure we do
2557                                  * things in the proper order.
2558                                  */
2559                                 host->data_early = 1;
2560                         } else {
2561                                 sdhci_finish_data(host);
2562                         }
2563                 }
2564         }
2565 }
2566
2567 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2568 {
2569         irqreturn_t result = IRQ_NONE;
2570         struct sdhci_host *host = dev_id;
2571         u32 intmask, mask, unexpected = 0;
2572         int max_loops = 16;
2573
2574         spin_lock(&host->lock);
2575
2576         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2577                 spin_unlock(&host->lock);
2578                 return IRQ_NONE;
2579         }
2580
2581         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2582         if (!intmask || intmask == 0xffffffff) {
2583                 result = IRQ_NONE;
2584                 goto out;
2585         }
2586
2587         do {
2588                 /* Clear selected interrupts. */
2589                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2590                                   SDHCI_INT_BUS_POWER);
2591                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2592
2593                 DBG("*** %s got interrupt: 0x%08x\n",
2594                         mmc_hostname(host->mmc), intmask);
2595
2596                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2597                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2598                                       SDHCI_CARD_PRESENT;
2599
2600                         /*
2601                          * There is a observation on i.mx esdhc.  INSERT
2602                          * bit will be immediately set again when it gets
2603                          * cleared, if a card is inserted.  We have to mask
2604                          * the irq to prevent interrupt storm which will
2605                          * freeze the system.  And the REMOVE gets the
2606                          * same situation.
2607                          *
2608                          * More testing are needed here to ensure it works
2609                          * for other platforms though.
2610                          */
2611                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2612                                        SDHCI_INT_CARD_REMOVE);
2613                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2614                                                SDHCI_INT_CARD_INSERT;
2615                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2616                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2617
2618                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2619                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2620
2621                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2622                                                        SDHCI_INT_CARD_REMOVE);
2623                         result = IRQ_WAKE_THREAD;
2624                 }
2625
2626                 if (intmask & SDHCI_INT_CMD_MASK)
2627                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2628                                       &intmask);
2629
2630                 if (intmask & SDHCI_INT_DATA_MASK)
2631                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2632
2633                 if (intmask & SDHCI_INT_BUS_POWER)
2634                         pr_err("%s: Card is consuming too much power!\n",
2635                                 mmc_hostname(host->mmc));
2636
2637                 if (intmask & SDHCI_INT_CARD_INT) {
2638                         sdhci_enable_sdio_irq_nolock(host, false);
2639                         host->thread_isr |= SDHCI_INT_CARD_INT;
2640                         result = IRQ_WAKE_THREAD;
2641                 }
2642
2643                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2644                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2645                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2646                              SDHCI_INT_CARD_INT);
2647
2648                 if (intmask) {
2649                         unexpected |= intmask;
2650                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2651                 }
2652
2653                 if (result == IRQ_NONE)
2654                         result = IRQ_HANDLED;
2655
2656                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2657         } while (intmask && --max_loops);
2658 out:
2659         spin_unlock(&host->lock);
2660
2661         if (unexpected) {
2662                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2663                            mmc_hostname(host->mmc), unexpected);
2664                 sdhci_dumpregs(host);
2665         }
2666
2667         return result;
2668 }
2669
2670 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2671 {
2672         struct sdhci_host *host = dev_id;
2673         unsigned long flags;
2674         u32 isr;
2675
2676         spin_lock_irqsave(&host->lock, flags);
2677         isr = host->thread_isr;
2678         host->thread_isr = 0;
2679         spin_unlock_irqrestore(&host->lock, flags);
2680
2681         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2682                 sdhci_card_event(host->mmc);
2683                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2684         }
2685
2686         if (isr & SDHCI_INT_CARD_INT) {
2687                 sdio_run_irqs(host->mmc);
2688
2689                 spin_lock_irqsave(&host->lock, flags);
2690                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2691                         sdhci_enable_sdio_irq_nolock(host, true);
2692                 spin_unlock_irqrestore(&host->lock, flags);
2693         }
2694
2695         return isr ? IRQ_HANDLED : IRQ_NONE;
2696 }
2697
2698 /*****************************************************************************\
2699  *                                                                           *
2700  * Suspend/resume                                                            *
2701  *                                                                           *
2702 \*****************************************************************************/
2703
2704 #ifdef CONFIG_PM
2705 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2706 {
2707         u8 val;
2708         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2709                         | SDHCI_WAKE_ON_INT;
2710
2711         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2712         val |= mask ;
2713         /* Avoid fake wake up */
2714         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2715                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2716         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2717 }
2718 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2719
2720 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2721 {
2722         u8 val;
2723         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2724                         | SDHCI_WAKE_ON_INT;
2725
2726         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2727         val &= ~mask;
2728         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2729 }
2730
2731 int sdhci_suspend_host(struct sdhci_host *host)
2732 {
2733         sdhci_disable_card_detection(host);
2734
2735         /* Disable tuning since we are suspending */
2736         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2737                 del_timer_sync(&host->tuning_timer);
2738                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2739         }
2740
2741         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2742                 host->ier = 0;
2743                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2744                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2745                 free_irq(host->irq, host);
2746         } else {
2747                 sdhci_enable_irq_wakeups(host);
2748                 enable_irq_wake(host->irq);
2749         }
2750         return 0;
2751 }
2752
2753 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2754
2755 int sdhci_resume_host(struct sdhci_host *host)
2756 {
2757         int ret = 0;
2758
2759         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2760                 if (host->ops->enable_dma)
2761                         host->ops->enable_dma(host);
2762         }
2763
2764         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2765                 ret = request_threaded_irq(host->irq, sdhci_irq,
2766                                            sdhci_thread_irq, IRQF_SHARED,
2767                                            mmc_hostname(host->mmc), host);
2768                 if (ret)
2769                         return ret;
2770         } else {
2771                 sdhci_disable_irq_wakeups(host);
2772                 disable_irq_wake(host->irq);
2773         }
2774
2775         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2776             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2777                 /* Card keeps power but host controller does not */
2778                 sdhci_init(host, 0);
2779                 host->pwr = 0;
2780                 host->clock = 0;
2781                 sdhci_do_set_ios(host, &host->mmc->ios);
2782         } else {
2783                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2784                 mmiowb();
2785         }
2786
2787         sdhci_enable_card_detection(host);
2788
2789         /* Set the re-tuning expiration flag */
2790         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2791                 host->flags |= SDHCI_NEEDS_RETUNING;
2792
2793         return ret;
2794 }
2795
2796 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2797
2798 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2799 {
2800         return pm_runtime_get_sync(host->mmc->parent);
2801 }
2802
2803 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2804 {
2805         pm_runtime_mark_last_busy(host->mmc->parent);
2806         return pm_runtime_put_autosuspend(host->mmc->parent);
2807 }
2808
2809 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2810 {
2811         if (host->runtime_suspended || host->bus_on)
2812                 return;
2813         host->bus_on = true;
2814         pm_runtime_get_noresume(host->mmc->parent);
2815 }
2816
2817 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2818 {
2819         if (host->runtime_suspended || !host->bus_on)
2820                 return;
2821         host->bus_on = false;
2822         pm_runtime_put_noidle(host->mmc->parent);
2823 }
2824
2825 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2826 {
2827         unsigned long flags;
2828
2829         /* Disable tuning since we are suspending */
2830         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2831                 del_timer_sync(&host->tuning_timer);
2832                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2833         }
2834
2835         spin_lock_irqsave(&host->lock, flags);
2836         host->ier &= SDHCI_INT_CARD_INT;
2837         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2838         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2839         spin_unlock_irqrestore(&host->lock, flags);
2840
2841         synchronize_hardirq(host->irq);
2842
2843         spin_lock_irqsave(&host->lock, flags);
2844         host->runtime_suspended = true;
2845         spin_unlock_irqrestore(&host->lock, flags);
2846
2847         return 0;
2848 }
2849 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2850
2851 int sdhci_runtime_resume_host(struct sdhci_host *host)
2852 {
2853         unsigned long flags;
2854         int host_flags = host->flags;
2855
2856         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2857                 if (host->ops->enable_dma)
2858                         host->ops->enable_dma(host);
2859         }
2860
2861         sdhci_init(host, 0);
2862
2863         /* Force clock and power re-program */
2864         host->pwr = 0;
2865         host->clock = 0;
2866         sdhci_do_set_ios(host, &host->mmc->ios);
2867
2868         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2869         if ((host_flags & SDHCI_PV_ENABLED) &&
2870                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2871                 spin_lock_irqsave(&host->lock, flags);
2872                 sdhci_enable_preset_value(host, true);
2873                 spin_unlock_irqrestore(&host->lock, flags);
2874         }
2875
2876         /* Set the re-tuning expiration flag */
2877         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2878                 host->flags |= SDHCI_NEEDS_RETUNING;
2879
2880         spin_lock_irqsave(&host->lock, flags);
2881
2882         host->runtime_suspended = false;
2883
2884         /* Enable SDIO IRQ */
2885         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2886                 sdhci_enable_sdio_irq_nolock(host, true);
2887
2888         /* Enable Card Detection */
2889         sdhci_enable_card_detection(host);
2890
2891         spin_unlock_irqrestore(&host->lock, flags);
2892
2893         return 0;
2894 }
2895 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2896
2897 #endif /* CONFIG_PM */
2898
2899 /*****************************************************************************\
2900  *                                                                           *
2901  * Device allocation/registration                                            *
2902  *                                                                           *
2903 \*****************************************************************************/
2904
2905 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2906         size_t priv_size)
2907 {
2908         struct mmc_host *mmc;
2909         struct sdhci_host *host;
2910
2911         WARN_ON(dev == NULL);
2912
2913         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2914         if (!mmc)
2915                 return ERR_PTR(-ENOMEM);
2916
2917         host = mmc_priv(mmc);
2918         host->mmc = mmc;
2919
2920         return host;
2921 }
2922
2923 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2924
2925 int sdhci_add_host(struct sdhci_host *host)
2926 {
2927         struct mmc_host *mmc;
2928         u32 caps[2] = {0, 0};
2929         u32 max_current_caps;
2930         unsigned int ocr_avail;
2931         unsigned int override_timeout_clk;
2932         int ret;
2933
2934         WARN_ON(host == NULL);
2935         if (host == NULL)
2936                 return -EINVAL;
2937
2938         mmc = host->mmc;
2939
2940         if (debug_quirks)
2941                 host->quirks = debug_quirks;
2942         if (debug_quirks2)
2943                 host->quirks2 = debug_quirks2;
2944
2945         override_timeout_clk = host->timeout_clk;
2946
2947         sdhci_do_reset(host, SDHCI_RESET_ALL);
2948
2949         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2950         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2951                                 >> SDHCI_SPEC_VER_SHIFT;
2952         if (host->version > SDHCI_SPEC_300) {
2953                 pr_err("%s: Unknown controller version (%d). "
2954                         "You may experience problems.\n", mmc_hostname(mmc),
2955                         host->version);
2956         }
2957
2958         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2959                 sdhci_readl(host, SDHCI_CAPABILITIES);
2960
2961         if (host->version >= SDHCI_SPEC_300)
2962                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2963                         host->caps1 :
2964                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2965
2966         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2967                 host->flags |= SDHCI_USE_SDMA;
2968         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2969                 DBG("Controller doesn't have SDMA capability\n");
2970         else
2971                 host->flags |= SDHCI_USE_SDMA;
2972
2973         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2974                 (host->flags & SDHCI_USE_SDMA)) {
2975                 DBG("Disabling DMA as it is marked broken\n");
2976                 host->flags &= ~SDHCI_USE_SDMA;
2977         }
2978
2979         if ((host->version >= SDHCI_SPEC_200) &&
2980                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2981                 host->flags |= SDHCI_USE_ADMA;
2982
2983         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2984                 (host->flags & SDHCI_USE_ADMA)) {
2985                 DBG("Disabling ADMA as it is marked broken\n");
2986                 host->flags &= ~SDHCI_USE_ADMA;
2987         }
2988
2989         /*
2990          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2991          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2992          * that during the first call to ->enable_dma().  Similarly
2993          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2994          * implement.
2995          */
2996         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2997                 host->flags |= SDHCI_USE_64_BIT_DMA;
2998
2999         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3000                 if (host->ops->enable_dma) {
3001                         if (host->ops->enable_dma(host)) {
3002                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3003                                         mmc_hostname(mmc));
3004                                 host->flags &=
3005                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3006                         }
3007                 }
3008         }
3009
3010         /* SDMA does not support 64-bit DMA */
3011         if (host->flags & SDHCI_USE_64_BIT_DMA)
3012                 host->flags &= ~SDHCI_USE_SDMA;
3013
3014         if (host->flags & SDHCI_USE_ADMA) {
3015                 /*
3016                  * The DMA descriptor table size is calculated as the maximum
3017                  * number of segments times 2, to allow for an alignment
3018                  * descriptor for each segment, plus 1 for a nop end descriptor,
3019                  * all multipled by the descriptor size.
3020                  */
3021                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3022                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3023                                               SDHCI_ADMA2_64_DESC_SZ;
3024                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3025                                                 SDHCI_ADMA2_64_ALIGN;
3026                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3027                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
3028                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
3029                 } else {
3030                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3031                                               SDHCI_ADMA2_32_DESC_SZ;
3032                         host->align_buffer_sz = SDHCI_MAX_SEGS *
3033                                                 SDHCI_ADMA2_32_ALIGN;
3034                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3035                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
3036                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
3037                 }
3038                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
3039                                                       host->adma_table_sz,
3040                                                       &host->adma_addr,
3041                                                       GFP_KERNEL);
3042                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
3043                 if (!host->adma_table || !host->align_buffer) {
3044                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3045                                           host->adma_table, host->adma_addr);
3046                         kfree(host->align_buffer);
3047                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3048                                 mmc_hostname(mmc));
3049                         host->flags &= ~SDHCI_USE_ADMA;
3050                         host->adma_table = NULL;
3051                         host->align_buffer = NULL;
3052                 } else if (host->adma_addr & host->align_mask) {
3053                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3054                                 mmc_hostname(mmc));
3055                         host->flags &= ~SDHCI_USE_ADMA;
3056                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3057                                           host->adma_table, host->adma_addr);
3058                         kfree(host->align_buffer);
3059                         host->adma_table = NULL;
3060                         host->align_buffer = NULL;
3061                 }
3062         }
3063
3064         /*
3065          * If we use DMA, then it's up to the caller to set the DMA
3066          * mask, but PIO does not need the hw shim so we set a new
3067          * mask here in that case.
3068          */
3069         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3070                 host->dma_mask = DMA_BIT_MASK(64);
3071                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3072         }
3073
3074         if (host->version >= SDHCI_SPEC_300)
3075                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3076                         >> SDHCI_CLOCK_BASE_SHIFT;
3077         else
3078                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3079                         >> SDHCI_CLOCK_BASE_SHIFT;
3080
3081         host->max_clk *= 1000000;
3082         if (host->max_clk == 0 || host->quirks &
3083                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3084                 if (!host->ops->get_max_clock) {
3085                         pr_err("%s: Hardware doesn't specify base clock "
3086                                "frequency.\n", mmc_hostname(mmc));
3087                         return -ENODEV;
3088                 }
3089                 host->max_clk = host->ops->get_max_clock(host);
3090         }
3091
3092         host->next_data.cookie = 1;
3093         /*
3094          * In case of Host Controller v3.00, find out whether clock
3095          * multiplier is supported.
3096          */
3097         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3098                         SDHCI_CLOCK_MUL_SHIFT;
3099
3100         /*
3101          * In case the value in Clock Multiplier is 0, then programmable
3102          * clock mode is not supported, otherwise the actual clock
3103          * multiplier is one more than the value of Clock Multiplier
3104          * in the Capabilities Register.
3105          */
3106         if (host->clk_mul)
3107                 host->clk_mul += 1;
3108
3109         /*
3110          * Set host parameters.
3111          */
3112         mmc->ops = &sdhci_ops;
3113         mmc->f_max = host->max_clk;
3114         if (host->ops->get_min_clock)
3115                 mmc->f_min = host->ops->get_min_clock(host);
3116         else if (host->version >= SDHCI_SPEC_300) {
3117                 if (host->clk_mul) {
3118                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3119                         mmc->f_max = host->max_clk * host->clk_mul;
3120                 } else
3121                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3122         } else
3123                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3124
3125         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3126                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3127                                         SDHCI_TIMEOUT_CLK_SHIFT;
3128                 if (host->timeout_clk == 0) {
3129                         if (host->ops->get_timeout_clock) {
3130                                 host->timeout_clk =
3131                                         host->ops->get_timeout_clock(host);
3132                         } else {
3133                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3134                                         mmc_hostname(mmc));
3135                                 return -ENODEV;
3136                         }
3137                 }
3138
3139                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3140                         host->timeout_clk *= 1000;
3141
3142                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3143                         host->ops->get_max_timeout_count(host) : 1 << 27;
3144                 mmc->max_busy_timeout /= host->timeout_clk;
3145         }
3146
3147         if (override_timeout_clk)
3148                 host->timeout_clk = override_timeout_clk;
3149
3150         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3151         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3152
3153         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3154                 host->flags |= SDHCI_AUTO_CMD12;
3155
3156         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3157         if ((host->version >= SDHCI_SPEC_300) &&
3158             ((host->flags & SDHCI_USE_ADMA) ||
3159              !(host->flags & SDHCI_USE_SDMA))) {
3160                 host->flags |= SDHCI_AUTO_CMD23;
3161                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3162         } else {
3163                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3164         }
3165
3166         /*
3167          * A controller may support 8-bit width, but the board itself
3168          * might not have the pins brought out.  Boards that support
3169          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3170          * their platform code before calling sdhci_add_host(), and we
3171          * won't assume 8-bit width for hosts without that CAP.
3172          */
3173         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3174                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3175
3176         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3177                 mmc->caps &= ~MMC_CAP_CMD23;
3178
3179         if (caps[0] & SDHCI_CAN_DO_HISPD)
3180                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3181
3182         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3183             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3184                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3185
3186         /* If there are external regulators, get them */
3187         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3188                 return -EPROBE_DEFER;
3189
3190         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3191         if (!IS_ERR(mmc->supply.vqmmc)) {
3192                 ret = regulator_enable(mmc->supply.vqmmc);
3193                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3194                                                     1950000))
3195                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3196                                         SDHCI_SUPPORT_SDR50 |
3197                                         SDHCI_SUPPORT_DDR50);
3198                 if (ret) {
3199                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3200                                 mmc_hostname(mmc), ret);
3201                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3202                 }
3203         }
3204
3205         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3206                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3207                        SDHCI_SUPPORT_DDR50);
3208
3209         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3210         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3211                        SDHCI_SUPPORT_DDR50))
3212                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3213
3214         /* SDR104 supports also implies SDR50 support */
3215         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3216                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3217                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3218                  * field can be promoted to support HS200.
3219                  */
3220                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3221                         mmc->caps2 |= MMC_CAP2_HS200;
3222         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3223                 mmc->caps |= MMC_CAP_UHS_SDR50;
3224
3225         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3226             (caps[1] & SDHCI_SUPPORT_HS400))
3227                 mmc->caps2 |= MMC_CAP2_HS400;
3228
3229         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3230             (IS_ERR(mmc->supply.vqmmc) ||
3231              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3232                                              1300000)))
3233                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3234
3235         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3236                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3237                 mmc->caps |= MMC_CAP_UHS_DDR50;
3238
3239         /* Does the host need tuning for SDR50? */
3240         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3241                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3242
3243         /* Does the host need tuning for SDR104 / HS200? */
3244         if (mmc->caps2 & MMC_CAP2_HS200)
3245                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3246
3247         /* Driver Type(s) (A, C, D) supported by the host */
3248         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3249                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3250         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3251                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3252         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3253                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3254
3255         /* Initial value for re-tuning timer count */
3256         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3257                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3258
3259         /*
3260          * In case Re-tuning Timer is not disabled, the actual value of
3261          * re-tuning timer will be 2 ^ (n - 1).
3262          */
3263         if (host->tuning_count)
3264                 host->tuning_count = 1 << (host->tuning_count - 1);
3265
3266         /* Re-tuning mode supported by the Host Controller */
3267         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3268                              SDHCI_RETUNING_MODE_SHIFT;
3269
3270         ocr_avail = 0;
3271
3272         /*
3273          * According to SD Host Controller spec v3.00, if the Host System
3274          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3275          * the value is meaningful only if Voltage Support in the Capabilities
3276          * register is set. The actual current value is 4 times the register
3277          * value.
3278          */
3279         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3280         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3281                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3282                 if (curr > 0) {
3283
3284                         /* convert to SDHCI_MAX_CURRENT format */
3285                         curr = curr/1000;  /* convert to mA */
3286                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3287
3288                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3289                         max_current_caps =
3290                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3291                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3292                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3293                 }
3294         }
3295
3296         if (caps[0] & SDHCI_CAN_VDD_330) {
3297                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3298
3299                 mmc->max_current_330 = ((max_current_caps &
3300                                    SDHCI_MAX_CURRENT_330_MASK) >>
3301                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3302                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3303         }
3304         if (caps[0] & SDHCI_CAN_VDD_300) {
3305                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3306
3307                 mmc->max_current_300 = ((max_current_caps &
3308                                    SDHCI_MAX_CURRENT_300_MASK) >>
3309                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3310                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3311         }
3312         if (caps[0] & SDHCI_CAN_VDD_180) {
3313                 ocr_avail |= MMC_VDD_165_195;
3314
3315                 mmc->max_current_180 = ((max_current_caps &
3316                                    SDHCI_MAX_CURRENT_180_MASK) >>
3317                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3318                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3319         }
3320
3321         /* If OCR set by external regulators, use it instead */
3322         if (mmc->ocr_avail)
3323                 ocr_avail = mmc->ocr_avail;
3324
3325         if (host->ocr_mask)
3326                 ocr_avail &= host->ocr_mask;
3327
3328         mmc->ocr_avail = ocr_avail;
3329         mmc->ocr_avail_sdio = ocr_avail;
3330         if (host->ocr_avail_sdio)
3331                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3332         mmc->ocr_avail_sd = ocr_avail;
3333         if (host->ocr_avail_sd)
3334                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3335         else /* normal SD controllers don't support 1.8V */
3336                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3337         mmc->ocr_avail_mmc = ocr_avail;
3338         if (host->ocr_avail_mmc)
3339                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3340
3341         if (mmc->ocr_avail == 0) {
3342                 pr_err("%s: Hardware doesn't report any "
3343                         "support voltages.\n", mmc_hostname(mmc));
3344                 return -ENODEV;
3345         }
3346
3347         spin_lock_init(&host->lock);
3348
3349         /*
3350          * Maximum number of segments. Depends on if the hardware
3351          * can do scatter/gather or not.
3352          */
3353         if (host->flags & SDHCI_USE_ADMA)
3354                 mmc->max_segs = SDHCI_MAX_SEGS;
3355         else if (host->flags & SDHCI_USE_SDMA)
3356                 mmc->max_segs = 1;
3357         else /* PIO */
3358                 mmc->max_segs = SDHCI_MAX_SEGS;
3359
3360         /*
3361          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3362          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3363          * is less anyway.
3364          */
3365         mmc->max_req_size = 524288;
3366
3367         /*
3368          * Maximum segment size. Could be one segment with the maximum number
3369          * of bytes. When doing hardware scatter/gather, each entry cannot
3370          * be larger than 64 KiB though.
3371          */
3372         if (host->flags & SDHCI_USE_ADMA) {
3373                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3374                         mmc->max_seg_size = 65535;
3375                 else
3376                         mmc->max_seg_size = 65536;
3377         } else {
3378                 mmc->max_seg_size = mmc->max_req_size;
3379         }
3380
3381         /*
3382          * Maximum block size. This varies from controller to controller and
3383          * is specified in the capabilities register.
3384          */
3385         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3386                 mmc->max_blk_size = 2;
3387         } else {
3388                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3389                                 SDHCI_MAX_BLOCK_SHIFT;
3390                 if (mmc->max_blk_size >= 3) {
3391                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3392                                 mmc_hostname(mmc));
3393                         mmc->max_blk_size = 0;
3394                 }
3395         }
3396
3397         mmc->max_blk_size = 512 << mmc->max_blk_size;
3398
3399         /*
3400          * Maximum block count.
3401          */
3402         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3403
3404         /*
3405          * Init tasklets.
3406          */
3407         tasklet_init(&host->finish_tasklet,
3408                 sdhci_tasklet_finish, (unsigned long)host);
3409
3410         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3411
3412         if (host->version >= SDHCI_SPEC_300) {
3413                 init_waitqueue_head(&host->buf_ready_int);
3414
3415                 /* Initialize re-tuning timer */
3416                 init_timer(&host->tuning_timer);
3417                 host->tuning_timer.data = (unsigned long)host;
3418                 host->tuning_timer.function = sdhci_tuning_timer;
3419         }
3420
3421         sdhci_init(host, 0);
3422
3423         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3424                                    IRQF_SHARED, mmc_hostname(mmc), host);
3425         if (ret) {
3426                 pr_err("%s: Failed to request IRQ %d: %d\n",
3427                        mmc_hostname(mmc), host->irq, ret);
3428                 goto untasklet;
3429         }
3430
3431 #ifdef CONFIG_MMC_DEBUG
3432         sdhci_dumpregs(host);
3433 #endif
3434
3435 #ifdef SDHCI_USE_LEDS_CLASS
3436         snprintf(host->led_name, sizeof(host->led_name),
3437                 "%s::", mmc_hostname(mmc));
3438         host->led.name = host->led_name;
3439         host->led.brightness = LED_OFF;
3440         host->led.default_trigger = mmc_hostname(mmc);
3441         host->led.brightness_set = sdhci_led_control;
3442
3443         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3444         if (ret) {
3445                 pr_err("%s: Failed to register LED device: %d\n",
3446                        mmc_hostname(mmc), ret);
3447                 goto reset;
3448         }
3449 #endif
3450
3451         mmiowb();
3452
3453         mmc_add_host(mmc);
3454
3455         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3456                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3457                 (host->flags & SDHCI_USE_ADMA) ?
3458                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3459                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3460
3461         sdhci_enable_card_detection(host);
3462
3463         return 0;
3464
3465 #ifdef SDHCI_USE_LEDS_CLASS
3466 reset:
3467         sdhci_do_reset(host, SDHCI_RESET_ALL);
3468         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3469         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3470         free_irq(host->irq, host);
3471 #endif
3472 untasklet:
3473         tasklet_kill(&host->finish_tasklet);
3474
3475         return ret;
3476 }
3477
3478 EXPORT_SYMBOL_GPL(sdhci_add_host);
3479
3480 void sdhci_remove_host(struct sdhci_host *host, int dead)
3481 {
3482         struct mmc_host *mmc = host->mmc;
3483         unsigned long flags;
3484
3485         if (dead) {
3486                 spin_lock_irqsave(&host->lock, flags);
3487
3488                 host->flags |= SDHCI_DEVICE_DEAD;
3489
3490                 if (host->mrq) {
3491                         pr_err("%s: Controller removed during "
3492                                 " transfer!\n", mmc_hostname(mmc));
3493
3494                         host->mrq->cmd->error = -ENOMEDIUM;
3495                         tasklet_schedule(&host->finish_tasklet);
3496                 }
3497
3498                 spin_unlock_irqrestore(&host->lock, flags);
3499         }
3500
3501         sdhci_disable_card_detection(host);
3502
3503         mmc_remove_host(mmc);
3504
3505 #ifdef SDHCI_USE_LEDS_CLASS
3506         led_classdev_unregister(&host->led);
3507 #endif
3508
3509         if (!dead)
3510                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3511
3512         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3513         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3514         free_irq(host->irq, host);
3515
3516         del_timer_sync(&host->timer);
3517
3518         tasklet_kill(&host->finish_tasklet);
3519
3520         if (!IS_ERR(mmc->supply.vqmmc))
3521                 regulator_disable(mmc->supply.vqmmc);
3522
3523         if (host->adma_table)
3524                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3525                                   host->adma_table, host->adma_addr);
3526         kfree(host->align_buffer);
3527
3528         host->adma_table = NULL;
3529         host->align_buffer = NULL;
3530 }
3531
3532 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3533
3534 void sdhci_free_host(struct sdhci_host *host)
3535 {
3536         mmc_free_host(host->mmc);
3537 }
3538
3539 EXPORT_SYMBOL_GPL(sdhci_free_host);
3540
3541 /*****************************************************************************\
3542  *                                                                           *
3543  * Driver init/exit                                                          *
3544  *                                                                           *
3545 \*****************************************************************************/
3546
3547 static int __init sdhci_drv_init(void)
3548 {
3549         pr_info(DRIVER_NAME
3550                 ": Secure Digital Host Controller Interface driver\n");
3551         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3552
3553         return 0;
3554 }
3555
3556 static void __exit sdhci_drv_exit(void)
3557 {
3558 }
3559
3560 module_init(sdhci_drv_init);
3561 module_exit(sdhci_drv_exit);
3562
3563 module_param(debug_quirks, uint, 0444);
3564 module_param(debug_quirks2, uint, 0444);
3565
3566 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3567 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3568 MODULE_LICENSE("GPL");
3569
3570 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3571 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");