1 // SPDX-License-Identifier: GPL-2.0
3 // Secure Digital Host Controller
5 // Copyright (C) 2018 Spreadtrum, Inc.
6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/highmem.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_gpio.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/slab.h>
21 #include "sdhci-pltfm.h"
23 /* SDHCI_ARGUMENT2 register high 16bit */
24 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
26 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
27 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
28 #define SDHCI_SPRD_DLL_EN BIT(21)
29 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
30 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
31 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
33 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
35 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
36 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
37 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
38 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
39 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
41 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
42 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
43 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
45 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
46 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
47 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
49 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
51 /* SDHCI_HOST_CONTROL2 */
52 #define SDHCI_SPRD_CTRL_HS200 0x0005
53 #define SDHCI_SPRD_CTRL_HS400 0x0006
54 #define SDHCI_SPRD_CTRL_HS400ES 0x0007
57 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
58 * reserved, and only used on Spreadtrum's design, the hardware cannot work
59 * if this bit is cleared.
63 #define SDHCI_HW_RESET_CARD BIT(3)
65 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
66 #define SDHCI_SPRD_CLK_MAX_DIV 1023
68 #define SDHCI_SPRD_CLK_DEF_RATE 26000000
69 #define SDHCI_SPRD_PHY_DLL_CLK 52000000
71 struct sdhci_sprd_host {
74 struct clk *clk_enable;
75 struct clk *clk_2x_enable;
76 struct pinctrl *pinctrl;
77 struct pinctrl_state *pins_uhs;
78 struct pinctrl_state *pins_default;
80 int flags; /* backup of host attribute */
81 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
84 struct sdhci_sprd_phy_cfg {
89 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
90 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
91 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
92 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
93 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
94 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
95 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
96 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
97 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
98 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
101 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
103 static void sdhci_sprd_init_config(struct sdhci_host *host)
107 /* set dll backup mode */
108 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
109 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
110 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
113 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
115 if (unlikely(reg == SDHCI_MAX_CURRENT))
116 return SDHCI_SPRD_MAX_CUR;
118 return readl_relaxed(host->ioaddr + reg);
121 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
123 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
124 if (unlikely(reg == SDHCI_MAX_CURRENT))
127 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
128 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
130 writel_relaxed(val, host->ioaddr + reg);
133 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
135 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
136 if (unlikely(reg == SDHCI_BLOCK_COUNT))
139 writew_relaxed(val, host->ioaddr + reg);
142 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
145 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
146 * standard specification, sdhci_reset() write this register directly
147 * without checking other reserved bits, that will clear BIT(3) which
148 * is defined as hardware reset on Spreadtrum's platform and clearing
149 * it by mistake will lead the card not work. So here we need to work
152 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
153 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
154 val |= SDHCI_HW_RESET_CARD;
157 writeb_relaxed(val, host->ioaddr + reg);
160 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
162 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
164 ctrl &= ~SDHCI_CLOCK_CARD_EN;
165 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
168 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
172 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
173 ctrl |= SDHCI_CLOCK_CARD_EN;
174 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
178 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
182 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
184 dll_dly_offset |= mask;
186 dll_dly_offset &= ~mask;
187 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
190 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
194 /* select 2x clock source */
195 if (base_clk <= clk * 2)
198 div = (u32) (base_clk / (clk * 2));
200 if ((base_clk / div) > (clk * 2))
203 if (div > SDHCI_SPRD_CLK_MAX_DIV)
204 div = SDHCI_SPRD_CLK_MAX_DIV;
214 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
217 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
220 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
222 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
223 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
224 sdhci_enable_clk(host, div);
226 /* enable auto gate sdhc_enable_auto_gate */
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
228 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
229 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
230 if (mask != (val & mask)) {
232 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
236 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
240 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
241 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
242 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
244 usleep_range(1000, 1250);
246 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
247 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
248 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
249 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
251 usleep_range(1000, 1250);
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
254 tmp |= SDHCI_SPRD_DLL_EN;
255 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
257 usleep_range(1000, 1250);
260 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
262 bool en = false, clk_changed = false;
265 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
266 } else if (clock != host->clock) {
267 sdhci_sprd_sd_clk_off(host);
268 _sdhci_sprd_set_clock(host, clock);
272 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
273 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
276 _sdhci_sprd_set_clock(host, clock);
280 * According to the Spreadtrum SD host specification, when we changed
281 * the clock to be more than 52M, we should enable the PHY DLL which
282 * is used to track the clock frequency to make the clock work more
283 * stable. Otherwise deviation may occur of the higher clock.
285 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
286 sdhci_sprd_enable_phy_dll(host);
289 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
291 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
293 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
296 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
301 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
304 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
305 struct mmc_host *mmc = host->mmc;
306 u32 *p = sprd_host->phy_delay;
309 if (timing == host->timing)
312 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
313 /* Select Bus Speed Mode for host */
314 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
316 case MMC_TIMING_UHS_SDR12:
317 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
319 case MMC_TIMING_MMC_HS:
320 case MMC_TIMING_SD_HS:
321 case MMC_TIMING_UHS_SDR25:
322 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
324 case MMC_TIMING_UHS_SDR50:
325 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
327 case MMC_TIMING_UHS_SDR104:
328 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
330 case MMC_TIMING_UHS_DDR50:
331 case MMC_TIMING_MMC_DDR52:
332 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
334 case MMC_TIMING_MMC_HS200:
335 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
337 case MMC_TIMING_MMC_HS400:
338 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
344 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
346 if (!mmc->ios.enhanced_strobe)
347 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
350 static void sdhci_sprd_hw_reset(struct sdhci_host *host)
355 * Note: don't use sdhci_writeb() API here since it is redirected to
356 * sdhci_sprd_writeb() in which we have a workaround for
357 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
360 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
361 val &= ~SDHCI_HW_RESET_CARD;
362 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
364 usleep_range(10, 20);
366 val |= SDHCI_HW_RESET_CARD;
367 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
368 usleep_range(300, 500);
371 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
373 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
377 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
382 static struct sdhci_ops sdhci_sprd_ops = {
383 .read_l = sdhci_sprd_readl,
384 .write_l = sdhci_sprd_writel,
385 .write_b = sdhci_sprd_writeb,
386 .set_clock = sdhci_sprd_set_clock,
387 .get_max_clock = sdhci_sprd_get_max_clock,
388 .get_min_clock = sdhci_sprd_get_min_clock,
389 .set_bus_width = sdhci_set_bus_width,
390 .reset = sdhci_reset,
391 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
392 .hw_reset = sdhci_sprd_hw_reset,
393 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
394 .get_ro = sdhci_sprd_get_ro,
397 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
399 struct sdhci_host *host = mmc_priv(mmc);
400 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
402 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
405 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
406 * block count register which doesn't support stuff bits of
407 * CMD23 argument on Spreadtrum's sd host controller.
409 if (host->version >= SDHCI_SPEC_410 &&
410 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
411 (host->flags & SDHCI_AUTO_CMD23))
412 host->flags &= ~SDHCI_AUTO_CMD23;
414 sdhci_request(mmc, mrq);
417 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
419 struct sdhci_host *host = mmc_priv(mmc);
420 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
423 if (!IS_ERR(mmc->supply.vqmmc)) {
424 ret = mmc_regulator_set_vqmmc(mmc, ios);
426 pr_err("%s: Switching signalling voltage failed\n",
432 if (IS_ERR(sprd_host->pinctrl))
435 switch (ios->signal_voltage) {
436 case MMC_SIGNAL_VOLTAGE_180:
437 ret = pinctrl_select_state(sprd_host->pinctrl,
438 sprd_host->pins_uhs);
440 pr_err("%s: failed to select uhs pin state\n",
448 case MMC_SIGNAL_VOLTAGE_330:
449 ret = pinctrl_select_state(sprd_host->pinctrl,
450 sprd_host->pins_default);
452 pr_err("%s: failed to select default pin state\n",
459 /* Wait for 300 ~ 500 us for pin state stable */
460 usleep_range(300, 500);
461 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
466 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
469 struct sdhci_host *host = mmc_priv(mmc);
470 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
471 u32 *p = sprd_host->phy_delay;
474 if (!ios->enhanced_strobe)
477 sdhci_sprd_sd_clk_off(host);
479 /* Set HS400 enhanced strobe mode */
480 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
481 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
482 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
483 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
485 sdhci_sprd_sd_clk_on(host);
487 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
488 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
489 SDHCI_SPRD_REG_32_DLL_DLY);
492 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
493 struct device_node *np)
495 u32 *p = sprd_host->phy_delay;
499 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
500 ret = of_property_read_u32_array(np,
501 sdhci_sprd_phy_cfgs[i].property, val, 4);
505 index = sdhci_sprd_phy_cfgs[i].timing;
506 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
510 static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
511 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
512 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
513 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
514 SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
515 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
516 .ops = &sdhci_sprd_ops,
519 static int sdhci_sprd_probe(struct platform_device *pdev)
521 struct sdhci_host *host;
522 struct sdhci_sprd_host *sprd_host;
526 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
528 return PTR_ERR(host);
530 host->dma_mask = DMA_BIT_MASK(64);
531 pdev->dev.dma_mask = &host->dma_mask;
532 host->mmc_host_ops.request = sdhci_sprd_request;
533 host->mmc_host_ops.hs400_enhanced_strobe =
534 sdhci_sprd_hs400_enhanced_strobe;
536 * We can not use the standard ops to change and detect the voltage
537 * signal for Spreadtrum SD host controller, since our voltage regulator
538 * for I/O is fixed in hardware, that means we do not need control
539 * the standard SD host controller to change the I/O voltage.
541 host->mmc_host_ops.start_signal_voltage_switch =
542 sdhci_sprd_voltage_switch;
544 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
545 MMC_CAP_ERASE | MMC_CAP_CMD23;
546 ret = mmc_of_parse(host->mmc);
550 sprd_host = TO_SPRD_HOST(host);
551 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
553 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
554 if (!IS_ERR(sprd_host->pinctrl)) {
555 sprd_host->pins_uhs =
556 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
557 if (IS_ERR(sprd_host->pins_uhs)) {
558 ret = PTR_ERR(sprd_host->pins_uhs);
562 sprd_host->pins_default =
563 pinctrl_lookup_state(sprd_host->pinctrl, "default");
564 if (IS_ERR(sprd_host->pins_default)) {
565 ret = PTR_ERR(sprd_host->pins_default);
570 clk = devm_clk_get(&pdev->dev, "sdio");
575 sprd_host->clk_sdio = clk;
576 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
577 if (!sprd_host->base_rate)
578 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
580 clk = devm_clk_get(&pdev->dev, "enable");
585 sprd_host->clk_enable = clk;
587 clk = devm_clk_get(&pdev->dev, "2x_enable");
589 sprd_host->clk_2x_enable = clk;
591 ret = clk_prepare_enable(sprd_host->clk_sdio);
595 ret = clk_prepare_enable(sprd_host->clk_enable);
599 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
603 sdhci_sprd_init_config(host);
604 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
605 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
606 SDHCI_VENDOR_VER_SHIFT);
608 pm_runtime_get_noresume(&pdev->dev);
609 pm_runtime_set_active(&pdev->dev);
610 pm_runtime_enable(&pdev->dev);
611 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
612 pm_runtime_use_autosuspend(&pdev->dev);
613 pm_suspend_ignore_children(&pdev->dev, 1);
615 sdhci_enable_v4_mode(host);
617 ret = sdhci_setup_host(host);
619 goto pm_runtime_disable;
621 sprd_host->flags = host->flags;
623 ret = __sdhci_add_host(host);
625 goto err_cleanup_host;
627 pm_runtime_mark_last_busy(&pdev->dev);
628 pm_runtime_put_autosuspend(&pdev->dev);
633 sdhci_cleanup_host(host);
636 pm_runtime_put_noidle(&pdev->dev);
637 pm_runtime_disable(&pdev->dev);
638 pm_runtime_set_suspended(&pdev->dev);
640 clk_disable_unprepare(sprd_host->clk_2x_enable);
643 clk_disable_unprepare(sprd_host->clk_enable);
646 clk_disable_unprepare(sprd_host->clk_sdio);
649 sdhci_pltfm_free(pdev);
653 static int sdhci_sprd_remove(struct platform_device *pdev)
655 struct sdhci_host *host = platform_get_drvdata(pdev);
656 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
657 struct mmc_host *mmc = host->mmc;
659 mmc_remove_host(mmc);
660 clk_disable_unprepare(sprd_host->clk_sdio);
661 clk_disable_unprepare(sprd_host->clk_enable);
662 clk_disable_unprepare(sprd_host->clk_2x_enable);
669 static const struct of_device_id sdhci_sprd_of_match[] = {
670 { .compatible = "sprd,sdhci-r11", },
673 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
676 static int sdhci_sprd_runtime_suspend(struct device *dev)
678 struct sdhci_host *host = dev_get_drvdata(dev);
679 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
681 sdhci_runtime_suspend_host(host);
683 clk_disable_unprepare(sprd_host->clk_sdio);
684 clk_disable_unprepare(sprd_host->clk_enable);
685 clk_disable_unprepare(sprd_host->clk_2x_enable);
690 static int sdhci_sprd_runtime_resume(struct device *dev)
692 struct sdhci_host *host = dev_get_drvdata(dev);
693 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
696 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
700 ret = clk_prepare_enable(sprd_host->clk_enable);
704 ret = clk_prepare_enable(sprd_host->clk_sdio);
708 sdhci_runtime_resume_host(host, 1);
712 clk_disable_unprepare(sprd_host->clk_enable);
715 clk_disable_unprepare(sprd_host->clk_2x_enable);
721 static const struct dev_pm_ops sdhci_sprd_pm_ops = {
722 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
723 pm_runtime_force_resume)
724 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
725 sdhci_sprd_runtime_resume, NULL)
728 static struct platform_driver sdhci_sprd_driver = {
729 .probe = sdhci_sprd_probe,
730 .remove = sdhci_sprd_remove,
732 .name = "sdhci_sprd_r11",
733 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
734 .pm = &sdhci_sprd_pm_ops,
737 module_platform_driver(sdhci_sprd_driver);
739 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
740 MODULE_LICENSE("GPL v2");
741 MODULE_ALIAS("platform:sdhci-sprd-r11");