1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/platform_data/mmc-sdhci-s3c.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
25 #include <linux/of_gpio.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/mmc/host.h>
31 #include "sdhci-s3c-regs.h"
34 #define MAX_BUS_CLK (4)
37 * struct sdhci_s3c - S3C SDHCI instance
38 * @host: The SDHCI host created
39 * @pdev: The platform device we where created from.
40 * @ioarea: The resource created when we claimed the IO area.
41 * @pdata: The platform data for this controller.
42 * @cur_clk: The index of the current bus clock.
43 * @clk_io: The clock for the internal bus interface.
44 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
47 struct sdhci_host *host;
48 struct platform_device *pdev;
49 struct resource *ioarea;
50 struct s3c_sdhci_platdata *pdata;
56 struct clk *clk_bus[MAX_BUS_CLK];
57 unsigned long clk_rates[MAX_BUS_CLK];
63 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
64 * @sdhci_quirks: sdhci host specific quirks.
66 * Specifies platform specific configuration of sdhci controller.
67 * Note: A structure for driver specific platform data is used for future
68 * expansion of its usage.
70 struct sdhci_s3c_drv_data {
71 unsigned int sdhci_quirks;
75 static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
77 return sdhci_priv(host);
81 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
82 * @host: The SDHCI host instance.
84 * Callback to return the maximum clock rate acheivable by the controller.
86 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
88 struct sdhci_s3c *ourhost = to_s3c(host);
89 unsigned long rate, max = 0;
92 for (src = 0; src < MAX_BUS_CLK; src++) {
93 rate = ourhost->clk_rates[src];
102 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
103 * @ourhost: Our SDHCI instance.
104 * @src: The source clock index.
105 * @wanted: The clock frequency wanted.
107 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
112 struct clk *clksrc = ourhost->clk_bus[src];
119 * If controller uses a non-standard clock division, find the best clock
120 * speed possible with selected clock source and skip the division.
122 if (ourhost->no_divider) {
123 rate = clk_round_rate(clksrc, wanted);
124 return wanted - rate;
127 rate = ourhost->clk_rates[src];
129 for (shift = 0; shift <= 8; ++shift) {
130 if ((rate >> shift) <= wanted)
135 dev_dbg(&ourhost->pdev->dev,
136 "clk %d: rate %ld, min rate %lu > wanted %u\n",
137 src, rate, rate / 256, wanted);
141 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
142 src, rate, wanted, rate >> shift);
144 return wanted - (rate >> shift);
148 * sdhci_s3c_set_clock - callback on clock change
149 * @host: The SDHCI host being changed
150 * @clock: The clock rate being requested.
152 * When the card's clock is going to be changed, look at the new frequency
153 * and find the best clock source to go with it.
155 static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
157 struct sdhci_s3c *ourhost = to_s3c(host);
158 unsigned int best = UINT_MAX;
164 host->mmc->actual_clock = 0;
166 /* don't bother if the clock is going off. */
168 sdhci_set_clock(host, clock);
172 for (src = 0; src < MAX_BUS_CLK; src++) {
173 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
180 dev_dbg(&ourhost->pdev->dev,
181 "selected source %d, clock %d, delta %d\n",
182 best_src, clock, best);
184 /* select the new clock source */
185 if (ourhost->cur_clk != best_src) {
186 struct clk *clk = ourhost->clk_bus[best_src];
188 clk_prepare_enable(clk);
189 if (ourhost->cur_clk >= 0)
190 clk_disable_unprepare(
191 ourhost->clk_bus[ourhost->cur_clk]);
193 ourhost->cur_clk = best_src;
194 host->max_clk = ourhost->clk_rates[best_src];
197 /* turn clock off to card before changing clock source */
198 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
200 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
201 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
202 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
203 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
205 /* reprogram default hardware configuration */
206 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
207 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
209 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
210 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
211 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
212 S3C_SDHCI_CTRL2_ENFBCLKRX |
213 S3C_SDHCI_CTRL2_DFCNT_NONE |
214 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
215 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
217 /* reconfigure the controller for new clock rate */
218 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
219 if (clock < 25 * 1000000)
220 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
221 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
223 sdhci_set_clock(host, clock);
227 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
228 * @host: The SDHCI host being queried
230 * To init mmc host properly a minimal clock value is needed. For high system
231 * bus clock's values the standard formula gives values out of allowed range.
232 * The clock still can be set to lower values, if clock source other then
233 * system bus is selected.
235 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
237 struct sdhci_s3c *ourhost = to_s3c(host);
238 unsigned long rate, min = ULONG_MAX;
241 for (src = 0; src < MAX_BUS_CLK; src++) {
242 rate = ourhost->clk_rates[src] / 256;
252 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
253 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
255 struct sdhci_s3c *ourhost = to_s3c(host);
256 unsigned long rate, max = 0;
259 for (src = 0; src < MAX_BUS_CLK; src++) {
262 clk = ourhost->clk_bus[src];
266 rate = clk_round_rate(clk, ULONG_MAX);
274 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
275 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
277 struct sdhci_s3c *ourhost = to_s3c(host);
278 unsigned long rate, min = ULONG_MAX;
281 for (src = 0; src < MAX_BUS_CLK; src++) {
284 clk = ourhost->clk_bus[src];
288 rate = clk_round_rate(clk, 0);
296 /* sdhci_cmu_set_clock - callback on clock change.*/
297 static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
299 struct sdhci_s3c *ourhost = to_s3c(host);
300 struct device *dev = &ourhost->pdev->dev;
301 unsigned long timeout;
304 host->mmc->actual_clock = 0;
306 /* If the clock is going off, set to 0 at clock control register */
308 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
312 sdhci_s3c_set_clock(host, clock);
314 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
316 clk = SDHCI_CLOCK_INT_EN;
317 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
321 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
322 & SDHCI_CLOCK_INT_STABLE)) {
324 dev_err(dev, "%s: Internal clock never stabilised.\n",
325 mmc_hostname(host->mmc));
332 clk |= SDHCI_CLOCK_CARD_EN;
333 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
337 * sdhci_s3c_set_bus_width - support 8bit buswidth
338 * @host: The SDHCI host being queried
339 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
341 * We have 8-bit width support but is not a v3 controller.
342 * So we add platform_bus_width() and support 8bit width.
344 static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
348 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
351 case MMC_BUS_WIDTH_8:
352 ctrl |= SDHCI_CTRL_8BITBUS;
353 ctrl &= ~SDHCI_CTRL_4BITBUS;
355 case MMC_BUS_WIDTH_4:
356 ctrl |= SDHCI_CTRL_4BITBUS;
357 ctrl &= ~SDHCI_CTRL_8BITBUS;
360 ctrl &= ~SDHCI_CTRL_4BITBUS;
361 ctrl &= ~SDHCI_CTRL_8BITBUS;
365 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
368 static struct sdhci_ops sdhci_s3c_ops = {
369 .get_max_clock = sdhci_s3c_get_max_clk,
370 .set_clock = sdhci_s3c_set_clock,
371 .get_min_clock = sdhci_s3c_get_min_clock,
372 .set_bus_width = sdhci_s3c_set_bus_width,
373 .reset = sdhci_reset,
374 .set_uhs_signaling = sdhci_set_uhs_signaling,
378 static int sdhci_s3c_parse_dt(struct device *dev,
379 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
381 struct device_node *node = dev->of_node;
384 /* if the bus-width property is not specified, assume width as 1 */
385 if (of_property_read_u32(node, "bus-width", &max_width))
387 pdata->max_width = max_width;
389 /* get the card detection method */
390 if (of_get_property(node, "broken-cd", NULL)) {
391 pdata->cd_type = S3C_SDHCI_CD_NONE;
395 if (of_get_property(node, "non-removable", NULL)) {
396 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
400 if (of_get_named_gpio(node, "cd-gpios", 0))
403 /* assuming internal card detect that will be configured by pinctrl */
404 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
408 static int sdhci_s3c_parse_dt(struct device *dev,
409 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
415 static const struct of_device_id sdhci_s3c_dt_match[];
417 static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
418 struct platform_device *pdev)
421 if (pdev->dev.of_node) {
422 const struct of_device_id *match;
423 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
424 return (struct sdhci_s3c_drv_data *)match->data;
427 return (struct sdhci_s3c_drv_data *)
428 platform_get_device_id(pdev)->driver_data;
431 static int sdhci_s3c_probe(struct platform_device *pdev)
433 struct s3c_sdhci_platdata *pdata;
434 struct sdhci_s3c_drv_data *drv_data;
435 struct device *dev = &pdev->dev;
436 struct sdhci_host *host;
437 struct sdhci_s3c *sc;
438 struct resource *res;
439 int ret, irq, ptr, clks;
441 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
442 dev_err(dev, "no device data specified\n");
446 irq = platform_get_irq(pdev, 0);
448 dev_err(dev, "no irq specified\n");
452 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
454 dev_err(dev, "sdhci_alloc_host() failed\n");
455 return PTR_ERR(host);
457 sc = sdhci_priv(host);
459 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
462 goto err_pdata_io_clk;
465 if (pdev->dev.of_node) {
466 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
468 goto err_pdata_io_clk;
470 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
471 sc->ext_cd_gpio = -1; /* invalid gpio number */
474 drv_data = sdhci_s3c_get_driver_data(pdev);
481 platform_set_drvdata(pdev, host);
483 sc->clk_io = devm_clk_get(dev, "hsmmc");
484 if (IS_ERR(sc->clk_io)) {
485 dev_err(dev, "failed to get io clock\n");
486 ret = PTR_ERR(sc->clk_io);
487 goto err_pdata_io_clk;
490 /* enable the local io clock and keep it running for the moment. */
491 clk_prepare_enable(sc->clk_io);
493 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
496 snprintf(name, 14, "mmc_busclk.%d", ptr);
497 sc->clk_bus[ptr] = devm_clk_get(dev, name);
498 if (IS_ERR(sc->clk_bus[ptr]))
502 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
504 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
505 ptr, name, sc->clk_rates[ptr]);
509 dev_err(dev, "failed to find any bus clocks\n");
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 host->ioaddr = devm_ioremap_resource(&pdev->dev, res);
516 if (IS_ERR(host->ioaddr)) {
517 ret = PTR_ERR(host->ioaddr);
521 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
523 pdata->cfg_gpio(pdev, pdata->max_width);
525 host->hw_name = "samsung-hsmmc";
526 host->ops = &sdhci_s3c_ops;
531 /* Setup quirks for the controller */
532 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
533 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
535 host->quirks |= drv_data->sdhci_quirks;
536 sc->no_divider = drv_data->no_divider;
539 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
541 /* we currently see overruns on errors, so disable the SDMA
542 * support as well. */
543 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
545 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
547 /* It seems we do not get an DATA transfer complete on non-busy
548 * transfers, not sure if this is a problem with this specific
549 * SDHCI block, or a missing configuration that needs to be set. */
550 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
552 /* This host supports the Auto CMD12 */
553 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
555 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
556 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
558 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
559 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
560 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
562 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
563 host->mmc->caps = MMC_CAP_NONREMOVABLE;
565 switch (pdata->max_width) {
567 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
569 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
574 host->mmc->pm_caps |= pdata->pm_caps;
576 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
577 SDHCI_QUIRK_32BIT_DMA_SIZE);
579 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
580 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
583 * If controller does not have internal clock divider,
584 * we can use overriding functions instead of default.
586 if (sc->no_divider) {
587 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
588 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
589 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
592 /* It supports additional host capabilities if needed */
593 if (pdata->host_caps)
594 host->mmc->caps |= pdata->host_caps;
596 if (pdata->host_caps2)
597 host->mmc->caps2 |= pdata->host_caps2;
599 pm_runtime_enable(&pdev->dev);
600 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
601 pm_runtime_use_autosuspend(&pdev->dev);
602 pm_suspend_ignore_children(&pdev->dev, 1);
604 mmc_of_parse(host->mmc);
606 ret = sdhci_add_host(host);
608 dev_err(dev, "sdhci_add_host() failed\n");
609 pm_runtime_forbid(&pdev->dev);
610 pm_runtime_get_noresume(&pdev->dev);
614 #ifdef CONFIG_PM_RUNTIME
615 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
616 clk_disable_unprepare(sc->clk_io);
622 clk_disable_unprepare(sc->clk_io);
625 sdhci_free_host(host);
630 static int sdhci_s3c_remove(struct platform_device *pdev)
632 struct sdhci_host *host = platform_get_drvdata(pdev);
633 struct sdhci_s3c *sc = sdhci_priv(host);
636 free_irq(sc->ext_cd_irq, sc);
638 #ifdef CONFIG_PM_RUNTIME
639 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
640 clk_prepare_enable(sc->clk_io);
642 sdhci_remove_host(host, 1);
644 pm_runtime_dont_use_autosuspend(&pdev->dev);
645 pm_runtime_disable(&pdev->dev);
647 clk_disable_unprepare(sc->clk_io);
649 sdhci_free_host(host);
654 #ifdef CONFIG_PM_SLEEP
655 static int sdhci_s3c_suspend(struct device *dev)
657 struct sdhci_host *host = dev_get_drvdata(dev);
659 return sdhci_suspend_host(host);
662 static int sdhci_s3c_resume(struct device *dev)
664 struct sdhci_host *host = dev_get_drvdata(dev);
666 return sdhci_resume_host(host);
670 #ifdef CONFIG_PM_RUNTIME
671 static int sdhci_s3c_runtime_suspend(struct device *dev)
673 struct sdhci_host *host = dev_get_drvdata(dev);
674 struct sdhci_s3c *ourhost = to_s3c(host);
675 struct clk *busclk = ourhost->clk_io;
678 ret = sdhci_runtime_suspend_host(host);
680 if (ourhost->cur_clk >= 0)
681 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
682 clk_disable_unprepare(busclk);
686 static int sdhci_s3c_runtime_resume(struct device *dev)
688 struct sdhci_host *host = dev_get_drvdata(dev);
689 struct sdhci_s3c *ourhost = to_s3c(host);
690 struct clk *busclk = ourhost->clk_io;
693 clk_prepare_enable(busclk);
694 if (ourhost->cur_clk >= 0)
695 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
696 ret = sdhci_runtime_resume_host(host);
702 static const struct dev_pm_ops sdhci_s3c_pmops = {
703 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
704 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
708 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
711 #define SDHCI_S3C_PMOPS NULL
714 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
715 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
718 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
720 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
723 static struct platform_device_id sdhci_s3c_driver_ids[] = {
726 .driver_data = (kernel_ulong_t)NULL,
728 .name = "exynos4-sdhci",
729 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
733 MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
736 static const struct of_device_id sdhci_s3c_dt_match[] = {
737 { .compatible = "samsung,s3c6410-sdhci", },
738 { .compatible = "samsung,exynos4210-sdhci",
739 .data = (void *)EXYNOS4_SDHCI_DRV_DATA },
742 MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
745 static struct platform_driver sdhci_s3c_driver = {
746 .probe = sdhci_s3c_probe,
747 .remove = sdhci_s3c_remove,
748 .id_table = sdhci_s3c_driver_ids,
750 .owner = THIS_MODULE,
752 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
753 .pm = SDHCI_S3C_PMOPS,
757 module_platform_driver(sdhci_s3c_driver);
759 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
760 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
761 MODULE_LICENSE("GPL v2");
762 MODULE_ALIAS("platform:s3c-sdhci");