drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/mbus.h>
  38
  39 #include "sdhci.h"
  40 #include "sdhci-pltfm.h"
  41
  42 #define PXAV3_RPM_DELAY_MS     50
  43
  44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  45 #define SDCLK_SEL       0x100
  46 #define SDCLK_DELAY_SHIFT       9
  47 #define SDCLK_DELAY_MASK        0x1f
  48
  49 #define SD_CFG_FIFO_PARAM       0x100
  50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  53
  54 #define SD_SPI_MODE          0x108
  55 #define SD_CE_ATA_1          0x10C
  56
  57 #define SD_CE_ATA_2          0x10E
  58 #define SDCE_MISC_INT           (1<<2)
  59 #define SDCE_MISC_INT_EN        (1<<1)
  60
  61 /*
  62  * These registers are relative to the second register region, for the
  63  * MBus bridge.
  64  */
  65 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
  66 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
  67 #define SDHCI_MAX_WIN_NUM       8
  68
  69 static int mv_conf_mbus_windows(struct platform_device *pdev,
  70                                 const struct mbus_dram_target_info *dram)
  71 {
  72         int i;
  73         void __iomem *regs;
  74         struct resource *res;
  75
  76         if (!dram) {
  77                 dev_err(&pdev->dev, "no mbus dram info\n");
  78                 return -EINVAL;
  79         }
  80
  81         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  82         if (!res) {
  83                 dev_err(&pdev->dev, "cannot get mbus registers\n");
  84                 return -EINVAL;
  85         }
  86
  87         regs = ioremap(res->start, resource_size(res));
  88         if (!regs) {
  89                 dev_err(&pdev->dev, "cannot map mbus registers\n");
  90                 return -ENOMEM;
  91         }
  92
  93         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
  94                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
  95                 writel(0, regs + SDHCI_WINDOW_BASE(i));
  96         }
  97
  98         for (i = 0; i < dram->num_cs; i++) {
  99                 const struct mbus_dram_window *cs = dram->cs + i;
 100
 101                 /* Write size, attributes and target id to control register */
 102                 writel(((cs->size - 1) & 0xffff0000) |
 103                         (cs->mbus_attr << 8) |
 104                         (dram->mbus_dram_target_id << 4) | 1,
 105                         regs + SDHCI_WINDOW_CTRL(i));
 106                 /* Write base address to base register */
 107                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 108         }
 109
 110         iounmap(regs);
 111
 112         return 0;
 113 }
 114
 115 static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
 116 {
 117         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 118         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 119
 120         if (mask == SDHCI_RESET_ALL) {
 121                 /*
 122                  * tune timing of read data/command when crc error happen
 123                  * no performance impact
 124                  */
 125                 if (pdata && 0 != pdata->clk_delay_cycles) {
 126                         u16 tmp;
 127
 128                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 129                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 130                                 << SDCLK_DELAY_SHIFT;
 131                         tmp |= SDCLK_SEL;
 132                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 133                 }
 134         }
 135 }
 136
 137 #define MAX_WAIT_COUNT 5
 138 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 139 {
 140         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 141         struct sdhci_pxa *pxa = pltfm_host->priv;
 142         u16 tmp;
 143         int count;
 144
 145         if (pxa->power_mode == MMC_POWER_UP
 146                         && power_mode == MMC_POWER_ON) {
 147
 148                 dev_dbg(mmc_dev(host->mmc),
 149                                 "%s: slot->power_mode = %d,"
 150                                 "ios->power_mode = %d\n",
 151                                 __func__,
 152                                 pxa->power_mode,
 153                                 power_mode);
 154
 155                 /* set we want notice of when 74 clocks are sent */
 156                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 157                 tmp |= SDCE_MISC_INT_EN;
 158                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 159
 160                 /* start sending the 74 clocks */
 161                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 162                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 163                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 164
 165                 /* slowest speed is about 100KHz or 10usec per clock */
 166                 udelay(740);
 167                 count = 0;
 168
 169                 while (count++ < MAX_WAIT_COUNT) {
 170                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 171                                                 & SDCE_MISC_INT) == 0)
 172                                 break;
 173                         udelay(10);
 174                 }
 175
 176                 if (count == MAX_WAIT_COUNT)
 177                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 178
 179                 /* clear the interrupt bit if posted */
 180                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 181                 tmp |= SDCE_MISC_INT;
 182                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 183         }
 184         pxa->power_mode = power_mode;
 185 }
 186
 187 static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 188 {
 189         u16 ctrl_2;
 190
 191         /*
 192          * Set V18_EN -- UHS modes do not work without this.
 193          * does not change signaling voltage
 194          */
 195         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 196
 197         /* Select Bus Speed Mode for host */
 198         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 199         switch (uhs) {
 200         case MMC_TIMING_UHS_SDR12:
 201                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 202                 break;
 203         case MMC_TIMING_UHS_SDR25:
 204                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 205                 break;
 206         case MMC_TIMING_UHS_SDR50:
 207                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 208                 break;
 209         case MMC_TIMING_UHS_SDR104:
 210                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 211                 break;
 212         case MMC_TIMING_UHS_DDR50:
 213                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 214                 break;
 215         }
 216
 217         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 218         dev_dbg(mmc_dev(host->mmc),
 219                 "%s uhs = %d, ctrl_2 = %04X\n",
 220                 __func__, uhs, ctrl_2);
 221
 222         return 0;
 223 }
 224
 225 static const struct sdhci_ops pxav3_sdhci_ops = {
 226         .platform_reset_exit = pxav3_set_private_registers,
 227         .set_uhs_signaling = pxav3_set_uhs_signaling,
 228         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 229         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 230         .set_bus_width = sdhci_set_bus_width,
 231 };
 232
 233 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
 234         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 235                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 236                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 237                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 238         .ops = &pxav3_sdhci_ops,
 239 };
 240
 241 #ifdef CONFIG_OF
 242 static const struct of_device_id sdhci_pxav3_of_match[] = {
 243         {
 244                 .compatible = "mrvl,pxav3-mmc",
 245         },
 246         {
 247                 .compatible = "marvell,armada-380-sdhci",
 248         },
 249         {},
 250 };
 251 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 252
 253 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 254 {
 255         struct sdhci_pxa_platdata *pdata;
 256         struct device_node *np = dev->of_node;
 257         u32 clk_delay_cycles;
 258
 259         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 260         if (!pdata)
 261                 return NULL;
 262
 263         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 264         if (clk_delay_cycles > 0)
 265                 pdata->clk_delay_cycles = clk_delay_cycles;
 266
 267         return pdata;
 268 }
 269 #else
 270 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 271 {
 272         return NULL;
 273 }
 274 #endif
 275
 276 static int sdhci_pxav3_probe(struct platform_device *pdev)
 277 {
 278         struct sdhci_pltfm_host *pltfm_host;
 279         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 280         struct device *dev = &pdev->dev;
 281         struct device_node *np = pdev->dev.of_node;
 282         struct sdhci_host *host = NULL;
 283         struct sdhci_pxa *pxa = NULL;
 284         const struct of_device_id *match;
 285
 286         int ret;
 287         struct clk *clk;
 288
 289         pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL);
 290         if (!pxa)
 291                 return -ENOMEM;
 292
 293         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 294         if (IS_ERR(host)) {
 295                 kfree(pxa);
 296                 return PTR_ERR(host);
 297         }
 298
 299         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
 300                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 301                 if (ret < 0)
 302                         goto err_mbus_win;
 303         }
 304
 305
 306         pltfm_host = sdhci_priv(host);
 307         pltfm_host->priv = pxa;
 308
 309         clk = clk_get(dev, NULL);
 310         if (IS_ERR(clk)) {
 311                 dev_err(dev, "failed to get io clock\n");
 312                 ret = PTR_ERR(clk);
 313                 goto err_clk_get;
 314         }
 315         pltfm_host->clk = clk;
 316         clk_prepare_enable(clk);
 317
 318         /* enable 1/8V DDR capable */
 319         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 320
 321         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 322         if (match) {
 323                 ret = mmc_of_parse(host->mmc);
 324                 if (ret)
 325                         goto err_of_parse;
 326                 sdhci_get_of_property(pdev);
 327                 pdata = pxav3_get_mmc_pdata(dev);
 328         } else if (pdata) {
 329                 /* on-chip device */
 330                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
 331                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 332
 333                 /* If slot design supports 8 bit data, indicate this to MMC. */
 334                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 335                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 336
 337                 if (pdata->quirks)
 338                         host->quirks |= pdata->quirks;
 339                 if (pdata->quirks2)
 340                         host->quirks2 |= pdata->quirks2;
 341                 if (pdata->host_caps)
 342                         host->mmc->caps |= pdata->host_caps;
 343                 if (pdata->host_caps2)
 344                         host->mmc->caps2 |= pdata->host_caps2;
 345                 if (pdata->pm_caps)
 346                         host->mmc->pm_caps |= pdata->pm_caps;
 347
 348                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
 349                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
 350                                                   0);
 351                         if (ret) {
 352                                 dev_err(mmc_dev(host->mmc),
 353                                         "failed to allocate card detect gpio\n");
 354                                 goto err_cd_req;
 355                         }
 356                 }
 357         }
 358
 359         pm_runtime_enable(&pdev->dev);
 360         pm_runtime_get_sync(&pdev->dev);
 361         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
 362         pm_runtime_use_autosuspend(&pdev->dev);
 363         pm_suspend_ignore_children(&pdev->dev, 1);
 364
 365         ret = sdhci_add_host(host);
 366         if (ret) {
 367                 dev_err(&pdev->dev, "failed to add host\n");
 368                 goto err_add_host;
 369         }
 370
 371         platform_set_drvdata(pdev, host);
 372
 373         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
 374                 device_init_wakeup(&pdev->dev, 1);
 375                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
 376         } else {
 377                 device_init_wakeup(&pdev->dev, 0);
 378         }
 379
 380         pm_runtime_put_autosuspend(&pdev->dev);
 381
 382         return 0;
 383
 384 err_of_parse:
 385 err_cd_req:
 386 err_add_host:
 387         pm_runtime_put_sync(&pdev->dev);
 388         pm_runtime_disable(&pdev->dev);
 389         clk_disable_unprepare(clk);
 390         clk_put(clk);
 391 err_clk_get:
 392 err_mbus_win:
 393         sdhci_pltfm_free(pdev);
 394         kfree(pxa);
 395         return ret;
 396 }
 397
 398 static int sdhci_pxav3_remove(struct platform_device *pdev)
 399 {
 400         struct sdhci_host *host = platform_get_drvdata(pdev);
 401         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 402         struct sdhci_pxa *pxa = pltfm_host->priv;
 403
 404         pm_runtime_get_sync(&pdev->dev);
 405         sdhci_remove_host(host, 1);
 406         pm_runtime_disable(&pdev->dev);
 407
 408         clk_disable_unprepare(pltfm_host->clk);
 409         clk_put(pltfm_host->clk);
 410
 411         sdhci_pltfm_free(pdev);
 412         kfree(pxa);
 413
 414         return 0;
 415 }
 416
 417 #ifdef CONFIG_PM_SLEEP
 418 static int sdhci_pxav3_suspend(struct device *dev)
 419 {
 420         int ret;
 421         struct sdhci_host *host = dev_get_drvdata(dev);
 422
 423         pm_runtime_get_sync(dev);
 424         ret = sdhci_suspend_host(host);
 425         pm_runtime_mark_last_busy(dev);
 426         pm_runtime_put_autosuspend(dev);
 427
 428         return ret;
 429 }
 430
 431 static int sdhci_pxav3_resume(struct device *dev)
 432 {
 433         int ret;
 434         struct sdhci_host *host = dev_get_drvdata(dev);
 435
 436         pm_runtime_get_sync(dev);
 437         ret = sdhci_resume_host(host);
 438         pm_runtime_mark_last_busy(dev);
 439         pm_runtime_put_autosuspend(dev);
 440
 441         return ret;
 442 }
 443 #endif
 444
 445 #ifdef CONFIG_PM_RUNTIME
 446 static int sdhci_pxav3_runtime_suspend(struct device *dev)
 447 {
 448         struct sdhci_host *host = dev_get_drvdata(dev);
 449         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 450         unsigned long flags;
 451
 452         if (pltfm_host->clk) {
 453                 spin_lock_irqsave(&host->lock, flags);
 454                 host->runtime_suspended = true;
 455                 spin_unlock_irqrestore(&host->lock, flags);
 456
 457                 clk_disable_unprepare(pltfm_host->clk);
 458         }
 459
 460         return 0;
 461 }
 462
 463 static int sdhci_pxav3_runtime_resume(struct device *dev)
 464 {
 465         struct sdhci_host *host = dev_get_drvdata(dev);
 466         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 467         unsigned long flags;
 468
 469         if (pltfm_host->clk) {
 470                 clk_prepare_enable(pltfm_host->clk);
 471
 472                 spin_lock_irqsave(&host->lock, flags);
 473                 host->runtime_suspended = false;
 474                 spin_unlock_irqrestore(&host->lock, flags);
 475         }
 476
 477         return 0;
 478 }
 479 #endif
 480
 481 #ifdef CONFIG_PM
 482 static const struct dev_pm_ops sdhci_pxav3_pmops = {
 483         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
 484         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
 485                 sdhci_pxav3_runtime_resume, NULL)
 486 };
 487
 488 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
 489
 490 #else
 491 #define SDHCI_PXAV3_PMOPS NULL
 492 #endif
 493
 494 static struct platform_driver sdhci_pxav3_driver = {
 495         .driver         = {
 496                 .name   = "sdhci-pxav3",
 497 #ifdef CONFIG_OF
 498                 .of_match_table = sdhci_pxav3_of_match,
 499 #endif
 500                 .owner  = THIS_MODULE,
 501                 .pm     = SDHCI_PXAV3_PMOPS,
 502         },
 503         .probe          = sdhci_pxav3_probe,
 504         .remove         = sdhci_pxav3_remove,
 505 };
 506
 507 module_platform_driver(sdhci_pxav3_driver);
 508
 509 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 510 MODULE_AUTHOR("Marvell International Ltd.");
 511 MODULE_LICENSE("GPL v2");
 512